ISL6721AB [RENESAS]
1A SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, PDSO16, 0.150 INCH, PLASTIC, MS-012AC, SOIC-16;
| 型号： | ISL6721AB |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 1A SWITCHING CONTROLLER, 1000kHz SWITCHING FREQ-MAX, PDSO16, 0.150 INCH, PLASTIC, MS-012AC, SOIC-16 信息通信管理 开关 光电二极管 |
| 文件： | 总23页 (文件大小：1006K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL6721
FN9110
Rev 9.00
May 20, 2016
Flexible Single-Ended Current Mode PWM Controller
The ISL6721 is a low power, single-ended Pulse Width
Modulating (PWM) current mode controller designed for a wide
range of DC/DC conversion applications including Boost,
Flyback and isolated output configurations. Peak current
mode control effectively handles power transients and
provides inherent overcurrent protection. Other features
include a low power mode where the supply current drops to
less than 200µA during overvoltage and overcurrent shutdown
faults.
Features
• 1A MOSFET gate driver
• 100µA start-up current
• Fast transient response with peak current mode control
• Adjustable switching frequency up to 1MHz
• Bidirectional synchronization
• Low power disable mode
This advanced BiCMOS design features low operating current,
adjustable operating frequency up to 1MHz, adjustable
soft-start, and a bidirectional SYNC signal that allows the
oscillator to be locked to an external clock for noise sensitive
applications.
• Delayed restart from OV and OC shutdown faults
• Adjustable slope compensation
• Adjustable soft-start
• Adjustable overcurrent shutdown threshold
• Adjustable UV and OV monitors
• Leading edge blanking
Applications
• Telecom and datacom power
• Wireless base station power
• File server power
• Integrated thermal shutdown
• 1% tolerance voltage reference
• Pb-free available (RoHS compliant)
• Industrial power systems
• Isolated buck and Flyback regulators
• Boost regulators
Related Literature
• AN1384, “ISL6841EVAL3Z Evaluation Board for General
Purpose Industrial Applications”
• AN1491, “ISL6721EVAL3Z: Resonant Reset Forward
Converters for Low Power”
ISL6721
(16 LD TSSOP)
(16 LD SOIC)
TOP VIEW
GATE
ISENSE
SYNC
SLOPE
UV
1
2
3
4
5
6
7
8
16 VC
15 PGND
14 VCC
13 VREF
12 LGND
11 SS
OV
RTCT
ISET
10 COMP
9
FB
FN9110 Rev 9.00
May 20, 2016
Page 1 of 23
ISL6721
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL6721ABZ
6721ABZ
ISL67 21AV
-40 to +105
-40 to +105
16 Ld SOIC (150 mil)
16 Ld TSSOP (4.4mm)
M16.15
ISL6721AV-T
(No longer available, recommended
replacement: ISL6721AVZ-T)
M16.173
M16.173
ISL6721AVZ
ISL6721EVAL3Z
NOTES:
ISL67 21AVZ
-40 to +105
16 Ld TSSOP (4.4mm)
Evaluation Board
1. Add “-T” suffix for 2.5k unit for Tape and Reel options. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6721. For more information on MSL please see techbrief TB363.
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER
UVLO thresholds (start/stop) (V)
UV threshold (V)
ISL6721
8.25/7.70
1.45
ISL6721A
6.80/6.20
1.93
FN9110 Rev 9.00
May 20, 2016
Page 2 of 23
ISL6721
Functional Block Diagram
VREF
5V
1%
V
VREF
CC
START/STOP
SOFT-START
CHARGE 70µA
CURRENT
UV COMPARATOR
+
-
ENABLE
ON
+
BG
-
SS CHARGE
SS
15µA
LGND
VOLTAGE CLAMP
THERMAL
OVERCURRENT
SHUTDOWN
DELAY
PROTECTION
25µA
SS CHARGED
+
-
RESTART
DELAY
4.375V
ISET
ON
0.8
ISENSE
S Q
5k
-
+
OC DETECT
+
S
+
VREF
R Q
OC LATCH
53µA
OVERCURRENT
COMPARATOR
Q
Q
100mV
SLOPE
50µs
RETRIGGERABLE
ONE SHOT
0.1
SS LOW
-
+
270mV
SS LOW
FAULT
LATCH
COMPARATOR
SS
SS CLAMP
ERROR
S Q
+
-
COMP
VFB
R Q
PWM
VREF
COMPARATOR
SET DOMINANT
+
-
VREF
2.5V
AMPLIFIER
UV COMPARATOR
4.65V
-
+
-
+
START
BG
1/3
100ns
BLANKING
OV
UV
+
-
VREF
2.50V
1.45V
-
+
20k
3.0V
1.5V
BLANKING
COMPARATOR
12k
3.0V
ON
-
+
30k
OSCILLATOR
COMPARATOR
VC
S Q
R Q
-
+
BI-DIRECTIONAL
SYNCHRONIZATION
RTCT
1mA
ON
GATE
OSC IN
VREF
36k
CLK OUT
+
-
NO EXT SYNC
4V
-
+
EXT SYNC BLANKING
2V
PGND
SYNC IN
SYNC OUT
VREF
100k
SYNC
4.5k
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
FN9110 Rev 9.00
May 20, 2016
Page 3 of 23
ISL6721
Typical Application - 48V Input Dual Output Flyback, 3.3V at 2.5A,
1.8V at 1.0A
SP1
SP2
CR5
T1
+3.3V
+1.8V
ISOLATION
XFMR
C
21
+
+
C
15
C
16
R
21
VIN+ P9
C
18
R
CR4
C
24
+
C
22
+
19
C
20
C
2
CR2
C
17
C
5
RETURN
CR6
R
R
1
36-75V
R
R
17
R
18
16
C
6
R
19
C
3
C
1
TP1
U2
C
14
Q1
2
R
4
R
3
R
15
R
22
C
13
R
23
U3
VIN-
R
20
TP2
U4
R
25
C
4
Q2
D1
GATE
ISENSE
VC
PGND
VC
TP3
SYNC
SYNC
R
14
VREF
LGND
SLOPE
UV
OV
R
5
TP4
SS
COMP
VFB
R
26
R
6
TP5
RTCT
ISET
D2
ISL6721
R
27
Q3
C
12
R
8
R
10
C
11
C10
C
C
C
9
7
8
VR1
R
12
R
13
R
7
R
11
R
9
FIGURE 2. TYPICAL APPLICATION - 48V INPUT DUAL OUTPUT FLYBACK, 3.3V AT 2.5A, 1.8V AT 1.0A
FN9110 Rev 9.00
May 20, 2016
Page 4 of 23
ISL6721
Typical Boost Converter Application Schematic
CR1
L
+VOUT
VIN+
1
+
C
C
3
2
R
C
12
12
RETURN
Q1
R
8
R
R
4
R
3
1
2
R
C
4
11
C
C
1
VIN+
C
U1
R
10
10
GATE
VC
PGND
VCC
ISENSE
SYNC
SLOPE VREF
UV
OV
LGND
SS
RTCT COMP
R
9
ISET
VFB
R
5
R
11
C
5
C
C
6
7
C
C
8
R
6
9
R
7
VIN-
FIGURE 3. TYPICAL BOOST CONVERTER APPLICATION SCHEMATIC
FN9110 Rev 9.00
May 20, 2016
Page 5 of 23
ISL6721
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V
V
. . . . . . . . . . . . . . . . . . . . . . . (GND -0.3V) to +20.0V
Thermal Resistance (Typical, Note 4)
(°C/W)
CC,
C
JA
GATE. . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to Gate Output Limit Voltage
PGND to LGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V
VREF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (GND - 0.3V) to 5.3V
Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(GND - 0.3V) to VREF
Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A
16 Ld SOIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16 Ld TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
80
105
Operating Conditions
Temperature Range
ISL6721Ax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
Supply Voltage Range (Typical, Note 5) . . . . . . . . . . . . . . . . 9VDC to 18VDC
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
5. All voltages are with respect to GND.
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 3
and “Typical Boost Converter Application Schematic” on page 5. 9V < V = VC < 20V, R = 11kΩ, C = 330 pF, T = -40°C to +105°C (Note 6), Typical
CC
T
t
A
values are at T = +25°C.
A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
UNDERVOLTAGE LOCKOUT
START Threshold
STOP Threshold
Hysteresis
7.95
8.25
7.70
0.55
100
200
4.5
8.55
8.20
1.00
175
V
V
7.40
0.50
V
Start-Up Current, I
CC
V
< START Threshold
-
-
-
-
µA
µA
mA
mA
CC
OC/OV Fault Operating Current, I
CC
300
10.0
12.0
Operating Current, I
CC
Operating Supply Current, I
REFERENCE VOLTAGE
Overall Accuracy
Includes 1nF GATE loading
8.0
C
Line, load, 0°C to +105°C
Line, load, -40°C to +105°C
4.95
4.90
-
5.00
5.00
5
5.05
5.05
-
V
V
Long Term Stability
Fault Voltage
T
= +125°C, 1000 hours (Note 8)
mV
V
A
4.50
4.65
75
4.65
4.80
165
-
4.75
4.95
250
-
V
Good Voltage
V
REF
Hysteresis
mV
mA
mA
Operational Current
Current Limit
-10
-20
-
-
CURRENT SENSE
Input Impedance
Offset Voltage
-
5
0.10
-
-
kΩ
V
0.08
0
0.11
1.5
Input Voltage Range
Blanking Time
V
(Note 8)
30
60
100
0.81
ns
V/V
Gain, A
CS
V
V
= 0V, V = 2.3V,
FB
= 0.35V, 1.5V
0.77
0.79
SLOPE
ISET
A
= ISET/ISENSE
CS
FN9110 Rev 9.00
May 20, 2016
Page 6 of 23
ISL6721
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 3
and “Typical Boost Converter Application Schematic” on page 5. 9V < V = VC < 20V, R = 11kΩ, C = 330 pF, T = -40°C to +105°C (Note 6), Typical
CC
T
t
A
values are at T = +25°C.
A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ERROR AMPLIFIER
Open Loop Voltage Gain
Gain-Bandwidth Product
Reference Voltage Initial Accuracy
Reference Voltage
(Note 8)
(Note 8)
60
-
90
15
-
dB
MHz
V
-
2.565
2.590
0.35
0.88
2
V
= COMP, T = +25°C (Note 8)
A
2.465
2.440
0.31
0.51
-2
2.515
2.515
0.33
0.75
0.1
FB
FB
V
= COMP
V
COMP to PWM Gain, A
COMP to PWM Offset
FB Input Bias Current
COMP Sink Current
COMP = 4V, T = +25°C
A
V/V
V
COMP
COMP = 4V (Note 8)
V
= 0V
µA
mA
mA
V
FB
COMP = 1.5V, V = 2.7V
2
6
-
FB
COMP Source Current
COMP = 1.5V, V = 2.3V
-0.25
4.25
0.4
-0.50
4.40
0.8
-
FB
COMP V
COMP V
PSRR
V
V
= 2.3V
= 2.7V
5.00
1.2
-
OH
FB
FB
V
OL
Frequency = 120Hz (Note 8)
60
80
dB
V
SS Clamp, V
COMP
SS = 2.5V, V = 0V, ISET = 2V
FB
2.4
2.5
2.6
OSCILLATOR
Frequency Accuracy
289
-
318
347
kHz
%
Frequency Variation with V
T = +105°C (f20V - f9V)/f9V
T = -40°C (f20V -f9V)/f9V
2
2
3
3
CC
Temperature Stability
Maximum Duty Cycle
(Note 8)
(Note 9)
-
8
-
%
%
V
68
75
81
Comparator High Threshold - Free Running
Comparator High Threshold - with External SYNC
Comparator Low Threshold
-
-
-
3.00
4.00
1.50
-
-
-
(Note 8)
V
V
Discharge Current
0°C to +105°C
-40°C to +105°C
0.75
0.70
1.00
1.00
1.20
1.20
mA
SYNCHRONIZATION
Input High Threshold
Input Pulse Width
-
-
-
-
2.5
-
V
25
ns
Input Frequency Range
(Note 8)
0.65 x Free
Running
1.0
MHz
Input Impedance
-
4.5
-
kΩ
V
V
V
R
R
= 4.5kΩ
2.5
-
-
-
OH
LOAD
LOAD
= open
-
-
0.1
55
V
OL
SYNC Advance
SYNC rising edge to GATE falling
edge, C = C = 100pF
25
ns
GATE
= 100pF
SYNC
Output Pulse Width
C
50
-
-
ns
SYNC
FN9110 Rev 9.00
May 20, 2016
Page 7 of 23
ISL6721
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 3
and “Typical Boost Converter Application Schematic” on page 5. 9V < V = VC < 20V, R = 11kΩ, C = 330 pF, T = -40°C to +105°C (Note 6), Typical
CC
T
t
A
values are at T = +25°C.
A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SOFT-START
Charging Current
SS = 2V
-40
-55
4.50
40
-70
4.74
55
µA
V
Charged Threshold Voltage
Initial Overcurrent Discharge Current
4.26
30
Sustained OC Threshold < SS <
Charged Threshold
µA
Overcurrent Shutdown Threshold Voltage
Charged Threshold minus,
0.095
0.125
0.155
V
T
= +25°C
A
Fault Discharge Current
Reset Threshold Voltage
SLOPE COMPENSATION
Charge Current
SS = 2V
= +25°C
0.25
0.22
1.00
0.27
-
mA
V
T
0.31
A
SLOPE = 2V, 0°C to +105°C
-40°C to +105°C
-45
-41
-53
-53
-65
-65
µA
V/V
V/V
V
Slope Compensation Gain
Fraction of slope voltage added to
0.097
0.082
-
-
0.103
0.118
0.2
I
, T = +25°C
SENSE
A
Fraction of slope voltage added to
-
I
(Note 6)
SENSE
Discharge Voltage
GATE OUTPUT
V
= 4.5V
0.1
RTCT
Gate Output Limit Voltage
V
= 20V, C
= 1nF,
11.0
13.5
1.5
16.0
2.2
V
V
V
C
GATE
= 0mA
I
OUT
Gate V
Gate V
V
- GATE, V = 10V,
= 150mA
-
-
OH
C
C
I
OUT
GATE - PGND, IOUT = 150mA
= 10mA
1.2
0.6
1.5
0.8
OL
I
OUT
Peak Output Current
Output “Faulted” Leakage
Rise Time
V
V
V
= 20V, C
= 1nF (Note 8)
-
1.2
-
1.0
2.6
60
-
-
A
C
C
C
GATE
= 20V, UV = 0V, GATE = 2V
mA
ns
= 20V, C
= 1nF
= 1nF
100
GATE
1V < GATE < 9V
Fall Time
V
= 20V, C
-
-
15
-
40
ns
ns
C
GATE
1V < GATE < 9V
Minimum ON-Time
ISET = 0.5V; V = 0V; VC = 11V
FB
110
ISENSE to GATE w/10:1 Divider
RTCT = 4.75V through 1kΩ
(Note 8)
OVERCURRENT PROTECTION
Minimum ISET Voltage
Maximum ISET Voltage
-
-
0.35
-
V
V
1.2
-1.0
150
-
-
I
Bias Current
V
= 1.00V
1.0
445
µA
ms
SET
ISET
Restart Delay
T
= +25°C
295
A
OV AND UV VOLTAGE MONITOR
Overvoltage Threshold
2.4
2.5
2.6
V
V
V
Undervoltage Fault Threshold
Undervoltage Clear Threshold
1.38
1.41
1.45
1.53
1.52
1.62
FN9110 Rev 9.00
May 20, 2016
Page 8 of 23
ISL6721
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 3
and “Typical Boost Converter Application Schematic” on page 5. 9V < V = VC < 20V, R = 11kΩ, C = 330 pF, T = -40°C to +105°C (Note 6), Typical
CC
T
t
A
values are at T = +25°C.
A
PARAMETER
TEST CONDITIONS
MIN
20
TYP
MAX
100
1.0
UNIT
mV
µA
Undervoltage Hysteresis Voltage
UV Bias Current
50
V
V
= 2.00V
-1.0
-1.0
-
-
UV
OV Bias Current
= 2.00V
1.0
µA
OV
THERMAL PROTECTION
Thermal Shutdown
Thermal Shutdown Clear
Hysteresis
(Note 8)
(Note 8)
(Note 8)
120
105
-
130
120
10
140
135
-
°C
°C
°C
NOTES:
6. Specifications at -40°C and +105°C are guaranteed by +25°C test with margin limits.
7. This is the V current consumed when the device is active but not switching. Does not include gate drive current.
CC
8. Limits should be considered typical and are not production tested.
9. This is the maximum duty cycle achievable using the specified values of R and C . Larger or smaller maximum duty cycles may be obtained using
T
T
other values for R and C . See Equations 1, 2, 3 and 4.
T
T
Typical Performance Curves
1.002
1.002
1.000
1.000
0.998
0.998
0.995
0.995
0.993
0.993
0.991
0.991
-40
-10
20
50
80
110
-40
-10
20
50
80
110
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 4. EA REFERENCE VOLTAGE vs TEMPERATURE
FIGURE 5. V
REFERENCE VOLTAGE vs TEMPERATURE
REF
3
1.002
0.996
0.989
0.983
0.976
0.970
10
100pF
100
220pF
330pF
470pF
680pF
1000pF
2000pF
10
-40
-10
20
50
80
110
10 20 30 40 50 60 70 80 90 100
R
(k)
TEMPERATURE (°C)
T
FIGURE 6. OSCILLATOR FREQUENCY vs TEMPERATURE
FIGURE 7. RESISTANCE FOR C CAPACITOR VALUES GIVEN
T
FN9110 Rev 9.00
May 20, 2016
Page 9 of 23
ISL6721
Exceeding the overcurrent threshold will start a delayed
shutdown sequence. Once an overcurrent condition is detected,
the soft-start charge current source is disabled and a discharge
current source is enabled. The soft-start capacitor begins
discharging, and if it discharges to less than 4.375V (sustained
overcurrent threshold), a shutdown condition occurs and the
GATE output is forced low. See “Overcurrent Operation” on
page 12 for more details. The GATE output remains low until the
reset threshold is attained. At this point, a soft-start cycle
begins.
Pin Descriptions
SLOPE - Means by which the ISENSE ramp slope may be
increased for improved noise immunity or improved control
loop stability for duty cycles greater than 50%. An internal
current source charges an external capacitor to GND during
each switching cycle. The resulting ramp is scaled and added
to the ISENSE signal.
SYNC - A bidirectional synchronization signal used to
coordinate the switching frequency of multiple units.
Synchronization may be achieved by connecting the SYNC
signal of each unit together or by using an external master
clock signal. The oscillator timing capacitor, C , is still required,
even if an external clock is used. The first unit to assert this
signal assumes control.
If the overcurrent condition ceases, and then an additional
50µs period elapses before the shutdown threshold is
reached, no shutdown occurs and the soft-start voltage is
allowed to recharge.
T
LGND - LGND is a small signal reference ground for all analog
functions on this device.
RTCT - This is the oscillator timing control pin. The operational
frequency and maximum duty cycle are set by connecting a
PGND - This pin provides a dedicated ground for the output
gate driver. The LGND and PGND pins should be connected
externally using a short printed circuit board trace close to the
IC. This is imperative to prevent large, high frequency switching
currents flowing through the ground metallization inside the IC.
(Decouple VC to PGND with a low ESR 0.1µF or larger
capacitor.)
resistor, R , between V
and this pin and a timing capacitor,
T
REF
C , from this pin to LGND. The oscillator produces a sawtooth
T
waveform with a programmable frequency range of 100kHz to
1.0MHz. The charge time, t , the discharge time, t , the
C
D
switching frequency, f , and the maximum duty cycle, Dmax,
sw
can be calculated from Equations 1, 2, 3 and 4:
(EQ. 1)
t
0.655 R C
S
C
T
T
GATE - This is the device output. It is a high current power
driver capable of driving the gate of a power MOSFET with
peak currents of 1.0A. This GATE output is actively held low
when VCC is below the UVLO threshold.
0.001 R – 3.6
T
T
------------------------------------------
(EQ. 2)
(EQ. 3)
(EQ. 4)
t
f
–R C LN
S
D
T
T
0.001 R – 1.9
1
+ t
C
-----------------
D
=
Hz
sw
The output high voltage is clamped to ~13.5V. Voltages
exceeding this clamp value should not be applied to the GATE
pin. The output stage provides very low impedance to
overshoot and undershoot.
t
Dmax = t f
C
sw
VC - This pin is for separate collector supply to the output gate
drive. Separate VC and PGND helps decouple the IC’s analog
circuitry from the high power gate drive noise. (Decouple VC to
PGND with a low ESR 0.1µF or larger capacitor.)
Figure 7 may be used as a guideline in selecting the capacitor
and resistor values required for a given frequency.
COMP - COMP is the output of the error amplifier and the input
of the PWM comparator. The control loop frequency
compensation network is connected between the COMP and
FB pins.
VCC - VCC is the power connection for the device. Although
quiescent current, I , is low, it is dependent on the frequency
CC
of operation. To optimize noise immunity, bypass VCC to LGND
with a ceramic capacitor as close to the VCC and LGND pins as
possible.
The ISL6721 features a built-in full cycle soft-start. Soft-start is
implemented as a clamp on the maximum COMP voltage.
FB - Feedback voltage input connected to the inverting input of
the error amplifier. The noninverting input of the error amplifier
is internally tied to a reference voltage. Current sense leading
edge blanking is disabled when the FB input is less than 2.0V.
The total supply current (I plus I ) will be higher, depending
CC
on the load applied to GATE. Total current is the sum of the
quiescent current and the average gate current. Knowing the
C
operating frequency, f , and the MOSFET gate charge, Qg, the
sw
average GATE output current can be calculated in Equation 5:
OV - Overvoltage monitor input pin. This signal is compared to
an internal 2.5V reference to detect an overvoltage condition.
Igate = Qg f
A
(EQ. 5)
sw
UV - Undervoltage monitor input pin. This signal is compared to
an internal 1.45V reference to detect an undervoltage
condition.
VREF - The 5V reference voltage output. Bypass to LGND with a
0.01µF or larger capacitor to filter this output as needed. Using
capacitance less than this value may result in unstable
operation.
ISENSE - This is the input to the current sense comparators.
The IC has two current sensing comparators, a PWM
comparator for peak current mode control, and an overcurrent
protection comparator. The overcurrent comparator threshold
is adjustable through the ISET pin.
FN9110 Rev 9.00
May 20, 2016
Page 10 of 23
ISL6721
SS - Connect the soft-start capacitor between this pin and
LGND to control the duration of soft-start. The value of the
capacitor determines both the rate of increase of the duty
cycle during start-up, and also controls the overcurrent
shutdown delay.
voltage. The error amplifier output rises as the soft-start
capacitor voltage rises. This has the effect of increasing the
output pulse width from zero to the steady state operating duty
cycle during the soft-start period. When the soft-start voltage
exceeds the error amplifier voltage, soft-start is completed.
Soft-start forces a controlled output voltage rise. Soft-start
occurs during start-up and after recovery from a fault condition
or overcurrent shutdown. The soft-start voltage is clamped to
4.5V.
ISET - A DC voltage between 0.35V and 1.2V applied to this
input sets the pulse-by-pulse overcurrent threshold. When
overcurrent inception occurs, the SS capacitor begins to
discharge and starts the overcurrent delayed shutdown cycle.
Gate Drive
Functional Description
The ISL6721 is capable of sourcing and sinking 1A peak
current. Separate collector supply (VC) and power ground
(PGND) pins help isolate the IC’s analog circuitry from the high
power gate drive noise. To limit the peak current through the
IC, an external resistor may be placed between the totem-pole
output of the IC (GATE pin) and the gate of the MOSFET. This
small series resistor also damps any oscillations caused by the
resonant tank of the parasitic inductances in the traces of the
board and the FET’s input capacitance.
Features
The ISL6721 current mode PWMs make an ideal choice for
low-cost Flyback and Forward topology applications requiring
enhanced control and supervisory capability. With adjustable
overvoltage and undervoltage thresholds, overcurrent
threshold, and hiccup delay, a highly flexible design with
minimal external components is possible. Other features
include peak current mode control, adjustable soft-start, slope
compensation, adjustable oscillator frequency, and a
bidirectional synchronization clock input.
Slope Compensation
For applications where the maximum duty cycle is less than
50%, slope compensation may be used to improve noise
immunity, particularly at lighter loads. The amount of slope
compensation required for noise immunity is determined
empirically, but is generally about 10% of the full scale current
feedback signal. For applications where the duty cycle is
greater than 50%, slope compensation is required to prevent
instability. Slope compensation is a technique in which the
current feedback signal is modified by adding additional slope
to it. The minimum amount of slope compensation required
corresponds to 1/2 the inductor downslope. However, adding
excessive slope compensation results in a control loop that
behaves more as a voltage mode controller than as current
mode controller.
Oscillator
The ISL6721 has a sawtooth oscillator with a programmable
frequency range to 1MHz, which can be programmed with a
resistor and capacitor on the RTCT pin. (Please refer to
Figure 7 on page 9 for the resistance and capacitance required
for a given frequency.)
Implementing Synchronization
The oscillator can be synchronized to an external clock applied
at the SYNC pin or by connecting the SYNC pins of multiple ICs
together. If an external master clock signal is used, it must be
at least 65% of the free running frequency of the oscillator for
proper synchronization. The external master clock signal
should have a pulse width greater than 20ns. If no master
clock is used, the first device to assert SYNC assumes control
of the SYNC signal. An external SYNC pulse is ignored if it
occurs during the first 1/3 of the switching cycle.
DOWNSLOPE
CURRENT SENSE SIGNAL
During normal operation the RTCT voltage charges from 1.5V
to 3.0V and back during each cycle. Clock and SYNC signals
are generated when the 3.0V threshold is reached. If an
external clock signal is detected during the latter 2/3 of the
charging cycle, the oscillator switches to external
TIME
FIGURE 8.
synchronization mode and relies upon the external SYNC
signal to terminate the oscillator cycle. The generation of a
SYNC signal is inhibited in this mode. If the RTCT voltage
exceeds 4.0V (i.e., no external SYNC signal terminates the
cycle), the oscillator reverts to the internal clock mode and a
SYNC signal is generated.
The minimum amount of capacitance to place at the SLOPE
pin is calculated in Equation 6:
t
–6
ON
(EQ. 6)
----------------------
SLOPE
C
= 4.2410
F
SLOPE
V
Where t is the On time and V
ON SLOPE
is the amount of voltage
Soft-Start Operation
The ISL6721 features soft-start using an external capacitor in
conjunction with an internal current source. Soft-start is used
to reduce voltage stresses and surge currents during start-up.
to be added as slope compensation to the current feedback
signal. In general, the amount of slope compensation added is
2 to 3 times the minimum required.
Upon start-up, the soft-start circuitry clamps the error amplifier
output (COMP pin) to a value proportional to the soft-start
FN9110 Rev 9.00
May 20, 2016
Page 11 of 23
ISL6721
Example:
and I drops to 200µA for approximately 295ms. A new
CC
soft-start cycle is then initiated. The shutdown and restart
behavior of the OC protection is often referred to as hiccup
operation due to its repetitive start-up and shutdown
characteristic.
Assume the inductor current signal presented at the ISENSE
pin decreases 125mV during the Off period, and:
Switching frequency, f = 250kHz
sw
If the overcurrent condition ceases at least 50µs prior to the
soft-start voltage reaching 4.375V, the soft-start charging and
discharging currents revert to normal operation and the
soft-start voltage is allowed to recover.
Duty Cycle, D = 60%
t
t
= D/f = 0.6/250E3 = 2.4µs
sw
ON
= (1 - D)/fsw = 1.6µs
OFF
Hiccup OC protection may be defeated by setting ISET to a
voltage that exceeds the Error Amplifier current control
voltage, or about 1.5V.
Determine the downslope:
Downslope = 0.125V/1.6µs = 78mV/µs. Now determine the
amount of voltage that must be added to the current sense
signal by the end of the On time.
Leading Edge Blanking
1
2
--
V
=
0.078 2.4 = 94mV
(EQ. 7)
The initial 100ns of the current feedback signal input at
ISENSE is removed by the leading edge blanking circuitry. The
blanking period begins when the GATE output leading edge
exceeds 3.0V. Leading edge blanking prevents current spikes
from parasitic elements in the power supply from causing
false trips of the PWM comparator and the overcurrent
comparator.
SLOPE
Therefore,
–6
–6
2.410
-----------------------
110pF
(EQ. 8)
C
= 4.2410
SLOPEMIN
0.094
An appropriate slope compensation capacitance for this
example would be 1/2 to 1/3 the calculated value, or between
68pF and 33pF.
Fault Conditions
A Fault condition occurs if VREF falls below 4.65V, the OV input
exceeds 2.50V, the UV input falls below 1.45V, or the junction
temperature of the die exceeds ~+130°C. When a Fault is
detected the GATE output is disabled and the soft-start
capacitor is quickly discharged. When the Fault condition
clears and the soft-start voltage is below the reset threshold, a
soft-start cycle begins.
Overvoltage and Undervoltage Monitor
The OV and UV signals are inputs to a window comparator used
to monitor the input voltage level to the converter. If the
voltage falls outside of the user designated operating range, a
shutdown fault occurs. For OV faults, the supply current, I , is
CC
reduced to 200µA for ~295ms at which time recovery is
attempted. If the fault is cleared, a soft-start cycle begins.
Otherwise another shutdown cycle occurs. A UV condition also
results in a shutdown fault, but the device does not enter the
low power mode and no restart delay occurs when the fault
clears.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. A unique
section of the ground plane must be designated for high di/dt
currents associated with the output stage. Power ground
(PGND) can be separated from the Logic Ground (LGND) and
connected at a single point. VC should be bypassed directly to
PGND with good high frequency capacitors. The return
connection for input power and the bulk input capacitor should
be connected to the PGND ground plane.
A resistor divider between V and LGND to each input
IN
determines the operational thresholds. The UV threshold has a
fixed hysteresis of 75mV nominal.
Overcurrent Operation
The overcurrent threshold level is set by the voltage applied at
the ISET pin. Setting the overcurrent level may be
accomplished by using a resistor divider network from VREF to
LGND. The ISET threshold should be set at a level that
corresponds to the desired peak output inductor current plus
the additive effects of slope compensation.
Reference Design
The “Typical Boost Converter Application Schematic” on
page 5 features the ISL6721 in a conventional dual output
10W discontinuous mode Flyback DC/DC converter. The
ISL6721EVAL1 demonstration unit implements this design
and is available for evaluation.
Overcurrent delayed shutdown is enabled once the soft-start
cycle is complete. If an overcurrent condition is detected, the
soft-start charging current source is disabled and the
The input voltage range is from 36VDC to 75VDC, and the two
outputs are 3.3V at 2.5A and 1.8V at 1.0A. Cross regulation is
achieved using the weighted sum of the two outputs.
discharging current source is enabled. The soft-start capacitor
is discharged at a rate of 40µA. At the same time, a 50µs
retriggerable one-shot timer is activated and it remains active
for 50µs after the overcurrent condition stops. The soft-start
discharge cycle cannot be reset until the one-shot timer
becomes inactive. If the soft-start capacitor discharges by
more than 0.125V to 4.375V, the output is disabled and the
soft-start capacitor is discharged. The output remains disabled
FN9110 Rev 9.00
May 20, 2016
Page 12 of 23
ISL6721
critical factor in determining the core size. The cross
sectional area of the core and the length of the air gap in the
magnetic path determine the energy storage capability.
Circuit Element Descriptions
The converter design may be broken down into the following
functional blocks:
• Determine maximum desired flux density. Depending on the
frequency of operation, the core material selected, and the
operating environment, the allowed flux density must be
determined. The decision of what flux density to allow is
often difficult to determine initially. Usually the highest flux
density that produces an acceptable design is used, but
often the winding geometry dictates a larger core than is
required based on flux density and energy storage
calculations.
• Input storage and filtering capacitor: C , C , C
1
2
3
• Isolation transformer: T
1
• Primary voltage clamp: C , R , C
R6 24 18
• Start bias regulator: R , R , R , Q , V
1
2
6
3
R1
• Operating bias and regulator: R , Q , D , C , C , D
25 R2 2
2
1
5
• Main MOSFET power switch: Q
1
• Current sense network: R , R , R , C
23 4
• Determine the number of primary turns.
• Determine the turns ratio.
4
3
• Feedback network: R , R , R , R , R , R , R , R
,
13 15 16 17 18 19 20 26
R
, C , C , U , U
27 13 14
2
3
• Select the wire gauge for each winding.
• Determine winding order and insulation requirements.
• Verify the design.
• Control circuit: C , C , C , C , C , C , R , R , R , R ,
10 11 12
7
8
9
5
6
8
9
R
, R , R , R , R
10 11 12 14 22
• Output rectification and filtering: C , C , C , C , C
,
R4 R5 15 16 19
C
, C , C
20 21 22
Input Power:
• Secondary snubber: R , C
21 17
• P
/efficiency = 14.3W (use 15W)
OUT
• Max On time: t
ON(MAX)
= D
/f = 2.25µs
MAX sw
Design Criteria
The following design requirements were selected:
• Average input current: I
Peak Primary Current:
= P /V = 0.42A
IN IN(MIN)
AVG(IN)
• Switching frequency, f : 200kHz
sw
2 I
AVGIN
• V : 36V to 75V
IN
----------------------------------------
(EQ. 9)
I
=
= 1.87
A
PPK
f
t
sw ONMAX
• V
• V
• V
: 3.3V at 2.5A
: 1.8V at 1.0A
: 12V at 50mA
OUT(1)
OUT(2)
Maximum Primary Inductance:
V
t
INMIN ONMAX
---------------------------------------------------------
OUT(BIAS)
Lpmax =
= 43.3
H
(EQ. 10)
I
PPK
• P : 10W
OUT
Choose desired primary inductance to be 40µH.
• Efficiency: 70%
• Maximum duty cycle, D
: 0.45
The core structure must be able to deliver a certain amount of
energy to the secondary on each switching cycle in order to
maintain the specified output power.
MAX
Transformer Design
The design of a Flyback transformer is a non-trivial affair. It is
an iterative process, which requires a great deal of experience
to achieve the desired result. It is a process of many
V
+ Vd
OUT
-----------------------------------
w = P
joules
OUT
(EQ. 11)
f
V
OUT
sw
compromises, and even experienced designers will produce
different designs when presented with identical requirements.
The iterative design process is not presented here for clarity.
Where w is the amount of energy required to be transferred
each cycle and Vd is the drop across the output rectifier.
The capacity of a gapped ferrite core structure to store energy
is dependent on the volume of the airgap and can be
expressed in Equation 12:
The abbreviated design process follows:
• Select a core geometry suitable for the application.
Constraints of height, footprint, mounting preference, and
operating environment will affect the choice.
(EQ. 12)
2 w
3
o
-----------------------------
Vg = Aeff lg =
m
2
B
• Select suitable core material(s).
Where Aeff is the effective cross sectional area of the core in
• Select maximum flux density desired for operation.
2
m , lg is the length of the airgap in meters, µ is the
o
-7
• Select core size. Core size will be dictated by the capability
of the core structure to store the required energy, the
number of turns that have to be wound and the wire gauge
needed. Often the window area (the space used for the
windings) and power loss determine the final core size. For
Flyback transformers, the ability to store energy is the
permeability of free space (410 ) and B is the change in
flux density in Tesla.
A core structure having less airgap volume than calculated will
be incapable of providing the full output power over some
portion of its operating range. On the other hand, if the length of
the airgap becomes large, magnetic field fringing around the
FN9110 Rev 9.00
May 20, 2016
Page 13 of 23
ISL6721
gap occurs. This has the effect of increasing the airgap volume.
Some fringing is usually acceptable, but excessive fringing can
cause increased losses in the windings around the gap resulting
in excessive heating. Once a suitable core and gap combination
are found, the iterative design cycle begins. A design is
developed and checked for ease of assembly and thermal
performance. If the core does not allow adequate space for the
windings, then a core with a larger window area is required. If
the transformer runs hot, it may be necessary to lower the flux
density (more primary turns, lower operating frequency), select
a less lossy core material, change the geometry of the windings
(winding order), use heavier gauge wire or multi-filar windings,
and/or change the type of wire used (Litz wire, for example).
The bias winding turns may be calculated similarly, only a
diode forward drop of 0.7V is used. The rounded off result is 17
turns for a 12V bias.
The next step is to determine the wire gauge. The RMS current
in the primary winding may be calculated using Equation 15:
t
ONMAX
I
= I
PPK
--------------------------
A
(EQ. 15)
PRMS
3 t
sw
The peak and RMS current values in the remaining windings
may be calculated using Equations 16 and 17:
2 I
t
OUT sw
Tr
------------------------------------
(EQ. 16)
I
=
A
SPK
For simplicity, only the final design is further described.
t
An EPCOS EFD 20/10/7 core using N87 material gapped to an
2
sw
I
= 2 I
OUT
--------------
3 Tr
A
(EQ. 17)
RMS
A value of 25nH/N was chosen. It has more than the
L
required air gap volume to store the energy required, but was
needed for the window area it provides.
The RMS current for the primary winding is 0.72A, for the 3.3V
output, 4.23A, for the 1.8V output, 1.69A, and for the bias
winding, 85mA.
-6
Aeff = 31 10
2
m
m
-3
lg = 1.56 10
To minimize the transformer leakage inductance, the primary
was split into two sections connected in parallel and
positioned such that the other windings were sandwiched
between them. The output windings were configured so that
the 1.8V winding is a tap off of the 3.3V winding. Tapping the
1.8V output requires that the shared portion of the secondary
conduct the combined current of both outputs. The secondary
wire gauge must be selected accordingly.
The flux density B is only 0.069T or 690 gauss, a relatively
low value.
Since:
2
N Aeff
o
p
(EQ. 13)
----------------------------------------
L
=
H
p
lg
The number of primary turns, N , may be calculated. The result
p
The determination of current carrying capacity of wire is a
compromise between performance, size, and cost. It is
affected by many design constraints such as operating
frequency (harmonic content of the waveform) and the winding
proximity/geometry. It generally ranges between 250 and
1000 circular mils per ampere. A circular mil is defined as the
area of a circle 0.001” (1 mil) in diameter. As the frequency of
operation increases, the AC resistance of the wire increases
due to skin and proximity effects. Using heavier gauge wire
may not alleviate the problem. Instead multiple strands of wire
in parallel must be used. In some cases, Litz wire is required.
is N = 40 turns. The secondary turns may be calculated as
p
follows:
Ig Vout + Vd tr
(EQ. 14)
-------------------------------------------------------
N
s
N
Ippk Aeff
p
o
Where tr is the time required to reset the core. Since
discontinuous MMF mode operation is desired, the core must
completely reset during the off time. To maintain
discontinuous mode operation, the maximum time allowed to
reset the core is t - t
where t = 1/f . The
sw ON(MAX)
sw sw
minimum time is application dependent and at the designers
discretion knowing that the secondary winding RMS current
and ripple current stress in the output capacitors increases
The winding configuration selected is:
Primary #1: 40T, 2 #30 bifilar
with decreasing reset time. The calculation for maximum N
s
Secondary: 5T, 0.003” (3 mil) copper foil tapped at 3T
Bias: 17T #32
for the 3.3 V output using t = t - t
= 2.75µs is 5.52
sw ON (MAX)
turns.
Primary #2: 40T, 2 #30 bifilar
The determination of the number of secondary turns is also
dependent on the number of outputs and the required turns
ratios required to generate them. If Schottky output rectifiers
are used and we assume a forward voltage drop of 0.45V, the
required turns ratio for the two output voltages, 3.3V and 1.8V,
is 5:3.
The internal spacing and insulation system was designed for
1500VDC dielectric withstand rating between the primary and
secondary windings.
Power MOSFET Selection
With a turns ratio of 5:3 for the secondary windings, we will
use N = 5 turns and N = 3 turns. Checking the reset time
using these values for the number of secondary turns yields a
duration of Tr = 2.33µs or about 47% of the switching period,
an acceptable result.
Selection of the main switching MOSFET requires
consideration of the voltage and current stresses that will be
encountered in the application, the power dissipated by the
device, its size, and its cost.
s1
s2
The input voltage range of the converter is 36VDC to
75VDC. This suggests a MOSFET with a voltage rating of 150V
FN9110 Rev 9.00
May 20, 2016
Page 14 of 23
ISL6721
is required due to the Flyback voltage likely to be seen on the
primary of the isolation transformer.
The losses associated with MOSFET operation may be divided
into three categories: conduction, switching and gate drive.
Ippk
The conduction losses are due to the MOSFETs ON-resistance.
2
Pcond = r
Iprms
W
(EQ. 18)
DSON
VD-S
Where r
is the ON-resistance of the MOSFET and Iprms
DS(ON)
is the RMS primary current. Determining the conduction losses
Tol
is complicated by the variation of r
with temperature. As
DS(ON)
junction temperature increases, so does r
, which
FIGURE 9. SWITCHING CYCLE
DS(ON)
increases losses and raises the junction temperature more,
and so on. It is possible for the device to enter a thermal
runaway situation without proper heatsinking. As a general
The final component of MOSFET loss is caused by the charging
of the gate capacitance through the device gate resistance.
Depending on the relative value of any external resistance in
the gate drive circuit, a portion of this power will be dissipated
externally.
rule of thumb, doubling the +25°C r
specification yields
DS(ON)
a reasonable value for estimating the conduction losses at
+125°C junction temperature.
(EQ. 22)
Pgate = Qg Vg f
W
The switching losses have two components, capacitive
switching losses and voltage/current overlap losses. The
capacitive losses occur during turn-on of the device and may
be calculated in Equation 19:
sw
Once the losses are known, the device package must be
selected and the heatsinking method designed. Since the
design requires a small surface mount part, an 8 Ld SOIC
package was selected. A Fairchild FDS2570 MOSFET was
selected based on these criteria. The overall losses are
estimated at 400mW.
2
1
2
--
Pswcap = Cfet V
f
W
(EQ. 19)
IN
sw
Where Cfet is the equivalent output capacitance of the
MOSFET. Device output capacitance is specified on datasheets
as Coss and is non-linear with applied voltage. To find the
equivalent discrete capacitance, Cfet, a charge model is used.
Using a known current source, the time required to charge the
MOSFET drain to the desired operating voltage is determined
and the equivalent capacitance may be calculated in
Equation 20:
Output Filter Design
In a Flyback design, the primary concern for the design of the
output filter is the capacitor ripple current stress and the ripple
and noise specification of the output.
The current flowing in and out of the output capacitors is the
difference between the winding current and the output current.
Ichg t
(EQ. 20)
-------------------
Cfet =
F
V
The peak secondary current, I
, is 10.73A for the 3.3V output
SPK
and 4.29A for the 1.8V output. The current flowing into the output
filter capacitor is the difference between the winding current and
the output current. Looking at the 3.3V output, the peak winding
The other component of the switching loss is due to the
overlap of voltage and current during the switching transition.
A switching transition occurs when the MOSFET is in the
process of either turning on or off. Since the load is inductive,
there is no overlap of voltage and current during the turn-on
transition, so only the turn-off transition is of significance. The
power dissipation may be estimated using Equation 21:
current is I
= 10.73A. The capacitor must store this amount
SPK
minus the output current of 2.5A, or 8.23A. The RMS ripple
current in the 3.3V output capacitor is about 3.5A . The RMS
RMS
ripple current in the 1.8V output capacitor is about 1.4A
.
RMS
1
x
Voltage deviation on the output during the switching cycle
(ripple and noise) is caused by the change in charge of the
output capacitor, the Equivalent Series Resistance (ESR), and
Equivalent Series Inductance (ESL). Each of these components
must be assigned a portion of the total ripple and noise
specification. How much to allow for each contributor is
dependent on the capacitor technology used.
--
(EQ. 21)
P
I
V t f
IN OL sw
sw
PPK
Where t is the duration of the overlap period and x ranges
OL
from about 3 through 6 in typical applications and depends on
where the waveforms intersect. This estimate may predict
higher dissipation than is realized because a portion of the
turn-off drain current is attributable to the charging of the
device output capacitance (Coss) and is not dissipative during
this portion of the switching cycle.
FN9110 Rev 9.00
May 20, 2016
Page 15 of 23
ISL6721
For purposes of this discussion, we will assume the following:
A block diagram of the feedback control loop is shown in
Figure 10.
•
3.3V output: 100mV total output ripple and noise
PRIMARY SIDE AMPLIFIER
- ESR: 60mV
- Capacitor Q: 10mV
- ESL: 30mV
+
REF
POWER
STAGE
V
OUT
PWM
Z
-
3
•
1.8V output: 50mV total output ripple and noise
Z
4
- ESR: 30mV
ERROR AMPLIFIER
- Capacitor Q: 5mV
- ESL: 15mV
Z
2
ISOLATION
For the 3.3V output:
-
Z
1
V
0.060
10.73 – 2.5
(EQ. 23)
--------------------------------
----------------------------
= 7.3m
ESR
=
I
– I
REF
+
SPK
OUT
The change in voltage due to the change in charge of the
output capacitor, Q, determines how much capacitance is
required on the output.
FIGURE 10. FEEDBACK CONTROL LOOP
The loop compensation is placed around the Error Amplifier
(EA) on the secondary side of the converter. The primary side
amplifier located in the control IC is used as a unity gain
inverting amplifier and provides no loop compensation. A
Type 2 error amplifier configuration was selected as a
precaution in case operation in continuous mode should occur
at some operating point.
–6
Ispk – Iout Tr
10.73 – 2.5 2.3310
---------------------------------------------
------------------------------------------------------------------
C
=
= 960F
(EQ. 24)
2 V
2 0.010
ESL adds to the ripple and noise voltage in proportion to the
rate of change of current into the capacitor (V = L di/dt).
–9
V dt
di
0.030 20010
V
OUT
--------------
---------------------------------------------
= 0.56nH
(EQ. 25)
L
=
10.73
Capacitors having high capacitance usually do not have
sufficiently low ESL. High frequency capacitors such as surface
mount ceramic or film are connected in parallel with the high
capacitance capacitors to address the effects of ESL. A
combination of high frequency and high ripple capability
capacitors is used to achieve the desired overall performance.
The analysis of the 1.8V output is similar to that of the 3.3V
output and is omitted for brevity. Two OSCON 4SEP560M
(560µF) electrolytic capacitors and a 22µF X5R ceramic 1210
capacitor were selected for both the 3.3 and 1.8V outputs. The
4SEP560M electrolytic capacitors are each rated at 4520mA
ripple current and 13mΩ of ESR. The ripple current rating of
just one of these capacitors is adequate, but two are needed to
meet the minimum ESR and capacitance values.
-
V
ERROR
REF
+
FIGURE 11. TYPE 2 ERROR AMPLIFIER
Development of a small signal model for current mode control
is rather complex. The method of reference (1) was selected
for its ability to accurately predict loop behavior. To further
simplify the analysis, the converter will be modeled as a single
output supply with all of the output capacitance reflected to
the 3.3V output. Once the “single” output system is
The bias output is of such low power and current that it places
negligible stress on its filter capacitor. A single 0.1µF ceramic
capacitor was selected.
compensated, adjustments to the compensation will be
required based on actual loop measurements.
The first parameter to determine is the peak current feedback
loop gain. Since this application is low power, a resistor in
series with the source of the power switching MOSFET is used
for the current feedback signal. For higher power applications,
a resistor would dissipate too much power and current
transformer would be used instead.
Control Loop Design
The major components of the feedback control loop are a
programmable shunt regulator, an opto-coupler, and the
inverting amplifier of the ISL6721. The opto-coupler is used to
transfer the error signal across the isolation barrier. The
opto-coupler offers a convenient means to cross the isolation
barrier, but it adds complexity to the feedback control loop. It
adds a pole at about 10kHz and a significant amount of gain
variation due the Current Transfer Ratio (CTR). The CTR of the
opto-coupler varies with initial tolerance, temperature, forward
current and age.
There is limited flexibility to adjust the current loop behavior
due to the need to provide overcurrent protection. Current limit
and the current loop gain are determined by the current sense
resistor and the ISET threshold. ISET was set at 1.0V, near its
maximum, to minimize noise effects. When determining ISET,
the internal gain and offset of the ISENSE signal in the control
IC must be taken into account. The maximum peak primary
current was determined earlier to be 1.87A, so a choice of
FN9110 Rev 9.00
May 20, 2016
Page 16 of 23
ISL6721
2.25A peak primary current for current limit is reasonable. A
The ratio of R to the parallel combination of R and R
15 17
18
current gain, A , of 0.5V/A was selected to achieve this.
determine the mid band gain of the error amplifier.
EXT
R
R + R
18
(EQ. 26)
ISET = 2.25 0.8 0.5 + 0.100 = 1.00
V
15
17
-----------------------------------------------
A
=
(EQ. 40)
midband
R
R
18
17
The control to output transfer function may be represented as
Equation 27. (see reference 2):
From Equation 27, it can be seen that the control to output
transfer function frequency dependence is a function of the
output load resistance, the value of output capacitance, and
the output capacitor ESR. These variations must be considered
when compensating the control loop. The worst case small
s
------
1 +
v
R
L f
s sw
2
o
z
o
-----
----------------
= K ---------------------------------
(EQ. 27)
v
c
s
------
1 +
p
signal operating point for the converter is at minimum V
,
IN
maximum load, maximum C
OUT
and minimum ESR.
If we ignore the current feedback sampled-data effects:
The higher the desired bandwidth of the converter, the more
difficult it is to create a solution that is stable over the entire
operating range. A good rule of thumb is to limit the bandwidth
I
spkmax
-------------------------
(EQ. 28)
K =
V
cmax
to about f /4. For this example, the bandwidth will be further
sw
R
o
= Load Resistance
(EQ. 29)
(EQ. 30)
(EQ. 31)
(EQ. 32)
(EQ. 33)
(EQ. 34)
(EQ. 35)
limited due to the low GBWP of the LM431-based Error Amplifier
and the opto-coupler. A bandwidth of approximately 5kHz was
selected.
L
= Secondary Inductance
s
2
C
1
For the EA compensation, the first pole is placed at the origin
--------------------
-----------------------------
C
=
=
or
or
f
=
p
p
z
o
c
R
R C
o
by default (C is an integrating capacitor). The first zero is
o
o
o
14
placed below the crossover frequency, f , usually around 1/3
co
1
1
-------------------
-------------------------------------
=
f
z
R
C
2 R C
f
. The second pole is placed at the lower of the ESR zero or at
co
c
o
c o
one half of the switching frequency. The midband gain is then
adjusted to obtain the desired crossover frequency. If the
phase margin is not adequate, the crossover frequency may
have to be reduced.
= Output Capacitance
= Output Capacitor ESR
= Control Voltage Range
R
V
Using this technique to determine the compensation, the
following values for the EA components were selected.
cmax
The value of K may be determined by assuming all of the
output power is delivered by the 3.3V output at the threshold
of current limit. The maximum power allowed was determined
earlier as 15W, therefore:
R
R
= R = R = 1kΩ
18 15
17
20
13
14
= Open
C
C
= 100nF
= 100pF
P
out
–6
15
3.3
-----------
2
t
sw
-------
2
510
V
out
Tr
-----------------------------------
-----------------------------------------
I
=
=
= 19.5
= 2.93
A
spkmax
–6
2.3310
(EQ. 36)
1
--------------------
v
= V
A
A
CS
V
cmax
ISENSE
EXT
A
COMP
(EQ. 37)
Where A
is the external gain of the current feedback
EXT
network, A is the IC internal gain, and A
is the gain
CS COMP
between the error amplifier and the PWM comparator.
The Type 2 compensation configuration has two poles and one
zero. The first pole is at the origin, and provides the integration
characteristic which results in excellent DC regulation.
Referring to the Typical Application Schematic on page 5, the
remaining pole and zero for the compensator are located at:
C
+ C
14
1
13
------------------------------------------------------------ --------------------------------------------
f
=
(EQ. 38)
pc
2 R C C
2 R C
15 14
15
14
13
1
--------------------------------------------
f
=
(EQ. 39)
zc
2 R C
15
13
FN9110 Rev 9.00
May 20, 2016
Page 17 of 23
ISL6721
TABLE 2. OUTPUT LOAD REGULATION, V = 48V (Continued)
IN
A Bode plot of the system at low line, maximum load appears
in Figures 12 and 13.
I
(A), 3.3V
1.38
1.87
2.39
0
I
(A), 1.8V
1.05
1.05
1.05
1.55
1.55
1.55
1.55
1.55
2.07
2.07
2.07
2.07
2.62
2.62
2.62
3.14
3.14
V
(V), 3.3V
V
(V), 1.8V
OUT
OUT
OUT
OUT
3.235
1.805
50
40
30
20
10
0
3.220
3.207
3.699
3.306
3.260
3.239
3.224
3.762
3.329
3.270
3.245
3.819
3.355
3.282
3.869
3.383
1.814
1.820
1.265
1.682
1.750
1.776
1.789
1.201
1.645
1.722
1.752
1.142
1.612
1.697
1.091
1.581
-10
-20
0.39
0.88
1.38
1.87
0
-30
-40
-50
10k
100k
FREQUENCY (Hz)
FIGURE 12. MAGNITUDE
1M
10M
100M
0.39
0.88
1.38
0
200
150
100
50
0.39
0.88
0
0
-50
-100
10k
100k
1M
10M
100M
0.39
FREQUENCY (Hz)
FIGURE 13. PHASE
Waveforms
Regulation Performance
Typical waveforms can be found in Figures 14 through 16.
Figure 14 shows the steady state operation of the sawtooth
oscillator waveform at RTCT (Trace 2) the SYNC output pulse
(Trace 1) and the GATE output to the converter FET (Trace 3).
Figure 15 shows the converter behavior while operating in an
overcurrent fault condition. Trace 1 is the soft-start voltage,
which increases from 0V to 4.5V, at which point the OC fault
function is enabled. The OC condition is detected and the
soft-start capacitor is discharged to the 4.375V OC fault
threshold at which point the IC enters the fault shutdown
mode. Trace 2 shows the behavior of the timing capacitor
voltage during a shutdown fault. Most of the functions of the IC
are depowered during a fault, and the oscillator is among
those functions. During a fault, the IC is turned off until the
restart delay has timed out. After the delay, power is restored
and the IC resumes normal operation. Trace 3 is the GATE
output during the soft-start cycle and OC fault.
TABLE 2. OUTPUT LOAD REGULATION, V = 48V
IN
I
(A), 3.3V
0
I
(A), 1.8V
V
(V), 3.3V
V
(V), 1.8V
OUT
OUT
OUT
OUT
0.030
0.030
0.030
0.030
0.030
0.030
0030
0.030
0.52
3.351
1.825
0.39
0.88
1.38
1.87
2.39
2.89
3.37
0
3.281
3.251
3.223
3.204
3.185
3.168
3.153
3.471
3.283
3.254
3.233
3.218
3.203
3.191
3.619
3.290
3.254
1.956
1.988
2.014
2.029
2.057
2.084
2.103
1.497
1.800
1.836
1.848
1.855
1.859
1.862
1.347
1.730
1.785
0.39
0.88
1.38
1.87
2.39
2.89
0
0.52
Figure 16 shows the switching FET waveforms during steady
state operation. Trace 1 is drain-source voltage and Trace 2 is
gate-source voltage
0.52
0.52
0.52
0.52
0.52
1.05
0.39
0.88
1.05
1.05
FN9110 Rev 9.00
May 20, 2016
Page 18 of 23
ISL6721
NOTE:
Trace 1: SYNC Output
Trace 2: RTCT Sawtooth
Trace 3: GATE Output
NOTE:
Trace 1: VD-S
Trace 3: VG-S
FIGURE 16. GATE AND DRAIN-SOURCE WAVEFORMS
FIGURE 14. TYPICAL WAVEFORMS
References
1. Ridley, R., “A New Continuous-Time Model for Current Mode
Control”, IEEE Transactions on Power Electronics, Vol. 6, No. 2,
April 1991.
2. Dixon, Lloyd H., “Closing the Feedback Loop”, Unitrode Power
Supply Design Seminar, SEM-700, 1990.
NOTE:
Trace 1: SS
Trace 2: RTCT Sawtooth
Trace 3: GATE Output
FIGURE 15. SOFT-START WITH OVERCURRENT FAULT
.
FN9110 Rev 9.00
May 20, 2016
Page 19 of 23
ISL6721
Component List
REFERENCE DESIGNATOR
VALUE
1.0µF
DESCRIPTION
C , C , C
3
Capacitor, 1812, X7R, 100V, 20%
Capacitor, 0603, X7R, 25V, 10%
1
2
C , C
13
0.1µF
5
C
, C , C , C
560µF
470pF
0.01µF
22µF
Capacitor, Radial, SANYO 4SEP560M
Capacitor, 0603, COG, 50V, 5%
Capacitor, 0805, X7R, 50V, 10%
Capacitor, 1210, X5R, 10V, 20%
Capacitor, 0603, COG, 50V, 5%
Capacitor, Disc, Murata DE1E3KX152MA5BA01
0Ω Jumper, 0603
15 16 19 20
C
C
17
18
C
, C
21 22
C , C
100pF
1500pF
4
14
C
C
C
6
7
8
330pF
Capacitor, 0603, COG, 50V, 5%
Capacitor, 0603, X7R, 16V, 10%
Diode, Fairchild ES1C
C , C , C , C
10 11 12
0.22µF
9
C , C
R2 R6
C
, C
R4 R5
Diode, IR 12CWQ03FN
Zener, 18V, Zetex BZX84C18
Diode, Schottky, BAT54C
FET, Fairchild FDS2570
Transistor, Zetex FMMT491A
Transistor, ON MJD31C
Resistor, 1206, 1%
D
D
Q
Q
Q
1
2
1
2
3
R , R
1.00k
20.0k
10.0k
38.3k
1.00k
10
1
2
R
Resistor, 0603, 1%
10
R , R , R , R , R
11 26 27
Resistor, 0603, 1%
7
9
R
Resistor, 0603, 1%
12
R
, R , R , R , R , R
Resistor, 0603, 1%
13 15 17 18 19 25
R
R
R
R
R
Resistor, 0603, 1%
14
16
21
22
24
165
Resistor, 0603, 1%
10.0
Resistor, 1206, 1%
5.11
3.92k
100
Resistor, 0603, 1%
Resistor, 2512, 1%
R , R
Resistor, 0603, 1%
3
23
R
R
R
1.00
221k
75.0k
Resistor, 2512, 1%
4
5
6
Resistor, 0603, 1%
Resistor, 0603, 1%
R , R
OMIT
8
20
T
Transformer, MIDCOM 31555
Opto-coupler, NEC PS2801-1
Shunt Reference, National LM431BIM3
PWM, Intersil ISL6721IB
Zener, 15V, Zetex BZX84C15
1
U
U
U
2
3
4
V
R1
FN9110 Rev 9.00
May 20, 2016
Page 20 of 23
ISL6721
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
FN9110.9
CHANGE
-Updated entire datasheet to Intersil new standard.
May 20, 2016
-Feature on page 1: updated from “Adjustable Overcurrent Shutdown Delay” to “Overcurrent Shutdown
Threshold”
Ordering information table on page 2: Added ISL6721EVAL3Z.
Page 2: Added table of differences.
Pin Descriptions for ISENSE on page 10: Removed “reduced discharge current” text.
Cosmetic changes throughout datasheet.
February 16, 2016
October 21, 2015
FN9110.8
FN9110.7
Updated Ordering Information Table on page 2: Reactivated the FG “ISL6721ABZ”.
Updated Ordering Information Table on page 2.
Added Revision History and About Intersil sections.
Updated POD M16.173 from rev 1 to rev 2. Changes since rev 1: Converted to new POD format by moving
dimensions from table onto drawing and adding land pattern. No dimension changes.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2003-2016. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9110 Rev 9.00
May 20, 2016
Page 21 of 23
ISL6721
Package Outline Drawing
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 2, 5/10
A
1
3
5.00 ±0.10
SEE DETAIL "X"
9
16
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
0.20 C B A
1
8
B
0.09-0.20
0.65
TOP VIEW
END VIEW
1.00 REF
-
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
GAUGE
PLANE
0.25 +0.05/-0.06
0.25
5
0.10
C B A
M
0.10 C
0°-8°
0.60 ±0.15
0.05 MIN
0.15 MAX
SIDE VIEW
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
(5.65)
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
is 0.07mm.
(0.65 TYP)
(0.35 TYP)
6. Dimension in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
7. Conforms to JEDEC MO-153.
FN9110 Rev 9.00
May 20, 2016
Page 22 of 23
ISL6721
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
N
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
0.0688
0.0098
0.020
MIN
1.35
0.10
0.33
0.19
9.80
3.80
MAX
NOTES
-B-
A
A1
B
0.0532
0.0040
0.013
1.75
0.25
0.51
0.25
10.00
4.00
-
-
1
2
3
L
9
SEATING PLANE
A
C
0.0075
0.3859
0.1497
0.0098
0.3937
0.1574
-
-A-
D
E
3
h x 45°
D
4
-C-
e
0.050 BSC
1.27 BSC
-
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
H
e
A1
C
5
h
L
B
0.10(0.004)
6
0.25(0.010) M
C
A M B S
N
16
16
7
0°
8°
0°
8°
-
NOTES:
Rev. 1 6/05
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
FN9110 Rev 9.00
May 20, 2016
Page 23 of 23
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