ISL6265CHRTZ_技术文档

DATASHEET

ISL6265C

FN6976

Rev 2.00

January 11, 2013

Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable

Mobile CPUs

The ISL6265C is a multi-output controller with embedded gate

Features

drivers. A single-phase controller powers the Northbridge

• Core Configuration Flexibility

(VDDNB) portion of the CPU. The two remaining controller

channels can be configured for two-phase or individual

single-phase outputs. For uniplane CPU applications, the

ISL6265C is configured as a two-phase buck converter. This

allows the controller to interleave channels to effectively double

the output voltage ripple frequency, and thereby reduce output

voltage ripple amplitude with fewer components, lower

component cost, reduced power dissipation, and smaller area.

For dual-plane processors, the ISL6265C can be configured as

independent single-phase controllers powering VDD0 and

VDD1.

- Dual Plane, Single-Phase Controllers

- Uniplane, Two-Phase Controller

• Precision Voltage Regulators

- 0.5% System Accuracy Over-temperature

• Voltage Positioning with Adjustable Load Line and Offset

• Internal Gate Drivers with 2A Driving Capability

• Differential Remote CPU Die Voltage Sensing

• Core Differential Current Sensing: DCR or Resistor

• Northbridge Lossless r_DS(ON)Current Sensing

The heart of the ISL6265C is the patented R³Technology™,

Intersil’s Robust Ripple Regulator modulator. Compared with

the traditional buck regulator, the R³Technology has a faster

transient response. This is due to the R³modulator

commanding variable switching frequency during a load

transient.

• Serial VID Interface

- Two Wire Clock and Data Bus

- Supports High-Speed I²C

- 0.500V to 1.55V in 12.5mV Steps

- Supports PSI_L Power-Saving Mode

The Serial VID Interface (SVI) allows dynamic adjustment of

the Core and Northbridge output voltages independently and in

combination from 0.500V to 1.55V. Core and Northbridge

output voltages achieve a 0.5% system accuracy

over-temperature.

• Core Outputs Feature Phase Shedding with PSI_L

• Adjustable Output-Voltage Offset

• Digital Soft-Start of all Outputs

A unity-gain differential amplifier is provided for remote CPU

die sensing. This allows the voltage on the CPU die to be

accurately regulated per AMD mobile CPU specifications. Core

output current sensing is realized using lossless inductor DCR

sensing. All outputs feature overcurrent, overvoltage and

undervoltage protection.

• User Programmable Switching Frequency

• Static and Dynamic Current Sharing (Uniplane Core)

• Overvoltage, Undervoltage, and Overcurrent Protection

• Pb-Free (RoHS compliant)

Applications

• AMD Griffin Platform CPU

Related Literature

• See FN6884 for “Multi-Output Controller with Integrated

MOSFET Drivers for AMD SVI Capable Mobile CPUs”

• Notebook Core/GPU Voltage Regulators

POWER

STAGE

CORE_0

CORE_1

POWER

STAGE

ISL6265C

POWER

STAGE

FIGURE 1. SIMPLIFIED SYSTEM DIAGRAM

FN6976 Rev 2.00

January 11, 2013

Page 1 of 27

ISL6265C

Functional Block Diagram

COMP_NB

RTN_NB

FB_NB

FSET_NB

VSEN_NB

PVCC

I

FSET_NB

VNB

BOOT_NB

UGATE_NB

PHASE_NB

LGATE_NB

1

3.0kΩ

FLT

1.5kΩ

SVC

SVD

MOSFET

DRIVER

NO DROOP

PSI_L

MODULATOR

NB

E/A

SHOOT-THRU

PROTECTION

I_OFS

PWROK

VREF_NB

VREF0

VREF_NB

DE MODE

PGND_NB

VIN

VREF1

OFS/FIXEN

PSI_L

PVCC

VCC

POWER-ON

ENABLE

RESET AND

SOFT-START

LOGIC

OCSET_NB

OCSET

RBIAS

FLT

VNB

V0

PGOOD

GND

FAULT

PROTECTION

RTN1

V1

ISEN0

MODE

ISEN1

VIN

VW0

PVCC

I

VW0

COMP0

FB0

BOOT0

UGATE0

PHASE0

LGATE0

FLT

E/A

I_OFS

MOSFET

DRIVER

VDIFF0

VSEN0

RTN0

VREF0

SHOOT-THRU

PROTECTION

VIN

V0

1



DE MODE

PGND0

NO

DROOP

MODE

ISEN0

ISEN1

MODULATOR

CORE

PSI_L

ISP0

ISN0

CURRENT

SENSE

PVCC

FLT

MODE

NO

CURRENT

BALANCE

BOOT1

UGATE1

PHASE1

LGATE1

ISP1

ISN1

CURRENT

SENSE

DROOP

MOSFET

DRIVER

MODE

V1

VSEN1

RTN1

SHOOT-THRU

PROTECTION

1



VREF1

DE MODE

PGND1

E/A

VDIFF1

I_OFS

PSI_L

I

VW1

FB1

COMP1

VW1

FIGURE 2. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL6265C

FN6976 Rev 2.00

January 11, 2013

Page 2 of 27

ISL6265C

Ordering Information

PART

MARKING

TEMP RANGE

(°C)

PACKAGE

(Pb-Free)

PART NUMBER (Notes 2, 3)

PKG. DWG. #

L48.6x6

ISL6265CHRTZ

6265C HRTZ

-10 to +100

48 Ld 6x6 TQFN

ISL6265CHRTZ-T (Note 1)

48 Ld 6x6 TQFN

Tape and Reel

L48.6x6

ISL6265CIRTZ

6265C IRTZ

-40 to +100

48 Ld 6x6 TQFN

L48.6x6

ISL6265CIRTZ-T (Note 1)

48 Ld 6x6 TQFN

Tape and Reel

NOTES:

1. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6265C. For more information on MSL please see techbrief TB363.

Pin Configuration

ISL6265C

(48 LD TQFN)

TOP VIEW

48 47 46 45 44 43 42 41 40 39 38 37

BOOT_NB

BOOT0

UGATE0

PHASE0

PGND0

LGATE0

PVCC

OFS/VFIXEN

PGOOD

PWROK

SVD

1

2

3

4

5

6

7

8

9

36

35

34

33

32

31

30

29

28

27

26

25

SVC

49

GND

[BOTTOM]

ENABLE

RBIAS

LGATE1

PGND1

PHASE1

UGATE1

BOOT1

OCSET

VDIFF0

FB0 10

COMP0 11

VW0 12

13 14 15 16 17 18 19 20 21 22 23 24

FN6976 Rev 2.00

January 11, 2013

Page 3 of 27

ISL6265C

Pin Descriptions

PIN(s)

SYMBOL(s)

DESCRIPTION

1

OFS/VFIXEN

A resistor from this pin to GND programs a DC current source, which generates a positive offset voltage

across the resistor between FB and VDIFF pins. In this case, the OFS pin voltage is +1.2V and VFIX mode

is not enabled. If OFS is pulled up to +3.3V, VFIX mode is enabled, the DAC decodes the SVC and SVD

inputs to determine the programmed voltage, and the OFS function is disabled. If OFS is pulled up to +5V,

the OFS function and VFIX mode are disabled.

2

3

PGOOD

PWROK

Controller power-good open-drain output. This pin is typically pulled up externally by a 2.0kΩ resistor to

+3.3V. During normal operation, this pin indicates whether all output voltages are within specified

overvoltage and undervoltage limits and no overcurrent condition is present. If any output voltage

exceeds these limits or a reset event occurs, the pin is pulled low. This pin is always low prior to the end

of soft-start.

System power good input. When this pin is high, the SVI interface is active and I²C protocol is running.

While this pin is low, the SVC, SVD, and VFIXEN input states determine the pre-PWROK metal VID or VFIX

mode voltage. This pin must be low prior to the ISL6265C PGOOD output going high per the AMD SVI

Controller Guidelines.

4

5

6

7

SVD

SVC

This pin is the serial VID data bidirectional signal to and from the master device on the AMD processor.

This pin is the serial VID clock input from the AMD processor.

ENABLE

RBIAS

Digital input enable. A high level logic signal on this pin enables the ISL6265C.

A 117kΩ resistor from RBIAS to GND sets internal reference currents. The addition of capacitance to this

pin must be avoided and can create instabilities in operation.

8

OCSET

CORE_0 and CORE_1 common overcurrent protection selection input. The voltage on this pin sets the

(ISPx - ISNx) voltage limit for OC trip.

9, 19

VDIFF0, VDIFF1

FB0, FB1

Output of the CORE_0 and CORE_1 differential amplifiers.

10, 20

These pins are the output voltage feedback to the inverting input of the CORE_0 and CORE_1 error

amplifiers.

11, 21

12, 22

COMP0, COMP1

VW0, VW1

The output of the CORE_0 and CORE_1 controller error amplifiers respectively. FBx, VDIFFx, and COMPx

pins are tied together through external R-C networks to compensate the regulator

A resistor from this pin to corresponding COMPx pin programs the switching frequency (for example,

6.81k ~ 300kHz).

13, 14, 23, 24

ISP0, ISN0, ISP1, ISN1 These pins are used for differentially sensing the corresponding channel output current. The sensed

current is used for channel balancing, protection, and core load line regulation.

Connect ISN0 and ISN1 to the node between the RC sense elements surrounding the inductor of their

respective channel. Tie the ISP0 and ISP1 pins to the VCORE side of their corresponding channel’s sense

capacitor. These pins can also be used for discrete resistor sensing.

15, 16

18, 17

VSEN0, RTN0

VSEN1, RTN1

Inputs to the CORE_0 VR controller precision differential remote sense amplifier. Connect to the sense

pins of the VDD0_FB[H,L] portion of the processor.

Inputs to the CORE_1 VR controller precision differential remote sense amplifier. Connect to the sense

pins of the VDD1_FB[H,L] portion of the processor. The RTN1 pin is also used for detection of the

VDD_PLANE_STRAP signal prior to enable.

30

PVCC

The power supply pin for the internal MOSFET gate drivers of the ISL6265C. Connect this pin to a +5V

power supply. Decouple this pin with a quality 1.0µF ceramic capacitor.

31, 29

32, 28

LGATE0, LGATE1

PGND0, PGND1

Connect these pins to the corresponding lower MOSFET gate(s).

The return path of the lower gate driver for CORE_0 and CORE_1 respectively. Connect these pins to the

corresponding sources of the lower MOSFETs.

33, 27

34, 26

35, 25

PHASE0, PHASE1

UGATE0, UGATE1

BOOT0, BOOT1

Switch node of the CORE_0 and CORE_1 controllers. Connect these pins to the sources of the

corresponding upper MOSFET(s). These pins are the return path for the upper MOSFET drives.

Connect these pins to the corresponding upper MOSFET gate(s). These pins control the upper MOSFET

gate(s) and are monitored for shoot-through prevention.

These pins provide the bias voltage for the corresponding upper MOSFET drives. Connect these pins to

appropriately chosen external bootstrap capacitors. Internal bootstrap diodes connected to the PVCC pin

provide the necessary bootstrap charge.

FN6976 Rev 2.00

January 11, 2013

Page 4 of 27

ISL6265C

Pin Descriptions(Continued)

PIN(s)

SYMBOL(s)

DESCRIPTION

36

BOOT_NB

This pin is the upper gate drive supply voltage for the Northbridge controller. Connect an appropriately

sized ceramic bootstrap capacitor between the BOOT_NB and PHASE_NB pins. An internal bootstrap

diode connected to the PVCC pin provides the necessary bootstrap charge.

37

38

UGATE_NB

PHASE_NB

Upper MOSFET gate signal from Northbridge controller.

Switch node of the Northbridge controller. This pin should connect to the source of the Northbridge

channel upper MOSFET(s).

39

40

LGATE_NB

PGND_NB

Lower MOSFET gate signal from Northbridge controller.

The return path of the Northbridge controller lower gate driver. Connect this pin to the source of the lower

MOSFET(s).

41

43, 42

44

OCSET_NB

VSEN_NB, RTN_NB

FSET_NB

Overcurrent protection selection input for the Northbridge controller. A resistor from this pin to

PHASE_NB sets the OC trip point.

Remote Northbridge voltage sense input and return. Connect isolated traces from these pins to the

Northbridge sense points of the processor.

A resistor from this pin to GND programs the switching frequency of the Northbridge controller (for

example, 22.1k ~ 260kHz).

45

46

47

COMP_NB

FB_NB

VCC

This pin is the output of the Northbridge controller error amplifier.

This pin is the output voltage feedback to the inverting input of the Northbridge controller error amplifier.

The bias supply for the IC’s control circuitry. Connect this pin to a +5V supply and decouple using a quality

0.1µF ceramic capacitor.

48

-

VIN

Battery supply voltage. It is used for input voltage feed-forward to improve the input line transient

performance.

GND

The bias and reference ground for the IC. The GND connection for the ISL6265C is through the thermal

pad on the bottom of the package.

FN6976 Rev 2.00

January 11, 2013

Page 5 of 27

ISL6265C

Simplified Application Circuit for Dual Plane and Northbridge Support

VIN

+5V

VIN

VCC

PVCC

GND

+VIN

SVI DATA

SVI CLOCK

ENABLE

SVD

C

IN

SVC

EN

UGATE0

PWROK

PGOOD

BOOT0

PHASE0

LGATE0

L

OUT

VDD0

VDDPWRGD

VSEN0

RTN0

REMOTE

SENSE

CORE

LOAD

PGND0

ISP0

VSEN1

RTN1

REMOTE

SENSE

ISN0

VDD_PLANE_STRAP

RBIAS

OFS/VFIXEN

VDIFF0

OCSET

+VIN

C

IN

FB0

UGATE1

BOOT1

ISL6265C

COMP0

L

OUT

VDD1

PHASE1

LGATE1

VW0

CORE

LOAD

PGND1

ISP1

VDIFF1

ISN1

+VIN

FB1

C

IN

COMP1

UGATE_NB

BOOT_NB

PHASE_NB

LGATE_NB

PGND_NB

L

OUT

VDDNB

VW1

FSET_NB

NB

LOAD

COMP_NB

FB_NB

OCSET_NB

VSEN_NB

RTN_NB

FIGURE 3. ISL6265C BASED DUAL-PLANE AND NORTHBRIDGE CONVERTERS WITH INDUCTOR DCR CURRENT SENSING

FN6976 Rev 2.00

January 11, 2013

Page 6 of 27

ISL6265C

Simplified Application Circuit for Uniplane Core and Northbridge Support

VIN

+5V

+VIN

VCC

PVCC

GND

C

L

IN

SVI DATA

SVI CLOCK

ENABLE

SVD

UGATE0

SVC

EN

BOOT0

PHASE0

LGATE0

OUT

PWROK

PGOOD

VDDPWRGD

CORE

LOAD

PGND0

ISP0

VSEN0

RTN0

REMOTE

SENSE

ISN0

REMOTE

SENSE

VSEN1

RTN1

VDD_PLANE_STRAP

RBIAS

OCSET

VDD0

OFS/VFIXEN

VDIFF0

+VIN

C

IN

UGATE1

BOOT1

FB0

L

OUT

ISL6265C

COMP0

PHASE1

LGATE1

CORE

LOAD

PGND1

ISP1

VW0

VDIFF1

OPEN

ISN1

+VIN

OPEN

FB1

C

IN

COMP1

UGATE_NB

BOOT_NB

PHASE_NB

LGATE_NB

PGND_NB

L

OUT

VDDNB

OPEN VW1

FSET_NB

NB

LOAD

OCSET_NB

VSEN_NB

RTN_NB

COMP_NB

FB_NB

FIGURE 4. ISL6265C BASED UNIPLANE AND NORTHBRIDGE CONVERTERS WITH INDUCTOR DCR CURRENT SENSING

FN6976 Rev 2.00

January 11, 2013

Page 7 of 27

ISL6265C

Simplified Application Circuit for Dual Layout

VIN

+5V

+VIN

VCC PVCC

GND

C

L

IN

SVI DATA

SVI CLOCK

ENABLE

SVD

UGATE0

SVC

EN

BOOT0

PHASE0

LGATE0

OUT

PWROK

PGOOD

PWROK

VDD0

VDDPWRGD

CORE

LOAD

PGND0

ISP0

VSEN0

RTN0

REMOTE

SENSE

VDD_PLANE_STRAP

+1.8V

ISN0

RTN1

REMOTE

SENSE

DNP UNIPLANE

VSEN1

RBIAS

DNP

UNIPLANE

VDD0

DUAL

OCSET

PLANE

OFS/VFIXEN

VDIFF0

+VIN

C

IN

UGATE1

BOOT1

FB0

L

OUT

ISL6265C

COMP0

PHASE1

LGATE1

VDD1

CORE

LOAD

PGND1

ISP1

VW0

VDIFF1

ISN1

+VIN

FB1

C

IN

COMP1

UGATE_NB

BOOT_NB

PHASE_NB

LGATE_NB

PGND_NB

L

OUT

VDDNB

VW1

FSET_NB

NB

LOAD

OCSET_NB

VSEN_NB

RTN_NB

COMP_NB

FB_NB

FIGURE 5. ISL6265C BASED UNIPLANE OR DUAL PLANE CORE CONVERTER WITH INDUCTOR DCR CURRENT SENSING

FN6976 Rev 2.00

January 11, 2013

Page 8 of 27

ISL6265C

Table of Contents

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

ISL6265C Gate Driver Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Core Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Serial VID Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Pre-PWROK Metal VID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

VFIX MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

SVI MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

VID-On-the-Fly Transition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

SVI WIRE Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

SVI Bus Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Current Sense. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Selecting RBIAS For Core Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Offset Resistor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Internal Driver Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

MOSFET Gate-Drive Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Diode Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Power-Savings Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Northbridge and Dual Plane Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Uniplane Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Fault Monitoring and Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Power-Good Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

General Application Design Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Selecting the LC Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Selection of the Input Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

MOSFET Selection and Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Selecting The Bootstrap Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PCB Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Power and Signal Layers Placement on the PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Signal Ground and Power Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Routing and Connection Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Copper Size for the Phase Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

FN6976 Rev 2.00

January 11, 2013

Page 9 of 27

ISL6265C

P

Absolute Maximum Ratings

Thermal Information

Supply Voltage, VCC, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 - +7V

Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V

Boot Voltage (BOOT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V

Boot to Phase Voltage (BOOT-PHASE) . . . . . . . . . . . . . . . . -0.3V to +7V(DC)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +9V (<10ns)

Phase Voltage (PHASE) . . . . . . . . . . . . . . . . -7V (<20ns Pulse Width, 10µJ)

UGATE Voltage (UGATE) . . . . . . . . . . . . . . . . . . . PHASE -0.3V (DC) to BOOT

LGATE Voltage (LGATE) . . . . . . . . . . . . . . . . . . . . . -0.3V (DC) to VCC + 0.3V

ALL Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to (VCC + 0.3V)

Open Drain Outputs, PGOOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 - +7V

Thermal Resistance (Typical)

TQFN Package (Notes 4, 5) . . . . . . . . . . . . .

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp



_JA(°C/W)

28



_JC(°C/W)

3.5

Recommended Operating Conditions

Supply Voltage, VCC, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%

Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V to 24V

Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4. _JAis measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

Brief TB379.

5. For _JC, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications VCC = PVCC = 5V, V_IN= 12V, T_A= -10°C to +100°C (ISL6265HRTZ), T_A= -40°C to +100°C (ISL6265IRTZ),

unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +100°C.

MIN

MAX

PARAMETER

INPUT POWER SUPPLY

+5V Supply Current

SYMBOL

I_VCC

TEST CONDITIONS

(Note 6)

TYP

(Note 6)

UNITS

EN = 3.3V

EN = 0V

-

7.8

10

1

mA

µA

V

-

4.35

4.1

-

POR (Power-On Reset) Threshold

VCC POR_r

VCC POR_f

I_VIN

VCC Rising

VCC Falling

-

3.9

-

4.5

-

V

Battery Supply Current (V_IN)

SYSTEM AND REFERENCES

System Accuracy

EN = 0V, VIN = 24V

1

µA

HRTZ

No load, closed loop, active mode

VID = 0.75V to 1.55V

-0.5

-

0.5

%

(V_core0,V_core1,V_{core_NB}

)

%Error

VID = 0.50V to 0.7375V

-5

-

+5

mV

%

(V_CORE

)

IRTZ

No load, closed loop, active mode

VID = 0.75V to 1.55V

-0.8

0.8

%Error

VID = 0.50V to 0.7375V

-8

-

+8

mV

V

(V_CORE

)

RBIAS Voltage

HRTZ

R_RBIAS= 117kΩ

1.15

1.17

1.19

R_RBIAS

IRTZ

R_RBIAS

R_RBIAS= 117kΩ

1.14

1.17

1.55

1.20

V

Maximum Output Voltage

Minimum Output Voltage

V_COREx

(max)

SVID = [000_0000b]

SVID = [101_0100b]

-

V_COREx

(min)

0.500

FN6976 Rev 2.00

January 11, 2013

Page 10 of 27

ISL6265C

Electrical Specifications VCC = PVCC = 5V, V_IN= 12V, T_A= -10°C to +100°C (ISL6265HRTZ), T_A= -40°C to +100°C (ISL6265IRTZ),

unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +100°C. (Continued)

MIN

MAX

PARAMETER

SYMBOL

TEST CONDITIONS

(Note 6)

TYP

300

(Note 6)

UNITS

kHz

CHANNEL FREQUENCY

Nominal CORE Switching Frequency

HRTZ

f_{SW_core0}

V_IN= 15.5V, V_DAC= 1.55V, V_FB0= 1.60V,

force V_{comp_0}= 2V, R_VW= 6.81kΩ, 2-Phase

Operation

285

315

IRTZ

f_{SW_core0}

V_IN= 15.5V, V_DAC= 1.55V, V_FB0= 1.60V,

force V_{comp_0}= 2V, R_VW= 6.81kΩ, 2-Phase

Operation

280

300

320

kHz

Nominal NB Switching Frequency

HRTZ

f_{SW_core_NB}

R_{FSET_NB}= 22.1kΩ, C_{FSET_NB}= 1nF,

285

300

315

kHz

V

_DAC= 0.5V, V_{sen_nb}= 0.51V

R_{FSET_NB}= 22.1kΩ, C_{FSET_NB}= 1nF,

_DAC= 0.5V, V_{sen_nb}= 0.51V

IRTZ

f_{SW_core_NB}

280

320

V

Core Frequency Adjustment Range

NB Frequency Adjustment Range

AMPLIFIERS

200

-

500

kHz

Error Amp DC Gain (Note 7)

A_V0

-

90

18

-

dB

Error Amp Gain-Bandwidth Product

(Note 7)

GBW

C_L= 20pF

MHz

Error Amp Slew Rate (Note 7)

CORE CURRENT SENSE

Current Imbalance Threshold

Input Bias Current

SR

-

5.0

-

V/µs

-

4

-

mV

nA

V

20

0.8

RTN1 Threshold

SOFT START/VID-ON-THE-FLY

Soft-Start Voltage Transition

VID on the Fly Transition

V_SS

1.25

5

1.875

7.5

2.50

10

mV/µs

GATE DRIVER DRIVING CAPABILITY [CORE AND NB]

UGATE Source Resistance (Note 8)

UGATE Source Current (Note 8)

UGATE Sink Resistance (Note 8)

UGATE Sink Current (Note 8)

LGATE Source Resistance (Note 8)

LGATE Source Current (Note 8)

LGATE Sink Resistance (Note 8)

LGATE Sink Current (Note 8)

UGATE to PHASE Resistance

R_SRC(UGATE)500mA Source Current

I_SRC(UGATE)V_{UGATE_PHASE}= 2.5V

R_SNK(UGATE)500mA Sink Current

I_SNK(UGATE)V_{UGATE_PHASE}= 2.5V

R_SRC(LGATE)500mA Source Current

I_SRC(LGATE)V_LGATE= 2.5V

R_SNK(LGATE)500mA Sink Current

I_SNK(LGATE)V_LGATE= 2.5V

R_p(UGATE)

-

1

2

1.5

Ω

A

-

1

1.5

Ω

A

2

-

1

1.5

Ω

A

2

-

0.5

4

0.9

Ω

A

-

1

kΩ

GATE DRIVER SWITCHING TIMING (Refer to “ISL6265C Gate Driver Timing Diagram” on page 13)

UGATE Rise Time (Note 7)

LGATE Rise Time (Note 7)

UGATE Fall Time (Note 7)

t_RU

t_RL

PV_CC= 5V, 3nF Load

-

8.0

4.0

36

-

ns

PV_CC= 5V, 3nF Load

t_FU

PV_CC= 5V, 3nF Load

LGATE Fall Time (Note 7)

t_FL

PV_CC= 5V, 3nF Load

UGATE Turn-on Propagation Delay

LGATE Turn-on Propagation Delay

t_PDHU

t_PDHL

PV_CC= 5V, Outputs Unloaded

20

FN6976 Rev 2.00

January 11, 2013

Page 11 of 27

ISL6265C

Electrical Specifications VCC = PVCC = 5V, V_IN= 12V, T_A= -10°C to +100°C (ISL6265HRTZ), T_A= -40°C to +100°C (ISL6265IRTZ),

unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +100°C. (Continued)

MIN

MAX

PARAMETER

BOOTSTRAP DIODE

SYMBOL

TEST CONDITIONS

(Note 6)

TYP

(Note 6)

UNITS

Forward Voltage

HRTZ

IRTZ

V_DDP= 5V, Forward Bias Current = 2mA

V_R= 16V

0.43

-

0.58

-

0.67

0.70

5

V

Leakage

µA

POWER-GOOD AND PROTECTION MONITOR

PGOOD Low Voltage

V_OL

I_PGOOD= 4mA

-

0.2

-

0.5

1

V

PGOOD Leakage Current

PGOOD High After Soft-Start

PGOOD Low After Fault

Undervoltage Threshold

I_OH

P_GOOD= 5V

-1

µA

µs

mV

Enable to PGOOD High, V_COREx= 1.1V

Fault to PGOOD Low

570

160

240

700

208

295

1010

250

350

HRTZ

U_VH

V_CORExfalls below set-point for 208µs

IRTZ

U_VH

V_CORExfalls below set-point for 208µs

V_Orising above threshold > 0.5µs

230

295

350

mV

V

Overvoltage Threshold

O_VHS

1.770

1.800

1.825

OVERCURRENT PROTECTION VDD0 AND VDD1

OCSET Reference Voltage

V_OCSET= 180mV; VIN = 15.5V

5

6.0

7

mV

(V_ISPx- V_ISNx

)

OVERCURRENT PROTECTION VDD_NB

OCSET_NB OCP Current

HRTZ

IRTZ

RBIAS pin to GND = 117kΩ; Trips after 8 PWM

cycles

9.2

10

10.8

µA

RBIAS pin to GND = 117kΩ; Trips after 8 PWM

9.2

10.9

cycles

OFFSET FUNCTION

OFS Pin Voltage For Droop Enabling

HRTZ

V_OFS

R_OFS= 240kΩ (OFS pin to GND)

I_OFS= =10µA

1.18

1.2

1.22

V

IRTZ

V_OFS

1.17

1.23

FB Pin Source Current

I_FB

9.0

9.9

1.8

10.8

µA

V

OFS Pin Voltage Threshold for VFIX

Mode and No Droop Operation

V_OFS

-

OFS Pin Voltage Threshold for SVI

Mode and No Droop Operation

V_OFS

I_OFS

-

4.0

-

V

OFS Bias

1.8V < OFS < VCC

µA

LOGIC INPUTS

ENABLE Low Threshold

ENABLE High Threshold

ENABLE Leakage Current

V_IL(3.3V)

V_IH(3.3V)

-

2.0

-1

-

1.35

1.6

0

0.9

V

-

Logic input is low

µA

Logic input is high at 3.3V

0

1

SVI INTERFACE

PWROK Input Low Threshold

PWROK Input High Threshold

SVC, SVD Input HIGH (VIH)

SVC, SVD Input LOW (VIL)

Schmitt Trigger Input Hysteresis

-

0.65

0.9

0.8

V

-

1.05

0.87

0.68

0.19

-

0.45

-

FN6976 Rev 2.00

January 11, 2013

Page 12 of 27

ISL6265C

Electrical Specifications VCC = PVCC = 5V, V_IN= 12V, T_A= -10°C to +100°C (ISL6265HRTZ), T_A= -40°C to +100°C (ISL6265IRTZ),

unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +100°C. (Continued)

MIN

MAX

PARAMETER

SVD Low Level Output Voltage

SVC, SVD Leakage

SYMBOL

TEST CONDITIONS

3mA Sink Current

(Note 6)

TYP

0.1

(Note 6)

UNITS

V

-

0.285

EN = 0V, SVC, SVD = 0V

EN = 5V, SVC, SVD = 1.8V

< -100

-

nA

DIFF AMP

Accuracy

HRTZ

IRTZ

VSEN = 0.5V to 1.55V; RTN = 0 ±0.1V

-2

-

2

mV

-2.5

2.5

NOTES:

6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested

7. Limits should be considered typical and are not production tested.

8. Limits established by characterization and are not production tested.

ISL6265C Gate Driver Timing Diagram

PWM

t

PDHU

t

FU

t

RU

1V

UGATE

LGATE

1V

t

FL

RL

t

PDHL

FN6976 Rev 2.00

January 11, 2013

Page 13 of 27

ISL6265C

A window voltage V_Wis referenced with respect to the error

amplifier output voltage V_COMP, creating an envelope into which

the ripple voltage V_Ris compared. The amplitude of V_Wis set by a

resistor connected across the FSET and GND pins. The V_R,V_COMP,

and V_Wsignals feed into a window comparator in which V_COMPis

the lower threshold voltage and V_Wis the higher threshold

voltage. Figure 7 shows PWM pulses being generated as V_R

traverses the V_Wand V_COMPthresholds. The PWM switching

frequency is proportional to the slew rates of the positive and

negative slopes of V_R;it is inversely proportional to the voltage

Theory of Operation

The ISL6265C is a flexible multi-output controller supporting

Northbridge and single or dual power planes required by Class M

AMD Mobile CPUs. In single plane applications, both core voltage

regulators operate single-phase. In uniplane core applications,

the core voltage regulators are configured to operate as a

two-phase regulator. All three regulator outputs include

integrated gate drivers for reduced system cost and small board

area. The regulators provide optimum steady-state and transient

performance for microprocessor applications. System efficiency

is enhanced by idling a phase in uniplane configurations at low-

current and implementing automatic DCM-mode operation when

PSI_L is asserted to logic low.

between V_Wand V_COMP

.

VIN

The heart of the ISL6265C is the R³Technology™, Intersil's

Robust Ripple Regulator modulator. The R³modulator combines

the best features of fixed frequency PWM and hysteretic PWM

while eliminating many of their shortcomings. The ISL6265C

modulator internally synthesizes an analog of the inductor ripple

current and uses hysteretic comparators on those signals to

establish PWM pulse widths. Operating on these large-

amplitude, noise-free synthesized signals allows the ISL6265C to

achieve lower output ripple and lower phase jitter than either

conventional hysteretic or fixed frequency PWM controllers.

Unlike conventional hysteretic converters, the ISL6265C has an

error amplifier that allows the controller to maintain a 0.5%

voltage regulation accuracy throughout the VID range from 0.75V

to 1.55V. Voltage regulation accuracy is slightly wider, ±5mV,

over the VID range from 0.7375V to 0.5V.

PWM FREQUENCY

CONTROL

FSET

-

+

g

+

V

m

IN

W

-

+

R

Q

S

PWM

V

VO

R

-

+

g V

-

m

O

V

COMP

+

-

+

C

R TO

PWM

CONTROL

ISL6265C

FIGURE 6. MODULATOR CIRCUITRY

The hysteresis window voltage is relative to the error amplifier

output such that load current transients result in increased

switching frequency, which gives the R³regulator a faster

response than conventional fixed frequency PWM controllers. In

uniplane configurations, transient load current is inherently

shared between active phases due to the use of a common

hysteretic window voltage. Individual average phase currents are

monitored and controlled to equally share current among the

active phases.

RIPPLE CAPACITOR VOLTAGE C

WINDOW VOLTAGE V

W

R

ERROR AMPLIFIER VOLTAGE V

COMP

Modulator

PWM

The ISL6265C modulator features Intersil’s R³technology, a

hybrid of fixed frequency PWM control and variable frequency

hysteretic control (see Figure 6). Intersil’s R³technology can

simultaneously affect the PWM switching frequency and PWM

duty cycle in response to input voltage and output load

transients. The R³modulator synthesizes an AC signal V_R, which

is an analog representation of the output inductor ripple current.

The duty-cycle of V_Ris the result of charge and discharge current

through a ripple capacitor C_R. The current through C_Ris provided

by a transconductance amplifier g_mthat measures the VIN and

VO voltages. The positive slope of V_Rcan be written as

determined by Equation 1:

FIGURE 7. MODULATOR WAVEFORMS DURING LOAD TRANSIENT

Initialization

Once sufficient bias is applied to the VCC pin, internal logic

checks the status of critical pins to determine the controller

operation profile prior to ENABLE. These pins include RTN1 which

determines single vs two-phase operation and OFS/VFIXEN for

enabling/disabling the SVI interface and core voltage droop.

Depending on the configuration set by these pins, the controller

then checks the state of the SVC and SVD pins to determine the

soft-start target output voltage level.

(EQ. 1)

V

= g   V – V



OUT

RPOS

m

IN

The negative slope of V_Rcan be written as determined by

Equation 2:

(EQ. 2)

V

= g  V

m OUT

RNEG

Where g_mis the gain of the transconductance amplifier.

FN6976 Rev 2.00

January 11, 2013

Page 14 of 27

ISL6265C

Power-On Reset

Mode Selection

The ISL6265C requires a +5V input supply tied to VCC and PVCC

to exceed a rising power-on reset (POR) threshold before the

controller has sufficient bias to guarantee proper operation. Once

this threshold is reached or exceeded, the ISL6265C has enough

bias to begin checking RTN1, OFS/VFIXEN, ENABLE, and SVI

inputs. Hysteresis between the rising the falling thresholds

assure the ISL6265C will not inadvertently turn-off unless the

bias voltage drops substantially (see “Electrical Specifications”

on page 12).

The OFS/VFIXEN pin selects between the AMD defined VFIX and

SVI modes of operation and enables droop if desired in SVI mode

only. If OFS/VFIXEN is tied to VCC, then SVI mode with no droop

on the core output(s) is selected. Connected to +3.3V, VFIX mode

is active with no droop on the core output(s). SVI mode with

droop is enabled when OFS/VFIXEN is tied to ground through a

resistor sized to set the core voltage positive offset. Further

information is provided in “Offset Resistor Selection” on page 20.

Serial VID Interface

Core Configuration

The on-board Serial VID Interface (SVI) circuitry allows the

processor to directly control the Core and Northbridge voltage

reference levels within the ISL6265C. The SVC and SVD states

are decoded according to the PWROK and VFIXEN inputs as

described in the following sections. The ISL6265C uses a

digital-to-analog converter (DAC) to generate a reference voltage

based on the decoded SVI value. See Figure 8 for a simple SVI

interface timing diagram.

The ISL6265C determines the core channel requirements of the

CPU based on the state of the RTN1 pin prior to ENABLE. If RTN1

is low prior to ENABLE, both VDD0 and VDD1 core planes are

required. The core controllers operate as independent

single-phase regulators. RTN1 is connected to the CPU Core1

negative sense point. For single core CPU designs (uniplane),

RTN1 is tied to a +1.8V or greater supply. Prior to ENABLE, RTN1

is detected as HIGH and the ISL6265C drives the core controllers

as a two-phase multi-phase regulator. Dual purpose motherboard

designs should include resistor options to open the CPU Core1

negative sense and connect the RTN1 pin to a pull-up resistor.

1

4

5

6

2

3

7

8

9

10

11

12

VCC

SVC

SVD

ENABLE

PWROK

V_SVI

METAL_VID

VDD AND VDDNB

VDDPWRGD

(PGOOD)

FIXEN

Interval 1 to 2: ISL6265C waits to POR.

Interval 2 to 3: SVC and SVD are externally set to pre-Metal VID code.

Interval 3 to 4: EN locks core output configuration and pre-Metal VID code. All outputs soft-start to this level.

Interval 4 to 5: PGOOD signal goes HIGH indicating proper operation.

Interval 5 to 6: CPU detects VDDPWRGD high and drives PWROK high to allow ISL6265C to prepare for SVI code.

Interval 6 to 7: SVC and SVD data lines communicate change in VID code.

Interval 7 to 8: ISL6265C responds to VID-ON-THE-FLY code change.

Interval 8 to 9: PWROK is driven low and ISL6265C returns all outputs to pre-PWROK Metal VID level.

Interval 9 to 10: PWROK driven high once again by CPU and ISL6265C prepares for SVI code.

Interval 10 to 11: SVC and SVD data lines communicate new VID code.

Interval 11 to 12: ISL6265C drives outputs to new VID code level.

Post 12 : Enable falls and all internal drivers are tri-stated and PGOOD is driven low.

FIGURE 8. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID STARTUP

FN6976 Rev 2.00

January 11, 2013

Page 15 of 27

ISL6265C

Pre-PWROK Metal VID

SVI MODE

Assuming the OFS/VFIXEN pin is not tied to +3.3V during

controller configuration, typical motherboard start-up begins with

the controller decoding the SVC and SVD inputs to determine the

pre-PWROK metal VID setting (see Table 1). Once the enable

input (EN) exceeds the rising enable threshold, the ISL6265C

decodes and locks the decoded value in an on-board hold

register.

Once the controller has successfully soft-started and PGOOD

transitions high, the processor can assert PWROK to signal the

ISL6265C to prepare for SVI commands. The controller actively

monitors the SVI interface for set VID commands to move the

plane voltages to start-up VID values. Details of the SVI Bus

protocol are provided in the AMD Design Guide for Voltage

Regulator Controllers Accepting Serial VID Codes specification.

The internal DAC circuitry begins to ramp Core and Northbridge

planes to the decoded pre-PWROK metal VID output level. The

digital soft-start circuitry ramps the internal reference to the

target gradually at a fixed rate of approximately 2mV/µs. The

controlled ramp of all output voltage planes reduces in-rush

current during the soft-start interval. At the end of the soft-start

interval, the PGOOD output transitions high indicating all output

planes are within regulation limits.

Once a set VID command is received, the ISL6265C decodes the

information to determine which output plane is affected and the

VID target required (see Table 3).The internal DAC circuitry steps

the required output plane voltage to the new VID level. During

this time, one or more of the planes could be targeted. In the

event either core voltage plane, VDD0 or VDD1, is commanded to

power-off by serial VID commands, the PGOOD signal remains

asserted. The Northbridge voltage plane must remain active

during this time.

TABLE 1. PRE-PWROK METAL VID CODES

If the PWROK input is de-asserted, then the controller steps both

Core and Northbridge planes back to the stored pre-PWROK

metal VID level in the holding register from initial soft-start. No

attempt is made to read the SVC and SVD inputs during this time.

If PWROK is reasserted, then the on-board SVI interface waits for

a set VID command.

SVC

0

SVD

0

OUTPUT VOLTAGE (V)

1.1

1.0

0.9

0.8

0

1

0

1

If EN goes low during normal operation, all internal drivers are

tri-stated and PGOOD is pulled low. This event clears the

pre-PWROK metal VID code and forces the controller to check

SVC and SVD upon restart.

If the EN input falls below the enable falling threshold, the

ISL6265C tri-states all outputs. PGOOD is pulled low with the loss

of EN. The Core and Northbridge planes will decay based on

output capacitance and load leakage resistance. If bias to VCC

falls below the POR level, the ISL6265C responds in the same

manner previously described. Once VCC and EN rise above their

respective rising thresholds, the internal DAC circuitry re-acquires

a pre-PWROK metal VID code and the controller soft-starts.

A POR event on VCC during normal operation will shutdown all

regulators and PGOOD is pulled low. The pre-PWROK metal VID

code is not retained.

VID-On-the-Fly Transition

Once PWROK is high, the ISL6265C detects this flag and begins

monitoring the SVC and SVD pins for SVI instructions. The

microprocessor will follow the protocol outlined in the following

sections to send instructions for VID-on-the-Fly transitions. The

ISL6265C decodes the instruction and acknowledges the new

VID code. For VID codes higher than the current VID level, the

ISL6265C begins stepping the required regulator output(s) to the

new VID target with a typical slew rate of 7.5mV/µs, which meets

the AMD requirements.

VFIX MODE

In VFIX Mode, the SVC and SVD levels fixed external to the

controller through jumpers to either GND or VDDIO. These inputs

are not expected to change. In VFIX mode, the IC decodes the

SVC and SVD states per Table 2.

TABLE 2. VFIXEN VID CODES

SVC

0

SVD

0

OUTPUT VOLTAGE (V)

When the VID codes are lower than the current VID level, the

ISL6265C begins stepping the regulator output to the new VID

target with a typical slew rate of -7.5mV/µs. Both Core and NB

regulators are always in CCM during a down VID transition. The

AMD requirements under these conditions do not require the

regulator to meet the minimum slew rate specification of

-5mV/µs. In either case, the slew rate is not allowed to exceed

10mV/µs. The ISL6265C does not change the state of PGOOD

(VDDPWRGD in AMD specifications) when a VID-on-the-fly

transition occurs.

1.4

1.2

1.0

0.8

0

1

0

1

Once enabled, the ISL6265C begins to soft-start both Core and

Northbridge planes to the programmed VFIX level. The internal

soft-start circuitry slowly ramps the reference up to the target

value. The same fixed internal rate of approximately 2mV/µs

results in a controlled ramp of the power planes. Once soft-start

has ended and all output planes are within regulation limits, the

PGOOD pin transitions high.

SVI WIRE Protocol

The SVI wire protocol is based on the I²C bus concept. Two wires

(serial clock (SVC) and serial data (SVD)), carry information

between the AMD processor (master) and VR controller (slave) on

the bus. The master initiates and terminates SVI transactions

In the same manner described in “Pre-PWROK Metal VID” on

page 16, the POR circuitry impacts the internal driver operation

and PGOOD status.

FN6976 Rev 2.00

January 11, 2013

Page 16 of 27

ISL6265C

and drives the clock, SVC, during a transaction. The AMD

processor is always the master and the voltage regulators are the

slaves. The slave receives the SVI transactions and acts

accordingly. Mobile SVI wire protocol timing is based on high-

speed mode I²C. See AMD Griffin (Family 11h) processor

publications for additional details.

TABLE 3. SERIAL VID CODES

VOLTAGE (V) SVID[6:0]

1.1500 100_0000b

SVID[6:0]

VOLTAGE (V)

1.5500

1.5375

1.5250

1.5125

1.5000

1.4875

1.4750

1.4625

1.4500

1.4375

1.4250

1.4125

1.4000

1.3875

1.3750

1.3625

1.3500

1.3375

1.3250

1.3125

1.3000

1.2875

1.2750

1.2625

1.2500

1.2375

1.2250

1.2125

1.2000

1.1875

1.1750

1.1625

SVID[6:0]

VOLTAGE (V)

0.7500

0.7375

0.7250

0.7125

0.7000

0.6875

0.6750

0.6625

0.6500

0.6375

0.6250

0.6125

0.6000

0.5875

0.5750

0.5625

0.5500

0.5375

0.5250

0.5125

0.5000

0.4875*

0.4750*

0.4625*

0.4500*

0.4375*

0.4250*

0.4125*

0.4000*

0.3875*

0.3750*

0.3625*

SVID[6:0]

VOLTAGE (V)

0.3500*

0.3375*

0.3250*

0.3125*

0.3000*

0.2875*

0.2750*

0.2625*

0.2500*

0.2375*

0.2250*

0.2125*

0.2000*

0.1875*

0.1750*

0.1625*

0.1500*

0.1375*

0.1250*

0.1125*

0.1000*

0.0875*

0.0750*

0.0625*

0.0500*

0.0375*

0.0250*

0.0125*

OFF

000_0000b

000_0001b

000_0010b

000_0011b

000_0100b

000_0101b

000_0110b

000_0111b

000_1000b

000_1001b

000_1010b

000_1011b

000_1100b

000_1101b

000_1110b

000_1111b

001_0000b

001_0001b

001_0010b

001_0011b

001_0100b

001_0101b

001_0110b

001_0111b

001_1000b

001_1001b

001_1010b

001_1011b

001_1100b

001_1101b

001_1110b

001_1111b

010_0000b

010_0001b

010_0010b

010_0011b

010_0100b

010_0101b

010_0110b

010_0111b

010_1000b

010_1001b

010_1010b

010_1011b

010_1100b

010_1101b

010_1110b

010_1111b

011_0000b

011_0001b

011_0010b

011_0011b

011_0100b

011_0101b

011_0110b

011_0111b

011_1000b

011_1001b

011_1010b

011_1011b

011_1100b

011_1101b

011_1110b

011_1111b

110_0000b

110_0001b

110_0010b

110_0011b

110_0100b

110_0101b

110_0110b

110_0111b

110_1000b

110_1001b

110_1010b

110_1011b

110_1100b

110_1101b

110_1110b

110_1111b

111_0000b

111_0001b

111_0010b

111_0011b

111_0100b

111_0101b

111_0110b

111_0111b

111_1000b

111_1001b

111_1010b

111_1011b

111_1100b

111_1101b

111_1110b

111_1111b

1.1375

1.1250

1.1125

1.1000

1.0875

1.0750

1.0625

1.0500

1.0375

1.0250

1.0125

1.0000

0.9875

0.9750

0.9625

0.9500

0.9375

0.9250

0.9125

0.9000

0.8875

0.8750

0.8625

0.8500

0.8375

0.8250

0.8125

0.8000

0.7875

0.7750

0.7625

100_0001b

100_0010b

100_0011b

100_0100b

100_0101b

100_0110b

100_0111b

100_1000b

100_1001b

100_1010b

100_1011b

100_1100b

100_1101b

100_1110b

100_1111b

101_0000b

101_0001b

101_0010b

101_0011b

101_0100b

101_0101b

101_0110b

101_0111b

101_1000b

101_1001b

101_1010b

101_1011b

101_1100b

101_1101b

101_1110b

101_1111b

OFF

NOTE: *Indicates a VID not required for AMD Family 10h processors.

FN6976 Rev 2.00

January 11, 2013

Page 17 of 27

ISL6265C

(See Table 3)

SVID

5

4

3

2

1

0

7

5

4

2

1

6

3

0

SVC

SVD

SLAVE ADDRESS PHASE

DATA PHASE

FIGURE 9. SEND BYTE EXAMPLE

The ISL6265C controls the no-load output voltage of core and

Northbridge output to an accuracy of ±0.5% over-the-range of 0.75V

to 1.5V. A fully differential amplifier implements core voltage

sensing for precise voltage control at the microprocessor die.

SVI Bus Protocol

The AMD processor bus protocol is compliant with SMBus send

byte protocol for VID transactions (see Figure 9). During a send

byte transaction, the processor sends the start sequence

followed by the slave address of the VR for which the VID

command applies. The address byte must be configured

according to Table 4. The processor then sends the write bit. After

the write bit, if the ISL6265C receives a valid address byte, it

sends the acknowledge bit. The processor then sends the PSI-L

bit and VID bits during the data phase. The Serial VID 8-bit data

field encoding is outlined in Table 5. If ISL6265C receives a valid

8-bit code during the data phase, it sends the acknowledge bit.

Finally, the processor sends the stop sequence. After the

ISL6265C has detected the stop, it can then proceed with the

VID-on-the-fly transition.

Switching Frequency

The R³modulator scheme is a variable frequency PWM

architecture. The switching frequency increases during the

application of a load to improve transient performance. It also

varies slightly due to changes in input and output voltage and

output current. This variation is normally less than 10% in

continuous conduction mode.

CORE FREQUENCY SELECTION

A resistor connected between the VW and COMP pins of the Core

segment of the ISL6265C adjusts the switching window and

therefore adjusts the switching frequency. The R_FSETresistor that

sets up the switching frequency of the converter operating in

CCM can be determined using Equation 3, where R_FSETis in kΩ

and the switching period is in ms. Designs for 300kHz switching

frequency would result in a R_FSETvalue of 6.81kΩ.

TABLE 4. SVI SEND BYTE ADDRESS DESCRIPTION

BITS

DESCRIPTION

6:4 Always 110b

3

2

Reserved by AMD for future use

VDD1, if set then the following data byte contains the VID for

VDD1

R

k = Periods – 0.4  2.33

(EQ. 3)

FSET

1

0

VDD0, if set then the following data byte contains the VID for

VID0

In discontinuous conduction mode (DCM) the ISL6265C runs in

period stretching mode.

VDDNB, if set then the following data byte contains the VID for

VIDNB

NORTHBRIDGE FREQUENCY SELECTION

The Northbridge switching frequency to programmed by a

resistor connected from the FSET_NB pin to the GND pin. The

approximate PWM switching frequency is written as shown in

Equation 4:

TABLE 5. SERIAL VID 8-BIT DATA FIELD ENCODING

DESCRIPTION

BITS

7

PSI_L:

1

(EQ. 4)

-----------------------------------

F

=

=0 means the processor is at an optimal load for the regulator(s)

to enter power-savings mode

SW

K  R

FSETNB

=1 means the processor is not at an optimal load for the

regulator(s) to enter power-saving mode

Estimating the value of R_{FSET_NB}is written as shown in

Equation 5:

6:0 SVID[6:0] as defined in Table 3.

1

K  F

--------------------

(EQ. 5)

R

=

FSET

SW

Operation

Where F_SWis the PWM switching frequency, R_{FSET_NB}is the

programming resistor and K = 1.5 x 10^-10

After the start-up sequence, the ISL6265C begins regulating the

core and Northbridge output voltages to the pre-PWROK metal

VID programmed. The controller monitors SVI commands to

determine when to enter power-savings mode, implement

dynamic VID changes, and shutdown individual outputs.

.

It is recommended that whenever the control loop compensation

network is modified, the switching frequency should be checked

and adjusted by changing R_{FSET_NB}if necessary.

FN6976 Rev 2.00

January 11, 2013

Page 18 of 27

ISL6265C

selected, such that the R-C time constant matches the inductor

L/DCR time constant (see Equation 9), then V_Cis equal to the

voltage drop across the DCR multiplied by the ratio of the resistor

divider, K.

Current Sense

Core and Northbridge regulators feature two different types of

current sense circuits.

R

 R

L

CORE CONTINUOUS CURRENT SENSE

1

2

(EQ. 9)

-------------

--------------------

 C

=

1

DCR

R + R

1 2

The ISL6265C provides for load current to be measured using

either resistors in series with the individual output inductors or

using the intrinsic series resistance of the inductors as shown in

the applications circuits in Figures 3 and 4. The load current in a

particular output is sampled continuously every switching cycle.

During this time, the current-sense amplifier uses the current

sense inputs to reproduce a signal proportional to the inductor

current. This sensed current is a scaled version of the inductor

current.

The inductor current sense information is used for current

balance in dual plane applications, overcurrent detection in core

outputs and output voltage droop depending on controller

configuration.

CORE DCR TEMPERATURE COMPENSATION

It may also be necessary to compensate for changes in inductor

DCR due to temperature. DCR shifts due to temperature cause

time constant mismatch, skewing inductor current accuracy.

Potential problems include output voltage droop and OC trip

point, both shifting significantly from expected levels. The

addition of a negative temperature coefficient (NTC) resistor to

the R-C network compensates for the rise in DCR due to

temperature. Typical NTC values are in the 10kΩ range. A second

resistor, R₃, in series with the NTC allows for more accurate time-

constant and resistor-ratio matching as the pair of resistors are

placed in parallel with R₂(Figure 10). The NTC resistor must be

placed next to the inductor for good heat transfer, while R₁, R₂,

R₃, and C₁are placed close to the controller for interference

immunity.

I

V

IN

L

UGATE

LGATE

L

DCR

V

OUT

MOSFET

DRIVER

INDUCTOR

-

C

OUT

V (s)

L

-

V (s)

C

R

C

1

2

R

ISL6265C INTERNAL CIRCUIT

CORE DCR COMPONENT SELECTION FOR DROOP

R

NTC

OPTIONAL

NTC

NETWORK

By adjusting the ratio between inductor DCR drop and the voltage

measured across the sense capacitor, the load line can be set to

any level, giving the converter the correct amount of droop at all

load currents.

ISP

ISN

R

3

CURRENT

SENSE

Equation 10 shows the relation between droop voltage,

maximum output current (I_MAX), OC trip level and current sense

FIGURE 10. DCR SENSING COMPONENTS

capacitor voltage at the OC current level, V_C(OC)

.

Inductor windings have a characteristic distributed resistance or

DCR (Direct Current Resistance). For simplicity, the inductor DCR

is considered as a separate lumped quantity, as shown in

Figure 10. The inductor current, I_L, flowing through the inductor,

passes through the DCR. Equation 6 shows the s-domain

equivalent voltage, V_L, across the inductor.

I

MAX

(EQ. 10)

-------------

V

=

 5  V

DROOP

C OC

I

OC

AMD specifications do not require droop and provide no load line

guidelines. Tight static output voltage tolerance limits push

acceptable level of droop below a useful level for Griffin

applications. Care must be taken in applications which

implement droop to balance time constant mismatch, sense

capacitor resistor ratio, OC trip and droop equations.

Temperature shifts related to DCR must also be addressed, as

outlined in the previous section.

V s = I  s  L + DCR

(EQ. 6)

L

A simple R-C network across the inductor (R₁, R₂and C) extracts

the DCR voltage, as shown in Equation 7. The voltage across the

sense capacitor, V_C, can be shown to be proportional to the

output current I_L, shown in Equation 7.

NORTHBRIDGE CURRENT SENSE

s  L







-------------

+ 1

(EQ. 7)



DCR

During the off-time following a PHASE transition low, the

Northbridge controller samples the voltage across the lower

MOSFET r_DS(ON). A ground-referenced amplifier is connected to

the PHASE node through a resistor, R_{OCSET_NB}. The voltage across

R_{OCSET_NB}is equal to the voltage drop across the r_DS(ON)of the

lower MOSFET while it is conducting. The resulting current into

the OCSET_NB pin is proportional to the inductor current. The

sensed inductor current is used for overcurrent protection and

described in the “Fault Monitoring and Protection” on page 21.

The Northbridge controller does not support output voltage

droop.

----------------------------------------------------------

V

s =

 K  DCR  I

C

L

R  R 









1

2

-----------------------

s 

 C + 1

1



R

+ R

2



1

Where:

R

2

--------------------

K =

(EQ. 8)

R

+ R

1

2

Sensing the time varying inductor current accurately requires

that the parallel R-C network time constant match the inductor

L/DCR time constant. If the R-C network components are

FN6976 Rev 2.00

January 11, 2013

Page 19 of 27

ISL6265C

PHASE pin low. The ISL6265C has an integrated boot diode

connected from the PVCC pin to the BOOT pin.

Selecting RBIAS For Core Outputs

To properly bias the ISL6265C, a reference current is established

by placing a 117kΩ, 1% tolerance resistor from the RBIAS pin to

ground. This will provide a highly accurate, 10µA current source

from which OC reference current is derived.

Diode Emulation

The ISL6265C implements forced continuous-conduction-mode

(CCM) at heavy load and diode-emulation-mode (DE) at light load,

to optimize efficiency in the entire load range. The transition is

automatically achieved by detecting the inductor current when

PSI_L is low. If PSI_L is high, the controller disables DE and

forces CCM on both Core and NB regulators.

Care must be taken in layout to place the resistor very close to

the RBIAS pin. A good quality signal ground should be connected

to the opposite end of the R_BIASresistor. Do not connect any

other components to this pin as this would negatively impact

performance. Capacitance on this pin could create instabilities

and is to be avoided.

Positive-going inductor current flows either from the source of

the high-side MOSFET, or into the drain of the low-side MOSFET.

Negative-going inductor current flows into the drain of the low-

side MOSFET. When the low-side MOSFET conducts positive

inductor current, the phase voltage is negative with respect to the

GND and PGND pins. Conversely, when the low-side MOSFET

conducts negative inductor current, the phase voltage is positive

with respect to the GND and PGND pins. The ISL6265C monitors

the phase voltage when the low-side MOSFET is conducting

inductor current to determine the direction of the inductor

current.

A resistor divider off this pin is used to set the Core side OC trip

level. Additional direction on how to size is provided in “Fault

Monitoring and Protection” on page 21 on how to size the resistor

divider.

Offset Resistor Selection

If the OFS pin is connected to ground through a resistor, the

ISL6265C operates in SVI mode with droop active. The resistor

between the OFS pin and ground sets the positive Core voltage

offset per Equation 11.

When the output load current is less than half the inductor ripple

current, the inductor current goes negative. Sinking the negative

inductor through the low-side MOSFET lowers efficiency by

preventing DCM period stretching and allowing unnecessary

conduction losses. In DE, the ISL6265C Core regulators

automatically enter DCM after the PHASE pin has detected

positive voltage and LGATE was allowed to go high. The NB

regulator enters DCM after the PHASE pin has detected positive

voltage and LGATE was allowed to go high for eight consecutive

PWM switching cycles. The ISL6265C turns off the low-side

MOSFET once the phase voltage turns positive, indicating

negative inductor current. The ISL6265C returns to CCM on the

following cycle after the PHASE pin detects negative voltage,

indicating that the body diode of the low-side MOSFET is

conducting positive inductor current.

1.2V  R

FB

----------------------------

R

=

(EQ. 11)

OFS

V

OFS

Where V_OFSis the user defined output voltage offset. Typically,

V_OFSis determined by taking half the total output voltage droop.

The resulting value centers the overall output voltage waveform

around the programmed SVID level. For example, R_FBof 1kΩ and

a total output droop of 24mV would result in an offset voltage of

12mV and a R_OFSof 100kΩ.

Internal Driver Operation

The ISL6265C features three internal gate-drivers to support the

Core and Northbridge regulators and to reduce solution size. The

drivers include a diode emulation mode, which helps to improve

light-load efficiency.

Efficiency can be further improved with a reduction of

unnecessary switching losses by reducing the PWM frequency. It

is characteristic of the R³architecture for the PWM frequency to

decrease while in diode emulation. The extent of the frequency

reduction is proportional to the reduction of load current. Upon

entering DCM, the PWM frequency makes an initial

step-reduction because of a 33% step-increase of the window

voltage V_W.

MOSFET Gate-Drive Outputs

The ISL6265C has internal gate-drivers for the high-side and low-

side N-Channel MOSFETs. The low-side gate-drivers are optimized

for low duty-cycle applications where the low-side MOSFET

conduction losses are dominant, requiring a low r_DS(ON)MOSFET.

The LGATE pull-down resistance is low in order to strongly clamp

the gate of the MOSFET below the V_GS(th)at turn-off. The current

transient through the gate at turn-off can be considerable

because the gate charge of a low r_DS(ON)MOSFET can be large.

Adaptive shoot-through protection prevents a gate-driver output

from turning on until the opposite gate-driver output has fallen

below approximately 1V.

Power-Savings Mode

The ISL6265C has two operating modes to optimize efficiency

based on the state of the PSI_L input from the AMD SVI control

signal. When this input is low, the controller expects to deliver

low power and enters a power-savings mode to improve

efficiency in this low power state. The controller’s operational

modes are designed to work in conjunction with the AMD SVI

control signal to maintain the optimal system configuration for

all conditions.

The high-side gate-driver output voltage is measured across the

UGATE and PHASE pins while the low-side gate-driver output

voltage is measured across the LGATE and PGND pins. The power

for the LGATE gate driver is sourced directly from the PVCC pin.

The power for the UGATE gate-driver is sourced from a “boot”

capacitor connected across the BOOT and PHASE pins. The boot

capacitor is charged from a 5V bias supply through a “boot

diode” each time the low-side MOSFET turns on, pulling the

Northbridge and Dual Plane Core

While PSI_L is high, the controller operates all three regulators in

forced CCM. If PSI_L is asserted low by the SVI interface, the

FN6976 Rev 2.00

January 11, 2013

Page 20 of 27

ISL6265C

ISL6265C initiates DE in all three regulators. This transition

allows the controller to achieve the highest possible efficiency

over the entire load range for each output. A smooth transition is

facilitated by the R³technology^™, which correctly maintains the

internally synthesized ripple current throughout mode transitions

of each regulator.

controller uses lower MOSFET r_DS(ON)sensing to detect output

current.

CORE OC DETECTION

Core outputs feature an OC monitor which compares a voltage set at

the OCSET pin to the voltage measured across the current sense

capacitor, V_C. When the voltage across the current sense capacitor

exceeds the programmed trip level, the comparator signals an OC fault.

Figure 11 shows the basic OC functions within the IC.

Uniplane Core

In uniplane mode, the ISL6265C Core regulator is in 2-phase

multiphase mode. The controller operates with both phases fully

active, responding rapidly to transients and delivering the

maximum power to the load. When the processor asserts PSI_L

low under reduced load levels, the ISL6265C sheds one phase to

eliminate switching losses associated with the idle channel. Even

with the regulator operating in single-phase mode, transient

response capability is maintained.

SEE FIGURE 9 FOR

ADDITIONAL DETAIL

CURRENT

SENSE

ISP

ISN

+

V

c

5x

_

While operating in single-phase DE with PSI_L low, the lower

MOSFET driver switches the lower MOSFET off at the point of zero

inductor current to prevent discharge current from flowing from

the output capacitor bank through the inductor. In DCM,

switching frequency is proportionately reduced, thus greatly

reducing both conduction and switching loss. In DCM, the

5 x V

@

C(OC)

1.17V

R

OC TRIP CURRENT

BIAS

CKT

10µA

R

BIAS

OC

-

OCSET

V

+

6

OCSET

V

OCSET

R

OCSET

switching frequency is defined by Equation 12.

6

2

ISL6265C

F

2  L  I

O

CCM

------------------- -------------------------------------

F

=



(EQ. 12)

DCM

2

V









1.33

O

---------

V

 1 –



O

FIGURE 11. OC TRIP CIRCUITRY

V



IN

The sense capacitor voltage, V_C, will increase as inductor current

rises per Equation 7. When the inductor current rises to the OC

trip level, the voltage across the sense capacitor will reach a

maximum based on the resistor ratio K. This maximum value,

V_C(OC), is gained up by a factor of 5 and compared to the static OC

trip level set by the OCSET pin.

Where F_CCMis equivalent to the Core frequency set by Equation 3.

Fault Monitoring and Protection

The ISL6265C actively monitors Core and Northbridge output

voltages and currents to detect fault conditions. These fault

monitors trigger protective measures to prevent damage to the

processor. One common power good indicator is provided for

linking to external system monitors.

The recommended voltage range for V_C,OCis 6mV to 25mV,

which sets the resistor divider ratio K, where I_OCis the

user-defined OC trip level (see Equation 13). Typical inductor DCR

values are on the order of 1mΩ which result in more than enough

voltage drop to support this V_C,OCrange.

Power-Good Signal

The power-good pin (PGOOD) is an open-drain logic output that

signals if the ISL6265C is not regulating Core and Northbridge

output voltages within the proper levels or output current in one

or more outputs has exceeded the maximum current setpoint.

V

COC

 DCR

(EQ. 13)

---------------------------

K =

I

OC

The resistor divider components also impact time-constant

matching, these components need to meet the parallel

combination requirements of Equation 9.

This pin must be tied to a +3.3V or +5V source through a resistor.

During shutdown and soft-start, PGOOD is pulled low and is

released high only after a successful soft-start has raised Core

and Northbridge output voltages within operating limits. PGOOD

is pulled low when an overvoltage, undervoltage, or overcurrent

(OC) condition is detected on any output or when the controller is

disabled by a POR or forcing enable (EN) low. Once a fault

condition is triggered, the controller acts to protect the processor.

The controller latches off and PGOOD is pulled low. Toggling EN

or VCC initiates a soft-start of all outputs. In the event of an OV,

the controller will not initiate a soft-start by toggling EN, but

requires VCC be lowered below the falling POR threshold to reset.

Based on the selected V_C(OC)level, the required OC monitor trip

level is set. The recommended V_C(OC)level range will result in an

OC monitor trip level range of 30mV to 125mV based on the

internal gain of 5.

This OC monitor trip level sets the voltage level required at the

OCSET pin to create an OC fault at the user-defined OC trip level.

A resistor divider from the RBIAS pin to ground with the mid-point

connected to OCSET sets the voltage at the pin (see Figure 11).

This voltage is internally divided by 6 and compared with V_C(OC)

Working backwards, the voltage required at the OCSET pin to

achieve this OC trip level ranges from 180mV to 0.750mV as

defined in Equation 14.

.

Overcurrent Protection

Core and Northbridge outputs feature two different methods of

current sensing. Core output current sensing is achieved via

inductor DCR or discrete resistor sensing. The Northbridge

(EQ. 14)

V

= V

 30

COC

OCSET

FN6976 Rev 2.00

January 11, 2013

Page 21 of 27

ISL6265C

The resistor divider ratio used to determine the R_BIASand R_OCSET

values is shown in Equation 15.

value by a nominal 295mV for 205µs. The PWM outputs turn off

both Core and Northbridge internal drivers and PGOOD goes low.

R

V

OCSET

1.17V

OCSET

(EQ. 15)

-----------------------------------------------

-----------------------

=

General Application Design

Guide

This design guide is intended to provide a high-level explanation of

the steps necessary to design a single-phase power converter. It is

assumed that the reader is familiar with many of the basic skills

and techniques referenced in the following section. In addition to

this guide, Intersil provides complete reference designs that

include schematics, bills of materials, and example board layouts.

R

+ R

OCSET

BIAS

The resistor values must also meet the R_BIASrequirement that

the total series resistance to ground equal 117kΩ. An OC

condition must be sustained for 100µs before action is taken by

the controller in response to the OC fault.

A short-circuit OC loop is also active based on the same sense

elements outlined above with a threshold set to 2.25x the OCSET

threshold set. The controller takes immediate action when this

fast OC fault is detected.

Selecting the LC Output Filter

The output inductor and output capacitor bank form a low-pass

filter responsible for smoothing the pulsating voltage at the

phase node. The output filter also must support the transient

energy required by the load until the controller can respond.

Because it has a low bandwidth compared to the switching

frequency, the output filter limits the system transient response.

The output capacitors must supply or sink load current while the

current in the output inductors increases or decreases to meet

the demand.

NORTHBRIDGE OC DETECTION

Northbridge OC sensing is achieved via r_DS(ON)sensing across the

lower MOSFET. An internal 10µA current source develops a

voltage across R_{OCSET_NB}, which is compared with the voltage

developed across the low-side MOSFET as measured at the

PHASE pin. When the voltage drop across the MOSFET exceeds

the voltage drop across the resistor, an OC event occurs. The

OCSET_NB resistor is selected based on the relationship in

Equation 16.

The duty cycle of an ideal buck converter is a function of the

input and the output voltage. This relationship is written as

Equation 17:

I

 r

OC DSON

(EQ. 16)

------------------------------------

=

R

OCSETNB

10A

V

O

Where I_OCis the OC trip level selected for the Northbridge

application and r_DS(ON)is the drain-source ON-resistance of the

lower MOSFET.

---------

D =

(EQ. 17)

V

IN

The output inductor peak-to-peak ripple current is written as

Equation 18:

OC FAULT RESPONSE

V

O ^{ 1 – D}

When an OC fault occurs on any combination of outputs, both

Core and Northbridge regulators shutdown and the driver outputs

are tri-stated. The PGOOD signal transitions low indicating a fault

condition. The controller will not attempt to restart the regulators

and the user must toggle either EN or VCC to clear the fault

condition.

-----------------------------

(EQ. 18)

I

=

P-P

SW ^{ L}

f

For this type of application, a typical step-down DC/DC converter

has an I_P-Pof 20% to 40% of the maximum DC output load

current. The value of I_P-Pis selected based upon several criteria

such as MOSFET switching loss, inductor core loss, and the

resistive loss of the inductor winding. The DC copper loss of the

inductor can be estimated by Equation 19:

Overvoltage Protection

The ISL6265C monitors the individual Core and Northbridge

output voltages using differential remote sense amplifiers. The

ISL6265C features a severe overvoltage (OV) threshold of 1.8V. If

any of the outputs exceed this voltage, an OV fault is immediately

triggered. PGOOD is latched low and the low-side MOSFETs of the

offending output(s) are turned on. The low-side MOSFETs will

remain on until the output voltage is pulled below 0.85V at which

time all MOSFETs are turned off. If the output again rises above

1.8V, the protection process repeats. This offers protection

against a shorted high-side MOSFET while preventing output

voltage from ringing below ground. The OV is reset by toggling EN

low. OV detection is active at all times that the controller is

enabled including after one of the other faults occurs so that the

processor is protected against high-side MOSFET leakage while

the MOSFETs are commanded off.

2

P

= I

 DCR

(EQ. 19)

COPPER

LOAD

Where I_LOADis the converter output DC current.

The copper loss can be significant so attention must be given to

the DCR selection. Another factor to consider when choosing the

inductor is its saturation characteristics at elevated temperature.

A saturated inductor could cause destruction of circuit

components as well as nuisance OCP faults.

A DC/DC buck regulator must have output capacitance C_Ointo

which ripple current I_P-Pcan flow. Current I_P-Pdevelops a

corresponding ripple voltage V_P-Pacross C_O,which is the sum of

the voltage drop across the capacitor ESR and of the voltage

change stemming from charge moved in and out of the

capacitor. These two voltages are written as shown in

Equation 20:

Undervoltage Protection

Undervoltage protection is independent of the OC limit. A fault

latches if any of the sensed output voltages are less than the VID set

(EQ. 20)

V

= I

PP ^{ ESR}

ESR

FN6976 Rev 2.00

January 11, 2013

Page 22 of 27

ISL6265C

and Equation 21:

Where:

- I_MAXis the maximum continuous I_LOADof the converter

I

PP

-----------------------------

(EQ. 21)

V

=

C

O ^{ f}

8 C

SW

- I_PP,Nis the ratio of inductor peak-to-peak ripple current to

I_MAX

If the output of the converter has to support a load with high

pulsating current, several capacitors will need to be paralleled to

reduce the total ESR until the required V_P-Pis achieved. The

inductance of the capacitor can cause a brief voltage dip if the

load transient has an extremely high slew rate. Capacitor ESL can

significantly impact output voltage ripple. Low inductance

capacitors should be considered. A capacitor dissipates heat as a

function of RMS current and frequency. Be sure that I_P-Pis shared

by a sufficient quantity of paralleled capacitors so that they

operate below the maximum rated RMS current at F_SW. Take into

account that the rated value of a capacitor can degrade as much

as 50% as the DC voltage across it increases.

- D is the duty cycle that is adjusted to take into account the

efficiency of the converter which is written as:

V

O

(EQ. 23)

-----------------

D =

V

 

IN

- where  is converter efficiency

Figure 13 provides the same input RMS current information for

two-phase designs.

0.3

Selection of the Input Capacitor

0.2

The input capacitors are responsible for sourcing the AC

component of the input current flowing into the upper MOSFETs.

Their RMS current capability must be sufficient to handle the AC

component of the current drawn by the upper MOSFETs, which is

related to duty cycle and the number of active phases.

I

= 0.5

P-P,N

I

= 0.75

0.1

P-P,N

I

= 0

P-P,N

The important parameters for the bulk input capacitance are the

voltage rating and the RMS current rating. For reliable operation,

select bulk capacitors with voltage and current ratings above the

maximum input voltage and capable of supplying the RMS

current required by the switching circuit. Their voltage rating

should be at least 1.25x greater than the maximum input

voltage, while a voltage rating of 1.5x is a preferred rating.

Figure 12 is a graph of the input RMS ripple current, normalized

relative to output load current, as a function of duty cycle for a

single-phase regulator that is adjusted for converter efficiency.

0

0.2

0.4

0.6

0.8

1.0

DUTY CYCLE (V V )

IN/

O

FIGURE 13. NORMALIZED RMS INPUT CURRENT FOR

2-PHASE CONVERTER

In addition to the bulk capacitance, some low ESL ceramic

capacitance is recommended to decouple between the drain of

the high-side MOSFET and the source of the low-side MOSFET.

0.60

I

= 0.50

I

= 1

P-P,N

0.55

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

MOSFET Selection and Considerations

I

= 0.75

P-P,N

The choice of MOSFETs depends on the current each MOSFET will

be required to conduct, the switching frequency, the capability of

the MOSFETs to dissipate heat, and the availability and nature of

heat sinking and air flow.

I

= 0

P-P,N

I

= 0.25

P-P,N

Typically, a MOSFET cannot tolerate even brief excursions beyond

their maximum drain to source voltage rating. The MOSFETs used

in the power stage of the converter should have a maximum V_DS

rating that exceeds the sum of the upper voltage tolerance of the

input power source and the voltage spike that occurs when the

MOSFETs switch.

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

DUTY CYCLE (V V )

1.0

There are several power MOSFETs readily available that are

optimized for DC/DC converter applications. The preferred high-

side MOSFET emphasizes low gate charge so that the device

spends the least amount of time dissipating power in the linear

region. The preferred low-side MOSFET emphasizes low r _DS(ON)

when fully saturated to minimize conduction loss.

IN/

O

FIGURE 12. NORMALIZED RMS INPUT CURRENT FOR

SINGLE PHASE CONVERTER

The normalized RMS current calculation is written as Equation 22:

For the low-side (LS) MOSFET, the power loss can be assumed to

be conductive only and is written as Equation 24:

2

D

12









------

I

=

D  1 – D +

 I

(EQ. 22)

IN_RMS N

PP,N

2

P

 I

 r

DSON_LS ^{ 1 – D}

(EQ. 24)

CON_LS

LOAD

FN6976 Rev 2.00

January 11, 2013

Page 23 of 27

ISL6265C

For the high-side (HS) MOSFET, the its conduction loss is written

as Equation 25:

Component Placement

There are two sets of critical components in a DC/DC converter;

the power components and the small signal components. The

power components are the most critical because they switch

large amount of energy. The small signal components connect to

sensitive nodes or supply critical bypassing current and signal

coupling.

2

P

= I

 r

DSON_HS ^{ D}

(EQ. 25)

CON_HS

LOAD

For the high-side MOSFET, the switching loss is written as

Equation 26:

IN ^{ I}VALLEY ^{ t}ON ^{ f}

V

IN ^{ I}PEAK ^{ t}OFF ^{ f}

SW

---------------------------------------------------------------- -------------------------------------------------------------

P

=

+

The power components should be placed first and these include

MOSFETs, input and output capacitors, and the inductor. It is

important to have a symmetrical layout for each power train,

preferably with the controller located equidistant from each

power train. Symmetrical layout allows heat to be dissipated

equally across all power trains. Keeping the distance between

the power train and the control IC short helps keep the gate drive

traces short. These drive signals include the LGATE, UGATE,

PGND, PHASE and BOOT.

SW_HS

2

(EQ. 26)

Where:

- I_VALLEYis the difference of the DC component of the inductor

current minus 1/2 of the inductor ripple current

- I_PEAKis the sum of the DC component of the inductor current

plus 1/2 of the inductor ripple current

- t_ONis the time required to drive the device into saturation

- t_OFFis the time required to drive the device into cut-off

GND

VIAS TO

Selecting The Bootstrap Capacitor

GROUND

PLANE

OUTPUT

CAPACITORS

All three integrated drivers feature an internal bootstrap Schottky

diode. Simply adding an external capacitor across the BOOT and

PHASE pins completes the bootstrap circuit. The bootstrap

function is also designed to prevent the bootstrap capacitor from

overcharging due to the large negative swing at the PHASE node.

This reduces voltage stress on the BOOT and PHASE pins.

SCHOTTKY

DIODE

VOUT

PHASE

NODE

LOW-SIDE

MOSFETS

INDUCTOR

HIGH-SIDE

MOSFETS

INPUT

CAPACITORS

VIN

The bootstrap capacitor must have a maximum voltage rating

above PVCC + 4V and its capacitance value is selected per

Equation 27:

FIGURE 14. TYPICAL POWER COMPONENT PLACEMENT

Q

g

When placing MOSFETs, try to keep the source of the upper

MOSFETs and the drain of the lower MOSFETs as close as

thermally possible (see Figure 14). Input high-frequency

capacitors should be placed close to the drain of the upper

MOSFETs and the source of the lower MOSFETs. Place the output

inductor and output capacitors between the MOSFETs and the

load. High-frequency output decoupling capacitors (ceramic)

should be placed as close as possible to the decoupling target

(microprocessor), making use of the shortest connection paths to

any internal planes. Place the components in such a way that the

area under the IC has less noise traces with high dV/dt and di/dt,

such as gate signals and phase node signals.

-----------------------

C



(EQ. 27)

BOOT

V

BOOT

Where:

- Q_gis the total gate charge required to turn on the high-side

MOSFET

- V_BOOT, is the maximum allowed voltage decay across the

boot capacitor each time the high-side MOSFET is switched

on

As an example, suppose the high-side MOSFET has a total gate

charge Q_g, of 25nC at V_GS= 5V, and a V_BOOTof 200mV. The

calculated bootstrap capacitance is 0.125µF; for a comfortable

margin, select a capacitor that is double the calculated

capacitance. In this example, 0.22µF will suffice. Use a low

temperature-coefficient ceramic capacitor.

Signal Ground and Power Ground

The bottom of the ISL6265C QFN package is the signal ground

(GND) terminal for analog and logic signals of the IC. Connect the

GND pad of the ISL6265C to the island of ground plane under the

top layer using several vias, for a robust thermal and electrical

conduction path. Connect the input capacitors, the output

capacitors, and the source of the lower MOSFETs to the power

ground plane.

PCB Layout Considerations

Power and Signal Layers Placement on the

PCB

As a general rule, power layers should be close together, either

on the top or bottom of the board, with the weak analog or logic

signal layers on the opposite side of the board. The ground-plane

layer should be adjacent to the signal layer to provide shielding.

The ground plane layer should have an island located under the

IC, the compensation components, and the FSET components.

The island should be connected to the rest of the ground plane

layer at one point.

Routing and Connection Details

Specific pins (and the trace routing from them), require extra

attention during the layout process. The following sub-sections

outline concerns by pin name.

FN6976 Rev 2.00

January 11, 2013

Page 24 of 27

ISL6265C

PGND PINS

FSET_NB PIN

This is the return path for the pull-down of the LGATE low-side

MOSFET gate driver. Ideally, PGND should be connected to the

source of the low-side MOSFET with a low-resistance, low-

inductance path.

This pin requires a quiet environment. The resistor R_FSETshould

be placed directly adjacent to this pin. Keep fast moving nodes

away from this pin.

LGATE ROUTING

VIN PIN

The LGATE trace has a signal going through it that is both high

dV/dt and di/dt, with high peak charging and discharging

current. Route this trace in parallel with the trace from the PGND

pin. These two traces should be short, wide, and away from other

traces. There should be no other weak signal traces in proximity

with these traces on any layer.

The VIN pin should be connected close to the drain of the high-

side MOSFET, using a low- resistance and low-inductance path.

VCC PIN

For best performance, place the decoupling capacitor very close

to the VCC and GND pins.

BOOT AND PHASE ROUTING

PVCC PIN

The signals going through these traces are both high dv/dt and

high di/dt, with high peak charging and discharging current.

Route the UGATE and PHASE pins in parallel with short and wide

traces. There should be no other weak signal traces in proximity

with these traces on any layer.

For best performance, place the decoupling capacitor very close

to the PVCC and respective PGND pins, preferably on the same

side of the PCB as the ISL6265C IC.

ENABLE AND PGOOD PINS

Copper Size for the Phase Node

These are logic signals that are referenced to the GND pin. Treat

as a typical logic signal.

The parasitic capacitance and parasitic inductance of the phase

node should be kept very low to minimize ringing. It is best to

limit the size of the PHASE node copper in strict accordance with

the current and thermal management of the application. An

MLCC should be connected directly across the drain of the upper

MOSFET and the source of the lower MOSFET to suppress the

turn-off voltage.

FB PINS

The input impedance of the FB pin is high, so place the voltage

programming and loop compensation components close to the

COMP, FB, and GND pins keeping the high impedance trace

short.

FN6976 Rev 2.00

January 11, 2013

Page 25 of 27

ISL6265C

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you

have the latest Rev.

DATE

REVISION

FN6976.2

CHANGE

November 7, 2012

Converted to new template.

page 3 - Ordering Information table, added industrial part number ISL6265CIRTZ.

In “Electrical Specifications” table, corrected conditions and standard over temp note in common conditions of

Spec table from: "VCC = PVCC = 5V, V_IN= 12V, Boldface limits apply over the operating temperature range,

-10°C to +100°C." to: “VCC = PVCC = 5V, V_IN= 12V, T_A= -10°C to +100°C (ISL6265HRTZ), T_A= -40°C to

+100°C (ISL6265IRTZ), unless otherwise specified. Boldface limits apply across the operating temperature

range, -40°C to +100°C.”

July 23, 2010

FN6976.1

Added “Related Literature*” on page 1.

On page 3; corrected part marking in “Ordering Information” from ISL6265C HRTZ to 6265C HRTZ

In “Thermal Information” on page 10, corrected Theta JC from 32 to 28

In “Electrical Specifications” table, corrected standard over temp note in common conditions of Spec table from

"Boldface limits apply over the operating temperature range, -40°C to +85°C." to "Boldface limits apply over

the operating temperature range, -10°C to +100°C."

On “Overvoltage Threshold” on page 12; changed typical from 1.795V to 1.800V and maximum from 1.820V to

1.825V.

March 10, 2010

FN6976.0

Initial Release.

About Intersil

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FN6976 Rev 2.00

January 11, 2013

Page 26 of 27

ISL6265C

Package Outline Drawing

L48.6x6

48 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 1, 4/07

4X

4.4

6.00

0.40

44X

A

6

B

PIN #1 INDEX AREA

48

37

6

1

36

PIN 1

INDEX AREA

4 .40 ± 0.15

25

12

0.15

(4X)

13

24

0.10 M C A B

C

0.05 M

TOP VIEW

48X 0.45 ± 0.10

BOTTOM VIEW

4

48X 0.20

SEE DETAIL "X"

C

0.10

C

MAX 0.80

BASE PLANE

SEATING PLANE

0.08

( 44 X 0 . 40 )

( 5. 75 TYP )

(

C

SIDE VIEW

4. 40 )

5

0 . 2 REF

C

( 48X 0 . 20 )

( 48X 0 . 65 )

0 . 00 MIN.

0 . 05 MAX.

DETAIL "X"

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3.

Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

FN6976 Rev 2.00

January 11, 2013

Page 27 of 27


型号：	ISL6265CHRTZ
厂家：	RENESAS TECHNOLOGY CORP
描述：	Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable Mobile CPUs
文件：	总27页 (文件大小：1226K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6265CHRTZ [RENESAS]

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