ISL58115 [RENESAS]
Laser Diode Driver with APC Amplifier for Printers;
| 型号： | ISL58115 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Laser Diode Driver with APC Amplifier for Printers PC |
| 文件： | 总9页 (文件大小：500K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL58115
FN6671
Rev 1.00
July 29, 2013
Laser Diode Driver with APC Amplifier for Printers
The ISL58115 is a high-performance laser driver that provides
controlled current to grounded laser diodes. A bias current is
summed with the switched current at the IOUT output, allowing
the user to optimize laser diode performance.
Features
• Voltage-controlled Output Current Source
• Very Few External Components Needed
• Internal LVDS Termination Resistors
• 300MHz Switching
Output switched current flows when the LVDS signal DATA is
high. The output current returns to the fixed-threshold value
when DATA is low. Complete I
shut-off is achieved by
OUT
• Up to 110mA Output Current
• Rise Time < 500ps
holding the CHPEN low, which will override all other control
pins.
• Fall Time < 500ps
A fast settling APC amplifier connects directly to the monitor
diode. The ISL58115 does not exhibit any time-dependent
droop since the calibration gain is stored as a digital number.
• APC Loop for Write Power Control
• Fast Settling APC Amplifier
• Single +5V Supply (±10%)
Ordering Information
• Disable Feature for Power-Up Protection and Conserving
Power
PACKAGE
PART NUMBER
(Notes 1, 2)
PART
MARKING
Tape & Reel
(Pb-free)
PKG.
DWG. #
• Zero Droop
• Pb-Free (RoHS compliant)
ISL58115CRZ-T13
58115 CRZ
24 Ld QFN
L24.4x5B
NOTES:
Load Configuration
1. Please refer to TB347 for details on reel specifications.
• Common-cathode LD, Common-anode PD
2. These Intersil Pb-free plastic packaged products employ special Pb-
free material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
IOUT PDIN
GND
Applications
• Laser Printer Applications
• Laser Diode Current Switching
FN6671 Rev 1.00
July 29, 2013
Page 1 of 9
ISL58115
Pin Configuration
ISL58115
(24 LD QFN)
TOP VIEW
NC
DATA
DATAB
GND
DIS
1
2
3
4
5
6
7
19 NC
18 GND
17 VCC
16 IOUT
15 VCC
14 VCC
13 PDIN
THERMAL
PAD
NC
NC
Pin Descriptions
PIN
PIN
NAME
NUMBER
I/O
TYPE
LVDS
DESCRIPTION
DATA
DATAB
GND
DIS
2
I
I
Input data to control Laser Switching Control
Input data to control Laser Switching Control
Ground
3
4, 18, 24
5
LVDS
Ground
Digital
I
I
Disable output current
NC
1, 6, 7, 19,
23
No connect
No connect
CHPEN
RPS
8
I
I
Digital
Analog
Analog
Analog
Analog
Chip Enable; Pull High to Enable
9
External resistor sets the Hsync detection power
Resistors set bias threshold current. See “Applications Information” on page 7 for more details
Bandgap derived internal reference
RBIAS
RSET
IVOUT
10
11
12
O
O
Calibrate channel with an external trimpot to GND
Adjust the IV amplifier gain
PDIN
VCC
13
14, 15, 17
16
I
Analog
Power
Analog
TLL
Photo Diode input to the IV amplifier
Supply Voltage
IOUT
HPSB
O
I
Laser Current Output
20
Hsync Power Select Enable; Active Low. During HPSB is low AND Hsync signal from photo
detector is low, the output current is set by RPS
CALB
VC
21
22
-
I
I
TTL
Samples the laser power for APC; Active Low
Analog
Voltage Controlling Laser Switching Current; 0V to 2V input for 0% to 100% output
Exposed Thermal Pad should be soldered to GND
Thermal
Pad
NOTE: Pins with the same name are not necessary internally connected together. LDD pins must not be used for connecting together external components
or features.
FN6671 Rev 1.00
July 29, 2013
Page 2 of 9
ISL58115
Absolute Maximum Ratings (T = +25°C)
Recommended Operating Conditions
A
Voltages Applied to:
Thermal Resistance (Typical, Notes 3, 4)
JA (°C/W)
42
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6.0V
CC
All Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V + 0.5V
24 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V
Operating Ambient Temperature Range . . . . . . . . . . . . . . . . 0°C to +85°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
I
OUT
CC
LVDS Max Current Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 3kV
Charged Device Model (Tested per JESD22-C110D) . . . . . . . . . . . .1.5kV
Machine Model (Tested per JESD22-A115B) . . . . . . . . . . . . . . . . . . 200V
Latch Up (Tested per JESD78B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
4. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise
noted, all tests are at the specified temperature and are pulsed tests, therefore: T = T = T
J
C
A
Electrical Specifications
V
= 5.0V, DIS = Lo, T = +25°C, R
= 3.0kΩ, unless otherwise indicated.
CC
A
SET
MIN
MAX
PARAMETER
DESCRIPTION
Supply Voltage
CONDITIONS
(Note 5)
TYP
5.0
0.3
22
(Note 5)
UNIT
V
V
4.5
5.5
1.0
31
CC
ISdis
IS2
Supply Current (Disabled)
Supply Current (Standby)
Low Voltage Threshold
High Voltage Threshold
Input Low Current
DIS = SLPEN = HPSB = Hi
DIS = Hi
mA
mA
V
V
V
All TTL inputs
All TTL inputs
All TTL inputs
All TTL inputs
1.2
LO
HI
2.8
-20
V
I
I
-10
µA
µA
V
LO
HI
Input High Current
1
V
V
V
V
VCC Shut Down Voltage
LVDS Input Level
2.5
0.2
2.9
SHUT
LVDS
CMR
C
Differential, with Vcm = 1.25V
V
LVDS Common Mode Voltage Range
Control Voltage
300mV
0.2
0.3
2.2
2.6
V
P-P
V
R
Internal LVDS Termination Resistor
180
TYP
Termination
Laser Amplifier Output
V
= 5.0V, DIS = Lo, T = +25°C, R = 3.0kΩ, unless otherwise indicated.
SET
CC
A
MIN
(Note 5)
MAX
(Note 5)
PARAMETER
OUT
DESCRIPTION
CONDITIONS
UNIT
I
IOUT
IOUT
Switched Output Current
Bias Output Current
Output Off Current
VC = 2.6V
= 1k
75
20
81
35
0
mA
mA
µA
SW-max
R
BIAS-max
BIAS
I
DIS pin set to HIGH
-75
200
+75
OFF
FREQ
Operating Frequency
I
I
= maximum switch current
MHz
%/V
ns
OP
OUT
OUT
IOUT
I
I
I
I
Supply Sensitivity
Rise Time
= 20mA, V = 5V ±10%
CC
13
0.5
0.7
5
PSRR
OUT
OUT
OUT
OUT
t
t
10% to 90%; typical LD for printer
90% to 10%; typical LD for printer
R-IOUT
F-IOUT
Fall Time
ns
OUTENx_t
on
on Propagation Delay
DATAx crossing to I
OUT
at 50% of final value
7
ns
FN6671 Rev 1.00
July 29, 2013
Page 3 of 9
ISL58115
Laser Amplifier Output
V
= 5.0V, DIS = Lo, T = +25°C, R = 3.0kΩ, unless otherwise indicated.
SET
CC
A
MIN
MAX
PARAMETER
BW
DESCRIPTION
Bandwidth of VC
CONDITIONS
(Note 5)
TYP
14
(Note 5)
UNIT
MHz
VC
APC Electrical Specifications
V
= 5.0V, DIS = Lo, T = +25°C, R
A
= 3.0kΩ, unless otherwise indicated.
SET
CC
MIN
MAX
PARAMETER
APC-50
DESCRIPTION
CONDITIONS
0V to 2V step of VC
External resistor RIV = 500
(Note 5)
TYP
7.5
(Note 5)
UNIT
µs
t
APC Response Time
IV Amplifier Gain
IVgain
3.1
k
NOTE:
5. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Timing Diagram
CHPEN
DIS
VC
CALB
DATA(LVDS)
HPSB
SET BY
RPS
FIXED BIAS
LEVEL
I
RISES TO
OUT
SET BY R
BIAS
ITS VC DEFINED
VALUE USING
THE LAST
OFF
OFF
I
CALIBRATION
GAIN SETTING IN
<1µs
OUT
FN6671 Rev 1.00
July 29, 2013
Page 4 of 9
ISL58115
I
Control
OUT
CHPEN
DIS
DATA
x
CALB
x
HPSB
I
COMMENTS
OUT
POWER-DOWN (SLEEP MODE)
0
x
x
x
OFF
OFF
CHPEN is slow to enable
STANDBY (FULL STANDBY CURRENT, NO I
)
OUTS
1
1
x
x
Full standby current, no I
OUT
NORMAL DRIVE
1
0
0
0
x
x
1
0
1
1
1
1
ON, BIAS ONLY
ON, CAL to level set by VC
ON
1
1
1
Hsync POWER
1
0
x
x
1
1
0
x
Hsync power
INVALID
Output current defined by RPS
INVALID LOGIC COMBINATION
1
0
NOTE: DATA1 and DATA2: 1 implies DATA>DATAB, 0 implies DATA<DATAB
FN6671 Rev 1.00
July 29, 2013
Page 5 of 9
ISL58115
Typical Application
+5V
DATA
GND
+
DATAB
-
LOGIC CNTRL
4.7µF
VCC
+
-
0.1µF
SWITCHING
DRIVER
GAIN
CONTROL
68
IOUT
VC
RPS
GND
+
LASER
VCC
-
VCC
RSET
3kΩ
0.1µF
RBIAS
BANDGAP
REF.
3kΩ
NC
NC
NC
NC
CALB
HPSP
PDIN
-
CAL.
POT
+
IV AMPLIFIER
5kΩ
IVOUT
NC
DIS
CHPEN
GND
LOGIC BLOCK
FN6671 Rev 1.00
July 29, 2013
Page 6 of 9
ISL58115
During calibration mode, the internal servo control will bring the
laser diode output power level to match the voltage control level
set by VC voltage.
Applications Information
APC System Overview
As the laser heats up (or ages) its output power declines relative
to the applied current, so some form of power control is required.
The laser is optically coupled to a photo-diode, so that the laser’s
optical output can be measured. Laser optical output power is
controlled by comparing the externally applied control voltage
with the voltage produced by the IV-amplifier which converts the
photo-diode’s output current into a voltage. Since the calibrated
gain is stored as a digital number in a register, the ISL58115
exhibits none of the time-dependent droop that is seen in most
printers' laser diode drivers. This is of particular importance
during high dot/inch graphics modes where the line may be
slowed down very significantly to allow 2400 dots per inch or
even more.
Horizontal edge detection
When HPSB is low, the output current is set by RPS. Asserting
HPSB low overrides both channel data inputs. HPSB should not
be asserted low during a calibration cycle. When HPSB is low, the
desired output current I
equation:
is governed by the following
RPS
RPS
CalDAC RSET
1.05V
(EQ. 3)
----------------------- ---------------
IRPS = 40
where the CalDAC setting (from the last write power calibration)
ensures laser temperature and aging compensation. The
CalDAC’s units are ohms. Full scale is about 380Ω and CalDAC is
defined as CalDAC = 255/code*380Ω.
Fixed-Threshold Laser Bias Control
The horizontal sync pulse is meant to be a power level that
overrides VC calibration and sets the output current to a fixed
level.
When a laser is driven from below threshold to well above
threshold, it exhibits a few cycles of a damped oscillation. The
amplitude of this oscillation is minimized when the laser is kept
above threshold. The “fixed” bias mode is set by asserting a logic
Low on the SLPEN pin. To set the laser bias threshold currents,
Typical Application
Upon the printer being powered up, the lasers should be
calibrated. This would establish nominal light power outputs,
typically a few milliwatts at the laser regardless of the ambient
temperature and also any laser aging.
I
, connect external resistors from RBIAS pins to GND. Figure
BIAS
1 shows value of R
corresponding to desired bias current.
BIAS
100
Once everything is ready for printing, the paper is in position and
the mirror-motor is phase-locked then the print line(s) can be
written. Before, or after, the beam is over the photo-sensitive
drum, each laser can be re-calibrated. This continual re-
calibration will compensate for any temperature drift of the laser,
especially at the initial warming up period.
10
Since the calibrated gain is stored as a digital number in a
register, the ISL58115 exhibits no time-dependent droop. With
no droop to degrade performance the only limitation now is the
lasers' own temperature change along the line. This in turn can
be compensated for to some extent by adding a data-dependent
compensation signal to the analog VCx input pin. It may be found
that in fast draft modes for example, that the laser temperature
change is sufficiently small that many lines can be written before
the laser(s) need to be re-calibrated. If the printed page has a low
enough duty cycle, no re-calibration may be needed at all.
1
0.1
1
10
R
(k)
BIAS
FIGURE 1. R
vs BIAS CURRENT
BIAS
Scaling External Resistors
is used to scale the switching output current. Switching
output current, I , is the function of VC and R
R
SET
.
SW SET
VC
2
--------------- --------------
I
= I
Gain
SW
–
(EQ. 1)
The ISL58115 has analog voltage inputs to allow the laser power
level to be adjusted during the line. Typically this would be driven
with a PWM, low bandwidth signal to compensate for the
differing beam path length as the beam is swept from one side
of the page to the other.
SW
R
R
SET
DAC
Where I Gain = ~17, R
SW
= 400.
DAC
R
sets bias threshold current. Figure 1 exhibits the
BIAS
relationship between I
Equation 2:
and R . The bias current is set as
BIAS
BIAS
Undervoltage, overcurrent and over-temperature error conditions
are ORed together and made available on the ERRB pin.
InternalVref
(EQ. 2)
-----------------------------------
I
= BiasChannelGain
BIAS
R
BIAS
Note on Illegal Logic Combination
In normal use, CALB going low (active) without DIS being low
(active) would be meaningless. Likewise with HPSB going low
(active). Therefore, a combination of these should be avoided at
all times. If this combination is applied, the chip will not work
properly. To exit this mode, either set CALB to Low or/and DIS to
Hi.
Where BiasChannelGain = ~40, InternalVref = 1.0V.
Controlling the Sampling
The switching levels are sampled independently. This can be
done during the “off-paper” period.
FN6671 Rev 1.00
July 29, 2013
Page 7 of 9
ISL58115
Power Supply Decoupling
DIS
Due to the high values of current being switched rapidly on and
off, it is important to ensure that the power supply is well
decoupled to ground. During switching, the V undergoes severe
current transients, thus every effort should be made to decouple
CC
CALB
HPSB
the V as close to the package as possible. Symptoms that
CC
could arise include poor rise/fall times, current overshoot, and
poor settling response. It is recommended that VCC inputs
should be bypassed with 4.7µF // 100nF // 470pF to GND
FIGURE 2. ILLEGAL COMBINATION
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
FN7659.1
FN7659.0
CHANGE
July 29, 2013
June 15, 2010
Conversion to New Intersil Template.
Initial release.
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
© Copyright Intersil Americas LLC 2010-2013. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6671 Rev 1.00
July 29, 2013
Page 8 of 9
ISL58115
Package Outline Drawing
L24.4x5B
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 10/06
4.00
2.50
A
PIN 1
PIN #1 INDEX AREA
24X0.40
INDEX AREA
CHAMFER 0.40×0 X 45°
B
20
24
6
6
1
19
3.50
0.5x6=3.00 REF
7
13
12
8
0.10
0.25±0.05
0.10
4X
0.50
M
C A B
TOP VIEW
0.5x4=2.00 REF
BOTTOM VIEW
SEE DETAIL X''
0.10
C
C
SEATING PLANE
0.08
0.90±0.10
C
(24x0.25)
(20x0.50)
SIDE VIEW
(3.50)
(4.80 TYP)
5
0 . 20 REF
C
(24x0.60)
(2.50)
(3.80 TYP)
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.20mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN6671 Rev 1.00
July 29, 2013
Page 9 of 9
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