ISL22424UFR16Z [RENESAS]
Dual Digitally Controlled Potentiometer (XDCP™), Low Noise, Low Power, SPI® Bus, 256 Taps; QFN16, TSSOP14; Temp Range: -40° to 125°C;
| 型号： | ISL22424UFR16Z |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Dual Digitally Controlled Potentiometer (XDCP™), Low Noise, Low Power, SPI® Bus, 256 Taps; QFN16, TSSOP14; Temp Range: -40° to 125°C |
| 文件： | 总20页 (文件大小：1166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL22424
FN6425
Rev 1.00
September 9, 2015
Dual Digitally Controlled Potentiometer (XDCP™) Low Noise, Low Power, SPI®
Bus, 256 Taps
The ISL22424 integrates two digitally controlled
potentiometers (DCP), control logic and non-volatile memory
Features
• Two potentiometers in one package
• 256 resistor taps
on a monolithic CMOS integrated circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wiper is controlled by the user through the SPI
serial interface. Each potentiometer has an associated
volatile Wiper Register (WRi) and a non-volatile Initial Value
Register (IVRi) that can be directly written to and read by the
user. The contents of the WRi control the position of the
wiper. At power-up the device recalls the contents of the
DCP’s IVRi to the corresponding WRi.
• SPI serial interface with write/read capability
• Daisy Chain Configuration
• Shutdown mode
• Non-volatile EEPROM storage of wiper position
• 13 General Purpose non-volatile registers
• High reliability
- Endurance: 1,000,000 data changes per bit per register
The ISL22424 also has 13 General Purpose non-volatile
registers that can be used as storage of lookup table for
multiple wiper position or any other valuable information.
- Register data retention: 50 years @ T 55°C
• Wiper resistance: 70 typical @ 1mA
• Standby current <4µA max
The ISL22424 features a dual supply, that is beneficial for
applications requiring a bipolar range for DCP terminals
• Shutdown current <4µA max
between V- and V
.
CC
• Dual power supply
Each DCP can be used as three-terminal potentiometer or
as two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
- V
CC
= 2.25V to 5.5V
- V- = -2.25V to -5.5V
• 10k 50kor 100k total resistance
• Extended industrial temperature range: -40ºC to +125ºC
• 14 Ld TSSOP or 16 Ld QFN
• Pb-free plus anneal product (RoHS compliant)
FN6425 Rev 1.00
September 9, 2015
Page 1 of 20
ISL22424
Ordering Information
PART NUMBER
(NOTES 1, 2)
RESISTANCE
OPTION (k)
TEMPERATURE
RANGE (°C)
PACKAGE
(Pb-Free)
PART MARKING
PKG. DWG. #
M14.173
ISL22424TFV14Z (No
longer available,
recommended
replacement:
ISL22424WFR16Z-TK)
22424TFVZ
22424TFRZ
22424UFVZ
22424UFRZ
100
100
50
-40 to +125
-40 to +125
-40 to +125
-40 to +125
14 Ld TSSOP
ISL22424TFR16Z (No
longer available,
recommended
replacement:
ISL22424WFR16Z-TK)
16 Ld QFN
14 Ld TSSOP
16 Ld QFN
L16.4x4A
M14.173
L16.4x4A
ISL22424UFV14Z (No
longer available,
recommended
replacement:
ISL22424WFR16Z-TK)
ISL22424UFR16Z (No
longer available,
recommended
50
replacement:
ISL22424WFR16Z-TK)
ISL22424WFV14Z
ISL22424WFR16Z
NOTES:
22424WFVZ
22424WFRZ
10
10
-40 to +125
-40 to +125
14 Ld TSSOP
16 Ld QFN
M14.173
L16.4x4A
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add “-TK” suffix for 1,000 Tape and Reel option
FN6425 Rev 1.00
September 9, 2015
Page 2 of 20
ISL22424
Block Diagram
RH0
RH1
V-
VCC
SCK
SDI
POWER UP,
CONTROL
AND
STATUS
LOGIC
SPI
INTERFACE
SDO
CS
WR0
WR0
VOLATILE
REGISTER
AND
VOLATILE
REGISTER
AND
WIPER
WIPER
CONTROL
CIRCUITRY
CONTROL
CIRCUITRY
NON-VOLATILE
REGISTERS
RW0
RL0
RW1
RL1
GND
Pinouts
ISL22424
(14 LD TSSOP)
TOP VIEW
ISL22424
(16 LD QFN)
TOP VIEW
RH0
RL0
1
2
3
4
5
6
7
14
VCC
CS
16 15 14 13
13
12
11
10
9
RW0
RH1
RL1
RW1
NC
1
2
3
4
12
11
10
9
SDI
GND
SCK
SDO
V-
NC
NC
NC
V-
RL0
RH0
V
CC
CS
8
5
6
7
8
FN6425 Rev 1.00
September 9, 2015
Page 3 of 20
ISL22424
Pin Descriptions
TSSOP PIN
QFN PIN
SYMBOL
RH0
RL0
DESCRIPTION
1
2
11
“High” terminal of DCP0
“Low” terminal of DCP0
“Wiper” terminal of DCP0
“High” terminal of DCP1
“Low” terminal of DCP1
“Wiper” terminal of DCP1
No connection
12
3
13
RW0
RH1
RL1
4
14
5
15
6
16
RW1
NC
7
1, 2, 3
8
4
V-
Negative power supply pin
9
5
SDO
SCK
GND
SDI
Data Output of the SPI serial interface
SPI interface clock input
10
11
12
13
14
6
7
Device ground pin
8
9
Data Input of the SPI serial interface
Chip Select active low input
CS
10
VCC
Positive power supply pin
EPAD*
Exposed Die Pad internally connected to V-
* Note: PCB thermal land for QFN EPAD should be connected to V- plane or left floating. For more information refer to
http://www.intersil.com/data/tb/TB389.pdf
FN6425 Rev 1.00
September 9, 2015
Page 4 of 20
ISL22424
Absolute Maximum Ratings
Thermal Information
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage at any Digital Interface Pin
Thermal Resistance (Typical, Note 3)
(°C/W)
JA
14 Lead TSSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
16 Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
with Respect to GND . . . . . . . . . . . . . . . . . . . . -0.3V to V
+0.3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V
CC
V
CC
V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to 0.3V
Voltage at any DCP pin with Respect to GND . . . . . . . . . . V- to V
CC
(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
I
W
Latchup . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level A @ +125°C
ESD
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350V
Recommended Operating Conditions
Temperature Range (Full Industrial) . . . . . . . . . . . .-40°C to +125°C
Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.25V to 5.5V
CC
V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.25V to -5.5V
Max Wiper Current Iw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Analog Specifications Over recommended operating conditions unless otherwise stated.
TYP
SYMBOL
PARAMETER
RHi to RLi resistance
TEST CONDITIONS
MIN
(NOTE 4)
MAX
UNIT
k
R
W option
U option
T option
10
TOTAL
50
k
100
k
RHi to RLi resistance tolerance
-20
V-
+20
%
End-to-End Temperature Coefficient
W option
±85
±45
ppm/°C
ppm/°C
V
U, T option
V
, V
RH RL
DCP terminal voltage
Wiper resistance
V
and V
to GND
V
CC
RHi
RLi
R
RH - floating, V = V-, force Iw current to the
70
10/10/25
0.1
250
W
RL
wiper, I = (V
- V )/R
W
CC RL TOTAL
C /C /C
W
Potentiometer capacitance
Leakage on DCP pins
See Macro Model below.
pF
µA
H
L
(Note 20)
I
Voltage at pin from V- to V
1
LkgDCP
CC
VOLTAGE DIVIDER MODE (V- @ RLi; V
@ RHi; measured at RWi, unloaded)
W option
CC
INL
Integral non-linearity
-1.5
-1.0
-1.0
-0.5
±0.5
±0.2
1.5
1.0
1.0
0.5
LSB
(Note 5)
(Note 9)
U, T option
W option
LSB
(Note 5)
DNL
(Note 8)
Differential non-linearity
Monotonic over all tap positions
±0.4
LSB
(Note 5)
U, T option
±0.15
LSB
(Note 5)
ZSerror
(Note 6)
Zero-scale error
W option
0
0
1
0.5
-1
5
2
0
0
2
LSB
(Note 5)
U, T option
W option
FSerror
(Note 7)
Full-scale error
-5
-2
-2
LSB
(Note 5)
U, T option
-1
V
DCP to DCP matching
Wipers at the same tap position, the same
voltage at all RH terminals and the same
voltage at all RL terminals
LSB
(Note 5)
MATCH
(Note 10)
TC
Ratiometric temperature coefficient
DCP register set to 80 hex
±4
ppm/°C
V
(Note 11, 20)
FN6425 Rev 1.00
September 9, 2015
Page 5 of 20
ISL22424
Analog Specifications Over recommended operating conditions unless otherwise stated. (Continued)
TYP
SYMBOL
PARAMETER
-3dB cut off frequency
TEST CONDITIONS
MIN
(NOTE 4)
MAX
UNIT
kHz
kHz
kHz
f
Wiper at midpoint (80hex) W option (10k)
Wiper at midpoint (80hex) U option (50k)
Wiper at midpoint (80hex) T option (100k)
1000
250
cutoff
(Note 20)
120
RESISTOR MODE (Measurements between R and R with R not connected, or between R and R with R not connected)
W
L
H
W
H
L
RINL
(Note 15)
Integral non-linearity
Differential non-linearity
Offset
W option
-3
±1.5
±0.4
±0.5
±0.15
1
3
1
MI
(Note 12)
U, T option
W option
-1
MI
(Note 12)
RDNL
(Note 14)
-1.5
-0.5
0
1.5
0.5
5
MI
(Note 12)
U, T option
W option
MI
(Note 12)
Roffset
MI
(Note 13)
(Note 12)
U, T option
0
0.5
2
MI
(Note 12)
R
DCP to DCP matching
Wipers at the same tap position with the
same terminal voltages
-2
2
MI
(Note 12)
MATCH
(Note 16)
TC
Resistance temperature coefficient
DCP register set between 32hex and FF hex
±40
ppm/°C
R
(Note 17, 20)
Operating Specifications Over the recommended operating conditions unless otherwise specified.
TYP
SYMBOL
PARAMETER
TEST CONDITIONS
= 5.5V, V- = 5.5V, f = 5MHz; (for SPI
MIN
(NOTE 4)
MAX
UNIT
I
V
Supply Current (volatile
V
0.6
1.0
mA
CC1
CC
CC
SCK
write/read)
Active, Read and Volatile Write states only)
V
= 2.25V, V- = -2.25V, f
= 5MHz; (for SPI
0.25
-0.3
-0.1
1.0
0.5
mA
mA
mA
mA
mA
mA
mA
µA
CC
SCK
Active, Read and Volatile Write states only)
I
V- Supply Current (volatile
write/read)
V- = -5.5V, V = 5.5V, f = 5MHz; (for SPI
Active, Read and Volatile Write states only)
-1.0
-0.5
V-1
CC
SCK
V- = -2.25V, V = 2.25V, f
Active, Read and Volatile Write states only)
= 5MHz; (for SPI
CC SCK
I
V
Supply Current
V
= 5.5V, V- = 5.5V, f = 5MHz; (for SPI
2.0
1.0
CC2
CC
CC
SCK
(non-volatile write/read)
Active, Read and Non-volatile Write states only)
V
= 2.25V, V- = -2.25V, f
= 5MHz; (for SPI
0.3
CC
SCK
Active, Read and Non-volatile Write states only)
I
V- Supply Current (non-volatile
write/read)
V- = -5.5V, V = 5.5V, f = 5MHz; (for SPI
Active, Read and Non-volatile Write states only)
-2.0
-1.0
-1.2
-0.4
0.5
V-2
CC
SCK
V- Supply Current (non-volatile
write/read)
V- = -2.25V, V = 2.25V, f
Active, Read and Non-volatile Write states only)
= 5MHz; (for SPI
CC SCK
I
V
Current (standby)
V
= +5.5V, V- = -5.5V @ +85°C, SPI interface
2.0
4.0
1.0
2.0
SB
CC
CC
in standby state
V
= +5.5V, V- = -5.5V @ +125°C, SPI
1.0
µA
CC
interface in standby state
V
= +2.25V, V- = -2.25V @ +85°C, SPI
0.2
µA
CC
interface in standby state
V
= +2.25V, V- = -2.25V @ +125°C, SPI
0.5
µA
CC
interface in standby state
FN6425 Rev 1.00
September 9, 2015
Page 6 of 20
ISL22424
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
TYP
SYMBOL
PARAMETER
V- Current (standby)
TEST CONDITIONS
MIN
(NOTE 4)
MAX
UNIT
I
V- = -5.5V, V = +5.5V @ +85°C, SPI interface
CC
-3.0
-0.7
µA
V-SB
in standby state
V- = -5.5V, V
= +5.5V @ +125°C, SPI
-5.0
-2.0
-3.0
-1.5
-0.3
-0.4
0.5
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µs
CC
interface in standby state
V- = -2.25V, V = +2.25V @ +85°C, SPI
CC
interface in standby state
V- = -2.25V, V = +2.25V @ +125°C, SPI
CC
interface in standby state
I
V
Current (shutdown)
V
= +5.5V, V- = -5.5V @ +85°C, SPI interface
2.0
4.0
1.0
2.0
SD
CC
CC
in standby state
V
= +5.5V, V- = -5.5V @ +125°C, SPI
1.0
CC
interface in standby state
V
= +2.25V, V- = -2.25V @ +85°C, SPI
0.2
CC
interface in standby state
V
= +2.25V, V- = -2.25V @ +125°C, SPI
0.5
CC
interface in standby state
I
V- Current (shutdown)
V- = -5.5V, V = +5.5V @ +85°C, SPI interface
CC
in standby state
-3.0
-5.0
-2.0
-3.0
-1
-0.7
-1.5
-0.3
-0.4
V-SD
V- = -5.5V, V
= +5.5V @ +125°C, SPI
CC
interface in standby state
V- = -2.25V, V = +2.25V @ +85°C, SPI
CC
interface in standby state
V- = -2.25V, V = +2.25V @ +125°C, SPI
interface in standby state
CC
I
Leakage current, at pins SCK,
SDI, SDO and CS
Voltage at pin from GND to V
1
LkgDig
CC
t
DCP wiper response time
CS rising edge to wiper new position
1.5
1.5
WRT
(Note 20)
t
DCP recall time from shutdown
CS rising edge to wiper stored position and RH
connection
µs
ShdnRec
(Note 20) mode
Vpor
Power-on recall voltage
ramp rate
Minimum Vcc at which memory recall occurs
1.9
0.2
2.1
5
V
VccRamp
V
V/ms
ms
CC
t
Power-up delay
V
above Vpor, to DCP Initial Value Register
CC
D
recall completed, and SPI Interface in standby
state
EEPROM SPECIFICATION
EEPROM Endurance
1,000,000
50
Cycles
Years
ms
EEPROM Retention
Temperature T +55ºC
t
Non-volatile Write Cycle time
12
20
WC
(Note 18)
SERIAL INTERFACE SPECIFICATIONS
V
SCK, SDI, and CS input buffer
LOW voltage
0.3 * V
V
V
IL
CC
V
SCK, SDI, and CS input buffer
HIGH voltage
0.7 * V
CC
IH
Hysteresis SCK, SDI, and CS input buffer
hysteresis
0.05 * V
0
V
CC
V
SDO output buffer LOW voltage
I
= 4mA for Open Drain output, pull-up
OL
0.4
2
V
OL
voltage Vpu = Vcc
R
SDO pull-up resistor off-chip
Maximum is determined by t
maximum bus load Cb = 30pF, f
and t
with
k
pu
(Note 19)
RO
FO
= 5MHz
SCK
FN6425 Rev 1.00
September 9, 2015
Page 7 of 20
ISL22424
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
TYP
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(NOTE 4)
MAX
UNIT
Cpin
SCK, SDI, SDO and CS pin
10
pF
(Note 20) capacitance
f
SPI frequency
5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
SCK
t
SPI clock cycle time
SPI clock high time
200
100
100
250
250
50
CYC
t
WH
t
SPI clock low time
WL
t
Lead time
LEAD
t
Lag time
LAG
t
SDI, SCK and CS input setup time
SDI, SCK and CS input hold time
SDI, SCK and CS input rise time
SDI, SCK and CS input fall time
SDO output Disable time
SDO output setup time
SDO output valid time
SDO output hold time
SDO output rise time
SDO output fall time
CS deselect time
SU
t
50
H
t
10
RI
t
10
20
FI
t
0
100
DIS
t
50
SO
t
150
0
V
t
HO
RO
t
R
R
= 2k, Cbus = 30pF
60
60
pu
pu
t
t
= 2k, Cbus = 30pF
FO
CS
2
NOTES:
4. Typical values are for T = +25°C and 3.3V supply voltage.
A
5. LSB: [V(RW)
255
– V(RW) ]/255. V(RW)
and V(RW) are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the
255 0
0
incremental voltage when changing from one tap to an adjacent tap.
6. ZS error = V(RW) /LSB.
0
7. FS error = [V(RW)
– V ]/LSB.
CC
255
8. DNL = [V(RW) – V(RW) ]/LSB-1, for i = 1 to 255. i is the DCP register setting.
i-1
i
9. INL = [V(RW) – i • LSB – V(RW)]/LSB for i = 1 to 255.
i
10. V
11.
= [V(RWx)i -V(RWy)i]/LSB, for i = 0 to 255, x = 0 to 1, y = 0 to 1.
MATCH
MaxVRW – MinVRW
6
10
i
i
for i = 16 to 240 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper
MaxVRW + MinVRW 2 165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.
--------------------------------------------------------------------------------------------- ----------------
TC
=
V
+
i
i
12. MI = |RW
– RW |/255. MI is a minimum increment. RW and RW are the measured resistances for the DCP register set to FF hex and
255 0
255
0
00 hex respectively.
13. Roffset = RW /MI, when measuring between RW and RL.
0
Roffset = RW
/MI, when measuring between RW and RH.
255
14. RDNL = (RW – RW )/MI -1, for i = 1 to 255.
i
i-1
15. RINL = [RW – (MI • i) – RW ]/MI, for i = 1 to 255.
i
0
16. R
17.
= [(Rx)i -(Ry)i]/MI, for i = 0 to 255, x = 0 to 1, y = 0 to 1.
6
MATCH
MaxRi – MinRi
10
for i = 16 to 240, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min ( ) is
the minimum value of the resistance over the temperature range.
--------------------------------------------------------------- ----------------
TC
=
R
165°C
MaxRi + MinRi 2
+
18. t
is the time from the end of a Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle.
WC
19. R is specified for the highest data rate transfer for the device. Higher value pull-up can be used at lower data rates.
pu
20. This parameter is not 100% tested.
FN6425 Rev 1.00
September 9, 2015
Page 8 of 20
ISL22424
DCP Macro Model
R
TOTAL
RH
RL
C
L
C
H
C
W
10pF
10pF
25pF
RW
Timing Diagrams
Input Timing
t
CS
CS
t
t
t
LAG
LEAD
CYC
SCK
...
t
t
t
RI
FI
t
t
WH
t
WL
SU
H
...
MSB
LSB
SDI
HIGH IMPEDANCE
SDO
Output Timing
CS
SCK
SDO
SDI
...
...
t
t
t
DIS
SO
HO
MSB
LSB
t
V
ADDR
XDCP Timing (for All Load Instructions)
CS
t
WRT
SCK
...
...
MSB
LSB
SDI
V
W
HIGH IMPEDANCE
SDO
FN6425 Rev 1.00
September 9, 2015
Page 9 of 20
ISL22424
Typical Performance Curves
80
2.0
1.5
1.0
0.5
0
T = +125ºC
70
60
50
40
30
20
10
0
T = +25ºC
T = -40ºC
I
CC
-0.5
-1.0
-1.5
-2.0
I
V-
0
50
100
150
200
250
-40
0
40
TEMPERATURE (°C)
80
120
TAP POSITION (DECIMAL)
FIGURE 2. STANDBY I
and I vs TEMPERATURE
V-
FIGURE 1. WIPER RESISTANCE vs TAP POSITION
[ I(RW) = V /R ] FOR 10k (W)
CC
CC TOTAL
0.50
0.50
0.25
0
V
= 5.5V
CC
T = +25ºC
T = +25ºC
V
= 2.25V
CC
0.25
0
-0.25
-0.50
-0.25
-0.50
V
= 5.5V
V
= 2.25V
100
CC
100
TAP POSITION (DECIMAL)
CC
0
50
150
200
250
0
50
150
200
250
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10k (W)
MODE FOR 10k (W)
2.0
0
10k
1.6
1.2
-1
V
= 2.25V
CC
50k
V
= 5.5V
CC
-2
0.8
-3
-4
50k
10k
V
= 2.25V
V
= 5.5V
CC
CC
0.4
0
-5
-40
0
40
80
120
-40
0
40
TEMPERATURE (ºC)
80
120
TEMPERATURE (ºC)
FIGURE 6. FS ERROR vs TEMPERATURE
FIGURE 5. ZS ERROR vs TEMPERATURE
FN6425 Rev 1.00
September 9, 2015
Page 10 of 20
ISL22424
Typical Performance Curves (Continued)
0.5
2.0
T = +25ºC
T = +25ºC
V
= 5.5V
1.5
1.0
CC
V
= 2.25V
0.25
0
CC
0.5
0
-0.25
-0.50
V
= 2.25V
100
CC
V
= 5.5V
CC
-0.5
0
50
150
200
250
0
50
100
150
200
250
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR
FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR
10k (W)
10k (W)
200
1.60
10k
160
1.20
10k
120
80
0.80
5.5V
0.40
0.00
50k
40
50k
2.25V
0
-0.40
16
66
116
166
216
266
-40
0
40
80
120
TAP POSITION (DECIMAL)
TEMPERATURE (ºC)
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
FIGURE 9. END TO END R
% CHANGE vs
TOTAL
TEMPERATURE
500
400
300
INPUT
OUTPUT
10k
200
100
50k
WIPER AT MID POINT (POSITION 80h)
R
= 10k
TOTAL
0
16
66
116
166
216
TAP POSITION (DECIMAL)
FIGURE 12. FREQUENCY RESPONSE (1MHz)
FIGURE 11. TC FOR RHEOSTAT MODE IN ppm
FN6425 Rev 1.00
September 9, 2015
Page 11 of 20
ISL22424
Typical Performance Curves (Continued)
CS
SCL
WIPER UNLOADED,
MOVEMENT FROM 0h to FFh
WIPER
FIGURE 13. MIDSCALE GLITCH, CODE 7Fh TO 80h
FIGURE 14. LARGE SIGNAL SETTLING TIME
in at the rising edge of the serial clock SCK, while the CS input
is low.
Pin Description
Potentiometer Pins
CHIP SELECT (CS)
RHI AND RLI
CS LOW enables the ISL22424, placing it in the active power
mode. A HIGH to LOW transition on CS is required prior to the
start of any operation after power up. When CS is HIGH, the
ISL22424 is deselected and the SDO pin is at high impedance,
and (unless an internal write cycle is underway) the device will
be in the standby state.
The high (RHi) and low (RLi) terminals of the ISL22424 are
equivalent to the fixed terminals of a mechanical potentiometer.
RHi and RLi are referenced to the relative position of the wiper
and not the voltage potential on the terminals. With WRi set to 255
decimal, the wiper will be closest to RHi, and with the WRi set to
0, the wiper is closest to RLi.
Principles of Operation
RWI
The ISL22424 is an integrated circuit incorporating two DCPs
with their associated registers, non-volatile memory and the
SPI serial interface providing direct communication between
host, potentiometers and memory. The resistor arrays are
comprised of individual resistors connected in a series. At
either end of the array and between each resistor is an
electronic switch that transfers the potential at that point to the
wiper.
RWi is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WRi register.
Bus Interface Pins
SERIAL CLOCK (SCK)
This is the serial clock input of the SPI serial interface.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
SERIAL DATA OUTPUT (SDO)
The SDO is a serial data output pin. During a read cycle, the
data bits are shifted out on the falling edge of the serial clock
SCK and will be available to the master on the following rising
edge of SCK.
When the device is powered down, the last value stored in IVRi
will be maintained in the non-volatile memory. When power is
restored, the content of the IVRi is recalled and loaded into the
corresponding WRi to set the wiper to the initial position.
The output type is configured through ACR[1] bit for Push - Pull
or Open Drain operation. Default setting for this pin is Push -
Pull. An external pull up resistor is required for Open Drain
output operation. Note: the external pull up voltage not allowed
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each DCP
are equivalent to the fixed terminals of a mechanical
beyond V
.
CC
potentiometer (RHi and RLi pins). The RWi pin of the DCP is
connected to intermediate nodes, and is equivalent to the wiper
terminal of a mechanical potentiometer. The position of the
wiper terminal within the DCP is controlled by an 8-bit volatile
Wiper Register (WRi). When the WRi of a DCP contains all
zeroes (WRi[7:0]= 00h), its wiper terminal (RWi) is closest to its
SERIAL DATA INPUT (SDI)
The SDI is the serial data input pin for the SPI interface. It
receives device address, operation code, wiper address and
data from the SPI remote host device. The data bits are shifted
FN6425 Rev 1.00
September 9, 2015
Page 12 of 20
ISL22424
“Low” terminal (RLi). When the WRi register of a DCP contains
all ones (WRi[7:0]= FFh), its wiper terminal (RWi) is closest to its
“High” terminal (RHi). As the value of the WRi increases from all
zeroes (0) to all ones (255 decimal), the wiper moves
monotonically from the position closest to RLi to the closest to
RHi. At the same time, the resistance between RWi and RLi
increases monotonically, while the resistance between RHi and
RWi decreases monotonically.
The register at address 0Fh is a read-only reserved register.
Information read from this register should be ignored.
The non-volatile IVRi and volatile WRi registers are accessible
with the same address.
The Access Control Register (ACR) contains information and
control bits described below in Table 2.
The VOL bit (ACR[7]) determines whether the access to wiper
registers WRi or initial value registers IVRi.
While the ISL22424 is being powered up, the WRi is reset to
80h (128 decimal), which locates RWi roughly at the center
between RLi and RHi. After the power supply voltage becomes
large enough for reliable non-volatile memory reading, the WRi
will be reloaded with the value stored in a corresponding non-
volatile Initial Value Register (IVRi).
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT #
7
6
5
4
0
3
0
2
0
1
0
0
BIT
VOL SHDN WIP
SDO
NAME
If VOL bit is 0, the non-volatile IVRi and General Purpose
The WRi and IVRi can be read or written to directly using the
SPI serial interface as described in the following sections.
registers are accessible. If VOL bit is 1, only the volatile WRi
are accessible. Note: value that is written to IVRi register also
is written to the corresponding WRi. The default value of this
bit is 0.
Memory Description
The ISL22424 contains two non-volatile 8-bit Initial Value
Registers (IVRi), thirteen non-volatile 8-bit General Purpose
(GP) registers, two volatile 8-bit Wiper Registers (WRi), and
volatile 8-bit Access Control Register (ACR). The memory map
of ISL22424 is in Table 1.
The SHDN bit (ACR[6]) disables or enables Shutdown mode.
When this bit is 0, DCP is in Shutdown mode, i.e. each DCP is
forced to end-to-end open circuit and RWi is shorted to RLi as
shown on Figure 15. Default value of SHDN bit is 1.
TABLE 1. MEMORY MAP
RHi
ADDRESS
(hex)
10
F
NON-VOLATILE
VOLATILE
N/A
ACR
RWi
Reserved
E
D
C
B
A
9
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
IVR1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
WR1
WR0
RLi
FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE
Setting SHDN bit to 1 is returned wipers to prior to Shutdown
Mode position.
The WIP bit (ACR[5]) is a read-only bit. It indicates that non-
volatile write operation is in progress. The WIP bit can be read
repeatedly after a non-volatile write to determine if the write
has been completed. It is impossible to write or read to the WRi
or ACR while WIP bit is 1.
8
7
6
5
The SDO bit (ACR[1]) configures type of SDO output pin. The
default value of SDO bit is 0 for Push - Pull output. SDO pin
can be configured as Open Drain output for some application.
In this case, an external pull up resistor is required. See
“Applications Information” on page 15.
4
3
2
1
SPI Serial Interface
0
IVR0
The ISL22424 supports an SPI serial protocol, mode 0. The
device is accessed via the SDI input and SDO output with data
clocked in on the rising edge of SCK, and clocked out on the
falling edge of SCK. CS must be LOW during communication
with the ISL22424. SCK and CS lines are controlled by the
host or master. The ISL22424 operates only as a slave device.
The non-volatile registers (IVRi) at address 0 and 1, contain
initial wiper position and volatile registers (WRi) contain current
wiper position.
FN6425 Rev 1.00
September 9, 2015
Page 13 of 20
ISL22424
All communication over the SPI interface is conducted by
sending the MSB of each byte of data first.
LOW. Then host must send a valid Instruction Byte followed by
one or more Data Bytes to SDI pin. The host terminates the
write operation by pulling the CS pin from LOW to HIGH.
Instruction is executed on rising edge of CS. For a write-to
address 0 or 1, the MSB of the byte at address 10h (ACR[7])
determines if the Data Byte is to be written to volatile or both
volatile and non-volatile registers. Refer to “Memory
Description” and Figure 16. Note: the internal non-volatile write
cycle starts with the rising edge of CS and requires up to 20ms.
During non-volatile write cycle the read operation to ACR
register is allowed to check WIP bit.
Protocol Conventions
The SPI protocol contains Instruction Byte followed by one or
more Data Bytes. A valid Instruction Byte contains instruction
as the three MSBs, with the following five register address bits
(see Table 3).
The next byte sent to the ISL22424 is the Data Byte.
TABLE 3. INSTRUCTION BYTE FORMAT
Read Operation
BIT #
7
6
5
4
3
2
1
0
A Read operation to the ISL22424 is a four byte operation. It
requires first, the CS transition from HIGH to LOW. Then the
host must send a valid Instruction Byte followed by “dummy”
Data Byte, a NOP Instruction Byte and another “dummy” Data
Byte to SDI pin. The SPI host receives the Instruction Byte
(instruction code + register address) and requested Data Byte
from SDO pin on rising edge of SCK during third and fourth
bytes respectively. The host terminates the read operation by
pulling the CS pin from LOW to HIGH (see Figure 17). Reading
from the IVRi will not change the WRi, if its contents are
different.
I2
I1
I0
R4
R3
R2
R1
R0
Table 4 contains a valid instruction set for ISL22424.
There are only sixteen register addresses possible for this
DCP. If the [R4:R0] bits are 00000 or 00001, then the read or
write is to either the IVRi or the WRi registers (depends of VOL
bit at ACR). If the [R4:R0] are 10000, then the operation is on
the ACR.
Write Operation
A Write operation to the ISL22424 is a two or more bytes
operation. First, It requires, the CS transition from HIGH to
TABLE 4. INSTRUCTION SET
INSTRUCTION SET
I2
0
I1
0
I0
0
R4
X
R3
X
R2
X
R1
X
R0
X
OPERATION
NOP
0
0
1
X
X
X
X
X
ACR READ
ACR WRITE
0
1
1
X
X
X
X
X
1
0
0
R4
R4
R3
R3
R2
R2
R1
R1
R0
R0
WR, IVR, GP or ACR READ
WR, IVR, GP or ACR WRITE
1
1
0
where X means “do not care”.
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
DATA BYTE
WR INSTRUCTION
ADDR
SDI
SDO
FIGURE 16. TWO BYTE WRITE SEQUENCE
FN6425 Rev 1.00
September 9, 2015
Page 14 of 20
ISL22424
1
8
16
24
32
CS
SCK
NOP
RD
RD
ADDR
SDI
ADDR
READ DATA
SDO
FIGURE 17. FOUR BYTE READ SEQUENCE
DCP(N-1). The write instruction is executed on the rising edge
of CS for all N DCPs simultaneously.
Applications Information
Communicating with ISL22424
Daisy Chain Read Operation
Communication with ISL22424 proceeds using SPI interface
through the ACR (address 10000b), IVRi (address 00000b,
00001b), WRi (addresses 00000b, 00001b) and General
Purpose registers (addresses from 00010b to 01110b).
The read operation consists of two parts: first, send read
instructions (N two bytes operation) with valid address;
second, read the requested data while sending NOP
instructions (N two bytes operation) as shown on Figure 20
and Figure 21.
The wiper position of each potentiometer is controlled by the
corresponding WRi register. Writes and reads can be made
directly to these registers to control and monitor the wiper
position without any non-volatile memory changes. This is
done by setting MSB bit at address 10000b to 1 (ACR[7] = 1).
The first part starts by HIGH to LOW transition on CS line,
followed by N two bytes read instruction on SDI line with
reversed chain access sequence: the instruction byte +
dummy data byte for the last DCP in chain is going first,
followed by LOW to HIGH transition on CS line. The read
instructions are executed during second part of read
sequence. It also starts by HIGH to LOW transition on CS line,
followed by N two bytes NOP instructions on SDI line and LOW
to HIGH transition of CS. The data is read on every even byte
during second part of read sequence while every odd byte
contains instruction code + address from which the data is
being read.
The non-volatile IVRi stores the power up position of the wiper.
IVRi is accessible when MSB bit at address 10000b is set to 0
(ACR[7] = 0). Writing a new value to the IVRi register will set a
new power up position for the wiper. Also, writing to this
registers will load the same value into the corresponding WRi
as the IVRi. Reading from the IVRi will not change the WRi, if
its contents are different.
Daisy Chain Configuration
When application needs more then one ISL22424, it can
Wiper Transition
communicate with all of them without additional CS lines by daisy
chaining the DCPs as shown on Figure 18. In Daisy Chain
configuration the SDO pin of previous chip is connected to SDI pin
of the following chip, and each CS and SCK pins are connected to
the corresponding microcontroller pins in parallel, like regular SPI
interface implementation. The Daisy Chain configuration can also
be used for simultaneous setting of multiple DCPs. Note, the
number of daisy chained DCPs is limited only by the driving
capabilities of SCK and CS pins of microcontroller; for larger
number of SPI devices buffering of SCK and CS lines is required.
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients, or overshoot/undershoot, resulting from the sudden
transition from a very low impedance “make” to a much higher
impedance “break within an extremely short period of time
(<50ns). Two such code transitions are EFh to F0h, and 0Fh to
10h. Note, that all switching transients will settle well within the
settling time as stated on the datasheet. A small capacitor can
be added externally to reduce the amplitude of these voltage
transients, but that will also reduce the useful bandwidth of the
circuit, thus may not be a good solution for some applications.
It may be a good idea, in that case, to use fast amplifiers in a
signal chain for fast recovery.
Daisy Chain Write Operation
The write operation starts by HIGH to LOW transition on CS
line, followed by N two bytes write instructions on SDI line with
reversed chain access sequence: the instruction byte + data
byte for the last DCP in chain is going first, as shown on Figure
19. The serial data is going through DCPs from DCP0 to
DCP(N-1) as follow: DCP0 --> DCP1 --> DCP2 --> ... -->
FN6425 Rev 1.00
September 9, 2015
Page 15 of 20
ISL22424
gain of the EL8173 from 90 to 110 with 5V output for 10A
current through current sense resistor.
Application Example
Figure 22 shows an example of using ISL22424 for gain setting
and offset correction in high side current measurement
application. DCP0 applies a programmable offset voltage of
±25mV to the FB+ pin of the Instrumentation Amplifier EL8173
to adjust output offset to zero voltages. DCP1 programs the
More application examples can be found at
http://www.intersil.com/data/an/AN1145.pdf
N DCP IN A CHAIN
CS
SCK
DCP0
DCP1
DCP2
DCP(N-1)
CS
MOSI
MISO
CS
CS
CS
SCK
SDI
SCK
SDI
SCK
SDI
SCK
SDI
µC
SDO
SDO
SDO
SDO
FIGURE 18. DAISY CHAIN CONFIGURATION
CS
SCK
16 CLKS
C P0
16 CLKLS
P2
16 CLKS
WR
D C
WR
D
D
C
P1
P2
WR
WR
D
SDI
D
C P1
SDO 0
WR
C
WR
D
C P2
SDO 1
SDO 2
FIGURE 19. DAISY CHAIN WRITE SEQUENCE OF N = 3 DCP
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
SDI
INSTRUCTION
ADDR
DATA IN
SDO
DATA OUT
FIGURE 20. TWO BYTE OPERATION
FN6425 Rev 1.00
September 9, 2015
Page 16 of 20
ISL22424
CS
SCK
SDI
16 CLKS
RD DCP2
16 CLKS
RD DCP1
16 CLKS
RD DCP0
16 CLKS
NOP
16 CLKS
NOP
16 CLKS
NOP
DCP0 OUT
DCP2 OUT
DCP1 OUT
SDO
FIGURE 21. DAISY CHAIN READ SEQUENCE OF N = 3 DCP
1.2V
PROCESSOR LOAD
10A, MAX
DC/DC CONVERTER
OUTPUT
0.005
+5V
8
10k
10k
0.1µF
EL8173IS
1
V +
S
3
2
7
5
IN+
IN-
EN
6
V
V
= 0V to + 5V to ADC
OUT
OUT
FB+
+5V
R
4
FB-
V -
S
150k, 1%
R
1
4
50k, 1%
RH1
RL1
RH0
RW1
R
5
309, 1%
R
2
1k, 1%
RW0
RL0
50k
50k
DCP0 (1/2 ISL22424U)
PROGRAMMABLE OFFSET ±25mV
DCP1 (1/2 ISL22424U)
PROGRAMMABLE GAIN 90 TO 110
R
6
R
3
1.37k, 1%
50k, 1%
-5V
ISL22424UFV14Z
14
1
2
3
+5V
Vcc
RH0
RL0
RW0
DCP0
DCP1
10
9
12
13
7
SCL
SDO
SDI
CS
SPI bus
4
5
6
RH1
RL1
RW1
NC
11
8
GND
-5V
V-
FIGURE 22. CURRENT SENSING WITH GAIN AND OFFSET CONTROL
FN6425 Rev 1.00
September 9, 2015
Page 17 of 20
ISL22424
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure
that you have the latest revision.
DATE
REVISION
CHANGE
September 9, 2015
FN6425.1
- Ordering Information Table on page 2.
- Added Revision History.
- Added About Intersil Verbiage.
- Updated POD L16.4X4A to latest revision changes are as follow:
Updated to new POD format by removing table listing dimensions and moving dimensions onto drawing.
Added Typical Recommended Land Pattern. Removed package option.
- Updated POD M14.173 to most current version changes are as follow:
Updated drawing to remove table and added land pattern.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2007-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6425 Rev 1.00
September 9, 2015
Page 18 of 20
ISL22424
Package Outline Drawing
L16.4x4A
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 3, 03/15
2.40
4.00
A
4X 1.50
6
B
PIN #1
INDEX AREA
13
16
6
PIN 1
INDEX AREA
12
0.50
1
4
12X
2.40
9
(4X)
0.15
5
8
0.10 M C A B
TOP VIEW
16x 0.40±0.01
+0.05
0.25
4
-0.07
BOTTOM VIEW
SEE
DETAIL "X"
0.90±0.10
C
0.10
SEATING
PLANE
0.08 C
C
SIDE VIEW
(3.8 TYP)
(
2.40)
(12x 0.50)
5
C
0.20 REF
(16x 0.25)
(16x 0.60)
+0.03/-0.02
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3. Unless otherwise specified, tolerance: Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be either
a mold or mark feature.
FN6425 Rev 1.00
September 9, 2015
Page 19 of 20
ISL22424
Package Outline Drawing
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09
A
1
3
5.00 ±0.10
SEE
DETAIL "X"
14
8
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
1
7
0.20 C B A
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
GAUGE
PLANE
0.25
5
0.25 +0.05/-0.06
0.10 CBA
0°-8°
0.60 ±0.15
0.05 MIN
0.15 MAX
0.10 C
SIDE VIEW
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
(5.65)
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.80mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead is 0.07mm.
6. Dimension in ( ) are for reference only.
(0.65 TYP)
(0.35 TYP)
7. Conforms to JEDEC MO-153, variation AB-1.
TYPICAL RECOMMENDED LAND PATTERN
FN6425 Rev 1.00
September 9, 2015
Page 20 of 20
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