ISL2101AAR3ZT [RENESAS]
IC HALF BRDG BASED MOSFET DRIVER, PDSO9, 3 X 3 MM, ROHS COMPLIANT, PLASTIC, MO-229-WEED-3, DFN-9, MOSFET Driver;
| 型号： | ISL2101AAR3ZT |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC HALF BRDG BASED MOSFET DRIVER, PDSO9, 3 X 3 MM, ROHS COMPLIANT, PLASTIC, MO-229-WEED-3, DFN-9, MOSFET Driver 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总10页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL2100A, ISL2101A
®
Data Sheet
June 8, 2006
FN6294.0
100V, 2A Peak, High Frequency
Half-Bridge Drivers
Features
• Drives N-Channel MOSFET Half-Bridge
• Space-Saving DFN Package
The ISL2100A, ISL2101A are 100V, high frequency,
half-bridge N-channel power MOSFET driver ICs. They are
based on the popular HIP2100, HIP2101 half-bridge drivers,
but offer several performance improvements. The ISL2100A
has additional input hysteresis for superior operation in noisy
environments and the inputs of the ISL2101A, like those of
the ISL2100A, can now safely swing to the V
Finally, both parts are available in a very compact 9 Ld DFN
package to minimize the required PCB footprint.
• DFN Package Compliant with 100V Conductor Spacing
Guidelines per IPC-2221
• Pb-Free Plus Anneal Available (RoHS Compliant)
• Bootstrap Supply Max Voltage to 114VDC
• On-Chip 1Ω Bootstrap Diode
supply rail.
DD
• Fast Propagation Times for Multi-MHz Circuits
• Drives 1nF Load with Typical Rise/Fall Times of 10ns
• CMOS Compatible Input Thresholds (ISL2100A)
• 3.3V/TTL Compatible Input Thresholds (ISL2101A)
• Independent Inputs Provide Flexibility
Ordering Information
PART
NUMBER
PART
TEMP.
PACKAGE
PKG.
(Notes 1, 2) MARKING RANGE (°C)
(Pb-Free) DWG. #
ISL2100AAR3Z 00AZ
ISL2101AAR3Z 01AZ
NOTES:
-40 to 125 9 Ld 3x3 DFN L9.3x3
-40 to 125 9 Ld 3x3 DFN L9.3x3
• No Start-Up Problems
• Outputs Unaffected by Supply Glitches, HS Ringing Below
Ground or HS Slewing at High dv/dt
1. Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS
compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
• Low Power Consumption
• Wide Supply Voltage Range (9V to 14V)
• Supply Undervoltage Protection
• 2.5Ω Typical Output Pull-Up/Pull-Down Resistance
2. Add “-T” suffix for Tape and Reel packing option.
Applications
• Telecom Half-Bridge Converters
• Telecom Full-Bridge Converters
• Two-Switch Forward Converters
• Active-Clamp Forward Converters
• Class-D Audio Amplifiers
Pinouts
ISL2100A, ISL2101A (DFN)
TOP VIEW
V
LO
V
1
9
8
7
6
5
DD
SS
HB
HO
HS
LI
2
3
4
EPAD
HI
NC
NOTE: EPAD = Exposed PAD.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006. All Rights Reserved.
1
All other trademarks mentioned are the property of their respective owners.
ISL2100A, ISL2101A
Application Block Diagram
+12V
+100V
SECONDARY
CIRCUIT
V
DD
HB
DRIVE
HI
HO
HS
LO
HI
LI
PWM
CONTROLLER
DRIVE
LO
ISL2100A
ISL2101A
REFERENCE
AND
ISOLATION
V
SS
Functional Block Diagram
HB
HO
V
DD
HI
UNDER
VOLTAGE
LEVEL SHIFT
DRIVER
HS
ISL2101A
ISL2101A
UNDER
VOLTAGE
LO
DRIVER
LI
V
SS
EPAD (DFN Package Only)
*EPAD = Exposed Pad. The EPAD is electrically isolated from all other pins. For
best thermal performance connect the EPAD to the PCB power ground plane.
FN6294.0
June 8, 2006
2
ISL2100A, ISL2101A
+48V
+12V
SECONDARY
CIRCUIT
ISL2100A
ISL2101A
PWM
ISOLATION
FIGURE 1. TWO-SWITCH FORWARD CONVERTER
+48V
SECONDARY
CIRCUIT
+12V
ISL2100A
ISL2101A
PWM
ISOLATION
FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE-CLAMP
FN6294.0
June 8, 2006
3
ISL2100A, ISL2101A
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V
LI and HI Voltages (Note 4) . . . . . . . . . . . . . . . -0.3V to V
Voltage on LO (Note 4) . . . . . . . . . . . . . . . . . . -0.3V to V
Voltage on HO (Note 4) . . . . . . . . . . . . . . V
Voltage on HS (Continuous) (Note 4) . . . . . . . . . . . . . . -1V to 110V
Voltage on HB (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118V
V
- V
(Notes 3, 4) . . . . . . . -0.3V to 18V
Thermal Resistance (Typical)
θ
(°C/W)
55
θ
JC
(°C/W)
7.5
DD, HB
HS
JA
+ 0.3V
+ 0.3V
+ 0.3V
DD
DD
HB
DFN (Note 5) . . . . . . . . . . . . . . . . . . . .
Max Power Dissipation at 25°C in Free Air (DFN, Note 5) . . . . 2.27W
Storage Temperature Range . . . . . . . . . . . . . . . . . . .-65°C to 150°C
Junction Temperature Range. . . . . . . . . . . . . . . . . . .-55°C to 150°C
Lead Temperature (Soldering 10s - SOIC Lead Tips Only) . . 300°C
For Recommended soldering conditions see Tech Brief TB389.
- 0.3V to V
HS
Average Current in V
to HB Diode . . . . . . . . . . . . . . . . . . 100mA
DD
Maximum Recommended Operating Conditions
Supply Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 14V
DD
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V
Voltage on HS . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V
Voltage on HB . . V + 8V to V + 14V and V
- 1V to V + 100V
HS HS DD
DD
HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the recommended operating conditions of this specification is not implied.
NOTES:
3. The ISL2100A-01A are capable of derated operation at supply voltages exceeding 14V. Figure 22 shows the high-side voltage derating curve
for this mode of operation.
4. All voltages referenced to V unless otherwise specified.
SS
5. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. For θ
JA
JC,
the “case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379 for details.
Electrical Specifications
V
= V
= 12V, V = V
SS
= 0V, No Load on LO or HO, Unless Otherwise Specified
HS
DD
HB
T = -40°C to
J
T
= 25°C
125°C
J
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP MAX
MIN
MAX UNITS
SUPPLY CURRENTS
V
V
V
V
Quiescent Current
Quiescent Current
Operating Current
Operating Current
I
I
ISL2100A; LI = HI = 0V
ISL2101A; LI = HI = 0V
ISL2100A; f = 500kHz
ISL2101A; f = 500kHz
LI = HI = 0V
-
-
-
-
-
-
-
-
0.1
0.3
1.6
1.9
0.1
2.0
0.05
0.9
0.25
0.45
2.2
2.5
0.15
2.5
1
-
-
-
-
-
-
-
-
0.3
0.55
2.7
3
mA
mA
mA
mA
mA
mA
µA
DD
DD
DD
DD
DD
DD
I
I
DDO
DDO
Total HB Quiescent Current
Total HB Operating Current
I
0.2
3
HB
I
f = 500kHz
HBO
HB to V Current, Quiescent
SS
I
LI = HI = 0V; V
HB
= V
= 114V
10
-
HBS
HS
= V = 114V
HS
HB to V Current, Operating
SS
I
f = 500kHz; V
-
mA
HBSO
HB
INPUT PINS
Low Level Input Voltage Threshold
Low Level Input Voltage Threshold
V
V
ISL2100A
ISL2101A
ISL2100A
ISL2101A
ISL2100A
3.7
4.4
1.8
6.6
1.8
2.2
210
-
-
2.7
1.2
-
-
-
V
V
IL
IL
1.4
High Level Input Voltage Threshold
High Level Input Voltage Threshold
Input Voltage Hysteresis
V
V
-
-
-
-
7.4
2.2
-
8.4
2.4
-
V
IH
-
V
IH
V
-
V
IHYS
Input Pull-down Resistance
R
-
100
500
kΩ
I
UNDER VOLTAGE PROTECTION
V
V
Rising Threshold
V
V
V
V
6.8
-
7.3
0.6
6.9
0.6
7.8
-
6.5
-
8.1
-
V
V
V
V
DD
DD
DDR
DDH
HBR
HBH
Threshold Hysteresis
HB Rising Threshold
6.2
-
7.5
-
5.9
-
7.8
-
HB Threshold Hysteresis
FN6294.0
June 8, 2006
4
ISL2100A, ISL2101A
Electrical Specifications
V
= V
= 12V, V = V
SS
= 0V, No Load on LO or HO, Unless Otherwise Specified (Continued)
HS
DD
HB
T = -40°C to
J
T
= 25°C
125°C
J
PARAMETERS
BOOT STRAP DIODE
Low Current Forward Voltage
High Current Forward Voltage
Dynamic Resistance
SYMBOL
TEST CONDITIONS
MIN
TYP MAX
MIN
MAX UNITS
V
I
I
I
= 100µA
= 100mA
= 100mA
-
-
-
0.5
0.7
0.8
0.6
0.9
1
-
-
-
0.7
1
V
V
Ω
DL
VDD-HB
VDD-HB
VDD-HB
V
DH
R
1.5
D
LO GATE DRIVER
Low Level Output Voltage
High Level Output Voltage
Peak Pull-Up Current
V
I
I
= 100mA
-
-
-
-
0.25
0.25
2
0.3
0.3
-
-
-
-
-
0.4
0.4
-
V
V
A
A
OLL
OHL
OHL
LO
LO
V
= -100mA, V
OHL
= V
- V
DD LO
I
V
V
= 0V
LO
LO
Peak Pull-Down Current
HO GATE DRIVER
I
= 12V
2
-
-
OLL
Low Level Output Voltage
High Level Output Voltage
Peak Pull-Up Current
V
I
I
= 100mA
-
-
-
-
0.25
0.25
2
0.3
0.3
-
-
-
-
-
0.4
0.4
-
V
V
A
A
OLH
OHH
OHH
HO
HO
V
= -100mA, V
= V - V
HB
OHH
HO
I
V
V
= 0V
HO
HO
Peak Pull-Down Current
I
= 12V
2
-
-
OLH
Switching Specifications
V
= V
= 12V, V = V = 0V, No Load on LO or HO, Unless Otherwise Specified
SS HS
DD
HB
T
= -40°C
J
T
= 25°C
to 125°C
J
TEST
PARAMETERS
SYMBOL
CONDITIONS
MIN TYP MAX MIN MAX UNITS
Lower Turn-Off Propagation Delay (LI Falling to LO Falling)
Upper Turn-Off Propagation Delay (HI Falling to HO Falling)
Lower Turn-On Propagation Delay (LI Rising to LO Rising)
Upper Turn-On Propagation Delay (HI Rising to HO Rising)
Delay Matching: Upper Turn-Off to Lower Turn-On
Delay Matching: Lower Turn-Off to Upper Turn-On
Either Output Rise/Fall Time (10% to 90%/90% to 10%)
Either Output Rise/Fall Time (3V to 9V/9V to 3V)
Minimum Input Pulse Width that Changes the Output
Bootstrap Diode Turn-On or Turn-Off Time
t
-
-
34
31
39
39
8
50
50
50
50
-
-
-
-
-
-
-
-
-
-
-
60
60
60
60
16
16
-
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
LPHL
t
t
HPHL
t
-
LPLH
HPLH
-
t
1
1
-
MON
t
6
-
MOFF
t
t
C = 1nF
10
0.5
-
-
RC, FC
L
t
t
C = 0.1µF
-
0.6
-
0.8
50
-
R, F
L
t
-
PW
t
-
10
-
BS
FN6294.0
June 8, 2006
5
ISL2100A, ISL2101A
Pin Descriptions
SYMBOL
DESCRIPTION
V
Positive supply to lower gate driver. Bypass this pin to V
.
SS
DD
HB
High-side bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin. Bootstrap
diode is on-chip.
HO
HS
HI
High-side output. Connect to gate of high-side power MOSFET.
High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this pin.
High-side input.
LI
Low-side input.
V
Chip negative supply, which will generally be ground.
SS
LO
Low-side output. Connect to gate of low-side power MOSFET.
Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
EPAD
Timing Diagrams
LI
HI
HI,
LI
t
t
,
t
t
,
HPLH
HPHL
LPHL
LO
HO
LPLH
t
t
MOFF
MON
HO,
LO
FIGURE 3. PROPAGATION DELAYS
FIGURE 4. DELAY MATCHING
Typical Performance Curves
10
10
1
1
0.1
0.1
3
3
.
.
1 10
10
100
1 10
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
T = -40C
T = 25C
T = -40C
T = 25C
T = 125C
T = 150C
T = 125C
T = 150C
FIGURE 5. ISL2100A IDD OPERATING CURRENT vs
FREQUENCY
FIGURE 6. ISL2101A IDD OPERATING CURRENT vs
FREQUENCY
FN6294.0
June 8, 2006
6
ISL2100A, ISL2101A
Typical Performance Curves (Continued)
10
1
10
1
0.1
0.01
0.1
0.01
3
3
.
.
1 10
10
100
1 10
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
T = -40C
T = -40C
T= 25C
T = 25C
T = 125C
T = 150C
T = 125C
T = 150C
FIGURE 7. IHB OPERATING CURRENT vs FREQUENCY
FIGURE 8. IHBS OPERATING CURRENT vs FREQUENCY
450
400
350
300
250
200
150
500
450
400
350
300
250
200
150
50
0
50
100
150
50
0
50
100
150
TEMPERATURE (C)
TEMPERATURE (C)
VDD = VHB = 9V
VDD = VHB = 12V
VDD = VHB = 14V
VDD = VHB = 9V
VDD = VHB = 12V
VDD = VHB = 14V
FIGURE 9. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE
FIGURE 10. LOW LEVEL OUTPUT VOLTAGE vs
TEMPERATURE
7.6
7.4
7.2
7
0.6
0.55
0.5
0.45
0.4
6.8
50
0
50
100
150
50
0
50
100
150
TEMPERATURE (C)
TEMPERATURE (C)
VDDR
VHBR
VDDH
VHBH
FIGURE 11. UNDERVOLTAGE LOCKOUT THRESHOLD vs
TEMPERATURE
FIGURE 12. UNDERVOLTAGE LOCKOUT HYSTERESIS vs
TEMPERATURE
FN6294.0
June 8, 2006
7
ISL2100A, ISL2101A
Typical Performance Curves (Continued)
55
50
45
40
35
30
25
20
55
50
45
40
35
30
25
20
50
0
50
100
150
50
0
50
100
150
TEMPERATURE (C)
TEMPERATURE (C)
tLPLH
tLPHL
tHPLH
tHPHL
tLPLH
tLPHL
tHPLH
tHPHL
FIGURE 13. ISL2100A PROPAGATION DELAYS vs
TEMPERATURE
FIGURE 14. ISL2101A PROPAGATION DELAYS vs
TEMPERATURE
10
9
10
9
8
8
7
7
6
6
5
5
4
4
3
2
3
50
0
50
100
150
50
0
50
100
150
TEMPERATURE (C)
TEMPERATURE (C)
tMON
tMON
tMOFF
tMOFF
FIGURE 15. ISL2100A DELAY MATCHING vs TEMPERATURE
FIGURE 16. ISL2101A DELAY MATCHING vs TEMPERATURE
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
VLO, VHO (V)
VLO, VHO (V)
FIGURE 17. PEAK PULL-UP CURRENT vs OUTPUT VOLTAGE
FIGURE 18. PEAK PULL-DOWN CURRENT vs OUTPUT
VOLTAGE
FN6294.0
June 8, 2006
8
ISL2100A, ISL2101A
Typical Performance Curves (Continued)
260
240
220
200
180
160
140
120
100
80
60
40
20
0
340
320
300
280
260
240
220
200
180
160
140
120
100
80
60
40
20
0
0
5
10
15
20
0
5
10
15
20
VDD, VHB (V)
VDD, VHB (V)
IDD
IHB
IDD
IHB
FIGURE 19. ISL2100A QUIESCENT CURRENT vs VOLTAGE
FIGURE 20. ISL2101A QUIESCENT CURRENT vs VOLTAGE
1
120
100
80
60
40
20
0
0.1
0.01
3
.
1 10
4
5
6
.
1 10
.
1 10
.
1 10
0.3
0.4
0.5
0.6
0.7
0.8
12
13
14
15
16
FORWARD VOLTAGE (V)
VHS to VSS VOLTAGE (V)
FIGURE 21. BOOTSTRAP DIODE I-V CHARACTERISTICS
FIGURE 22. VHS VOLTAGE vs VDD VOLTAGE
FN6294.0
June 8, 2006
9
ISL2100A, ISL2101A
Dual Flat No-Lead Plastic Package (DFN)
L9.3x3
2X
9 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
0.15 C
A
A
D
MILLIMETERS
2X
0.15
C B
SYMBOL
MIN
0.80
NOMINAL
0.90
MAX
1.00
NOTES
A
A1
A3
b
-
-
0.20
1.85
0.80
-
0.05
-
E
0.20 REF
0.25
-
5
0.30
2.10
1.05
4, 7
INDEX
AREA
D
3.00 BSC
2.00
-
D2
E
6, 7
TOP VIEW
B
A
3.00 BSC
0.95
-
// 0.10
0.08
C
E2
e
6, 7
0.50 BSC
-
-
C
k
0.60
0.25
-
-
A3
C
SIDE VIEW
L
0.35
0.45
7
SEATING
PLANE
N
9
2
Rev. 0 3/06
D2
D2/2
2
6
7
NOTES:
(DATUM B)
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
1
5
3. All dimensions are in millimeters. Angles are in degrees.
INDEX
AREA
NX k
E2
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
(DATUM A)
5. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
E2/2
NX L
6. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
N
N-1
NX b
4
7
7. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
e
(Nd-1)Xe
REF.
M
0.10
C A B
8. COMPLIANT TO JEDEC MO-229-WEED-3 except for
dimensions E2 & D2.
BOTTOM VIEW
C
L
(A1)
NX (b)
L
8
4
e
SECTION "C-C"
TERMINAL TIP
FOR ODD TERMINAL/SIDE
C C
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6294.0
June 8, 2006
10
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