ICL3222ECB [RENESAS]
DUAL LINE TRANSCEIVER, PDSO18, PLASTIC, MS-013-AB, SOIC-18;
| 型号： | ICL3222ECB |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | DUAL LINE TRANSCEIVER, PDSO18, PLASTIC, MS-013-AB, SOIC-18 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总33页 (文件大小：654K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
±15kV ESD Protected, +3V to +5.5V, 1µA, 250kbps,
RS-232 Transmitters/Receivers
ICL3221E, ICL3222E, ICL3223E,
ICL3232E, ICL3241E, ICL3243E
The Intersil ICL32xxE devices are 3.0V to 5.5V powered
RS-232 transmitters/receivers which meet ElA/TIA-232
Features
• ESD Protection for RS-232 I/O Pins to ±15kV
(IEC61000)
• Drop in Replacements for MAX3221E, MAX3222E,
MAX3223E, MAX3232E, MAX3241E, MAX3243E,
SP3243E
and V.28/V.24 specifications, even at V
= 3.0V.
CC
Additionally, they provide ±15kV ESD protection
(IEC61000-4-2 Air Gap and Human Body Model) on
transmitter outputs and receiver inputs (RS-232 pins).
Targeted applications are PDAs, Palmtops, and notebook
and laptop computers where the low operational, and
even lower standby, power consumption is critical.
Efficient on-chip charge pumps, coupled with manual and
automatic power-down functions (except for the
ICL3232E), reduce the standby supply current to a 1µA
trickle. Small footprint packaging, and the use of small,
low value capacitors ensure board space savings as well.
Data rates greater than 250kbps are guaranteed at worst
case load conditions. This family is fully compatible with
3.3V-only systems, mixed 3.3V and 5.0V systems, and
5.0V-only systems.
• ICL3221E is a Low Power, Pin Compatible Upgrade
for 5V MAX221E
• ICL3222E is a Low Power, Pin Compatible Upgrade
for 5V MAX242E, and SP312E
• ICL3232E is a Low Power Upgrade for HIN232E,
ICL232 and Pin Compatible Competitor Devices
• RS-232 Compatible with V
= 2.7V
CC
• Meets EIA/TIA-232 and V.28/V.24 Specifications at 3V
• Latch-Up Free
• On-Chip Voltage Converters Require Only Four
External 0.1µF Capacitors
• Manual and Automatic Power-Down Features
• Guaranteed Mouse Driveability (ICL324xE Only)
• Receiver Hysteresis For Improved Noise Immunity
• Guaranteed Minimum Data Rate. . . . . . . . 250kbps
• Wide Power Supply Range . . . . Single +3V to +5.5V
• Low Supply Current in Power-Down State . . . . . 1µA
• Pb-Free Available (RoHS Compliant)
The ICL324XE are 3-driver, 5-receiver devices that
provide a complete serial port suitable for laptop or
notebook computers. Both devices also include
noninverting always-active receivers for “wake-up”
capability.
The ICL3221E, ICL3223E and ICL3243E, feature an
automatic power-down function which powers down
the on-chip power-supply and driver circuits. This occurs
when an attached peripheral device is shut off or the
RS-232 cable is removed, conserving system power
automatically without changes to the hardware or
operating system. These devices power up again when a
valid RS-232 voltage is applied to any receiver input.
Applications
• Any System Requiring RS-232 Communication Ports
- Battery Powered, Hand-Held, and Portable
Equipment
- Laptop Computers, Notebooks, Palmtops
- Modems, Printers and other Peripherals
- Digital Cameras
Table 1 summarizes the features of the devices
represented by this data sheet, while Application Note
AN9863 summarizes the features of each device
comprising the ICL32xxE 3V family.
- Cellular/Mobile Phones
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
February 22, 2010
FN4910.21
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2000-2005, 2007-2008, 2010. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
TABLE 1. SUMMARY OF FEATURES
NUMBER OF
MONITOR
NUMBER NUMBER RECEIVERS
AUTOMATIC
POWER-
DOWN
DATA
RATE
RECEIVER
ENABLE
PART
READY
MANUAL
NUMBER
OF Tx
OF Rx
(R
)
(kbps)
FUNCTION?
OUTPUT? POWER-DOWN? FUNCTION?
OUTB
ICL3221E
ICL3222E
ICL3223E
ICL3232E
ICL3241E
ICL3243E
1
2
2
2
3
3
1
2
2
2
5
5
0
250
250
250
250
250
250
Yes
Yes
Yes
No
No
No
No
No
No
No
Yes
Yes
Yes
No
Yes
No
0
0
0
2
1
Yes
No
Yes
No
Yes
Yes
No
Yes
Typical Operating Circuits
ICL3221E
C
(OPTIONAL CONNECTION, NOTE)
3
+3.3V
+
0.1µF
15
2
+
4
C
1
0.1µF
3
C1+
V
C
0.1µF
CC
3
+
V+
V-
C1-
5
C
2
C2+
+
7
0.1µF
C
4
0.1µF
6
C2-
+
T
1
11
13
T1
T1
OUT
IN
TTL/CMOS
RS-232
LOGIC LEVELS
9
1
8
LEVELS
R1
R1
IN
OUT
5kΩ
R
1
EN
16
10
V
CC
FORCEOFF
INVALID
12
TO POWER
CONTROL LOGIC
FORCEON
GND
14
NOTE: THE NEGATIVE TERMINAL OF C CAN BE CONNECTED TO EITHER V
3
OR GND
CC
FN4910.21
February 22, 2010
2
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Typical Operating Circuits (Continued)
ICL3222E
C
(OPTIONAL CONNECTION, NOTE)
3
+3.3V
+
0.1µF
17
2
3
C
0.1µF
C1+
V
CC
1
+
+
C
3
+
+
V+
V-
4
5
0.1µF
C1-
C
0.1µF
2
C2+
7
C
4
0.1µF
6
C2-
T
T
1
2
12
15
8
T1
T2
T1
T2
IN
IN
OUT
OUT
11
13
TTL/CMOS
RS-232
LOGIC LEVELS
14
9
LEVELS
R1
R1
R2
OUT
IN
IN
5kΩ
R
1
10
1
R2
OUT
5kΩ
R
2
EN
18
V
CC
SHDN
GND
16
NOTE: THE NEGATIVE TERMINAL OF C CAN BE CONNECTED TO EITHER V
3
OR GND
CC
ICL3223E
+3.3V
+
0.1µF
19
2
C
0.1µF
C1+
3
1
V
CC
C
0.1µF
+
3
+
V+
V-
4
C1-
5
C
0.1µF
2
C2+
+
7
C
4
0.1µF
6
C2-
+
T
T
1
2
13
17
8
T1
T2
T1
T2
IN
IN
OUT
OUT
12
15
TTL/CMOS
RS-232
LOGIC LEVELS
16
9
LEVELS
R1
R2
R1
R2
OUT
OUT
IN
IN
5kΩ
R
1
10
1
5kΩΩ
R
2
EN
20
11
V
FORCEOFF
INVALID
CC
14
TO POWER
CONTROL LOGIC
FORCEON
GND
18
FN4910.21
February 22, 2010
3
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Typical Operating Circuits (Continued)
ICL3232E
+3.3V
C
C
(OPTIONAL CONNECTION, NOTE)
+
3
0.1µF
16
NOTE: THE NEGATIVE TERMINAL OF C CAN
3
1
C
0.1µF
C1+
V
2
6
1
BE CONNECTED TO EITHER V
OR GND
CC
CC
+
+
3
+
V+
V-
3
4
0.1µF
C1-
C
0.1µF
2
C2+
C
4
5
C2-
0.1µF
+
T
T
1
2
11
14
7
T1
T2
T1
IN
OUT
OUT
10
12
T2
IN
TTL/CMOS
LOGIC LEVELS
RS-232
13
LEVELS
R1
R1
OUT
IN
R
5kΩ
5kΩ
1
9
8
R2
R2
OUT
IN
R
2
GND
15
FN4910.21
February 22, 2010
4
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Typical Operating Circuits (Continued)
ICL3241E
ICL3243E
+3.3V
+
+3.3V
0.1µF
28
+
26
0.1µF
26
27
C
0.1µF
C1+
1
V
CC
C
3
0.1µF
27
3
28
C
0.1µF
+
3
+
C
0.1µF
+
V+
V-
C1+
C1-
V
CC
1
V+
V-
24
+
+
C1-
24
1
2
C
0.1µF
2
C2+
1
+
3
9
C
2
0.1µF
C
4
0.1µF
C2+
C
4
0.1µF
C2-
2
+
+
C2-
T
T
T
1
2
3
T
T
T
1
2
3
14
9
14
T1
IN
T1
IN
T1
OUT
T1
OUT
13
10
11
10
11
RS-232
LEVELS
13
12
T2
T3
IN
IN
RS-232
LEVELS
T2
T3
IN
IN
T2
T3
OUT
OUT
T2
T3
OUT
OUT
12
21
R1
R2
OUTB
OUTB
20
19
20
19
R2
OUTB
4
5
4
5
R1
TTL/CMOS
LOGIC
LEVELS
OUT
R1
R1
R2
OUT
IN
R1
R2
IN
IN
R
5kΩ
5kΩ
1
R
TTL/CMOS
LOGIC
LEVELS
1
2
5kΩ
5kΩ
5kΩ
18
17
16
R2
18
OUT
R2
OUT
IN
R
2
R
6
7
8
R3
R4
R5
OUT
OUT
OUT
17
16
6
7
RS-232
LEVELS
R3
R4
R5
RS-232
LEVELS
IN
IN
IN
R3
R4
R3
R4
5kΩ
OUT
IN
R
R
3
4
R
R
3
4
OUT
IN
5kΩ
5kΩ
5kΩ
5kΩ
15
23
15
23
8
EN
R
R5
R5
5
OUT
IN
R
5
22
FORCEON
V
CC
SHDN
GND
22
21
25
V
CC
FORCEOFF
INVALID
TO POWER
CONTROL
LOGIC
GND
25
FN4910.21
February 22, 2010
5
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Pin Configurations
ICL3221E
ICL3222E
(18 LD PDIP, SOIC)
TOP VIEW
(16 LD SSOP, TSSOP)
TOP VIEW
EN
C1+
V+
1
2
3
4
5
6
7
8
16 FORCEOFF
EN
C1+
V+
1
2
3
4
5
6
7
8
9
18 SHDN
15 VCC
17 VCC
14 GND
16 GND
15 T1OUT
14 R1IN
13 R1OUT
12 T1IN
11 T2IN
13 T1OUT
12 FORCEON
11 T1IN
C1-
C2+
C2-
V-
C1-
C2+
C2-
10 INVALID
V-
R1IN
9
R1OUT
T2OUT
R2IN
10
R2OUT
ICL3222E
ICL3223E
(20 LD SSOP, TSSOP)
(20 LD SSOP, TSSOP)
TOP VIEW
TOP VIEW
EN
1
2
20 FORCEOFF
EN
C1+
1
2
20 SHDN
19 VCC
18 GND
17 T1OUT
16 R1IN
15 R1OUT
14 NC
C1+
V+
19 VCC
3
18 GND
3
V+
17 T1OUT
16 R1IN
C1-
4
C1-
4
C2+
5
C2+
5
C2-
6
15 R1OUT
14 FORCEON
13 T1IN
C2-
6
V-
7
V-
7
T2OUT
R2IN
R2OUT
8
T2OUT
R2IN
R2OUT
8
13 T1IN
9
12
T2IN
9
12
T2IN
10
11 INVALID
10
11 NC
ICL3232E
ICL3232E
(16 LD SOIC, SSOP, TSSOP-16)
(20 LD TSSOP-20)
TOP VIEW
TOP VIEW
C1+
V+
1
2
3
4
5
6
7
8
16 VCC
NC
C1+
V+
1
2
20 NC
15 GND
14 T1OUT
13 R1IN
12 R1OUT
11 T1IN
10 T2IN
19 VCC
C1-
3
18 GND
17 T1OUT
16 R1IN
15 R1OUT
14 T1IN
C2+
C2-
C1-
4
C2+
C2-
5
V-
6
T2OUT
R2IN
V-
7
9
R2OUT
T2OUT
R2IN
NC
8
13
12
T2IN
R2OUT
9
10
11 NC
FN4910.21
February 22, 2010
6
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Pin Configurations (Continued)
ICL3241E
(28 LD SOIC, SSOP, TSSOP)
TOP VIEW
ICL3243E
(28 LD SOIC, SSOP, TSSOP)
TOP VIEW
C2+
C2-
1
2
28 C1+
27 V+
C2+
C2-
1
2
28 C1+
27 V+
3
26 VCC
25 GND
24 C1-
V-
3
26 VCC
V-
R1IN
R2IN
R3IN
R4IN
R5IN
T1OUT
T2OUT
4
25 GND
R1IN
R2IN
R3IN
R4IN
R5IN
T1OUT
T2OUT
4
5
5
24 C1-
6
23 EN
6
23 FORCEON
22 FORCEOFF
21 INVALID
7
22 SHDN
21 R1OUTB
7
8
8
9
20
R2OUTB
9
20
R2OUTB
10
19 R1OUT
18 R2OUT
17 R3OUT
16 R4OUT
15 R5OUT
10
19 R1OUT
18 R2OUT
17 R3OUT
16 R4OUT
15 R5OUT
T3OUT 11
T3IN 12
T2IN 13
T1IN 14
T3OUT 11
T3IN 12
T2IN 13
T1IN 14
Pin Descriptions
PIN
FUNCTION
VCC
V+
System power supply input (3.0V to 5.5V).
Internally generated positive transmitter supply (+5.5V).
Internally generated negative transmitter supply (-5.5V).
Ground connection.
V-
GND
C1+
C1-
External capacitor (voltage doubler) is connected to this lead.
External capacitor (voltage doubler) is connected to this lead.
External capacitor (voltage inverter) is connected to this lead.
External capacitor (voltage inverter) is connected to this lead.
TTL/CMOS compatible transmitter Inputs.
C2+
C2-
TIN
TOUT
RIN
±15kV ESD Protected, RS-232 level (nominally ±5.5V) transmitter outputs.
±15kV ESD Protected, RS-232 compatible receiver inputs.
TTL/CMOS level receiver outputs.
ROUT
ROUTB
TTL/CMOS level, noninverting, always enabled receiver outputs.
INVALID Active low output that indicates if no valid RS-232 levels are present on any receiver input.
EN
Active low receiver enable control; doesn’t disable R
outputs.
Active low input to shut down transmitters and on-board power supply, to place device in low power mode.
OUTB
SHDN
FORCEOFF Active low to shut down transmitters and on-chip power supply. This overrides any automatic circuitry and
FORCEON (see Table 2).
FORCEON Active high input to override automatic power-down circuitry thereby keeping transmitters active (FORCEOFF must
be high).
FN4910.21
February 22, 2010
7
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Ordering Information
PART NUMBER
(Note 3)
PART
MARKING
TEMP RANGE
(°C)
PKG.
DWG. #
PACKAGE
16 Ld SSOP
ICL3221ECA
ICL 3221ECA
0 to +70
0 to +70
M16.209
ICL3221ECA-T (Note 1)
ICL3221ECAZ (Note 2)
ICL3221ECAZ-T (Notes 1, 2)
ICL3221ECAZA (Note 2)
ICL 3221ECA
ICL32 21ECAZ
ICL32 21ECAZ
ICL32 21ECAZ
16 Ld SSOP
M16.209
M16.209
M16.209
M16.209
M16.209
M16.173
M16.173
M16.173
M16.209
M16.209
M16.209
M16.209
M16.173
M16.173
M20.209
M20.209
M20.209
E18.3
0 to +70
16 Ld SSOP (Pb-free)
16 Ld SSOP (Pb-free)
16 Ld SSOP (Pb-free)
16 Ld SSOP (Pb-free)
16 Ld TSSOP
0 to +70
0 to +70
ICL3221ECAZA-T (Notes 1, 2) ICL32 21ECAZ
0 to +70
ICL3221ECV
3221 ECV
0 to +70
ICL3221ECVZ (Note 2)
ICL3221ECVZ-T (Notes 1, 2)
ICL3221EIA
3221 ECVZ
0 to +70
16 Ld TSSOP (Pb-free)
16 Ld TSSOP (Pb-free)
16 Ld SSOP
3221 ECVZ
0 to +70
ICL 3221EIA
ICL 3221EIA
ICL32 21EIAZ
ICL32 21EIAZ
3221 EIVZ
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
0 to +70
ICL3221EIA-T (Note 1)
ICL3221EIAZ (Note 2)
ICL3221EIAZ-T (Notes 1, 2)
ICL3221EIVZ (Note 2)
ICL3221EIVZ-T (Notes 1, 2)
ICL3222ECA-T (Note 1)
ICL3222ECAZ (Note 2)
ICL3222ECAZ-T (Notes 1, 2)
ICL3222ECP
16 Ld SSOP
16 Ld SSOP (Pb-free)
16 Ld SSOP (Pb-free)
16 Ld TSSOP (Pb-free)
16 Ld TSSOP (Pb-free)
20 Ld SSOP
3221 EIVZ
ICL 3222ECA
ICL32 22ECAZ
ICL32 22ECAZ
ICL3222ECP
ICL 3222ECV
ICL32 22ECVZ
ICL32 22ECVZ
ICL32 22EIAZ
ICL32 22EIAZ
ICL3222EIB
ICL3222EIB
3222EIBZ
0 to +70
20 Ld SSOP (Pb-free)
20 Ld SSOP (Pb-free)
18 Ld PDIP
0 to +70
0 to +70
ICL3222ECV-T (Note 1)
ICL3222ECVZ (Note 2)
ICL3222ECVZ-T (Notes 1, 2)
ICL3222EIAZ (Note 2)
ICL3222EIAZ-T (Notes 1, 2)
ICL3222EIB
0 to +70
20 Ld TSSOP
M20.173
M20.173
M20.173
M20.209
M20.209
M18.3
0 to +70
20 Ld TSSOP (Pb-free)
20 Ld TSSOP (Pb-free)
20 Ld SSOP (Pb-free)
20 Ld SSOP (Pb-free)
18 Ld SOIC
0 to +70
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
0 to +70
ICL3222EIB-T (Note 1)
ICL3222EIBZ (Note 2)
ICL3222EIBZ-T (Notes 1, 2)
ICL3222EIV
18 Ld SOIC
M18.3
18 Ld SOIC (Pb-free)
18 Ld SOIC (Pb-free)
20 Ld TSSOP
M18.3
3222EIBZ
M18.3
ICL 3222EIV
ICL 3222EIV
ICL32 22EIVZ
ICL32 22EIVZ
ICL 3223ECA
ICL 3223ECA
ICL32 23ECAZ
ICL32 23ECAZ
ICL 3223ECV
ICL32 23ECVZ
ICL32 23ECVZ
M20.173
M20.173
M20.173
M20.173
M20.209
M20.209
M20.209
M20.209
M20.173
M20.173
M20.173
ICL3222EIV-T (Note 1)
ICL3222EIVZ (Note 2)
ICL3222EIVZ-T (Notes 1, 2)
ICL3223ECA
20 Ld TSSOP
20 Ld TSSOP (Pb-free)
20 Ld TSSOP (Pb-free)
20 Ld SSOP
ICL3223ECA-T (Note 1)
ICL3223ECAZ (Note 2)
ICL3223ECAZ-T (Notes 1, 2)
ICL3223ECV
0 to +70
20 Ld SSOP
0 to +70
20 Ld SSOP (Pb-free)
20 Ld SSOP (Pb-free)
20 Ld TSSOP
0 to +70
0 to +70
ICL3223ECVZ (Note 2)
ICL3223ECVZ-T (Notes 1, 2)
0 to +70
20 Ld TSSOP (Pb-free)
20 Ld TSSOP (Pb-free)
0 to +70
FN4910.21
February 22, 2010
8
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Ordering Information (Continued)
PART NUMBER
(Note 3)
PART
MARKING
TEMP RANGE
(°C)
PKG.
DWG. #
PACKAGE
20 Ld SSOP
ICL3223EIA
ICL 3223EIA
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
0 to +70
M20.209
ICL3223EIA-T (Note 1)
ICL3223EIAZ (Note 2)
ICL3223EIAZ-T (Notes 1, 2)
ICL3223EIV
ICL 3223EIA
ICL32 23EIAZ
ICL32 23EIAZ
ICL 3223EIV
ICL32 23EIVZ
ICL32 23EIVZ
ICL 3232ECA
ICL 3232ECA
3232 ECAZ
3232 ECAZ
3232ECBZ
20 Ld SSOP
M20.209
M20.209
M20.209
M20.173
M20.173
M20.173
M16.209
M16.209
M16.209
M16.209
M16.3
20 Ld SSOP (Pb-free)
20 Ld SSOP (Pb-free)
20 Ld TSSOP
ICL3223EIVZ (Note 2)
ICL3223EIVZ-T (Notes 1, 2)
ICL3232ECA
20 Ld TSSOP (Pb-free)
20 Ld TSSOP (Pb-free)
16 Ld SSOP
ICL3232ECA-T (Note 1)
ICL3232ECAZ (Note 2)
ICL3232ECAZ-T (Notes 1, 2)
ICL3232ECBZ (Note 2)
ICL3232ECBZ-T (Notes 1, 2)
ICL3232ECBN
0 to +70
16 Ld SSOP
0 to +70
16 Ld SSOP (Pb-free)
16 Ld SSOP (Pb-free)
16 Ld SOIC (Pb-free)
16 Ld SOIC (Pb-free)
16 Ld SOIC
0 to +70
0 to +70
3232ECBZ
0 to +70
M16.3
3232ECBN
0 to +70
M16.15
M16.15
M16.15
M16.15
M16.173
M16.173
M16.173
M20.173
M20.173
M16.173
M16.173
M16.209
M16.209
M16.209
M16.3
ICL3232ECBN-T (Note 1)
ICL3232ECBNZ (Note 2)
3232ECBN
0 to +70
16 Ld SOIC
3232ECBNZ
0 to +70
16 Ld SOIC (Pb-free)
16 Ld SOIC (Pb-free)
16 Ld TSSOP
ICL3232ECBNZ-T (Notes 1, 2) 3232ECBNZ
0 to +70
ICL3232ECV-16T (Note 1)
ICL3232ECV-16Z (Note 2)
3232E CV-16
0 to +70
3232E CV-16Z
0 to +70
16 Ld TSSOP (Pb-free)
16 Ld TSSOP (Pb-free)
20 Ld TSSOP (Pb-free)
20 Ld TSSOP (Pb-free)
16 Ld TSSOP (Pb-free)
16 Ld TSSOP (Pb-free)
16 Ld SSOP
ICL3232ECV-16Z-T (Notes 1, 2) 3232E CV-16Z
ICL3232ECV-20Z (Note 2) ICL3232 ECV-20Z
ICL3232ECV-20Z-T (Notes 1, 2) ICL3232 ECV-20Z
ICL3232EFV-16Z (Note 2) 3232E FV-16Z
ICL3232EFV-16Z-T (Notes 1, 2) 3232E FV-16Z
0 to +70
0 to +70
0 to +70
-40 to +125
-40 to +125
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
0 to +70
ICL3232EIA-T (Note 1)
ICL3232EIAZ (Note 2)
ICL3232EIAZ-T (Notes 1, 2)
ICL3232EIB-T (Note 1)
ICL3232EIBZ (Note 2)
ICL3232EIBZ-T (Notes 1, 2)
ICL3232EIBNZ (Note 2)
ICL3232 EIA
3232 EIAZ
3232 EIAZ
ICL3232EIB
3232EIBZ
16 Ld SSOP (Pb-free)
16 Ld SSOP (Pb-free)
16 Ld SOIC
16 Ld SOIC (Pb-free)
16 Ld SOIC (Pb-free)
16 Ld SOIC (Pb-free)
16 Ld SOIC (Pb-free)
16 Ld TSSOP
M16.3
3232EIBZ
M16.3
3232EIBNZ
M16.15
M16.15
M16.173
M16.173
M16.173
M16.173
M20.173
M20.173
M28.209
ICL3232EIBNZ-T (Notes 1, 2) 3232EIBNZ
ICL3232EIV-16
3232E IV-16
3232E IV-16
3232E IV-16Z
ICL3232EIV-16-T (Note 1)
ICL3232EIV-16Z (Note 2)
16 Ld TSSOP
16 Ld TSSOP (Pb-free)
16 Ld TSSOP (Pb-free)
20 Ld TSSOP (Pb-free)
20 Ld TSSOP (Pb-free)
28 Ld SSOP
ICL3232EIV-16Z-T (Notes 1, 2) 3232E IV-16Z
ICL3232EIV-20Z (Note 2) ICL3232 EIV-20Z
ICL3232EIV-20Z-T (Notes 1, 2) ICL3232 EIV-20Z
ICL3241ECA ICL 3241ECA
FN4910.21
February 22, 2010
9
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Ordering Information (Continued)
PART NUMBER
(Note 3)
PART
MARKING
TEMP RANGE
(°C)
PKG.
DWG. #
PACKAGE
28 Ld SSOP
ICL3241ECA-T (Note 1)
ICL3241ECAZ (Note 2)
ICL3241ECAZ-T (Notes 1, 2)
ICL3241ECBZ (Note 2)
ICL3241ECBZ-T (Notes 1, 2)
ICL3241ECVZ (Note 2)
ICL3241EIA-T (Note 1)
ICL3241EIAZ (Note 2)
ICL3241EIAZ-T (Notes 1, 2)
ICL3241EIBZ (Note 2)
ICL3241EIBZ-T (Notes 1, 2)
ICL3241EIV-T (Note 1)
ICL3241EIVZ (Note 2)
ICL3241EIVZ-T (Notes 1, 2)
ICL3243ECA
ICL 3241ECA
0 to +70
0 to +70
M28.209
ICL3241 ECAZ
ICL3241 ECAZ
ICL3241ECBZ
ICL3241ECBZ
ICL3241 ECVZ
ICL 3241EIA
ICL3241 EIAZ
ICL3241 EIAZ
ICL3241EIBZ
ICL3241EIBZ
ICL3241 EIV
ICL3241 EIVZ
ICL3241 EIVZ
ICL 3243ECA
ICL 3243ECA
ICL32 43ECAZ
ICL32 43ECAZ
ICL3243ECBZ
ICL3243ECBZ
ICL3243 ECV
ICL3243 ECVZ
ICL3243 ECVZ
ICL 3243EIA
ICL32 43EIAZ
ICL32 43EIAZ
ICL3243 EIV
ICL3243 EIVZ
ICL3243 EIVZ
28 Ld SSOP (Pb-free)
28 Ld SSOP (Pb-free)
28 Ld SOIC (Pb-free)
28 Ld SOIC (Pb-free)
28 Ld TSSOP (Pb-free)
28 Ld SSOP
M28.209
M28.209
M28.3
0 to +70
0 to +70
0 to +70
M28.3
0 to +70
M28.173
M28.209
M28.209
M28.209
M28.3
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
0 to +70
28 Ld SSOP (Pb-free)
28 Ld SSOP (Pb-free)
28 Ld SOIC (Pb-free)
28 Ld SOIC (Pb-free)
28 Ld TSSOP
M28.3
M28.173
M28.173
M28.173
M28.209
M28.209
M28.209
M28.209
M28.3
28 Ld TSSOP (Pb-free)
28 Ld TSSOP (Pb-free)
28 Ld SSOP
ICL3243ECA-T (Note 1)
ICL3243ECAZ (Note 2)
ICL3243ECAZ-T (Notes 1, 2)
ICL3243ECBZ (Note 2)
ICL3243ECBZ-T (Notes 1, 2)
ICL3243ECV-T (Note 1)
ICL3243ECVZ (Note 2)
ICL3243ECVZ-T (Notes 1, 2)
ICL3243EIA-T (Note 1)
ICL3243EIAZ (Note 2)
ICL3243EIAZ-T (Notes 1, 2)
ICL3243EIV
0 to +70
28 Ld SSOP
0 to +70
28 Ld SSOP (Pb-free)
28 Ld SSOP (Pb-free)
28 Ld SOIC (Pb-free)
28 Ld SOIC (Pb-free)
28 Ld TSSOP
0 to +70
0 to +70
0 to +70
M28.3
0 to +70
M28.173
M28.173
M28.173
M28.209
M28.209
M28.209
M28.173
M28.173
M28.173
0 to +70
28 Ld TSSOP (Pb-free)
28 Ld TSSOP (Pb-free)
28 Ld SSOP
0 to +70
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
28 Ld SSOP (Pb-free)
28 Ld SSOP (Pb-free)
28 Ld TSSOP
ICL3243EIVZ (Note 2)
ICL3243EIVZ-T (Notes 1, 2)
NOTES:
28 Ld TSSOP (Pb-free)
28 Ld TSSOP (Pb-free)
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ICL3221E, ICL3222E, ICL3223E, ICL3232E,
ICL3241E, ICL3243E. For more information on MSL please see techbrief TB363.
FN4910.21
February 22, 2010
10
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Table of Contents
Related Literature ............................................................................................................................... 1
Typical Operating Circuits.................................................................................................................... 2
Pin Configurations............................................................................................................................... 6
Pin Descriptions .................................................................................................................................. 7
Ordering Information .......................................................................................................................... 8
Absolute Maximum Ratings .............................................................................................................. 12
Thermal Information ........................................................................................................................ 12
Recommended Operating Conditions................................................................................................ 12
Electrical Specifications.................................................................................................................... 12
Detailed Description .......................................................................................................................... 14
Charge-Pump ................................................................................................................................. 14
Transmitters................................................................................................................................... 14
Receivers....................................................................................................................................... 14
Low Power Operation ........................................................................................................................ 15
Pin Compatible Replacements for 5V Devices ...................................................................................... 15
Power-Down Functionality (Except ICL3232E).................................................................................. 15
Software Controlled (Manual) Power-Down ......................................................................................... 15
Automatic Power-Down (ICL3221E, ICL3223E, ICL3243E Only) ............................................................. 17
Receiver ENABLE Control (ICL3221E, ICL3222E, ICL3223E, ICL3241E Only)............................................ 18
Capacitor Selection............................................................................................................................ 18
Power Supply Decoupling.................................................................................................................. 18
Operation Down to 2.7V .................................................................................................................... 18
Transmitter Outputs when Exiting Power-Down................................................................................ 18
Mouse Driveability............................................................................................................................. 18
High Data Rates................................................................................................................................. 19
Interconnection with 3V and 5V Logic............................................................................................... 19
±15kV ESD Protection ....................................................................................................................... 20
Human Body Model (HBM) Testing..................................................................................................... 20
IEC61000-4-2 Testing...................................................................................................................... 20
Typical Performance Curves VCC = 3.3V, TA = +25°C.............................................................................. 20
Die Characteristics ............................................................................................................................ 21
Revision History ................................................................................................................................ 22
Products............................................................................................................................................ 22
Package Outline Drawings................................................................................................................. 23
FN4910.21
February 22, 2010
11
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Absolute Maximum Ratings
Thermal Information
V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
Thermal Resistance (Typical, Note 4)
Θ
(°C/W)
JA
CC
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -7V
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14V
Input Voltages
18 Ld PDIP Package* . . . . . . . . . . . . . . . . .
16 Ld Wide SOIC Package . . . . . . . . . . . . . .
16 Ld Narrow SOIC Package . . . . . . . . . . . .
18 Ld SOIC Package . . . . . . . . . . . . . . . . . .
28 Ld SOIC Package . . . . . . . . . . . . . . . . . .
16 Ld SSOP Package. . . . . . . . . . . . . . . . . .
20 Ld SSOP Package. . . . . . . . . . . . . . . . . .
16 Ld TSSOP Package. . . . . . . . . . . . . . . . .
20 Ld TSSOP Package. . . . . . . . . . . . . . . . .
28 Ld SSOP and TSSOP Packages. . . . . . . . .
80
100
115
75
T
R
, FORCEOFF, FORCEON, EN, SHDN . . . . . . -0.3V to 6V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
IN
75
IN
Output Voltages
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±13.2V
135
122
145
140
100
T
R
OUT
, INVALID . . . . . . . . . . . . . . . . . -0.3V to V
+0.3V
OUT CC
Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
T
OUT
Maximum Junction Temperature (Plastic Package) . +150°C
Maximum Storage Temperature Range . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
ESD Rating . . . . . . . . . . . . . . . . . . See Specification Table
Recommended Operating Conditions
Temperature Range
ICL32xxECX . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
ICL32xxEFX . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C
ICL32xxEIX. . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (V ) . . . . . . . . . . . . . . . . . . . . 3.3V or 5V
CC
Rx Input Voltage . . . . . . . . . . . . . . . . . . . . . -15V to +15V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTE:
4. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief
JA
TB379 for details.
Electrical Specifications Test Conditions: V = 3V to 5.5V, C - C = 0.1µF; Unless Otherwise Specified.
CC
1
4
Typicals are at T = +25°C. Boldface limits apply over the operating temperature
A
range.
TEMP
MIN
MAX
PARAMETER
TEST CONDITIONS
(°C) (Note 6)
TYP
(Note 6) UNITS
DC CHARACTERISTICS
Supply Current, Automatic All R Open, FORCEON = GND, FORCEOFF = V
Power-Down
25
25
25
-
-
-
1.0
1.0
0.3
10
10
µA
µA
IN
(ICL3221E, ICL3223E, ICL3243E Only)
CC
Supply Current,
Power-Down
FORCEOFF = SHDN = GND (Except ICL3232E)
Supply Current,
Automatic Power-Down
Disabled
All Outputs Unloaded,
FORCEON=FORCEOFF ICL3243
= SHDN = V
CC
V
= 3.0V, ICL3241,
1.0
mA
CC
V
V
= 3.0V, ICL3223
25
25
-
-
0.7
0.3
3.0
1.0
mA
mA
CC
CC
= 3.15V, ICL3221,
ICL3222, ICL3223,
ICL3232
LOGIC AND TRANSMITTER INPUTS AND RECEIVER OUTPUTS
Input Logic Threshold Low , FORCEON, FORCEOFF, EN, SHDN
Input Logic Threshold High T , FORCEON,
T
Full
Full
Full
Full
Full
Full
-
2.0
2.4
-
-
0.8
-
V
V
IN
V
V
= 3.3V
= 5.0V
-
IN
FORCEOFF, EN, SHDN
CC
CC
-
-
V
Input Leakage Current
T
, FORCEON,
All but ICL3232EF
ICL3232EF
±0.01
±0.01
±0.05
±1.0
±10
±10
µA
µA
µA
IN
FORCEOFF, EN, SHDN
-
Output Leakage Current
(Except ICL3232E)
FORCEOFF = GND or EN = V
-
CC
Output Voltage Low
Output Voltage High
I
I
= 1.6mA
Full
Full
Full
-
-
0.4
V
V
V
OUT
OUT
= -1.0mA
All but ICL3232EF
ICL3232EF
V
V
- 0.6 V
- 0.1
-
-
CC
CC
CC
- 0.9 V
- 0.1
CC
FN4910.21
February 22, 2010
12
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Electrical Specifications Test Conditions: V = 3V to 5.5V, C - C = 0.1µF; Unless Otherwise Specified.
CC
1
4
Typicals are at T = +25°C. Boldface limits apply over the operating temperature
A
range. (Continued)
TEMP
MIN
MAX
PARAMETER
TEST CONDITIONS
(°C) (Note 6)
TYP
(Note 6) UNITS
AUTOMATIC POWER-DOWN (ICL3221E, ICL3223E, ICL3243E Only, FORCEON = GND, FORCEOFF = V
CC
)
Receiver Input Thresholds ICL32xxE Powers Up (see Figure 6)
to Enable Transmitters
Full
Full
Full
Full
25
-2.7
-0.3
-
-
2.7
0.3
0.4
-
V
V
Receiver Input Thresholds ICL32xxE Powers Down (see Figure 6)
to Disable Transmitters
-
-
INVALID Output Voltage
Low
I
= 1.6mA
V
OUT
INVALID Output Voltage
High
I
= -1.0mA
V
- 0.6
-
V
OUT
CC
Receiver Threshold to
Transmitters Enabled Delay
-
-
100
-
µs
(t
)
WU
Receiver Positive or
Negative Threshold to
INVALID High Delay
25
25
1
-
-
µs
µs
(t
)
INVH
Receiver Positive or
-
30
Negative Threshold to
INVALID Low Delay (t
RECEIVER INPUTS
Input Voltage Range
Input Threshold Low
)
INVL
25
25
25
25
25
25
25
-25
0.6
0.8
-
-
25
-
V
V
V
V
V
V
= 3.3V
= 5.0V
= 3.3V
= 5.0V
1.2
1.5
1.5
1.8
0.5
5
CC
CC
CC
CC
-
V
Input Threshold High
2.4
2.4
-
V
-
V
Input Hysteresis
Input Resistance
-
V
3
7
kΩ
TRANSMITTER OUTPUTS
Output Voltage Swing
Output Resistance
All Transmitter Outputs Loaded with 3kΩ to Ground Full
±5.0
300
-
±5.4
10M
±35
-
-
V
Ω
V
= V+ = V- = 0V, Transmitter Output = ±2V
Full
Full
CC
Output Short-Circuit
Current
±60
mA
Output Leakage Current
V
= ±12V, V
CC
= 0V or 3V to 5.5V,
Full
Full
Full
-
-
±25
µA
V
OUT
Automatic Power-Down or
FORCEOFF = SHDN = GND
MOUSE DRIVEABILITY (ICL324XE Only)
TransmitterOutputVoltage T1 = T2 = GND, T3 = V , T3
Loaded
±5
-
-
IN
IN
IN
CC
OUT
OUT
Loaded with
(see Figure 9)
with 3kΩ to GND, T1
2.5mA Each
and T2
OUT
TIMING CHARACTERISTICS
Maximum Data Rate
R = 3kΩ, C = 1000pF, One Transmitter
Switching
250
500
-
kbps
L
L
Receiver Propagation Delay Receiver Input to
Receiver Output,
t
t
25
25
-
-
0.15
0.15
-
-
µs
µs
PHL
PLH
C = 150pF
L
Receiver Output Enable
Time
Normal Operation (Except ICL3232E)
25
-
200
-
ns
FN4910.21
February 22, 2010
13
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Electrical Specifications Test Conditions: V = 3V to 5.5V, C - C = 0.1µF; Unless Otherwise Specified.
CC
1
4
Typicals are at T = +25°C. Boldface limits apply over the operating temperature
A
range. (Continued)
TEMP
MIN
MAX
PARAMETER
TEST CONDITIONS
(°C) (Note 6)
TYP
(Note 6) UNITS
Receiver Output Disable
Time
Normal Operation (Except ICL3232E)
25
-
200
-
ns
Transmitter Skew
t
t
to t
to t
(Note 5)
25
25
25
25
-
-
100
50
-
-
ns
ns
PHL
PLH
PLH
Receiver Skew
-
PHL
Transition Region Slew Rate
V
= 3.3V,
C = 150pF to 2500pF
4
6
30
30
V/µs
V/µs
CC
L
L
R = 3kΩ to 7kΩ,
Measured from 3V to
-3V or -3V to 3V
C = 150pF to 1000pF
-
L
ESD PERFORMANCE
RS-232 Pins (TOUT, RIN)
Human Body Model
25
25
25
25
-
-
-
-
±15
±8
-
-
-
-
kV
kV
kV
kV
IEC61000-4-2 Contact Discharge
IEC61000-4-2 Air Gap Discharge
Human Body Model
±15
±2
All Other Pins
NOTES:
5. Transmitter skew is measured at the transmitter zero crossing points.
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
Except for the ICL3232E, all transmitter outputs
disable and assume a high impedance state when the
device enters the power-down mode (see Table 2).
These outputs may be driven to ±12V when disabled.
Detailed Description
ICL32xxE interface ICs operate from a single +3V to
+5.5V supply, guarantee a 250kbps minimum data
rate, require only four small external 0.1µF capacitors,
feature low power consumption, and meet all ElA
RS-232C and V.28 specifications. The circuit is divided
into three sections: charge pump, transmitters and
receivers.
All devices guarantee a 250kbps data rate for full load
conditions (3kΩ and 1000pF), V ≥ 3.0V, with one
CC
transmitter operating at full speed. Under more typical
conditions of V ≥ 3.3V, R = 3kΩ, and C = 250pF,
CC
L
L
one transmitter easily operates at 900kbps.
Charge-Pump
Transmitter inputs float if left unconnected, and may
Intersil’s new ICL32xxE family utilizes regulated on-
chip dual charge pumps as voltage doublers, and
voltage inverters to generate ±5.5V transmitter
cause I
the best performance.
increases. Connect unused inputs to GND for
CC
supplies from a V
supply as low as 3.0V. This allows
CC
Receivers
these devices to maintain RS-232 compliant output
levels over the ±10% tolerance range of 3.3V powered
systems. The efficient on-chip power supplies require
only four small, external 0.1µF capacitors for the
All the ICL32xxE devices contain standard inverting
receivers that three-state (except for the ICL3232E)
via the EN or FORCEOFF control lines. Additionally, the
two ICL324XE products include noninverting
(monitor) receivers (denoted by the ROUTB label)
that are always active, regardless of the state of any
control lines. All the receivers convert RS-232 signals
to CMOS output levels and accept inputs up to ±25V
while presenting the required 3kΩ to 7kΩ input
impedance (see Figure 1) even if the power is off
(VCC = 0V). The receivers’ Schmitt trigger input
stage uses hysteresis to increase noise immunity and
decrease errors due to slow input signal transitions.
voltage doubler and inverter functions at V
= 3.3V.
CC
See “Capacitor Selection” on page 18 and Table 3 on
page 18 for capacitor recommendations for other
operating conditions. The charge pumps operate
discontinuously (i.e., they turn off as soon as the V+
and V- supplies are pumped up to the nominal values),
resulting in significant power savings.
Transmitters
The transmitters are proprietary, low dropout, inverting
drivers that translate TTL/CMOS inputs to EIA/TIA-232
output levels. Coupled with the on-chip ±5.5V
supplies, these transmitters deliver true RS-232 levels
over a wide range of single supply system voltages.
The ICL3221E, ICL3222E, ICL3223E, ICL3241E
inverting receivers disable only when EN is driven high.
ICL3243E receivers disable during forced (manual)
power-down, but not during automatic power-down
(see Table 2).
FN4910.21
February 22, 2010
14
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
ICL3241E and ICL3243E monitor receivers remain
active even during manual power-down and forced
receiver disable, making them extremely useful for
Ring Indicator monitoring. Standard receivers driving
powered down peripherals must be disabled to
prevent current flow through the peripheral’s
protection diodes (see Figures 2 and 3). This renders
them useless for wake up functions, but the
corresponding monitor receiver can be dedicated to
this task as shown in Figure 3.
Power-Down Functionality
(Except ICL3232E)
The already low current requirement drops
significantly when the device enters power-down
mode. In power-down, supply current drops to 1µA,
because the on-chip charge pump turns off (V+
collapses to V , V- collapses to GND), and the
CC
transmitter outputs three-state. Inverting receiver
outputs may or may not disable in power-down; refer
to Table 2 for details. This micro-power mode makes
these devices ideal for battery powered and portable
applications.
V
CC
R
R
XIN
XOUT
GND ≤ V
≤ V
CC
-25V ≤ V
RIN
≤ +25V 5kΩ
ROUT
Software Controlled (Manual) Power-Down
GND
Most devices in the ICL32xxE family provide pins that
allow the user to force the IC into the low power,
standby state.
FIGURE 1. INVERTING RECEIVER CONNECTIONS
On the ICL3222E and ICL3241E, the power-down
control is via a simple shutdown (SHDN) pin. Driving
this pin high enables normal operation, while driving it
low forces the IC into its power-down state. Connect
Low Power Operation
These 3V devices require a nominal supply current of
0.3mA, even at V
= 5.5V, during normal operation
CC
(not in power-down mode). This is considerably less
than the 5mA to 11mA current required by comparable
5V RS-232 devices, allowing users to reduce system
power simply by switching to this new family.
SHDN to V
if the power-down function isn’t needed.
CC
Note that all the receiver outputs remain enabled
during shutdown (see Table 2). For the lowest power
consumption during power-down, the receivers should
also be disabled by driving the EN input high (see next
section, and Figures 2 and 3).
Pin Compatible Replacements for 5V
Devices
The ICL3221E, ICL3222E, ICL3232E are pin compatible
with existing 5V RS-232 transceivers - See the
“Features” section on page 1 for details.
The ICL3221E, ICL3223E, and ICL3243E utilize a two
pin approach where the FORCEON and FORCEOFF
inputs determine the IC’s mode. For always enabled
operation, FORCEON and FORCEOFF are both strapped
high. To switch between active and power-down
modes, under logic or software control, only the
FORCEOFF input need be driven. The FORCEON state
isn’t critical, as FORCEOFF dominates over FORCEON.
Nevertheless, if strictly manual control over power-
down is desired, the user must strap FORCEON high to
disable the automatic power-down circuitry. ICL3243E
inverting (standard) receiver outputs also disable when
the device is in manual power-down, thereby
eliminating the possible current path through a
shutdown peripheral’s input protection diode (see
Figures 2 and 3).
This pin compatibility coupled with the low I
CC
and
wide operating supply range, make the ICL32xxE
potential lower power, higher performance drop-in
replacements for existing 5V applications. As long as
the ±5V RS-232 output swings are acceptable, and
transmitter input pull-up resistors aren’t required, the
IICL32xxE should work in most 5V applications.
When replacing a device in an existing 5V application,
it is acceptable to terminate C to V
the “Typical Operating Circuits” on page 2.
as shown on
3
CC
Nevertheless, terminate C to GND if possible, as
3
slightly better performance results from this
configuration.
TABLE 2. POWER-DOWN AND ENABLE LOGIC TRUTH TABLE
RS-232
SIGNAL
PRESENT
AT
FORCEOFF
R
OUTB
TRANSMITTER RECEIVER OUTPUTS INVALID
RECEIVER OR SHDN FORCEON
EN
MODE OF
INPUT?
INPUT
INPUT
INPUT
OUTPUTS
OUTPUTS (NOTE 7) OUTPUT
OPERATION
ICL3222E, ICL3241E
N/A
N/A
L
L
N/A
N/A
L
High-Z
High-Z
Active
Active
Active
N/A
N/A
Manual Power-Down
H
High-Z
Manual Power-Down with
Receiver Disabled
N/A
N/A
H
H
N/A
N/A
L
Active
Active
Active
Active
Active
N/A
N/A
Normal Operation
H
High-Z
Normal Operation with
Receiver Disabled
FN4910.21
February 22, 2010
15
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
TABLE 2. POWER-DOWN AND ENABLE LOGIC TRUTH TABLE (Continued)
RS-232
SIGNAL
PRESENT
AT
FORCEOFF
R
OUTB
TRANSMITTER RECEIVER OUTPUTS INVALID
RECEIVER OR SHDN FORCEON
EN
MODE OF
INPUT?
INPUT
INPUT
INPUT
OUTPUTS
OUTPUTS (NOTE 7) OUTPUT
OPERATION
ICL3221E, ICL3223E
No
No
H
H
H
H
H
H
L
H
H
L
L
H
L
Active
Active
Active
Active
High-Z
High-Z
High-Z
High-Z
Active
High-Z
Active
High-Z
Active
High-Z
Active
High-Z
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
L
L
Normal Operation
(Auto Power-Down Disabled)
Yes
Yes
No
H
H
L
Normal Operation
(Auto Power-Down Enabled)
L
H
L
L
Power-Down Due to Auto
Power-Down Logic
No
L
H
L
L
Yes
Yes
X
X
H
H
Manual Power-Down
L
H
Manual Power-Down
with Receiver Disabled
No
No
L
L
X
X
L
High-Z
High-Z
Active
N/A
N/A
L
L
Manual Power-Down
H
High-Z
Manual Power-Down
with Receiver Disabled
ICL3243E
No
H
H
H
H
L
N/A
N/A
N/A
Active
Active
High-Z
Active
Active
Active
Active
Active
Active
L
H
L
Normal Operation
(Auto Power-Down Disabled)
Yes
No
Normal Operation
(Auto Power-Down Enabled)
L
Power-Down Due to Auto
Power-Down Logic
Yes
No
L
L
X
X
N/A
N/A
High-Z
High-Z
High-Z
High-Z
Active
Active
H
L
Manual Power-Down
Manual Power-Down
NOTE:
7. Applies only to the ICL3241E and ICL3243E.
The INVALID output always indicates whether or not a
valid RS-232 signal is present at any of the receiver
inputs (see Table 2), giving the user an easy way to
determine when the interface block should power
down. In the case of a disconnected interface cable
where all the receiver inputs are floating (but pulled to
GND by the internal receiver pull down resistors), the
INVALID logic detects the invalid levels and drives the
output low. The power management logic then uses
this indicator to power down the interface block.
Reconnecting the cable restores valid levels at the
receiver inputs, INVALID switches high, and the power
management logic wakes up the interface block.
INVALID can also be used to indicate the DTR or RING
INDICATOR signal, as long as the other receiver inputs
are floating, or driven to GND (as in the case of a
powered down driver). Connecting FORCEOFF and
FORCEON together disables the automatic power-down
feature, enabling them to function as a manual
SHUTDOWN input (see Figure 4).
V
CC
V
CC
CURRENT
FLOW
V
CC
V
= V
CC
OUT
Rx
POWERED
DOWN
UART
Tx
OLD
RS-232 CHIP
SHDN = GND
GND
FIGURE 2. POWER DRAIN THROUGH POWERED
DOWN PERIPHERAL
FN4910.21
February 22, 2010
16
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
V
CC
MASTER POWER-DOWN LINE
0.1µF
POWER
MANAGEMENT
UNIT
TRANSITION
DETECTOR
1MΩ
TO
WAKE-UP
LOGIC
ICL324XE
FORCEOFF
FORCEON
V
CC
ICL3221E, ICL3223E, ICL3243E
R2
OUTB
R
T
V
= HI-Z
X
OUT
FIGURE 5. CIRCUIT TO PREVENT AUTO
POWER-DOWN FOR 100ms AFTER
FORCED POWER-UP
R2
OUT
POWERED
DOWN
UART
R2
IN
T1
IN
X
Automatic Power-Down
T1
OUT
(ICL3221E, ICL3223E, ICL3243E Only)
FORCEOFF = GND
OR SHDN = GND, EN = V
CC
Even greater power savings is available by using the
devices which feature an automatic power-down
function. When no valid RS-232 voltages (see Figure 6)
are sensed on any receiver input for 30µs, the charge
pump and transmitters power-down, thereby reducing
supply current to 1µA. Invalid receiver levels occur
whenever the driving peripheral’s outputs are shut off
(powered down) or when the RS-232 interface cable is
disconnected. The ICL32xxE powers back up whenever it
detects a valid RS-232 voltage level on any receiver
input. This automatic power-down feature provides
additional system power savings without changes to the
existing operating system.
FIGURE 3. DISABLED RECEIVERS PREVENT POWER
DRAIN
FORCEOFF
PWR
FORCEON
MGT
LOGIC
INVALID
ICL3221E,
ICL3223E,
ICL3243E
VALID RS-232 LEVEL - ICL32xxE IS ACTIVE
2.7V
INDETERMINATE - POWER-DOWN MAY OR
MAY NOT OCCUR
I/O
UART
CPU
0.3V
INVALID LEVEL - POWER-DOWN OCCURS AFTER 30µs
-0.3V
INDETERMINATE - POWER-DOWN MAY OR
MAY NOT OCCUR
FIGURE 4. CONNECTIONS FOR MANUAL
POWER-DOWN WHEN NO VALID
RECEIVER SIGNALS ARE PRESENT
-2.7V
VALID RS-232 LEVEL - ICL32xxE IS ACTIVE
FIGURE 6. DEFINITION OF VALID RS-232 RECEIVER
LEVELS
With any of the control schemes, the time required to
exit power-down, and resume transmission is only
100µs. A mouse, or other application, may need more
time to wake up from shutdown. If automatic
power-down is being utilized, the RS-232 device will
reenter power-down if valid receiver levels aren’t
reestablished within 30µs of the ICL32xxE powering up.
Figure 5 illustrates a circuit that keeps the ICL32xxE from
initiating automatic power-down for 100ms after
powering up. This gives the slow-to-wake peripheral
circuit time to reestablish valid RS-232 output levels.
Automatic power-down operates when the FORCEON
input is low, and the FORCEOFF input is high. Tying
FORCEON high disables automatic power-down, but
manual power-down is always available via the
overriding FORCEOFF input. Table 2 summarizes the
automatic power-down functionality.
FN4910.21
February 22, 2010
17
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Devices with the automatic power-down feature include
an INVALID output signal, which switches low to indicate
that invalid levels have persisted on all of the receiver
inputs for more than 30µs (see Figure 7). INVALID
switches high 1µs after detecting a valid RS-232 level on
a receiver input. INVALID operates in all modes (forced
or automatic power-down, or forced on), so it is also
useful for systems employing manual power-down
circuitry. When automatic power-down is utilized,
INVALID = 0 indicates that the ICL32xxE is in
power-down mode.
larger nominal value. The capacitor’s equivalent series
resistance (ESR) usually rises at low temperatures and it
influences the amount of ripple on V+ and V-.
TABLE 3. REQUIRED CAPACITOR VALUES
V
(V)
C
(µF)
C , C , C
CC
1
2
3
4
(µF)
3.0 to 3.6
4.5 to 5.5
3.0 to 5.5
0.1
0.1
0.047
0.1
0.33
0.47
The time to recover from automatic power-down mode is
typically 100µs.
Power Supply Decoupling
In most circumstances a 0.1µF bypass capacitor is
RECEIVER
INPUTS
INVALID
REGION
adequate. In applications that are particularly sensitive
to power supply noise, decouple V to ground with a
}
CC
capacitor of the same value as the charge-pump
capacitor C . Connect the bypass capacitor as close as
possible to the IC.
TRANSMITTER
OUTPUTS
1
V
CC
0
Operation Down to 2.7V
INVALID
OUTPUT
t
t
INVH
INVL
ICL32xxE transmitter outputs meet RS-562 levels
PWR UP
AUTOPWDN
(±3.7V), at full data rate, with V
as low as 2.7V.
CC
V+
RS-562 levels typically ensure interoperability with
RS-232 devices.
V
CC
0
Transmitter Outputs when
Exiting Power-Down
V-
Figure 8 shows the response of two transmitter outputs
when exiting power-down mode. As they activate, the
two transmitter outputs properly go to opposite RS-232
levels, with no glitching, ringing, nor undesirable
transients. Each transmitter is loaded with 3kΩ in parallel
with 2500pF. Note that the transmitters enable only
when the magnitude of the supplies exceed
FIGURE 7. AUTOMATIC POWER-DOWN AND
INVALID TIMING DIAGRAMS
Receiver ENABLE Control
(ICL3221E, ICL3222E, ICL3223E, ICL3241E
Only)
approximately 3V..
Several devices also feature an EN input to control the
receiver outputs. Driving EN high disables all the
inverting (standard) receiver outputs placing them in a
high impedance state. This is useful to eliminate supply
current, due to a receiver output forward biasing the
protection diode, when driving the input of a powered
5V/DIV
FORCEOFF
T1
down (V
= GND) peripheral (see Figure 2). The enable
CC
input has no effect on transmitter nor monitor (R
outputs.
)
OUTB
2V/DIV
Capacitor Selection
The charge pumps require 0.1µF capacitors for 3.3V
T2
operation. For other supply voltages refer to Table 3 for
capacitor values. Do not use values smaller than those
listed in Table 3. Increasing the capacitor values (by a
factor of 2) reduces ripple on the transmitter outputs and
V
= +3.3V
CC
C1 - C4 = 0.1µF
TIME (20µs/DIV)
slightly reduces power consumption. C , C , and C can
2
3
4
FIGURE 8. TRANSMITTER OUTPUTS WHEN EXITING
POWER-DOWN
be increased without increasing C ’s value, however, do
1
not increase C without also increasing C , C , and C to
1
2
3
4
maintain the proper ratios (C to the other capacitors).
1
Mouse Driveability
When using minimum required capacitor values, make
sure that capacitor values do not degrade excessively
with temperature. If in doubt, use capacitors with a
The ICL3241E and ICL3243E have been specifically
designed to power a serial mouse while operating from
low voltage supplies. Figure 9 shows the transmitter
FN4910.21
February 22, 2010
18
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
output voltages under increasing load current. The
on-chip switching regulator ensures the transmitters will
5V/DIV
supply at least ±5V during worst case conditions (15mA
T1
IN
for paralleled V+ transmitters, 7.3mA for single V-
transmitter). The Automatic Power-Down feature does
not work with a mouse, so FORCEOFF and FORCEON
should be connected to V
.
CC
T1
OUT
OUT
6
5
4
3
V
+
OUT
R1
V
= 3.0V
CC
2
1
V
= +3.3V
CC
C1 - C4 = 0.1µF
T1
0
V
+
OUT
5µs/DIV
-1
-2
-3
-4
-5
-6
T2
T3
FIGURE 11. LOOPBACK TEST AT 120kbps
ICL3241E, ICL3243E
V
V
-
CC
1
OUT
V
-
OUT
5V/DIV
T1
0
2
3
4
5
6
7
8
9
10
IN
LOAD CURRENT PER TRANSMITTER (mA)
FIGURE 9. TRANSMITTER OUTPUT VOLTAGE vs LOAD
CURRENT (PER TRANSMITTER, i.e.,
DOUBLE CURRENT AXIS FOR TOTAL
T1
OUT
OUT
V
CURRENT)
OUT+
High Data Rates
The ICL32xxE maintain the RS-232 ±5V minimum
transmitter output voltages even at high data rates.
Figure 10 details a transmitter loopback test circuit, and
Figure 11 illustrates the loopback test result at 120kbps.
For this test, all transmitters were simultaneously driving
RS-232 loads in parallel with 1000pF, at 120kbps.
Figure 12 shows the loopback results for a single
transmitter driving 1000pF and an RS-232 load at
250kbps. The static transmitters were also loaded with
an RS-232 receiver.
R1
V
= +3.3V
CC
C1 - C4 = 0.1µF
2µs/DIV
FIGURE 12. LOOPBACK TEST AT 250kbps
Interconnection with 3V and 5V
Logic
V
The ICL32XX directly interface with 5V CMOS and TTL
logic families. Nevertheless, with the ICL32XX at 3.3V,
and the logic supply at 5V, AC, HC, and CD4000 outputs
can drive ICL32XX inputs, but ICL32XX outputs do not
CC
+
0.1µF
V
CC
V+
V-
+
+
reach the minimum V for these logic families. See
Table 4 for more information.
C1+
IH
+
C
C
1
2
C
3
4
C1-
C2+
C2-
ICL32xxE
TABLE 4. LOGIC FAMILY COMPATIBILITY WITH
VARIOUS SUPPLY VOLTAGES
C
+
SYSTEM
POWER-SUPPLY
VOLTAGE
(V)
V
CC
SUPPLY
VOLTAGE
(V)
T
T
IN
OUT
COMPATIBILITY
1000pF
R
IN
R
OUT
3.3
3.3
Compatible with all CMOS
families.
EN
5K
5
5
Compatible with all TTL and
CMOS logic families.
SHDN OR
V
CC
FORCEOFF
FIGURE 10. TRANSMITTER LOOPBACK TEST CIRCUIT
FN4910.21
February 22, 2010
19
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
TABLE 4. LOGIC FAMILY COMPATIBILITY WITH
IEC61000-4-2 Testing
The IEC61000 test method applies to finished
VARIOUS SUPPLY VOLTAGES (Continued)
SYSTEM
POWER-SUPPLY
VOLTAGE
(V)
V
CC
equipment, rather than to an individual IC. Therefore,
the pins most likely to suffer an ESD event are those that
are exposed to the outside world (the RS-232 pins in this
case), and the IC is tested in its typical application
configuration (power applied) rather than testing each
pin-to-pin combination. The lower current limiting
resistor coupled with the larger charge storage capacitor
yields a test that is much more severe than the HBM test.
The extra ESD protection built into this device’s RS-232
pins allows the design of equipment meeting level 4
criteria without the need for additional board level
protection on the RS-232 port.
SUPPLY
VOLTAGE
(V)
COMPATIBILITY
5
3.3
Compatible with ACT and
HCT CMOS, and with TTL.
ICL32XX outputs are
incompatible with AC, HC,
and CD4000 CMOS inputs.
±15kV ESD Protection
All pins on ICL32XX devices include ESD protection
structures, but the ICL32xxE family incorporates
advanced structures which allow the RS-232 pins
(transmitter outputs and receiver inputs) to survive ESD
events up to ±15kV. The RS-232 pins are particularly
vulnerable to ESD damage because they typically
connect to an exposed port on the exterior of the finished
product. Simply touching the port pins, or connecting a
cable, can cause an ESD event that might destroy
unprotected ICs. These new ESD structures protect the
device whether or not it is powered up, protect without
allowing any latch-up mechanism to activate, and don’t
interfere with RS-232 signals as large as ±25V.
AIR-GAP DISCHARGE TEST METHOD
For this test method, a charged probe tip moves toward
the IC pin until the voltage arcs to it. The current
waveform delivered to the IC pin depends on approach
speed, humidity, temperature, etc., so it is difficult to
obtain repeatable results. The “E” device RS-232 pins
withstand ±15kV air-gap discharges.
CONTACT DISCHARGE TEST METHOD
During the contact discharge test, the probe contacts the
tested pin before the probe tip is energized, thereby
eliminating the variables associated with the air-gap
discharge. The result is a more repeatable and
predictable test, but equipment limits prevent testing
devices at voltages higher than ±8kV. All “E” family
devices survive ±8kV contact discharges on the RS-232
pins.
Human Body Model (HBM) Testing
As the name implies, this test method emulates the ESD
event delivered to an IC during human handling. The
tester delivers the charge through a 1.5kΩ current
limiting resistor, making the test less severe than the
IEC61000 test which utilizes a 330Ω limiting resistor. The
HBM method determines an IC’s ability to withstand the
ESD transients typically present during handling and
manufacturing. Due to the random nature of these
events, each pin is tested with respect to all other pins.
The RS-232 pins on “E” family devices can withstand
HBM ESD events to ±15kV.
Typical Performance Curves
V
= 3.3V, T = +25°C.
CC A
25
6
V
+
OUT
4
2
20
1 TRANSMITTER AT 250kbps
1 OR 2 TRANSMITTERS AT 30kbps
15
10
5
0
-SLEW
-2
-4
+SLEW
V
-
OUT
-6
0
1000
2000
3000
4000
5000
0
1000
2000
3000
4000
5000
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
FIGURE 13. TRANSMITTER OUTPUT VOLTAGE vs
LOAD CAPACITANCE
FIGURE 14. SLEW RATE vs LOAD CAPACITANCE
FN4910.21
February 22, 2010
20
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Typical Performance Curves
V
= 3.3V, T = +25°C. (Continued)
CC
A
45
45
ICL3221E
ICL3222E, ICL3223E, ICL3232E
40
35
30
25
20
15
10
40
250kbps
35
250kbps
30
25
120kbps
20kbps
20
15
10
120kbps
20kbps
5
0
5
0
0
1000
2000
3000
4000
5000
0
1000
2000
3000
4000
5000
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
FIGURE 16. SUPPLY CURRENT vs LOAD
FIGURE 15. SUPPLY CURRENT vs LOAD
CAPACITANCE WHEN TRANSMITTING
DATA
CAPACITANCE WHEN TRANSMITTING
DATA
45
40
35
30
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
NO LOAD
ALL OUTPUTS STATIC
ICL324XE
250kbps
ICL3221E, ICL3222E, ICL3223E, ICL3232E
120kbps
25
20
20kbps
4000
ICL324XE
15
10
ICL324XE
2.5 3.0
3.5
4.0
4.5
5.0
5.5
6.0
5000
2000
3000
1000
0
SUPPLY VOLTAGE (V)
LOAD CAPACITANCE (pF)
FIGURE 18. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 17. SUPPLY CURRENT vs LOAD
CAPACITANCE WHEN TRANSMITTING
DATA
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
ICL3221E: 286
ICL3222E: 338
ICL3223E: 357
ICL3232E: 296
ICL324XE: 464
PROCESS:
Si Gate CMOS
FN4910.21
February 22, 2010
21
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
2/22/10 FN4910.21 Revision history begins with this revision.
Converted to new Intersil template.
Added new temp grade (F = extended industrial) to ICL3232. Updated ordering info table, Operating
Conditions, and added 125°C specs for input lkg currents, and rcvr output high voltage.
Pages 8-10: Removed all withdrawn devices from Ordering Information table.
Pages 12-14: Added "Boldface limits apply over the operating temperature range." to common
conditions of Electrical Specs table. Replaced Note 6 "Parts are 100% tested at +25°C. Full temp limits
are guaranteed by bench and tester characterization." with "Parameters with MIN and/or MAX limits
are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested."
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
FN4910.21
February 22, 2010
22
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Dual-In-Line Plastic Packages (PDIP)
E18.3 (JEDEC MS-001-BC ISSUE D)
N
18 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
INCHES
MILLIMETERS
1
2
3
N/2
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
0.015
0.115
0.014
0.045
0.008
0.845
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
21.47
0.13
7.62
6.10
4
D
E
BASE
PLANE
0.195
0.022
0.070
0.014
0.880
-
4.95
0.558
1.77
0.355
22.35
-
-
A2
A
-
SEATING
PLANE
L
C
L
B1
C
8, 10
D1
B1
-
eA
A1
A
D1
e
D
5
eC
C
B
eB
D1
E
5
0.010 (0.25) M
C
B S
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
e
A
6
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
e
-
0.430
0.150
-
10.92
3.81
7
B
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in
N
18
18
JEDEC seating plane gauge GS-3.
Rev. 2 11/03
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
e
6. E and
are measured with the leads constrained to be perpendic-
A
-C-
ular to datum
.
7. e and e are measured at the lead tips with the leads unconstrained.
B
C
e
must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3
may have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
FN4910.21
February 22, 2010
23
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
N
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
0.25(0.010)
M
B M
H
AREA
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
0.0688
0.0098
0.020
MIN
1.35
0.10
0.33
0.19
9.80
3.80
MAX
1.75
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
-
1
2
3
0.25
-
L
0.51
9
SEATING PLANE
A
0.0075
0.3859
0.1497
0.0098
0.3937
0.1574
0.25
-
-A-
10.00
4.00
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
16
16
7
0°
8°
0°
8°
-
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
FN4910.21
February 22, 2010
24
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Thin Shrink Small Outline Plastic Packages (TSSOP)
M16.173
N
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
0.25(0.010)
M
B M
E
AREA
INCHES
MIN
MILLIMETERS
E1
-B-
GAUGE
PLANE
SYMBOL
MAX
0.043
0.006
0.037
0.012
0.008
0.201
0.177
MIN
-
MAX
1.10
0.15
0.95
0.30
0.20
5.10
4.50
NOTES
A
A1
A2
b
-
-
0.002
0.033
0.0075
0.0035
0.193
0.169
0.05
0.85
0.19
0.09
4.90
4.30
-
1
2
3
-
L
0.25
0.010
0.05(0.002)
D
SEATING PLANE
A
9
-A-
c
-
D
3
-C-
E1
e
4
α
0.026 BSC
0.65 BSC
-
A2
e
A1
c
E
0.246
0.020
0.256
0.028
6.25
0.50
6.50
0.70
-
b
0.10(0.004)
L
6
0.10(0.004) M
C
A M B S
N
16
16
7
o
o
o
o
0
8
0
8
-
α
NOTES:
Rev. 1 2/02
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact. (Angles in degrees)
FN4910.21
February 22, 2010
25
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Small Outline Plastic Packages (SSOP)
M16.209 (JEDEC MO-150-AC ISSUE B)
N
16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
GAUGE
PLANE
SYMBOL
MIN
MAX
0.078
-
MIN
-
MAX
2.00
-
NOTES
-B-
A
A1
A2
B
-
-
0.002
0.065
0.009
0.004
0.233
0.197
0.05
1.65
0.22
0.09
5.90
5.00
-
1
2
3
0.072
0.014
0.009
0.255
0.220
1.85
0.38
0.25
6.50
5.60
-
L
0.25
0.010
SEATING PLANE
A
9
-A-
C
D
E
-
D
3
-C-
4
α
e
0.026 BSC
0.65 BSC
-
A2
e
A1
C
H
L
0.292
0.022
0.322
0.037
7.40
0.55
8.20
0.95
-
B
0.10(0.004)
6
0.25(0.010) M
C
A M B S
N
α
16
16
7
0°
8°
0°
8°
-
NOTES:
Rev. 3 6/05
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.20mm (0.0078
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.20mm (0.0078 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.13mm (0.005 inch) total in excess of “B” dimen-
sion at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
FN4910.21
February 22, 2010
26
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Small Outline Plastic Packages (SOIC)
M16.3 (JEDEC MS-013-AA ISSUE C)
N
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
0.25(0.010)
M
L
B M
H
AREA
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
10.10
7.40
MAX
2.65
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
0.4133
0.2992
-
0.30
-
1
2
3
0.51
9
SEATING PLANE
A
0.0091
0.3977
0.2914
0.32
-
-A-
10.50
7.60
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
16
16
7
0°
8°
0°
8°
-
NOTES:
Rev. 1 6/05
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
FN4910.21
February 22, 2010
27
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Small Outline Plastic Packages (SOIC)
M18.3 (JEDEC MS-013-AB ISSUE C)
N
18 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
0.25(0.010)
M
L
B M
H
AREA
INCHES
MIN
MILLIMETERS
E
SYMBOL
MAX
0.1043
0.0118
0.0200
0.0125
0.4625
0.2992
MIN
2.35
0.10
0.33
0.23
11.35
7.40
MAX
2.65
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
-
0.30
-
1
2
3
0.51
9
SEATING PLANE
A
0.0091
0.4469
0.2914
0.32
-
-A-
11.75
7.60
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
18
18
7
0°
8°
0°
8°
-
NOTES:
Rev. 1 6/05
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Thelead width“B”, as measured 0.36mm (0.014inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
FN4910.21
February 22, 2010
28
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Thin Shrink Small Outline Plastic Packages (TSSOP)
M20.173
N
20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
INDEX
0.25(0.010)
M
B M
E
PACKAGE
AREA
E1
-B-
INCHES
MIN
MILLIMETERS
GAUGE
PLANE
SYMBOL
MAX
0.047
0.006
0.051
0.0118
0.0079
0.260
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
6.60
4.50
NOTES
A
A1
A2
b
-
-
1
2
3
0.002
0.031
0.0075
0.0035
0.252
0.169
0.05
0.80
0.19
0.09
6.40
4.30
-
L
0.25
0.010
-
0.05(0.002)
D
SEATING PLANE
A
9
-A-
c
-
D
3
-C-
α
E1
e
4
A2
e
A1
0.026 BSC
0.65 BSC
-
c
b
0.10(0.004)
E
0.246
0.256
6.25
0.45
6.50
0.75
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
6
N
20
20
7
NOTES:
o
o
o
o
0
8
0
8
-
α
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
Rev. 1 6/98
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
FN4910.21
February 22, 2010
29
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Shrink Small Outline Plastic Packages (SSOP)
M20.209 (JEDEC MO-150-AE ISSUE B)
N
20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
M
M
B
0.25(0.010)
H
AREA
INCHES
MIN
MILLIMETERS
E
GAUGE
PLANE
SYMBOL
MAX
0.078
0.008’
0.070’
0.015
0.008
0.289
0.212
MIN
1.73
0.05
1.68
0.25
0.09
7.07
5.20’
MAX
1.99
0.21
1.78
0.38
0.20’
7.33
5.38
NOTES
-B-
A
A1
A2
B
0.068
0.002
0.066
0.010’
0.004
0.278
0.205
1
2
3
L
0.25
0.010
SEATING PLANE
A
9
-A-
C
D
E
D
3
4
-C-
α
e
0.026 BSC
0.65 BSC
A2
e
A1
C
H
L
0.301
0.025
0.311
0.037
7.65
0.63
7.90’
0.95
B
0.10(0.004)
6
7
M
M
S
B
0.25(0.010)
C
A
N
α
20
20
0 deg.
8 deg.
0 deg.
8 deg.
NOTES:
Rev. 3 11/02
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess
of “B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
FN4910.21
February 22, 2010
30
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Thin Shrink Small Outline Plastic Packages (TSSOP)
M28.173
N
28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
INDEX
PACKAGE
0.25(0.010)
M
B M
E
AREA
E1
-B-
INCHES
MIN
MILLIMETERS
GAUGE
PLANE
SYMBOL
MAX
0.047
0.006
0.051
0.0118
0.0079
0.386
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
9.80
4.50
NOTES
A
A1
A2
b
-
-
1
2
3
0.002
0.031
0.0075
0.0035
0.378
0.169
0.05
0.80
0.19
0.09
9.60
4.30
-
L
-
0.25
0.010
0.05(0.002)
D
SEATING PLANE
A
9
-A-
c
-
D
3
-C-
E1
e
4
α
A2
e
A1
0.026 BSC
0.65 BSC
-
c
b
0.10(0.004)
E
0.246
0.256
6.25
0.45
6.50
0.75
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
6
N
28
28
7
o
o
o
o
NOTES:
0
8
0
8
-
α
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AE, Issue E.
Rev. 0 6/98
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
FN4910.21
February 22, 2010
31
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Shrink Small Outline Plastic Packages (SSOP)
M28.209 (JEDEC MO-150-AH ISSUE B)
N
28 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
GAUGE
PLANE
SYMBOL
MIN
MAX
0.078
-
MIN
-
MAX
2.00
-
NOTES
-B-
A
A1
A2
B
-
-
0.002
0.065
0.009
0.004
0.390
0.197
0.05
1.65
0.22
0.09
9.90
5.00
-
1
2
3
0.072
0.014
0.009
0.413
0.220
1.85
0.38
0.25
10.50
5.60
-
L
0.25
0.010
SEATING PLANE
A
9
-A-
C
D
E
-
D
3
-C-
4
α
e
0.026 BSC
0.65 BSC
-
A2
e
A1
C
H
L
0.292
0.022
0.322
0.037
7.40
0.55
8.20
0.95
-
B
0.10(0.004)
6
0.25(0.010) M
C
A M B S
N
α
28
28
7
NOTES:
0°
8°
0°
8°
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
Rev. 2 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.20mm (0.0078 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.20mm (0.0078
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.13mm (0.005 inch) total in excess of
“B” dimension at maximum material condition.
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
FN4910.21
February 22, 2010
32
ICL3221E, ICL3222E, ICL3223E, ICL3232E, ICL3241E, ICL3243E
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
0.25(0.010)
M
L
B M
H
AREA
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
18.10
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
-
1
2
3
9
SEATING PLANE
A
0.0091
0.6969
0.2914
-
0.7125 17.70
3
-A-
o
h x 45
D
0.2992
7.40
4
0.05 BSC
1.27 BSC
-
-C-
α
H
h
0.394
0.01
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
0.016
6
0.25(0.010) M
C
A M B S
N
α
28
28
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN4910.21
February 22, 2010
33
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