HSP45102SC-4096 [RENESAS]
0-BIT, DSP-NUM CONTROLLED OSCILLATOR, PDSO28, PLASTIC, MS-013AE, SOIC-28;
| 型号： | HSP45102SC-4096 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 0-BIT, DSP-NUM CONTROLLED OSCILLATOR, PDSO28, PLASTIC, MS-013AE, SOIC-28 时钟 光电二极管 外围集成电路 |
| 文件： | 总9页 (文件大小：189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HSP45102
®
Data Sheet
April 25, 2007
FN2810.9
12-Bit Numerically Controlled Oscillator
Features
The Intersil HSP45102 is Numerically Controlled Oscillator
(NCO12) with 32-bit frequency resolution and 12-bit output.
With over 69dB of spurious free dynamic range and worst
case frequency resolution of 0.009Hz, the NCO12 provides
significant accuracy for frequency synthesis solutions at a
competitive price.
• 33MHz, 40MHz Versions
• 32-Bit Frequency Control
• BFSK, QPSK Modulation
• Serial Frequency Load
• 12-Bit Sine Output
The frequency to be generated is selected from two frequency
control words. A single control pin selects which word is used
to determine the output frequency. Switching from one
frequency to another occurs in one clock cycle, with a 6 clock
pipeline delay from the time that the new control word is
loaded until t4-he new frequency appears on the output.
• Offset Binary Output Format
• 0.009Hz Tuning Resolution at 40MHz
• Spurious Frequency Components <-69dBc
• Fully Static CMOS
• Low Cost
Two pins, P0-1, are provided for phase modulation. They are
encoded and added to the top two bits of the phase
accumulator to offset the phase in 90° increments.
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
The 13-bit output of the Phase Offset Adder is mapped to the
sine wave amplitude via the Sine ROM. The output data
format is offset binary to simplify interfacing to D/A
converters. Spurious frequency components in the output
sinusoid are less than -69dBc.
• Direct Digital Synthesis
• Modulation
• PSK Communications
• Related Products
The NCO12 has applications as a Direct Digital Synthesizer
and modulator in low cost digital radios, satellite terminals,
and function generators.
- HI5731 12-Bit, 100MHz D/A Converter
Ordering Information
TEMP.
PKG.
PART NUMBER
HSP45102SC-33
PART MARKING
HSP45102SC-33
RANGE (°C)
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
PACKAGE
28 Ld SOIC (300 mil)
DWG. #
M28.3
HSP45102SC-33Z (Note)
HSP45102SC-40
HSP45102SC-33Z
HSP45102SC -40
HSP45102SC-40Z
HSP45102SI -33
HSP45102SI-33Z
28 Ld SOIC (300 mil) (Pb-free)
28 Ld SOIC (300 mil)
M28.3
M28.3
M28.3
M28.3
M28.3
HSP45102SC-40Z (Note)
HSP45102SI-3396
28 Ld SOIC (300 mil)(Pb-free)
28 Ld SOIC (300 mil) (Tape and Reel)
28 Ld SOIC (300 mil) (Pb-free)
HSP45102SI-33Z (Note)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1999, 2004, 2005, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
HSP45102
Block Diagram
CLK
PO-1
32
32
MSB/LSB
SFTEN
SD
PHASE
OFFSET
ADDER
FREQUENCY
CONTROL
SECTION
13
12
PHASE
ACCUMULATOR
SINE
ROM
13
OUT0-11
SCLK
LOAD
TXFR
ENPHAC
SEL_L/M
Pinout
HSP45102
(28 LEAD SOIC)
TOP VIEW
OUT6
OUT5
28
1
2
3
4
5
6
7
8
9
OUT7
OUT8
OUT9
OUT10
OUT11
GND
27 OUT4
26 OUT3
25 OUT2
24 OUT1
23 OUT0
22 V
CC
21 GND
20
V
CC
SEL_L/M
P0
SFTEN 10
MSB/LSB 11
ENPHAC 12
SD 13
19 P1
18 LOAD
17 TXFR
16 CLK
15 GND
SCLK 14
FN2810.9
April 25, 2007
2
HSP45102
Pin Description
NAME
TYPE
DESCRIPTION
V
+5V power supply pin.
Ground
CC
GND
P0-1
I
Phase modulation inputs (become active after a pipeline delay of four clocks). A phase shift of 0°, 90°,
180°, or 270° can be selected as shown in Table 1.
CLK
SCLK
I
I
I
NCO clock. (CMOS level)
This pin clocks the frequency control shift register.
SEL_L/M
A high on this input selects the least significant 32 bits of the 64-bit frequency register as the input to
the phase accumulator; a low selects the most significant 32 bits.
SFTEN
I
I
The active low input enables the shifting of the frequency register.
MSB/LSB
This input selects the shift direction of the frequency register. A low on this input shifts in the data LSB
first; a high shifts in the data MSB first.
ENPHAC
I
This pin, when low, enables the clocking of the Phase Accumulator. This input has a pipeline delay of
four clocks.
SD
I
I
Data on this pin is shifted into the frequency register by the rising edge of SCLK when SFTEN is low.
TXFR
This active low input is clocked onto the chip by CLK and becomes active after a pipeline delay of four
clocks. When low, the frequency control word selected by SEL_L/M is transferred from the frequency
register to the phase accumulator’s input register.
LOAD
I
This input becomes active after a pipeline delay of five clocks. When low, the feedback in the phase
accumulator is zeroed.
OUT0-11
O
Output data. OUT0 is LSB. Unsigned.
All inputs are TTL level, with the exception of CLK.
Overline designates active low signals.
FN2810.9
April 25, 2007
3
HSP45102
PHASE OFFSET ADDER
A
D
D
E
R
R.P0-1
R
E
G
2-DLY
R
E
G
OUT0-11
SINE
ROM
13
13
12
R
E
G
/
/
/
P0-1
R.P0-1
13 MSBs
CLK
CLK
/
ENPHAC
TXFR
LOAD
CLK
R.ENPHAC
4-DLY
R
E
G
R.TXFR
R.LOAD
32
32
R
E
G
/
/
CLK
32
‘0’
/
A
D
D
E
R
FREQUENCY
CONTROL
SECTION
R.LOAD
ACCUMULATOR
INPUT
FRCTRL
0-31
REGISTER
32
32
/
64-BIT
SHIFT
REG
32
R
FRCTRL
32-63
/
32
E
/
R.TXFR
/
32
/
G
32
/
CLK
R
SD
E
R.ENPHAC
SCLK
G
CLK
SFTEN
MSB/LSB
SEL_L/M
(HIGH SELECTS FRCTRL0-31, LOW SELECTS FRCTRL32-63)
PHASE ACCUMULATOR
FIGURE 1. NCO-12 FUNCTIONAL BLOCK DIAGRAM
the phase modulation bits P0-1. The architecture is shown in
Figure 1. The most significant 13 bits of the 32-bit phase
accumulator are summed with the two-bit phase offset to
generate the 13-bit phase input to the Sine Rom. A value of
0 corresponds to 0°, a value of 1000 hexadecimal
corresponds to a value of 180°.
Functional Description
The NCO12 produces a 12-bit sinusoid whose frequency
and phase are digitally controlled. The frequency of the sine
wave is determined by one of two 32-bit words. Selection of
the active word is made by SEL_L/M. The phase of the
output is controlled by the two-bit input P0-1, which is used
to select a phase offset of 0°, 90°, 180°, or 270°.
The phase accumulator advances the phase by the amount
programmed into the frequency control register. The output
frequency is equal to:
As shown in the Block Diagram, the NCO12 consists of a
Frequency Control Section, a Phase Accumulator, a Phase
Offset Adder and a Sine ROM. The Frequency Control
section serially loads the frequency control word into the
frequency register. The Phase Accumulator and Phase
Offset Adder compute the phase angle using the frequency
control word and the two phase modulation inputs. The Sine
ROM generates the sine of the computed phase angle. The
format of the 12-bit output is offset binary.
32
f
= (N × f
⁄ 2 ), or
(EQ. 1)
(EQ. 2)
LO
CLK
f
⎛
⎜
⎝
⎞
32
OUT
-------------
N = INT
2
,
⎟
⎠
f
CLK
where N is the 32 bits of frequency control word that is
programmed. INT[•] is the integer of the computation. For
example, if the control word is 20000000 hexadecimal and the
clock frequency is 30MHz, then the output frequency would
Frequency Control Section
The Frequency Control Section shown in Figure 1 serially
loads the frequency data into a 64-bit, bidirectional shift
register. The shift direction is selected with the MSB/LSB
input. When this input is high, the frequency control word on
the SD input is shifted into the register MSB first. When
MSB/LSB is low the data is shifted in LSB first. The register
shifts on the rising edge of SCLK when SFTEN is low. The
timing of these signals is shown in Figures 2A and 2B.
be f
/8, or 3.75MHz.
CLK
The frequency control multiplexer selects the least
significant 32 bits from the 64-bit frequency control register
when SEL_L/M is high, and the most significant 32 bits
when SEL_L/M is low. When only one frequency word is
desired, SEL_L/M and MSB/LSB must be either both high or
both low. This is due to the fact that when a frequency
control word is loaded into the shift register LSB first, it
enters through the most significant bit of the register. After
32 bits have been shifted in, they will reside in the 32 most
significant bits of the 64-bit register.
The 64 bits of the frequency register are sent to the Phase
Accumulator Section where 32 bits are selected to control
the frequency of the sinusoidal output.
Phase Accumulator Section
The phase accumulator and phase offset adder compute the
phase of the sine wave from the frequency control word and
When TXFR is asserted, the 32 bits selected by the frequency
control multiplexer are clocked into the phase accumulator
FN2810.9
April 25, 2007
4
HSP45102
input register. At each clock, the contents of this register are
TABLE 1. PHASE MAPPING
P0-1 CODING
summed with the current contents of the accumulator to step to
the new phase. The phase accumulator stepping may be
inhibited by holding ENPHAC high. The phase accumulator
may be loaded with the value in the input register by asserting
LOAD, which zeroes the feedback to the phase accumulator.
P1
0
P0
0
PHASE SHIFT (DEGREES)
0
0
1
90
The phase adder sums the encoded phase modulation bits
P0-1 and the output of the phase accumulator to offset the
phase by 0°, 90°, 180° or 270°. The two bits are encoded to
produce the phase mapping shown in Table 1. This phase
mapping is provided for direct connection to the in-phase
and quadrature data bits for QPSK modulation.
1
0
270
180
1
1
ROM Section
The ROM section generates the 12-bit sine value from the
13-bit output of the phase adder. The output format is offset
binary and ranges from 001 to FFF hexadecimal, centered
around 800 hexadecimal.
SCLK
SD
2
1
0
61
63
62
SFTEN
MSB/LSB
FIGURE 2A. FREQUENCY LOADING ENABLED BY SFTEN
SCLK
SD
2
1
0
61
63
62
SFTEN
MSB/LSB
FIGURE 2B. FREQUENCY LOADING CONTROLLED BY SCLK
CLK
LOAD
1
2
3
4
5
6
7
8
9
10
11
TXFR
ENPHAC
SEL_L/M
OUT0-11
NEW
DATA
FIGURE 3. I/O TIMING
FN2810.9
April 25, 2007
5
HSP45102
Absolute Maximum Ratings T = +25°C
Thermal Information
A
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
Input, Output or I/O Voltage Applied . . . . .GND -0.5V to V +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical, Note 1)
θ
(°C/W)
JA
CC
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Operating Voltage Range (Commercial, Industrial). . +4.75V to +5.25V
Operating Temperature Range (Commercial) . . . . . . . 0°C to +70°C
Operating Temperature Range (Industrial) . . . . . . . .-40°C to +85°C
Die Characteristics
Backside Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
CC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
DC Electrical Specifications
PARAMETER
Logical One Input Voltage
SYMBOL
TEST CONDITIONS
MIN
2.0
-
MAX
-
UNITS
V
V
V
V
V
V
= 5.25V
= 4.75V
= 5.25V
= 4.75V
IH
CC
CC
CC
CC
Logical Zero Input Voltage
High Level Clock Input
Low Level Clock Input
V
0.8
-
V
IL
V
3.0
-
V
IHC
V
V
0.8
-
V
ILC
OH
Output HIGH Voltage
I
I
= -400μA, V
= 4.75V
= 4.75V
CC
2.6
-
V
OH
OL
CC
Output LOW Voltage
V
= +2.0mA, V
0.4
10
500
99
V
OL
Input Leakage Current
I
V
V
= V
= V
or GND, V
or GND, V
= 5.25V
-10
-
μA
μA
mA
I
IN
IN
CC
CC
CC
CC
Standby Power Supply Current
Operating Power Supply Current
I
= 5.25V, Note 4
CCSB
CCOP
I
f = 33MHz, V = V
IN
or GND
-
CC
= 5.25V, Notes 2 and 4
V
CC
Capacitance T = +25°C, Note 3
A
PARAMETER
Input Capacitance
SYMBOL
TEST CONDITIONS
FREQ = 1MHz, V = Open. All
measurements are referenced to device
ground
MIN
MAX
10
UNITS
pF
C
-
-
IN
CC
Output Capacitance
C
10
pF
O
NOTES:
2. Power supply current is proportional to operating frequency. Typical rating for I
is 3mA/MHz.
CCOP
3. Not tested, but characterized at initial design and at major process/design changes.
4. Output load per test load circuit with switch open and C = 40pF.
L
FN2810.9
April 25, 2007
6
HSP45102
AC Electrical Specifications
V
= 5.0V ±5%, T = 0°C to +70°C, T = -40°C to +85°C (Note 5)
CC
A
A
-33 (33MHz)
MIN MAX
30
-40 (40MHz)
MIN MAX
25
PARAMETER
Clock Period
SYMBOL
NOTES
UNITS
ns
t
-
-
CP
Clock High
t
12
12
12
12
0
-
-
-
-
-
-
-
-
-
-
-
10
10
10
12
0
-
-
-
-
-
-
-
-
-
-
-
ns
CH
Clock Low
t
ns
CL
SCLK High/Low
t
ns
SW
Setup Time SD to SCLK Going High
Hold Time SD from SCLK Going High
t
ns
DS
DH
MS
MH
t
ns
Setup Time SFTEN, MSB/LSB to SCLK Going High
Hold Time SFTEN, MSB/LSB from SCLK Going High
Setup Time SCLK High to CLK Going High
Setup Time P0-1 to CLK Going High
t
15
0
12
0
ns
t
ns
t
Note 6
16
15
1
15
12
1
ns
SS
PS
PH
t
ns
Hold Time P0-1 from CLK Going High
t
ns
Setup Time LOAD, TXFR, ENPHAC, SEL_L/M
to CLK Going High
t
15
13
ns
ES
EH
OH
Hold Time LOAD, TXFR, ENPHAC, SEL_L/M
from CLK Going High
t
1
-
1
-
ns
CLK to Output Delay
Output Rise, Fall Time
NOTES:
t
2
8
15
-
2
8
13
-
ns
ns
t
Note 7
RF
5. AC testing is performed as follows: Input levels (CLK Input) 4.0V and 0V; Input levels (all other inputs) 0V and 3.0V; Timing reference levels
(CLK) 2.0V; All others 1.5V. Output load per test load circuit with switch closed and C = 40pF. Output transition is measured at V > 1.5V and
L
OH
V
< 1.5V.
OL
6. If TXFR is active, care must be taken to not violate setup and hold times as data from the shift registers may not have settled before CLK occurs.
7. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design
changes.
AC Test Load Circuit
S
DUT
1
C
(NOTE)
L
±
I
1.5V
I
OL
OH
SWITCH S1 OPEN FOR I
AND I
CCOP
CCSB
EQUIVALENT CIRCUIT
NOTE: Test head capacitance.
FN2810.9
April 25, 2007
7
HSP45102
Waveforms
t
CP
t
t
CL
CH
CLK
P0-1
t
t
t
t
PS
ES
PH
EH
LOAD, TXFR,
ENPHAC, SEL_L/M
t
t
RF
OH
OUT0-11
t
t
t
SW
SW
SS
SCLK
SD
t
t
DH
DS
t
t
MH
MS
MSB/LSB,
SFTEN
FIGURE 4.
FN2810.9
April 25, 2007
8
HSP45102
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
0.25(0.010)
M
B M
H
AREA
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
18.10
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
-
1
2
3
L
9
SEATING PLANE
A
0.0091
0.6969
0.2914
-
0.7125 17.70
3
-A-
o
h x 45
D
0.2992
7.40
4
0.05 BSC
1.27 BSC
-
-C-
α
H
h
0.394
0.01
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
0.016
6
0.25(0.010) M
C
A M B S
N
α
28
28
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN2810.9
April 25, 2007
9
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