HM62V16102LBPI-3 [RENESAS]
Standard SRAM, 1MX16, 35ns, CMOS, PBGA48, 0.75 MM PITCH, CSP-48;
| 型号： | HM62V16102LBPI-3 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Standard SRAM, 1MX16, 35ns, CMOS, PBGA48, 0.75 MM PITCH, CSP-48 静态存储器 |
| 文件： | 总19页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM62V16102I Series
Wide Temperature Range Version
16 M SRAM (1-Mword × 16-bit)
ADE-203-1248A(Z)
Preliminary
Rev. 0.1
Sep. 27, 2001
Description
The Hitachi HM62V16102I Series is 16-Mbit static RAM organized 1-Mword × 16-bit. HM62V16102I
Series has realized higher density, higher performance and low power consumption by employing Hi-CMOS
process technology. It offers low power standby power dissipation; therefore, it is suitable for battery backup
systems. It is packaged in 48 bumps chip size package with 0.75 mm bump pitch for high density surface
mounting.
Features
•
•
•
•
Single 2.5 V and 3.0 V supply: 2.2 V to 3.6 V
Fast access time: 25/35 ns (max)
Page access time: 15/20 ns (max)
Power dissipation:
Active: TBD (typ)
Standby: 1.5 µW (typ)
•
Completely static memory.
No clock or timing strobe required
Equal access and cycle times
Common data input and output.
Three state output
•
•
•
•
Battery backup operation.
2 chip selection for battery backup
Temperature range: –40 to +85°C
Preliminary: The specification of this device are subject to change without notice. Please contact your
nearest Hitachi’s Sales Dept. regarding specification.
HM62V16102I Series
Ordering Information
Type No.
Access time
Package
HM62V16102LBPI-2
HM62V16102LBPI-3
25 ns
35 ns
48-bumps CSP with 0.75 mm bump pitch (TBD)
HM62V16102LBPI-2SL
HM62V16102LBPI-3SL
25 ns
35 ns
2
HM62V16102I Series
Pin Arrangement
48-bumps CSP
1
2
3
4
5
6
A
LB
OE
A0
A1
A2
CS2
I/O8
I/O9
UB
A3
A5
A4
A6
CS1
I/O0
I/O2
B
C
I/O10
I/O1
D
E
F
V
V
I/O11
I/O12
A17
A7
I/O3
I/O4
V
CC
SS
V
A16
V
SS
CC
SS
I/O14 I/O13
A14
A12
A9
A15
A13
A10
I/O5
WE
A11
I/O6
I/O7
NU
G
I/O15
A18
A19
A8
H
(Top view)
Pin Description
Pin name
A0 to A19
I/O0 to I/O15
CS1
Function
Address input
Data input/output
Chip select 1
Chip select 2
Write enable
CS2
WE
OE
Output enable
Lower byte select
Upper byte select
Power supply
Ground
LB
UB
VCC
VSS
NU*1
Not used (test mode pin)
Note: 1. This pin should be connected to a ground (VSS), or not be connected (open).
3
HM62V16102I Series
Block Diagram
TBD
4
HM62V16102I Series
Operation Table
CS1 CS2 WE
OE
×
UB
×
LB
×
I/O0 to I/O7
High-Z
High-Z
High-Z
Dout
I/O8 to I/O15
High-Z
High-Z
High-Z
Dout
Operation
Standby
H
×
×
×
L
×
×
×
×
Standby
×
L
L
L
L
L
L
L
×
×
×
H
L
H
L
Standby
H
H
H
H
H
H
H
H
H
H
L
L
Read
L
H
L
L
Dout
High-Z
Dout
Lower byte read
Upper byte read
Write
L
H
L
High-Z
Din
×
L
Din
L
×
H
L
L
Din
High-Z
Din
Lower byte write
Upper byte write
Output disable
L
×
H
×
High-Z
High-Z
H
H
×
High-Z
Note: H: VIH, L: VIL, ×: VIH or VIL
Absolute Maximum Ratings
Parameter
Symbol
VCC
Value
Unit
Power supply voltage relative to VSS
–0.5 to + 4.6
–0.5*1 to VCC + 0.3*2
1.0
V
Terminal voltage on any pin relative to VSS
Power dissipation
VT
V
PT
W
°C
°C
Storage temperature range
Tstg
Tbias
–55 to +125
–40 to +85
Storage temperature range under bias
Notes: 1. VT min: –2.0 V for pulse half-width ≤ 10 ns.
2. Maximum voltage is +4.6 V.
DC Operating Conditions
Parameter
Symbol Min
Typ
Max
Unit
Note
Supply voltage
VCC
VSS
VIH
VIL
2.2
2.5/3.0
3.6
V
0
0
0
V
Input high voltage
0.75 × VCC
–0.3
—
—
—
VCC + 0.3
0.25 × VCC
85
V
Input low voltage
V
1
Ambient temperature range
Ta
–40
°C
Note: 1. VIL min: –2.0 V for pulse half-width ≤ 10 ns.
5
HM62V16102I Series
DC Characteristics
Parameter
Symbol Min
Typ*1 Max Unit Test conditions
Input leakage current
Output leakage current
|ILI|
—
—
—
—
1
1
µA
µA
Vin = VSS to VCC
|ILO|
CS1 = VIH or CS2 = VIL or
OE = VIH or WE = VIL or
LB = UB =VIH, VI/O = VSS to VCC
Operating current
ICC
—
—
—
—
—
—
1
mA
mA
mA
CS1 = 0.2 V, CS2 = VCC – 0.2 V,
Others = VCC – 0.2 V/0.2 V,
II/O = 0 mA
Average operating current
ICC1
50
15
Min. cycle, duty = 100%,
II/O = 0 mA, CS1 = VIL, CS2 = VIH,
Others = VIH/VIL
ICC2
Cycle time = 70 ns, duty = 100%,
II/O = 0 mA, CS1 = 0.2 V,
CS2 = VCC – 0.2 V,
Others = VCC – 0.2 V/0.2 V
ICC3
—
—
—
5
mA
µA
Cycle time = 1 µs, duty = 100%,
II/O = 0 mA, CS1 ≤ 0.2 V,
CS2 ≥ VCC – 0.2 V
VIH ≥ VCC – 0.2 V, VIL ≤ 0.2 V
2
Standby current
ISB1
*
0.5
30
0 V ≤ Vin
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS1 ≥ VCC – 0.2 V,
CS2 ≥ VCC – 0.2 V or
(3) LB = UB ≥ VCC – 0.2 V,
CS2 ≥ VCC – 0.2 V,
CS1 ≤ 0.2 V
3
ISB1
*
—
0.5
—
5
µA
V
Output high VCC = 2.7 V to 3.6 V VOH
voltage
2.2
—
IOH = –1 mA
VCC = 2.2 V to 3.6 V VOH
VCC – 0.2 —
—
V
V
IOH = –100 µA
IOL = 2 mA
Output low VCC = 2.7 V to 3.6 V VOL
voltage
—
—
0.4
VCC = 2.2 V to 3.6 V VOL
—
—
0.2
V
IOL = 100 µA
Notes: 1. Typical values are at VCC = 2.5 V/3.0 V, Ta = +25°C and not guaranteed.
2. This characteristic is guaranteed only for L-version.
3. This characteristic is guaranteed only for L-SL version.
6
HM62V16102I Series
Capacitance (Ta = +25°C, f = 1.0 MHz)
Parameter
Symbol
Cin
Min
—
Typ
—
Max
8
Unit
pF
Test conditions Note
Input capacitance
Input/output capacitance
Vin = 0 V
VI/O = 0 V
1
1
CI/O
—
—
10
pF
Note: 1. This parameter is sampled and not 100% tested.
7
HM62V16102I Series
AC Characteristics (Ta = –40 to +85°C, VCC = 2.2 V to 3.6 V, unless otherwise noted.)
Test Conditions
•
•
•
•
Input pulse levels: VIL = 0 V, VIH = VCC
Input rise and fall time: 3 ns
Input and output timing reference levels: 0.5 × VCC
Output load: See figures (Including scope and jig)
VTM
R1
R2
Dout
R1 = 3000 Ω
30pF
R2 = 3000 Ω
VTM = VCC
8
HM62V16102I Series
Read Cycle
HM62V16102I
-2
-3
Parameter
Symbol
tRC
Min
25
—
—
—
—
5
Max Min
Max Unit
Notes
Read cycle time
—
25
25
25
15
—
25
—
—
—
—
12
12
12
12
35
—
—
—
—
5
—
35
35
35
20
—
35
—
—
—
—
15
15
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
Chip select access time
tAA
tACS1
tACS2
tOE
Output enable to output valid
Output hold from address change
LB, UB access time
tOH
tBA
—
5
—
5
Chip select to output in low-Z
tCLZ1
tCLZ2
tBLZ
2, 3
5
5
2, 3
LB, UB enable to low-z
5
5
2, 3
Output enable to output in low-Z
Chip deselect to output in high-Z
tOLZ
3
3
2, 3
tCHZ1
tCHZ2
tBHZ
0
0
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
0
0
LB, UB disable to high-Z
0
0
Output disable to output in high-Z
tOHZ
0
0
Page Mode Cycle
HM62V16102I
-2
-3
Parameter
Symbol
tPC
Min
15
Max Min
Max Unit
Notes
Page read cycle time
Page address access time
—
20
—
—
ns
ns
tPA
—
15
20
9
HM62V16102I Series
Write Cycle
HM62V16102I
-2
-3
Parameter
Symbol
tWC
Min
25
20
20
20
20
0
Max Min
Max Unit
Notes
Write cycle time
—
—
—
—
—
—
—
—
—
—
12
12
35
30
30
25
30
0
—
—
—
—
—
—
—
—
—
—
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to end of write
Chip selection to end of write
Write pulse width
tAW
tCW
5
4
tWP
LB, UB valid to end of write
Address setup time
tBW
tAS
6
7
Write recovery time
tWR
0
0
Data to write time overlap
Data hold from write time
Output active from end of write
Output disable to output in High-Z
Write to output in high-Z
tDW
15
0
15
0
tDH
tOW
5
5
2
tOHZ
tWHZ
0
0
1, 2
1, 2
0
0
Notes: 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit
conditions and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device
and from device to device.
4. A write occures during the overlap of a low CS1, a high CS2, a low WE and a low LB or a low UB.
A write begins at the latest transition among CS1 going low, CS2 going high, WE going low and LB
going low or UB going low. A write ends at the earliest transition among CS1 going high, CS2
going low, WE going high and LB going high or UB going high. tWP is measured from the beginning
of write to the end of write.
5. tCW is measured from the later of CS1 going low or CS2 going high to the end of write.
6. tAS is measured from the address valid to the beginning of write.
7. tWR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write
cycle.
10
HM62V16102I Series
Timing Waveform
Read Cycle
tRC
Address
Valid address
tAA
tACS1
CS1
2, 3
2, 3
1, 2, 3
tCLZ1
*
tCHZ1
*
CS2
tACS2
tCLZ2
1, 2, 3
*
tCHZ2
*
1, 2, 3
tBHZ
*
tBA
LB, UB
2, 3
tBLZ
*
1, 2, 3
tOHZ
*
tOE
OE
2, 3
tOLZ
*
tOH
High impedance
Dout
Valid data
11
HM62V16102I Series
Page Mode Cycle
1st read
Page read
t
RC
A3 to A19
A0 to A2
Valid address
t
AA
t
t
t
PC
PC
PC
Valid address
Valid address
Valid address
Valid address
t
t
t
PA
PA
PA
t
AA
t
t
OH
t
OH
OH
CS1
OE
t
ACS
t
CLZ
t
OLZ
t
OE
High-Z
Dout
Valid data
Valid data
Valid data
Valid data
= V or V
IH
IL
12
HM62V16102I Series
Write Cycle (1) (WE Clock)
tWC
Valid address
Address
7
tWR
*
5
5
tCW
*
CS1
tCW
*
CS2
tBW
LB, UB
tAW
4
tWP
*
6
WE
tAS*
tDW
Valid data
tDH
Din
1, 2
tWHZ
*
2
tOW
*
High impedance
Dout
13
HM62V16102I Series
Write Cycle (2) (CS Clock, OE= VIH)
tWC
Valid address
tAW
Address
6
7
5
5
tAS
*
tWR*
tCW
*
CS1
tCW
*
CS2
tBW
LB, UB
4
tWP
*
WE
tDW
Valid data
tDH
Din
High impedance
Dout
14
HM62V16102I Series
Write Cycle (3) (LB, UB Clock, OE = VIH)
tWC
Valid address
tAW
Address
5
5
7
tCW
*
tWR
*
CS1
tCW
*
CS2
6
tBW
tAS
*
LB, UB
4
tWP
*
WE
tDW
Valid data
tDH
Din
High impedance
Dout
15
HM62V16102I Series
Low VCC Data Retention Characteristics (Ta = –40 to +85°C)
Parameter
Symbol
Min
Typ*4
Max
Unit
Test conditions*3
VCC for data retention
VDR
1.2
—
3.6
V
Vin ≥ 0V
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS2 ≥ VCC – 0.2 V,
CS1 ≥ VCC – 0.2 V or
(3) LB = UB ≥ VCC – 0.2 V,
CS2 ≥ VCC – 0.2 V,
CS1 ≤ 0.2 V
1
Data retention current
ICCDR
*
*
—
0.5
30
µA
VCC = 1.5 V, Vin ≥ 0V
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS2 ≥ VCC – 0.2 V,
CS1 ≥ VCC – 0.2 V or
(3) LB = UB ≥ VCC – 0.2 V,
CS2 ≥ VCC – 0.2 V,
CS1 ≤ 0.2 V
2
ICCDR
tCDR
—
0
0.5
—
5
µA
ns
Chip deselect to data
retention time
—
See retention waveform
Operation recovery time
tR
tRC*5
—
—
ns
Notes: 1. This characteristic is guaranteed only for L-version.
2. This characteristic is guaranteed only for L-SL version.
3. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, LB, UB buffer and Din buffer. If
CS2 controls data retention mode, Vin levels (address, WE, OE, CS1, LB, UB, I/O) can be in the
high impedance state. If CS1 controls data retention mode, CS2 must be CS2 ≥ VCC – 0.2 V or 0 V
≤ CS2 ≤ 0.2 V. The other input levels (address, WE, OE, LB, UB, I/O) can be in the high
impedance state.
4. Typical values are at VCC = 1.5 V, Ta = +25˚C and not guaranteed.
5. tRC = read cycle time.
16
HM62V16102I Series
Low VCC Data Retention Timing Waveform (1) (CS1 Controlled)
Data retention mode
tCDR
tR
VCC
2.2 V
VIH
VDR
CS1
0 V
≥
CS1 VCC – 0.2 V
Low VCC Data Retention Timing Waveform (2) (CS2 Controlled)
tCDR
Data retention mode
tR
VCC
2.2 V
CS2
VDR
VIL
<
<
0 V CS2 0.2 V
0 V
Low VCC Data Retention Timing Waveform (3) (LB, UB Controlled)
Data retention mode
tCDR
tR
VCC
2.2 V
VIH
VDR
LB, UB
0 V
≥
LB, UB VCC – 0.2 V
17
HM62V16102I Series
Package Dimensions
HM62V16102LBPI Series (TBD)
TBD
18
HM62V16102I Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: (03) 3270-2111 Fax: (03) 3270-5109
URL
http://www.hitachisemiconductor.com/
For further information write to:
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(America) Inc.
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Hitachi Europe Ltd.
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Hitachi Asia Ltd.
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Fax: <44> (1628) 585200
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(Taipei Branch Office)
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Copyright © Hitachi, Ltd., 2001. All rights reserved. Printed in Japan.
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19
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