HD74LV2GT123AUS [RENESAS]
LV/LV-A/LVX/H SERIES, MONOSTABLE MULTIVIBRATOR, PDSO8, SSOP-8;
| 型号： | HD74LV2GT123AUS |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | LV/LV-A/LVX/H SERIES, MONOSTABLE MULTIVIBRATOR, PDSO8, SSOP-8 振荡器 转换器 电平转换器 |
| 文件： | 总14页 (文件大小：131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74LV2GT123A
Retriggerable Monostable Multivibrator /
CMOS Logic Level Shifter
REJ03D0004-0300Z
Rev.3.00
Oct.22.2003
Description
The HD74LV2GT123A features output pulse duration control by three methods. In the first method, the A
input is low and the B input goes high. In the second method, the B input is high and the A input goes low.
In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high. The basic
pulse duration is programmed by selecting external resistance and capacitance values. The external timing
capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected
between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance
between Rext/Cext and VCC. Once triggered, the basic pulse duration can be extended by retriggering the
gated low level active (A) or high level active (B) input. Pulse duration can be reduced by taking CLR low.
The output pulse equation is simply : tWQ = Cext • Rext. The input protection circuitry on this device
allows over voltage tolerance on the input, allowing the device to be used as a logic–level translator from
3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while
operating at the high-voltage power supply. Low voltage and high speed operation is suitable for the
battery powered products (e.g., notebook computers), and the low power consumption extends the battery
life.
Features
•
•
•
The basic gate function is lined up as Renesas uni logic series.
Supplied on emboss taping for high-speed automatic mounting.
Control input is TTL compatible input level.
Supply voltage range : 3.0 to 5.5 V
Operating temperature range : –40 to +85°C
•
•
Logic-level translate function
3.0 V CMOS logic → 5.0 V CMOS logic (@VCC = 5.0 V)
1.8 V or 2.5 V CMOS logic → 3.3 V CMOS logic (@VCC = 3.3 V)
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
•
•
•
Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
All the logical inputs have hysteresis voltage for the slow transition.
Ordering Information
Part Name
Package Type
Package Code Package
Taping
Abbreviation Abbreviation (Quantity)
HD74LV2GT123AUSE SSOP-8 pin
TTP-8DBV
US E (3,000 pcs / Reel)
Rev.3.00, Oct.22.2003, page 1 of 1
HD74LV2GT123A
Outline and Article Indication
• HD74LV2GT123A
Index band
Lot No.
Y M W
Y : Year code
(the last digit of year)
M : Month code
W : Week code
T 2 3
SSOP–8
Marking
Function Table
Inputs
Output Q
CLR
L
A
X
H
X
L
B
X
X
L
L
H
L
L
H
H
↑
H
↓
H
H
↑
L
H : High level
L : Low level
X : Immaterial
↑ : Low to high transition
↓ : High to low transition
: High level pulse
Rev.3.00, Oct.22.2003, page 2 of 13
HD74LV2GT123A
Pin Arrangement
1
2
3
4
A
B
8
7
6
5
VCC
Rext / Cext
CLR
GND
Cext
Q
(Top view)
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit Test Conditions
Supply voltage range
Input voltage range *1
Output voltage range *1, 2
VCC
VI
–0.5 to 7.0
–0.5 to 7.0
V
V
V
VO
–0.5 to VCC + 0.5
Output : H or L
CC : OFF
–0.5 to 7.0
–20
V
Input clamp current
IIK
IOK
IO
mA
mA
mA
mA
VI < 0
Output clamp current
Continuous output current
±50
VO < 0 or VO > VCC
VO = 0 to VCC
±25
Continuous current through
VCC or GND
I
CC or IGND
±50
Maximum power dissipation
at Ta = 25°C (in still air) *3
PT
200
mW
°C
Storage temperature
Tstg
–65 to 150
Notes:
The absolute maximum ratings are values, which must not individually be exceeded, and
furthermore no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Rev.3.00, Oct.22.2003, page 3 of 13
HD74LV2GT123A
Recommended Operating Conditions
Item
Symbol
VCC
VI
Min
3.0
0
Typ
—
—
—
—
—
—
—
—
—
—
Max
5.5
5.5
VCC
–6
Unit
V
Conditions
Supply voltage range
Input voltage range
Output voltage range
Output current
V
VO
0
V
IOH
—
—
—
—
0
mA
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
–12
6
IOL
12
Input transition rise or fall rate ∆t / ∆v
100
20
ns / V VCC = 3.0 to 3.6 V
CC = 4.5 to 5.5 V
0
V
External timing resistance
External capacitance
Rext
1
—
kΩ
VCC = 4.5 to 5.5 V
Cext
—
1
Unlimited —
F
Supply transition rise rate
∆t / ∆VCC
—
—
—
ms / V
°C
Operating free-air temperature Ta
–40
85
Note: Unused or floating inputs must be held high or low.
Logic Diagram
Rext/
Cext
Cext
A
B
Q
Q
CLR
CLR
Rev.3.00, Oct.22.2003, page 4 of 13
HD74LV2GT123A
Electrical Characteristic
•
Ta = –40 to 85°C
Item
Symbol VCC (V) *
Min
1.5
2.0
—
Typ
—
Max
—
Unit Test condition
Input voltage
VIH
VIL
VH
3.0 to 3.6
4.5 to 5.5
3.0 to 3.6
4.5 to 5.5
3.3
V
—
—
—
0.6
0.8
—
—
—
–
Hysteresis voltage
Output voltage
—
0.10
0.15
—
V
V
VT+ – VT
5.0
—
—
VOH
Min to Max VCC–0.1
—
IOH = –50 µA
IOH = –6 mA
3.0
2.48
3.8
—
—
—
4.5
—
—
IOH = –12 mA
IOL = 50 µA
VOL
Min to Max
3.0
—
0.1
0.44
0.55
±1
—
—
IOL = 6 mA
4.5
—
—
IOL = 12 mA
Input current
IIN
IIN
0 to 5.5
5.5
—
—
µA
µA
VIN = 5.5 V or GND
VIN = VCC or GND
Input current
Rext / Cext
—
—
±2.5
Quiescent
supply current
ICC
5.5
5.5
—
—
—
—
10
µA
VIN = VCC or GND,
IO = 0
ICC–T
1.5
mA
One input VIN = 3.4 V,
other input VCC or
GND
Active state
supply current
∆ICC
4.5
5.5
0
—
—
—
—
—
—
—
3.0
650
975
5
µA
VIN = VCC or GND
Rext / Cext = 0.5VCC
Output leakage current IOFF
Input capacitance CIN
µA
VIN or VO = 0 to 5.5 V
VIN = VCC or GND
5.0
—
pF
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating
conditions.
Rev.3.00, Oct.22.2003, page 5 of 13
HD74LV2GT123A
Switching Characteristics
•
VCC = 3.3 ± 0.3 V
Ta = 25°C
Ta = –40 to 85°C
Test
FROM
TO
Item
Symbol
Unit Conditions (Input) (Output)
Min
—
—
—
—
—
—
—
Typ Max Min Max
Propagation tPLH
delay time
10.0 21.0 1.0
11.5 24.5 1.0
24.0
27.5
18.5
22.0
26.0
29.5
300
ns
ns
ns
CL = 15 pF A or B
CL = 50 pF
Q
Q
Q
tPHL
8.0
9.5
16.0 1.0
19.5 1.0
CL = 15 pF CLR
CL = 50 pF
tPLH
10.0 22.5 1.0
11.5 26.0 1.0
CL = 15 pF CLR
(Trigger)
CL = 50 pF
Output pulse twQ
width
150
100
1.0
240
110
1.1
—
ns
CL = 50 pF,
Cext = 28 pF, Rext = 2 kΩ
90
90
0.9
110
1.1
µs
CL = 50 pF,
Cext = 0.01 µF, Rext = 10 kΩ
0.9
ms CL = 50 pF,
Cext = 0.1 µF, Rext = 10 kΩ
A, B or CLR
Pulse width
tw
5.0
—
—
—
—
5.0
—
—
—
ns
ns
Retrigger time trr
30
A or B
(Rext = 1 kΩ, Cext = 100 pF)
—
1.2
—
—
—
µs
A or B
(Rext = 1 kΩ, Cext = 0.01 µF)
•
VCC = 5.0 ± 0.5 V
Ta = 25°C
Ta = –40 to 85°C
Test
FROM
TO
Item
Symbol
Unit Conditions (Input) (Output)
Min
—
—
—
—
—
—
—
Typ Max Min
Max
14.0
16.0
11.0
13.0
15.0
17.0
240
Propagation tPLH
delay time
7.3
8.5
5.9
7.5
7.3
8.7
140
12.0 1.0
14.0 1.0
ns
ns
ns
CL = 15 pF A or B
CL = 50 pF
Q
Q
Q
tPHL
9.4
1.0
CL = 15 pF CLR
CL = 50 pF
11.4 1.0
12.9 1.0
14.9 1.0
tPLH
CL = 15 pF CLR
(Trigger)
CL = 50 pF
Output pulse twQ
width
200
110
1.1
—
ns
CL = 50 pF,
Cext = 28 pF, Rext = 2 kΩ
90
100
1.0
90
0.9
110
1.1
µs
CL = 50 pF,
Cext = 0.01 µF, Rext = 10 kΩ
0.9
ms CL = 50 pF,
Cext = 0.1 µF, Rext = 10 kΩ
Pulse width
tw
5.0
—
—
—
—
5.0
—
—
—
ns
ns
A, B or CLR
Retrigger time trr
20
A or B
(Rext = 1 kΩ, Cext = 100 pF)
—
0.95
—
—
—
µs
A or B
(Rext = 1 kΩ, Cext = 0.01 µF)
Rev.3.00, Oct.22.2003, page 6 of 13
HD74LV2GT123A
Operating Characteristics
•
CL = 50 pF
Ta = 25°C
Item
Symbol
VCC (V)
Unit
Test Conditions
Min
Typ
Max
Power dissipation
capacitance
CPD
5.0
—
31.0
—
pF
f = 10 MHz
Test Circuit
VCC
Cext
Rext
Cext = 28 pF or 100 pF or 0.01 µF or 0.1 µF
Rext = 1 kΩ or 2 kΩ or 5 kΩ or 10 kΩ
–
+
VCC
VCC
Cext Rext/
Cext
A
Input
Q
Output
B
CL = 15 pF or 50 pF
CLR
GND
Note : CL includes the probe and jig capacitance.
Rev.3.00, Oct.22.2003, page 7 of 13
HD74LV2GT123A
Timing Diagram
trr
A
B
CLR
Rext/
Cext
Q
tw
tw
tw +trr
Caution in use
In order to prevent any malfunctions due to noise, connect a high frequency
performance capacitor between Vcc and GND, and keep the wiring between the
External components and Cext, Rext/Cext pins as short as possible.
Large values of Cext may cause problems when powering down the HD74LV2GT123A
because of the amount of energy stored in the capacitor. When a system containing
this device is powered down, the capacitor may discharge from Vcc through the protection
diodes at pin 7 pin.
Current through the input protection diodes must be limited to 20 mA; therefore, the turn-off
time of the Vcc power supply must not be faster than t = Vcc • Cext/(20 mA). For example,
if Vcc = 5 V and Cext = 22 µF, the Vcc supply must turn off no faster than t = (5 V) • (22 µF)/
20 mA = 5.5 ms. This is usually not a problem because power supplies are heavily filtered
and cannot discharge at this rate.
When a more rapid decrease of Vcc to zero volts occurs, the HD74LV2GT123A may sustain
damage.
To avoid this possibility, use an external calmping diode.
The input pins for unused circuit should be used under conditions to fix the outputs to avoid
malfunction caused by noises. Also, it's recommended that Rext / Cext terminals are open and
external parts are not connected to.
Rev.3.00, Oct.22.2003, page 8 of 13
HD74LV2GT123A
• Waveform – 1
tf
VI
90%
Vref
Input A
10%
tr
GND
VI
90%
Input B
Vref
10%
10%
GND
tf
tr
tr
VI
90%
Vref
90%
Vref
10%
90%
Vref
10%
Input CLR
GND
tw (L)
tPLH(trigger)
tPHL
VOH
VOL
Output Q
50%
50%
Rev.3.00, Oct.22.2003, page 9 of 13
HD74LV2GT123A
• Waveform – 2
tf
tr
tr
VI
90%
Vref
90%
Vref
90%
Vref
10%
Input A
10%
90%
10%
GND
tw (H)
tw (L)
tf
tr
tf
VI
90%
Vref
90%
Vref
Vref
Input B
10%
10%
10%
GND
tw (L)
tw (H)
VOH
VOL
Output Q
50%
50%
tw (out)
• Waveform – 3
tf
tr
tf
VI
90%
Vref
90%
90%
Vref
Input A
10%
10%
90%
10%
GND
trr
tf
tr
tr
VI
90%
90%
Vref
Vref
10%
Input B
10%
10%
GND
VOH
Output Q
50%
50%
VOL
tw (out) + trr
INPUTS
VCC (V)
Vref
50%
VI
tr / tf
3.3 0.3 2.5 V
5.0 0.5 3 V
≤
≤
3.0 ns
3.0 ns 1.5 V
Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω.
2. The output are measured one at a time with one transition per measurement.
Rev.3.00, Oct.22.2003, page 10 of 13
HD74LV2GT123A
Application Data
Vcc = 5.0 V
10000.0
1000.0
100.0
10.0
Rext
1 kΩ
1.0
0.1
10 kΩ
100 kΩ
1 MΩ
102
103
104
105
106
107
Timing capacitance
Cext (pF)
Vcc = 3.3 V
10000.0
1000.0
100.0
10.0
Rext
1 kΩ
1.0
0.1
10 kΩ
100 kΩ
1 MΩ
102
103
104
105
106
107
Timing capacitance
Cext (pF)
Rev.3.00, Oct.22.2003, page 11 of 13
HD74LV2GT123A
Rext = 2 kΩ
1.4
1.3
1.2
1.1
1.0
0.9
Cext
1000 pF
10000 pF
100000 pF
1000000 pF
0.8
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Supply voltage
VCC (V)
Rext = 10kΩ
1.4
1.3
1.2
1.1
1.0
0.9
Cext
1000pF
10000pF
100000pF
1000000pF
0.8
3.0
3.5
4.0
Supply voltage
4.5
5.0
5.5
6.0
VCC (V)
Rev.3.00, Oct.22.2003, page 12 of 13
HD74LV2GT123A
Package Dimensions
2.0 ± 0.2
1.5 ± 0.2
Unit: mm
(0.5) (0.5) (0.5)
+ 0.1
− 0.05
8 − 0.2
Package Code
JEDEC
JEITA
TTP–8DBV
0.010 g
Mass (reference value)
Rev.3.00, Oct.22.2003, page 13 of 13
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circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
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