HD74LV1GT126ACME-E [RENESAS]
LV/LV-A/LVX/H SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO5, SC-88A, CMPAK-5;
| 型号： | HD74LV1GT126ACME-E |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | LV/LV-A/LVX/H SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO5, SC-88A, CMPAK-5 转换器 电平转换器 逻辑集成电路 光电二极管 栅 驱动 |
| 文件： | 总8页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74LV1GT126A
Bus Buffer Gate with 3–state Output /
CMOS Logic Level Shifter
REJ03D0124-0900
Rev.9.00
Mar 21, 2008
Description
The HD74LV1GT126A has a bus buffer gate with 3–state output in a 5 pin package. Output is disabled when the
associated output enable (OE) input is low. To ensure the high impedance state during power up or power down, OE
should be connected to VCC through a pull-down resistor; the minimum value of the resistor is determined by the current
sourcing capability of the driver. The input protection circuitry on this device allows over voltage tolerance on the
input, allowing the device to be used as a logic–level translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from
1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high-voltage power supply. Low voltage and high-
speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power
consumption extends the battery life.
Features
•
•
•
The basic gate function is lined up as Renesas uni logic series.
Supplied on emboss taping for high-speed automatic mounting.
TTL compatible input level.
Supply voltage range : 3.0 to 5.5 V
Operating temperature range : –40 to +85°C
•
•
Logic-level translate function
3.0 V CMOS logic → 5.0 V CMOS logic (@VCC = 5.0 V)
1.8 V or 2.5 V CMOS logic → 3.3 V CMOS logic (@VCC = 3.3 V)
All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V, Output : Z)
Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
All the logical input has hysteresis voltage for the slow transition.
Ordering Information
•
•
•
Package Code
(Previous Code)
PTSP0005ZC-A
(CMPAK-5V)
Package
Taping Abbreviation
(Quantity)
Part Name
Package Type
CMPAK–5 pin
VSON–5 pin
Abbreviation
HD74LV1GT126ACME
HD74LV1GT126AVSE
CM
E (3000 pcs/reel)
E (3000 pcs/reel)
PUSN0005KA-A
(TNP-5DV)
VS
Note: Please consult the sales office for the above package availability.
REJ03D0124-0900 Rev.9.00, Mar 21, 2008
Page 1 of 7
HD74LV1GT126A
Outline and Article Indication
• HD74LV1GT126A
Index band
Marking
T C
= Control code
CMPAK–5
• HD74LV1GT126A
Marking
T C
= Control code
VSON–5
Function Table
Inputs
Output Y
OE
H
A
H
L
H
L
H
L
X
Z
H : High level
L : Low level
X : Immaterial
Z : High impedance
REJ03D0124-0900 Rev.9.00, Mar 21, 2008
Page 2 of 7
HD74LV1GT126A
Pin Arrangement
1
2
3
OE
A
5
VCC
GND
4
Y
(Top view)
Absolute Maximum Ratings
Item
Symbol
Ratings
–0.5 to 7.0
–0.5 to 7.0
–0.5 to VCC + 0.5
–0.5 to 7.0
–20
Unit
Test Conditions
Supply voltage range
Input voltage range *1
VCC
VI
V
V
Output : H or L
CC : OFF or Output : Z
Output voltage range *1, 2
VO
V
V
Input clamp current
IIK
IOK
IO
mA
mA
mA
VI < 0
Output clamp current
Continuous output current
±50
VO < 0 or VO > VCC
VO = 0 to VCC
±25
Continuous current through
VCC or GND
I
CC or IGND
±50
mA
Maximum power dissipation
at Ta = 25°C (in still air) *3
PT
200
mW
°C
Storage temperature
Tstg
–65 to 150
Notes:
The absolute maximum ratings are values, which must not individually be exceeded, and furthermore no two
of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are
observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
Recommended Operating Conditions
Item
Supply voltage range
Input voltage range
Symbol
VCC
Min
3.0
0
Max
5.5
5.5
VCC
5.5
6
Unit
V
Conditions
VI
V
0
Output voltage range
VO
IOH
IOL
V
0
Output : Z
—
—
—
—
0
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
VCC = 3.0 to 3.6 V
VCC = 4.5 to 5.5 V
mA
mA
12
Output current
–6
–12
100
20
Input transition rise or fall rate
Operating free-air temperature
∆t / ∆v
ns / V
°C
0
Ta
–40
85
Note: Unused or floating inputs must be held high or low.
REJ03D0124-0900 Rev.9.00, Mar 21, 2008
Page 3 of 7
HD74LV1GT126A
Electrical Characteristic
•
Ta = –40 to 85°C
Item
Symbol VCC (V) *
Min
1.5
2.0
—
Typ
—
Max
—
Unit
Test condition
3.0 to 3.6
VIH
4.5 to 5.5
—
—
Input voltage
V
3.0 to 3.6
VIL
—
0.6
0.8
—
4.5 to 5.5
—
—
3.3
—
0.10
0.15
—
–
Hysteresis voltage
VH
V
V
VT+ – VT
5.0
—
—
Min to Max VCC–0.1
—
IOH = –50 µA
IOH = –6 mA
IOH = –12 mA
IOL = 50 µA
VOH
3.0
4.5
2.48
3.8
—
—
—
—
—
Output voltage
Input current
Min to Max
3.0
—
0.1
0.44
0.55
±1
VOL
—
—
IOL = 6 mA
4.5
—
—
IOL = 12 mA
IIN
0 to 5.5
—
—
µA
µA
VIN = 5.5 V or GND
Off state output
current
IOZ
Min to Max
5.5
—
—
—
±5
—
—
—
10
VO = 5.5 V or GND
Quiescent
supply current
VIN = VCC or GND,
IO = 0
ICC
µA
One input VIN = 3.4 V,
other input VCC or GND
∆ICC
5.5
1.5
mA
Output leakage current
Input capacitance
IOFF
CIN
0
—
—
—
5
µA
VIN or VO = 0 to 5.5 V
VIN = VCC or GND
5.0
3.0
—
pF
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Switching Characteristics
•
VCC = 3.3 ± 0.3 V
Ta = 25°C
Typ
5.0
Ta = –40 to 85°C
Test
FROM
TO
Item
Symbol
Unit
ns
Conditions (Input) (Output)
Min
—
Max
9.0
Min
1.0
1.0
1.0
1.0
1.0
1.0
Max
10.5
13.0
10.5
13.0
11.5
15.0
CL = 15 pF
Propagation
delay time
tPLH
tPHL
A
Y
Y
Y
—
6.5
11.5
9.0
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
—
5.0
tZH
tZL
Enable time
Disable time
ns
OE
OE
—
6.5
11.5
10.0
13.5
—
4.5
tHZ
tLZ
ns
—
6.0
•
VCC = 5.0 ± 0.5 V
Ta = 25°C
Typ
3.5
Ta = –40 to 85°C
Test
FROM
TO
Item
Symbol
Unit
ns
Conditions (Input) (Output)
Min
—
Max
5.5
7.5
5.1
7.1
6.8
8.8
Min
1.0
1.0
1.0
1.0
1.0
1.0
Max
6.5
CL = 15 pF
Propagation
delay time
tPLH
tPHL
A
Y
Y
Y
—
4.6
8.5
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
—
3.6
6.0
tZH
tZL
Enable time
Disable time
ns
OE
OE
—
4.6
8.0
—
3.3
8.0
tHZ
tLZ
ns
—
4.3
10.0
REJ03D0124-0900 Rev.9.00, Mar 21, 2008
Page 4 of 7
HD74LV1GT126A
Operating Characteristics
•
CL = 50 pF
Ta = 25°C
Typ
Item
Symbol VCC (V)
CPD 5.0
Unit
Test Conditions
f = 10 MHz
Min
Max
Power dissipation
capacitance
—
11.5
—
pF
Test Circuit
VCC
VCC
Input
Output
Pulse Generator
1 kΩ
S1
OPEN
*1 See under table
GND
ZOUT = 50 Ω
CL=
15 or 50 pF
TEST
S1
tPLH/ tPHL
tZH/ tHZ
tZL / tLZ
OPEN
GND
VCC
Note: 1. CL includes probe and jig capacitance.
REJ03D0124-0900 Rev.9.00, Mar 21, 2008
Page 5 of 7
HD74LV1GT126A
Waveforms
• Waveforms – 1
tr
tf
VI
90 %
Vref
90 %
Vref
Input A
10 %
10 %
GND
tPHL
tPLH
VOH
Output Y
50%
50%
VOL
• Waveforms – 2
tr
tf
VI
90 %
Vref
90 %
Vref
Input OE
10 %
10 %
tLZ
GND
VCC
tZL
50%
50%
Waveform – A
Waveform – B
VOL + 0.3 V
VOL
VOH
tZH
tHZ
VOH– 0.3 V
GND
INPUTS
tr / tf
VCC (V)
Vref
VI
3.3 0.3 2.5 V
5.0 0.5 3 V
≤
≤
50%
3.0 ns 1.5 V
3.0 ns
Notes: 1. Input waveform : PRR ≤ 1 MHz, Zo = 50 Ω.
2. Waveform – A is for an output with internal conditions such that the output is low
except when disabled by the output control.
3. Waveform – B is for an output with internal conditions such that the output is high
except when disabled by the output control.
4. The output are measured one at a time with one transition per measurement.
REJ03D0124-0900 Rev.9.00, Mar 21, 2008
Page 6 of 7
HD74LV1GT126A
Package Dimensions
JEITA Package Code
SC-88A
RENESAS Code
PTSP0005ZC-A
Previous Code
MASS[Typ.]
0.006g
CMPAK-5 / CMPAK-5V
D
A
e
Q
c
E
HE
L
P
L
Reference
Symbol
Dimension in Millimeters
A
A
L
1
A
3
Min
0.8
0
Nom
Max
1.1
0.1
1.0
b
A
x
S
A
M
A1
A2
A3
e
0.8
0.9
0.25
0.22
0.2
b
0.15
0.1
0.3
b
1
A
2
1
A
c
0.13
0.11
2.0
0.15
c
1
D
E
e
1.8
2.2
1.15
1.25
0.65
2.1
1.35
A
y
S
S
e
1
H
E
1.8
0.3
0.1
0.2
2.4
0.7
b
L
L
1
0.5
b
1
L
P
0.6
l
1
c1
x
0.05
0.05
0.35
y
c
b
2
1
e
b
2
1.5
l
1
0.9
A-A Section
Pattern of terminal position areas
Q
0.25
JEITA Package Code
P-USON5-1.2x1.6-0.50
RENESAS Code
PUSN0005KA-A
Previous Code
MASS[Typ.]
0.002g
TNP-5D/TNP-5DV
D
0.1
1.0
5
4
1
3
c
Dimension in Millimeters
Reference
Symbol
Min Nom Max
1.6
D
E
1.55
1.65
1.1 1.2 1.3
0.6
A
A1
A2
b
0.2 0.3
0.5
0.15
b1
e
e
b
Lp
x
y
ZD
c
0.07 0.12 0.22
c1
HE
L1
1.55 1.6 1.65
0.2
REJ03D0124-0900 Rev.9.00, Mar 21, 2008
Page 7 of 7
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
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but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
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Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
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© 2008. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .7.2
相关型号：
HD74LV1GT126AVSE-E
LV/LV-A/LVX/H SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO5, 1.20 X 1.60 MM, 0.50 MM PITCH, PLASTIC, VSON-5
RENESAS
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