HD74LS374FPEL-E [RENESAS]

IC,FLIP-FLOP,OCTAL,D TYPE,LS-TTL,SOP,20PIN,PLASTIC;
HD74LS374FPEL-E
型号: HD74LS374FPEL-E
厂家: RENESAS TECHNOLOGY CORP    RENESAS TECHNOLOGY CORP
描述:

IC,FLIP-FLOP,OCTAL,D TYPE,LS-TTL,SOP,20PIN,PLASTIC

光电二极管 逻辑集成电路 触发器
文件: 总8页 (文件大小:96K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
HD74LS374  
Octal D-type Edge-triggered Flip-Flops (with three-state outputs)  
REJ03D0483–0200  
Rev.2.00  
Feb.18.2005  
The HD74LS374, 8-bit register features totem-pole three-state outputs designed specifically for driving highly-  
capacitive or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive  
provide this register with the capability of being connected directly to and driving the bus lines in a bus-organized  
system without need for interface or pull-up components. They are particularly attractive for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops are edge-triggered D-type flip-  
flops. On the positive transition the clock, the Q outputs will be set to the logic states that ware setup at the D inputs.  
Features  
Ordering Information  
Package Code  
(Previous Code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
Package Type  
PRDP0020AC-B  
(DP-20NEV)  
HD74LS374P  
DILP-20 pin  
P
PRSP0020DD-B  
(FP-20DAV)  
HD74LS374FPEL  
HD74LS374RPEL  
SOP-20 pin (JEITA)  
SOP-20 pin (JEDEC)  
FP  
RP  
EL (2,000 pcs/reel)  
EL (1,000 pcs/reel)  
PRSP0020DC-A  
(FP-20DBV)  
Note: Please consult the sales office for the above package availability.  
Pin Arrangement  
Output  
1
Control  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
VCC  
2
3
1Q  
1D  
Q
Q
D
8Q  
8D  
OE  
OE  
CK D  
CK  
4
2D  
7D  
D
Q
D
Q
CK  
OE  
CK  
OE  
5
2Q  
7Q  
6Q  
6D  
6
3Q  
Q
Q
D
OE  
OE  
CK D  
CK  
7
3D  
8
4D  
5D  
D
Q
D
Q
CK  
OE  
CK  
OE  
9
4Q  
5Q  
Clock  
10  
GND  
(Top view)  
Rev.2.00, Feb.18.2005, page 1 of 7  
HD74LS374  
Function Table  
Inputs  
Outputs  
Output control  
Clock  
D
H
L
Q
H
L
L
L
L
L
X
X
X
Q0  
Z
H
Notes: H; high level, L; low level, X; irrelevant  
; transition from low to high level  
Q0; level of Q before the indicated steady state input conditions were established  
Z; off (high-impedance) state of a three state output  
Block Diagram  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
Q
Q
Q
Q
Q
Q
Q
Q
CK  
CK  
CK  
CK  
CK  
CK  
CK  
CK  
D
D
D
D
D
D
D
D
Output 1D  
Control  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
Clock  
Absolute Maximum Ratings  
Item  
Supply voltage  
Symbol  
VCC  
Ratings  
Unit  
7
7
V
V
Input voltage  
VIN  
Power dissipation  
Storage temperature  
PT  
400  
mW  
°C  
Tstg  
–65 to +150  
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.  
Recommended Operating Conditions  
Item  
Symbol  
VCC  
Min  
4.75  
Typ  
5.00  
Max  
5.25  
5.5  
–2.6  
24  
Unit  
Supply voltage  
Output voltage  
V
V
VOH  
IOH  
mA  
mA  
°C  
ns  
ns  
ns  
ns  
Output current  
IOL  
Operating temperature  
Clock pulse width  
Topr  
–20  
15  
25  
75  
“H” Level  
“L” Level  
tw  
15  
Data setup time  
Data hold time  
tsu  
th  
20↑  
0↑  
Rev.2.00, Feb.18.2005, page 2 of 7  
HD74LS374  
Electrical Characteristics  
(Ta = –20 to +75 °C)  
Item  
Input voltage  
Symbol  
min.  
2.0  
typ.*  
max.  
Unit  
V
Condition  
VIH  
VIL  
0.8  
V
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V,  
IOH = –2.6 mA  
VOH  
VOL  
2.4  
V
V
Output voltage  
0.4  
0.5  
IOL = 12 mA  
IOL = 24 mA  
VO = 2.7 V  
VO = 0.4 V  
VCC = 4.75 V,  
VIH = 2 V, VIL = 0.8 V  
IOZH  
IOZL  
IIH  
20  
VCC = 5.25 V,  
VIH = 2 V, VIL = 0.8 V  
Output current  
Input current  
µA  
–20  
20  
µA  
mA  
mA  
mA  
VCC = 5.25 V, VI = 2.7 V  
VCC = 5.25 V, VI = 0.4 V  
VCC = 5.25 V, VI = 7 V  
VCC = 5.25 V  
IIL  
–0.4  
0.1  
II  
Short-circuit output current  
Supply current  
IOS  
–30  
–130  
VCC = 5.25 V,  
VI = 4.5 V (Output control)  
ICC  
VIK  
27  
40  
mA  
V
Input clamp voltage  
–1.5  
VCC = 4.75 V, IIN = –18 mA  
Note: * VCC = 5 V, Ta = 25°C  
Switching Characteristics  
(VCC = 5 V, Ta = 25°C)  
Item  
Symbol  
Inputs  
Output  
min.  
35  
typ.  
50  
15  
19  
20  
21  
12  
14  
max.  
Unit  
Condition  
Maximum clock frequency  
ƒmax  
tPLH  
tPHL  
tZH  
Clock  
Q
MHz  
28  
Propagation delay time  
Output enable time  
Output disable time  
Clock  
OC  
Q
CL = 45 pF,  
RL = 667 Ω  
28  
28  
Q
Q
ns  
tZL  
28  
tHZ  
20  
CL = 5 pF,  
RL = 667 Ω  
OC  
tLZ  
25  
Rev.2.00, Feb.18.2005, page 3 of 7  
HD74LS374  
Testing Method  
Test Circuit  
VCC  
Output  
Load circuit 1  
L
R
S
1
4.5V  
Input  
1Q  
5k  
S
2
OC  
1D  
C
L
Output  
Output  
Output  
Output  
Output  
Output  
Output  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
Same as Load Circuit 1.  
Same as Load Circuit 1.  
Same as Load Circuit 1.  
Same as Load Circuit 1.  
Same as Load Circuit 1.  
Same as Load Circuit 1.  
Same as Load Circuit 1.  
P.G.  
2D  
Zout = 50Ω  
3D  
4D  
Input  
5D  
P.G.  
Zout = 50Ω  
6D  
7D  
8D  
Clock  
Notes:  
1. CL includes probe and jig capacitance.  
2. All diodes are 1S2074(H).  
Rev.2.00, Feb.18.2005, page 4 of 7  
HD74LS374  
Waveforms 1  
tTLH  
tTHL  
3V  
0V  
90%  
90%  
1.3 V  
1.3 V  
1.3 V  
Data  
10%  
10%  
tsu  
tsu  
th  
th  
tTLH  
tTHL  
3V  
0V  
90%90%  
1.3 V 1.3 V  
Clock  
1.3 V  
10%  
10%  
tw  
tw  
tPLH  
tPHL  
VOH  
Q
S1  
, S  
2
Closed 1.3 V  
1.3 V  
VOL  
Notes:  
1. Input pulse; tTLH 15 ns, tTHL 6 ns  
Clock input; PRR = 1 MHz, duty cycle 50%  
Data input pulse; PRR = 500 kHz, duty cycle 50%  
2. ƒmax: tTLH 2.5 ns, tTHL 2.5 ns  
Waveforms 2  
tTHL  
tTLH  
3V  
0V  
90%  
1.3V  
90%  
1.3V  
Output  
Control  
10%  
tZL  
10%  
4.5V  
tLZ  
S1, S2 closed  
S
S
1
2
closed,  
open  
1.5V  
1.3V  
1.3V  
Waveform A  
Waveform B  
VOL  
VOH  
1.5V  
tZH  
tHZ  
0.5V  
0.5V  
S
S
1
2
open,  
closed  
0V  
S1, S2 closed  
Notes:  
1. Input pulse; tTLH 15 ns, tTHL 6 ns, PRR = 1 MHz, duty cycle 50%  
2. Waveform A if for an output with internal conditions such that the output is low except when  
disabled by the output control. Waveform B is for an output with internal conditions such that  
the output is high except when disabled by the output control.  
Rev.2.00, Feb.18.2005, page 5 of 7  
HD74LS374  
Package Dimensions  
JEITA Package Code  
P-DIP20-6.3x24.5-2.54  
RENESAS Code  
PRDP0020AC-B  
Previous Code  
DP-20NEV  
MASS[Typ.]  
1.26g  
D
20  
11  
1
10  
b 3  
0.89  
Z
Dimension in Millimeters  
Reference  
Symbol  
Min  
Nom  
7.62  
Max  
e
1
D
24.50  
6.30  
25.40  
7.00  
5.08  
E
A
A 1  
0.51  
0.40  
b
0.48  
1.30  
0.25  
0.56  
p
b
c
θ
bp  
3
e
c
0.19  
0.31  
e1  
0
°
15°  
e
Z
L
2.29  
2.54  
2.54  
2.79  
1.27  
( Ni/Pd/Au plating )  
JEITA Package Code  
RENESAS Code  
PRSP0020DD-B  
Previous Code  
FP-20DAV  
MASS[Typ.]  
0.31g  
P-SOP20-5.5x12.6-1.27  
NOTE)  
1. DIMENSIONS"*1 (Nom)"AND"*2"  
DO NOT INCLUDE MOLD FLASH.  
2. DIMENSION"*3"DOES NOT  
INCLUDE TRIM OFFSET.  
*1  
D
F
20  
11  
bp  
Index mark  
Dimension in Millimeters  
Reference  
Symbol  
Min  
Nom  
12.60  
5.50  
Max  
13.0  
Terminal cross section  
( Ni/Pd/Au plating )  
D
E
A 2  
A 1  
A
1
10  
x
0.00  
0.34  
0.15  
0.10  
0.40  
0.20  
0.20  
2.20  
0.46  
*3  
e
bp  
Z
M
L1  
b p  
b 1  
c
0.25  
c
1
θ
0
°
8°  
H E  
e
7.50  
7.80  
1.27  
8.00  
y
x
0.12  
0.15  
0.80  
0.90  
L
y
Z
L
Detail F  
0.50  
0.70  
1.15  
L
1
Rev.2.00, Feb.18.2005, page 6 of 7  
HD74LS374  
JEITA Package Code  
P-SOP20-7.5x12.8-1.27  
RENESAS Code  
PRSP0020DC-A  
Previous Code  
FP-20DBV  
MASS[Typ.]  
0.52g  
*1  
D
F
NOTE)  
20  
11  
1. DIMENSIONS"*1 (Nom)"AND"*2"  
@ DO NOT INCLUDE MOLD FLASH.  
2. DIMENSION"*3"DOES NOT  
@ INCLUDE TRIM OFFSET.  
bp  
Index mark  
Dimension in Millimeters  
Reference  
Symbol  
Min  
Nom  
12.80  
7.50  
Max  
13.2  
Terminal cross section  
( Ni/Pd/Au plating )  
D
E
A 2  
A 1  
A
1
10  
x
0.10  
0.34  
0.20  
0.20  
0.40  
0.25  
0.30  
2.65  
0.46  
*3  
e
bp  
Z
M
L1  
b p  
b 1  
c
0.30  
c
1
θ
H E  
e
0
°
8°  
10.00  
10.40  
1.27  
10.65  
x
0.12  
0.15  
L
y
y
Z
0.935  
1.27  
L
0.40  
0.70  
1.45  
Detail F  
L
1
Rev.2.00, Feb.18.2005, page 7 of 7  
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