HD74LS107A [RENESAS]
Dual J-K Negative-edge-triggered Flip-Flops (with Clear); 双路JK下降沿触发的触发器（带清除）
| 型号： | HD74LS107A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Dual J-K Negative-edge-triggered Flip-Flops (with Clear) |
| 文件： | 总7页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74LS107A
Dual J-K Negative-edge-triggered Flip-Flops (with Clear)
REJ03D0425–0300
Rev.3.00
Jul.13.2005
Features
•
Ordering Information
Package Code
(Previous Code)
Package
Abbreviation
Taping Abbreviation
(Quantity)
Part Name
Package Type
DILP-14 pin
PRDP0014AB-B
(DP-14AV)
HD74LS107AP
HD74LS107AFPEL
P
—
PRSP0014DF-B
(FP-14DAV)
SOP-14 pin (JEITA)
FP
EL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Pin Arrangement
1
2
3
4
5
6
7
14
13
12
11
10
9
1J
1Q
VCC
J
CLR
1CLR
1CK
2K
Q
CK
Q
1Q
K
1K
K
2Q
Q
2CLR
2CK
2J
CK
Q
2Q
J
CLR
8
GND
(Top view)
Function Table
Inputs
Outputs
Clear
Clock
J
X
L
K
X
L
Q
Q
H
L
X
↓
L
QO
H
H
H
H
H
H
QO
L
↓
H
L
L
↓
H
H
X
L
H
↓
H
X
Toggle
H
QO
QO
Notes: H; high level, L; low level, X; irrelevant
↓; transition from high to low level
Q; level of Q before the indicated steady-state input conditions were established.
Q; complement of QO or level of Q before the indicated steady-state input conditions were established.
Toggle; each output changes to the complement of its previous level on each active transition indicated by ↓.
Rev.3.00, Jul.13.2005, page 1 of 6
HD74LS107A
Block Diagram (1/2)
Q
K
Q
Clear
J
Clock
Absolute Maximum Ratings
Item
Supply voltage
Symbol
VCC
Ratings
Unit
V
7
Input voltage
VIN
7
V
Power dissipation
Storage temperature
PT
400
mW
°C
Tstg
–65 to +150
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item
Symbol
VCC
Min
4.75
—
Typ
5.00
—
Max
5.25
–400
8
Unit
Supply voltage
Output current
V
µA
mA
°C
IOH
IOL
—
—
Operating temperature
Clock frequency
Topr
fclock
–20
0
25
—
75
30
MHz
ns
Clock High
20
—
—
Pulse width
tw
Clear Low
“H” Data
“L” Data
25
—
—
ns
20↓
20↓
0↓
—
—
ns
Setup time
Hold time
tsu
th
—
—
ns
—
—
ns
Rev.3.00, Jul.13.2005, page 2 of 6
HD74LS107A
Electrical Characteristics
(Ta = –20 to +75 °C)
Item
Symbol
VIH
min.
2.0
—
typ.*
—
max.
—
Unit
V
Condition
Input voltage
VIL
—
0.8
V
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V,
IOH = –400 µA
VOH
VOL
2.7
—
—
V
V
Output voltage
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.5
0.4
20
IOL = 8 mA
IOL = 4 mA
VCC = 4.75 V, VIH = 2 V,
VIL = 0.8 V
J, K
IIH
µA
VCC = 5.25 V, VI = 2.7 V
VCC = 5.25 V, VI = 0.4 V
Clear
Clock
J, K
60
80
–0.4
–0.8
–0.8
0.1
0.3
0.4
Input
current
IIL
mA
Clear
Clock
J, K
II
mA
mA
VCC = 5.25 V, VI = 7 V
VCC = 5.25 V
Clear
Clock
Short-circuit output
current
IOS
–20
—
–100
Supply current**
ICC
VIk
—
—
4
6
mA
V
VCC = 5.25 V
Input clamp voltage
—
–1.5
VCC = 4.75 V, IIN = –18 mA
Notes: * VCC = 5 V, Ta = 25°C
** With all outputs open, ICC is measured with the Q and Q outputs high in turn. At the tires of measurement, the
clock input is grounded.
Switching Characteristics
(VCC = 5 V, Ta = 25°C)
Item
Symbol
fmax
Inputs
Outputs
min.
30
typ.
45
max.
—
Unit
MHz
ns
Condition
Maximum clock frequency
CL = 15 pF,
RL = 2 kΩ
tPLH
Clear
Clock
—
15
20
Propagation delay time
Q, Q
tPHL
—
15
20
ns
Timing Definition
tw
3 V
1.3 V
1.3 V
th
1.3 V
th
Clock
J, K
0 V
3 V
tsu
tsu
1.3 V
1.3 V
1.3 V
0 V
"H" Data
"L" Data
Rev.3.00, Jul.13.2005, page 3 of 6
HD74LS107A
Testing Method
Test Circuit
1. ƒmax, tPLH, tPHL, (Clock→Q, Q)
VCC Output Q
Input 4.5V
Load circuit 1
R
L
J
Q
P.G.
C
L
CK
Z
out=50Ω
Output Q
K
Same as Load Circuit 1.
Q
CLR
Notes:
1. Test is put into the each flip-flop.
2. CL includes probe and jig capacitance.
3. All diodes are 1S2074(H).
2. tPHL (Clear→Q), tPLH (Clear→Q)
VCC Output Q
4.5V
Load circuit 1
Input
R
L
J
Q
P.G.
C
L
CK
Z
out=50Ω
Output Q
K
Input
Same as Load Circuit 1.
Q
CLR
P.G.
Zout=50Ω
Notes:
1. Test is put into the each flip-flop.
2. CL includes probe and jig capacitance.
3. All diodes are 1S2074(H).
Rev.3.00, Jul.13.2005, page 4 of 6
HD74LS107A
Waveforms 1
tTLH
tTHL
t
w
(L)
3 V
0 V
90% 90%
1.3 V 1.3 V
1.3 V 1.3 V
10%
10%
tPLH
Clock
t
w
(H)
tPHL
VOH
1.3 V
1.3 V
1.3 V
VOL
Q
tPHL
tPLH
VOH
Q
1.3 V
VOL
Note: Clock input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz,
duty cycle = 50% and: for fmax, tTHL
tTHL ≤ 2.5 ns.
Waveforms 2
tTHL
tTLH
3V
Clear
90%
1.3V
90%
1.3V
10%
10%
tw (CLR)
0V
3V
tTLH
tTHL
90% 90%
1.3V 1.3V
10%
10%
Clock
Q
0V
tw (CK) ≥ 20ns
tPHL
VOH
1.3V
VOL
tPLH
VOH
1.3V
VOL
Q
Note: Clear and clock input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz.
Rev.3.00, Jul.13.2005, page 5 of 6
HD74LS107A
Package Dimensions
JEITA Package Code
P-DIP14-6.3x19.2-2.54
RENESAS Code
PRDP0014AB-B
Previous Code
DP-14AV
MASS[Typ.]
0.97g
D
14
8
1
7
b 3
Z
Dimension in Millimeters
Reference
Symbol
Min
Nom
7.62
19.2
6.3
Max
e 1
D
20.32
7.4
E
A
5.06
A 1
b p
b 3
c
0.51
0.40
0.48
1.30
0.25
0.56
b p
e
c
0.19
0.31
e1
θ
0
°
15°
e
2.29
2.54
2.54
2.79
2.39
Z
( Ni/Pd/Au plating )
L
JEITA Package Code
RENESAS Code
PRSP0014DF-B
Previous Code
FP-14DAV
MASS[Typ.]
0.23g
P-SOP14-5.5x10.06-1.27
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
*1
D
F
14
8
bp
Index mark
Dimension in Millimeters
Reference
Symbol
Min
Nom
10.06
5.50
Max
10.5
Terminal cross section
( Ni/Pd/Au plating )
D
E
A 2
A 1
A
1
7
0.00
0.34
0.15
0.10
0.40
0.20
0.20
2.20
0.46
*3
e
bp
Z
x
M
L1
b p
b 1
c
0.25
c
1
θ
H E
e
0
°
8°
7.50
7.80
1.27
8.00
x
0.12
0.15
1.42
0.90
L
y
y
Z
Detail F
L
0.50
0.70
1.15
L
1
Rev.3.00, Jul.13.2005, page 6 of 6
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