HD74AC194P [RENESAS]

AC SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16, DP-16;


型号：	HD74AC194P
厂家：	RENESAS TECHNOLOGY CORP
描述：	AC SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16, DP-16 移位寄存器
文件：	总8页 (文件大小：214K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HD74AC194

4-bit Bidirectional Unviersal Shift Register

REJ03D0259–0200Z

(Previous ADE-205-379 (Z))

Rev.2.00

Jul.16.2004

Description

This bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a

shift register. It features parallel inputs, parallel outputs, right shift and left shift serial inputs, operating mode control

inputs, and a direct overriding clear line. The register has four destinct modes of operation: parallel (broadside) load,

shift right (in the direction Q₀toward Q₃); shift left; inhibit clock (do nothing).

Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S₀

and S₁, high. The data are loaded into their respective flip-flops and appear at the output after the positive transition of

the clock input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising

edge of the clock pulse when S₀is high and S₁is low. Serial date for this mode is entered at the shift right data input.

When S₀is low and S₁is high, data shifts left synchronously and new data is entered at the shifts left serial input.

Clocking of the flip-flops is inhibited when both mode control inputs are low. The mode control inputs should be

changed only when the clock input is high.

Features

•

Asynchronous Master Reset

Hole (Do Nothing) Mode

Outputs Source/Sink 24 mA

•

Ordering Information

Part Name

Package Type

Package Code Package Abbreviation Taping Abbreviation (Quantity)

HD74AC194FPEL SOP-16 pin (JEITA) FP-16DAV

HD74AC194RPEL SOP-16 pin (JEDEC) FP-16DNV

EL (2,000 pcs/reel)

EL (2,500 pcs/reel)

Notes: 1. Please consult the sales office for the above package availability.

2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of

the package code.

Rev.2.00, Jul.16.2004, page 1 of 7

HD74AC194

Pin Arrangement

16 VCC

D_SR

15 Q

12 Q

11 CP

10 S

D_SL

GND

(Top view)

Logic Symbol

DSR P0 P1 P2 P3 DSL

Rev.2.00, Jul.16.2004, page 2 of 7

HD74AC194

Pin Names

S₀, S₁

P₀to P₃

D_SR

D_SL

Mode Control Inputs

Parallel Data Inputs

Serial Data Input (Shift Right)

Serial Data Input (Shift Left)

Clock Pulse Input (Active Rising Edge)

Asynchronous Master Reset Input (Active LOW)

Parallel Outputs

Q₀to Q₃

Logic Diagram

DSR

CL CL

Mode Select Table

Inputs

S₀D_SR

Output

Operating Mode

S₁

D_SL

P_n

Q₀

Q₁

Q₂

Q₃

Reset

Hold

p_n

q₀

q₁

q₂

q₀

p₁

q₂

q₃

q₁

p₂

q₃

Shift Left

q₂

p₃

Shift Right

p₀

Parallel Load

: HIGH Voltage Level

: LOW Voltage Level

p_n(q_n) : Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH

clock transition

: Immaterial

Rev.2.00, Jul.16.2004, page 3 of 7

HD74AC194

Timing Diagram

Mode

Control

Inputs

Parallel

Data

Inputs

Parallel

Data

Inputs

Outputs

Shift Right

Shift Left

Inhibit

Clear

Load

Clear

Absolute Maximum Ratings

Item

Supply voltage

Symbol

Ratings

Unit

Condition

V_CC

I_IK

–0.5 to 7

DC input diode current

–20

V_I= –0.5V

V_I= Vcc+0.5V

DC input voltage

V_I

–0.5 to Vcc+0.5

DC output diode current

I_OK

–50

V_O= –0.5V

V_O= Vcc+0.5V

DC output voltage

V_O

–0.5 to Vcc+0.5

±50

DC output source or sink current

DC V_CCor ground current per output pin

Storage temperature

I_O

°C

I_CC, I_GND

Tstg

±50

–65 to +150

Recommended Operating Conditions

Item

Symbol

Ratings

2 to 6

Unit

Condition

Supply voltage

V_CC

Input and output voltage

Operating temperature

V_I, V_O

0 to V_CC

–40 to +85

°C

ns/V

Input rise and fall time

(except Schmitt inputs)

tr, tf

V_CC= 3.0V

V_CC= 4.5 V

V_CC= 5.5 V

V_IN30% to 70% V_CC

Rev.2.00, Jul.16.2004, page 4 of 7

HD74AC194

DC Characteristics

Item

Sym-

bol

Vcc

(V)

Ta = 25°C

Ta = –40 to

Unit

Condition

+85°C

min.

2.1

3.15

3.85

—

typ.

1.5

max.

—

min.

2.1

3.15

3.85

—

max.

—

Input Voltage

V_IH

V_IL

3.0

V_OUT= 0.1 V or V_CC–0.1 V

4.5

5.5

3.0

4.5

5.5

3.0

4.5

5.5

3.0

4.5

5.5

3.0

4.5

5.5

3.0

4.5

5.5

2.25

2.75

1.50

2.25

2.75

2.99

4.49

5.49

—

0.9

1.35

1.65

—

0.9

1.35

1.65

—

V_OUT= 0.1 V or V_CC–0.1 V

—

Output voltage

V_OH

2.9

4.4

5.4

2.58

3.94

4.94

—

2.9

4.4

5.4

2.48

3.80

4.80

—

V_IN= V_ILor V_IH

I_OUT= –50 µA

—

V_IN= V_ILor V_IH

I_OH= –12 mA

—

I_OH= –24 mA

—

V_OL

0.002 0.1

0.001 0.1

0.1

0.37

±1.0

V_IN= V_ILor V_IH

I_OUT= 50 µA

—

0.32

—

V_IN= V_ILor V_IH

I_OL= 12 mA

I_OL= 24 mA

—

0.32

±0.1

—

Input leakage

current

I_IN

—

µA

V_IN= V_CCor GND

Dynamic output

current*

I_OLD

I_OHD

I_CC

5.5

—

µA

V_OLD= 1.1 V

—

–75

—

V_OHD= 3.85 V

Quiescent supply

current

8.0

V_IN= V_CCor ground

*Maximum test duration 2.0 ms, one output loaded at a time.

AC Characteristics

Ta = +25°C

C_L= 50 pF

Ta = –40°C to +85°C

C_L= 50 pF

Item

Maximum clock

frequency

Symbol V_CC(V)*¹

Min

Typ

—

Max

Min

Max

Unit

f_max

3.3

5.0

3.3

5.0

3.3

5.0

3.3

5.0

MHz

100

1.0

—

Propagation delay

CP to Q_n

t_PLH

t_PHL

—

13.0

10.0

1.0

15.0

11.5

15.0

11.5

12.5

9.0

Propagation delay

CP to Q_n

13.0

10.0

10.5

8.0

Propagation delay

MR to Q_n

Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V

Voltage Range 5.0 is 5.0 V ± 0.5 V

Rev.2.00, Jul.16.2004, page 5 of 7

HD74AC194

AC Operating Requirements

Ta = –40°C

to +85°C

C_L= 50 pF

Ta = +25°C

C_L= 50 pF

Item

Setup time, HIGH or LOW

Pn or D_SRor D_SLto CP

Hold time, HIGH or LOW

Pn or D_SRor D_SLto CP

Setup time, HIGH or LOW

S_nto CP

Symbol V_CC(V)*¹

Typ

Guaranteed Minimum

Unit

t_su

t_h

t_su

t_h

t_rec

t_w

3.3

5.0

3.3

5.0

3.3

5.0

3.3

5.0

3.3

5.0

3.3

5.0

—

5.5

7.0

5.0

3.0

2.0

7.5

5.5

0.0

0.5

7.0

5.0

4.0

2.0

1.5

6.0

4.5

0.0

0.5

5.5

4.5

Hold time, HIGH or LOW

S_nto CP

Recovery time

MR to CP

Pulse width

Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V

Voltage Range 5.0 is 5.0 V ± 0.5 V

Capacitance

Item

Input capacitance

Symbol

Typ

Unit

Condition

C_IN

4.5

V_CC= 5.5 V

V_CC= 5.0 V

Power dissipation capacitance

C_PD

100

Rev.2.00, Jul.16.2004, page 6 of 7

HD74AC194

Package Dimensions

As of January, 2003

Unit: mm

10.06

10.5 Max

+ 0.20

7.80

– 0.30

0.80 Max

1.15

0˚ – 8˚

1.27

0.70 ± 0.20

*0.40 ± 0.06

0.15

0.12

Package Code

JEDEC

FP-16DAV

—

JEITA

Mass (reference value)

Conforms

0.24 g

*Ni/Pd/Au plating

As of January, 2003

Unit: mm

9.9

10.3 Max

1.27

+ 0.10

6.10

– 0.30

1.08

0.635 Max

0˚ – 8˚

+ 0.67

0.60

– 0.20

*0.40 ± 0.06

0.15

0.25

Package Code

JEDEC

JEITA

FP-16DNV

Conforms

0.15 g

*Ni/Pd/Au plating

Mass (reference value)

Rev.2.00, Jul.16.2004, page 7 of 7

Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

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Colophon .1.0

HD74AC194P [RENESAS]

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