HA16108FP-E [RENESAS]
2A SWITCHING CONTROLLER, 600kHz SWITCHING FREQ-MAX, PDSO16, SOP-16;
| 型号： | HA16108FP-E |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 2A SWITCHING CONTROLLER, 600kHz SWITCHING FREQ-MAX, PDSO16, SOP-16 开关 光电二极管 |
| 文件： | 总40页 (文件大小：455K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HA16107P/FP, HA16108P/FP
PWM Switching Regulator for
High-performance Voltage Mode Control
REJ03F0141-0400
(Previous: ADE-204-012C)
Rev.4.00
Jun 15, 2005
Description
The IC products in this series are primary control switching regulator control IC’s appropriate for obtaining stabilized
DC voltages from commercial AC power.
These IC’s can directly drive power MOS FET’s, they have a timer function built in to the secondary overcurrent
protection, and they can perform intermittent operation or delayed latched shutdown as protection operations in unusual
conditions. They can be used to implement switching power supplies with a high level of safety due to the wide range
of built-in functionality.
Functions
•
•
•
•
•
•
•
•
•
•
6.45 V reference voltage
Triangle wave generator
Error amplifier
Under voltage lockout protector
PWM comparator
Pulse-by-pulse current limitting
Timer-latch current limitting (HA16107)
ON/OFF timer function (HA16108)
Soft start and quick shutdown
Output circuit for power MOS FET driving
Features
•
•
•
•
•
•
Operating frequencies up to a high 600 kHz
Built-in pre-driver circuit for driving power MOS FET
Built-in timer latch over-current protection function (HA16107)
The OCL enables intermittent operation by an ON/OFF timer for prevention of secondary overcurrent. (HA16108)
The UVL function (under voltage lockout) is applied to both Vin and Vref.
ON/OFF reset: an auto-reset function which is based on the time constant of an external capacitor and observation
of drops in Vin.
•
•
Since the over-voltage protection function OVP (the TL pin) only observes voltage drops in Vin, it is possible to use
the OVP and ON/OFF pin for independent purposes.
Built-in 34 V Zener diode between Vin and ground.
Rev.4.00 Jun 15, 2005 page 1 of 39
HA16107P/FP, HA16108P/FP
Ordering Information
Typical Threshold Voltage
UVL1 OVP
Hi: 16.2 V
Package Code
(Previous Code)
Product
HA16107P
Notes
7.0 V
Timer latch protection DP-16
PRSP0016DH-A
Lo: 9.5 V
HA16107FP
(FP-16DA)
DP-16
HA16108P
Hi: 16.2 V
Lo: 9.5 V
Hi: 7.0 V
On-off timer
protection
Lo: 1.3 V
HA16108FP
PRSP0016DH-A
(FP-16DA)
Pin Arrangement
Note 2
TL, ON/OFF
VIN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OUT
E/O
CL(+)
VE
IN(−)
NC
CL(−)
GND
Note 1
RT1
CT
IN(+)
ST
RT2
Vref
(Top view)
Notes: 1. In the SOP package models (HA16107FP and HA16108FP) pins 4, 5, and 13 are connected
inside the IC. However, all must be connected to the system ground.
2. Pin 16 is TL (HA16107), ON/OFF (HA16108).
Rev.4.00 Jun 15, 2005 page 2 of 39
HA16107P/FP, HA16108P/FP
Pin Functions
•
HA16107P, HA16108P
Pin No. Symbol
Pin Functions
1
VIN
Input voltage
2
OUT
CL (+)
VE
Pulse output
3
Current limiter
4
Output ground
Current limiter
5
CL (–)
RT1
6
Timing resistor (rising time)
Timing capacitor
Timing resistor (falling time)
Reference voltage output
Soft start
7
CT
8
RT2
9
Vref
10
11
12
13
14
15
16
ST
IN (+)
GND
NC
Error amp (+) input
Ground
NC
IN (–)
E/O
Error amp (–) input
Error output
TL, ON/OFF
Timer latch (HA16107), ON/OFF (HA16108)
•
HA16107FP, HA16108FP
Pin No. Symbol
Pin Functions
Input voltage
1
VIN
2
OUT
CL (+)
GND
GND
RT1
Pulse output
3
Current limiter
4
Ground
5
Ground
6
Timing resistor (rising time)
Timing capacitor
7
CT
8
RT2
Timing resistor (falling time)
Reference voltage output
Soft start
9
Vref
10
11
12
13
14
15
16
ST
IN (+)
GND
GND
IN (–)
E/O
Error amp (+) input
Ground
Ground
Error amp (–) input
Error output
TL, ON/OFF
Timer latch (HA16107), ON/OFF (HA16108)
Rev.4.00 Jun 15, 2005 page 3 of 39
HA16107P/FP, HA16108P/FP
Block Diagram
• HA16107P/FP
TL
E/O
15
IN (−)
NC
13
GND
12
IN (+)
11
ST
10
Vref
9
16
14
−
EA
Error amp.
+
140 µA
VIN
34 V
UVL1
Vref
6.45 V
H
L
zener type
Ref.
voltage
Gen.
UVL2
16 µA
VL VH
O
V
P
H
L
UVL2
R
S
Q
4 V 5 V
4 µA
UVL1
ST
On/Off latch
(VTH = 7 V)
Triangle waveform
UVL1 and UVL2
Pulse-by-pulse latch
PWM Comparator
+ + −
Triangle waveform OSC
3.4 V 10 µA
Vref
Q
R
Triangle waveform
Latch reset pulse
QCLM
Q
S
Current
limiter
ON duty pulse
OUT
VC
VE
1
2
3
4
5
6
7
8
VIN
OUT
CL (+)
VE
CL (−)
RT1
RT2
CT
• HA16108P/FP
ON/OFF
E/O
15
IN (−)
NC
13
GND
12
IN (+)
11
ST
10
Vref
9
16
14
−
EA
Error amp.
+
140 µA
VIN
34 V
Vref
UVL1
6.45 V
H
L
zener type
Ref.
voltage
Gen.
UVL2
16 µA
VL VH
O
V
P
H
L
UVL2
R
S
Q
4 V 5 V
4 µA
UVL1
ST
Triangle waveform
UVL1 and UVL2
On/Off latch
(VTH = 7 V)
PWM Comparator
+ + −
Triangle waveform OSC
3.4 V 10 µA
Pulse-by-pulse latch
Vref
Q
R
Triangle waveform
Latch reset pulse
QCLM
Q
S
Current
limiter
ON duty pulse
OUT
VC
VE
1
2
3
4
5
6
7
8
VIN
OUT
CL (+)
VE
CL (−)
RT1
CT
RT2
Note: Dotted lines apply to the SOP package model (pins 4, 5, and 13: ground)
Rev.4.00 Jun 15, 2005 page 4 of 39
HA16107P/FP, HA16108P/FP
Function and Timing Chart
Triangle Waveform and PWM Output
• Timing chart (during normal operation)
Triangle waveform
is output to CT pin
VTH 4.2 V typ
E/O
CT
VTL 2.2 V typ
2VBE
0 V
VRT2
OUT
VIN
0 V
Dead band
tDB
tON
• Oscillator equivalent circuit
Vref
9
(connected internally)
× 2
× 2
× 2
RT2
VRT2
−
+
8
I2
I1
I1
Comparator for
triangle waveform
oscillation
6
7
2I2
−
× 2
RT1
CT
+
0.6 V
The ×2s are transistors whose emitter area is doubled.
Vref − 2VBE
RT1
CT × RT1 × 2V
RT2
≈
I1 =
I2 =
tDB
=
0.4 × CT × RT1 (s)
Du max =
Vref − 2VBE
2RT1
Vref − 2VBE
RT2
RT2
1 − Du max
≈
≈
tON tDB
(s)
fOSC
(Hz)
2RT1 − RT2
tDB
Note: When fOSC is high, the actual value will differ from that given by the formula due to the delay time.
Determine the correct constants after constructing a test circuit.
Rev.4.00 Jun 15, 2005 page 5 of 39
HA16107P/FP, HA16108P/FP
1. Timing in Normal Operation
Timing in these ICs is based on a triangular voltage waveform. The rising edge (leading edge) defines the deadband
time tDB. The falling edge (trailing edge) defines the ON-duty control band tON. PWM output is on in the area
within tON that is bounded above by the triangle wave VCT and error output VE/O
The following pin outputs are related to PWM control:
CT (pin 7): triangle-wave voltage output
.
E/O (pin 15): error output voltage
RT2 (pin 8): ON-duty pulse output voltage
OUT (pin 2): PWM pulse output (for driving the gate of a power MOS FET)
2. Triangle Oscillator, Waveform and Frequency
The triangle oscillator in these ICs generates a triangular waveform by charging and discharging timing capacitor CT
with a constant current, as shown in the equivalent circuit. The CT charge current is:
V
REF − 2VBE
I(CTchg) = I1 =
RT1
The discharge current is:
V
REF − 2VBE
I(CTdischg) = 2I2 − I1, where I2 =
RT2
In these equations Vref (reference voltage) is typically 6.45 V, and VBE (base-emitter voltage of internal transistors)
is about 0.7 V.
The deadband time is:
CT × RT1 × 2V
tDB
=
+ 0.25 µs
V
REF − 2VBE
≈ 0.4 × CT × RT1 + 0.25 µs
The ON-duty time is:
RT2
2RT1 − RT2
tON = tDB
×
The 0.25 µs in these equations is a correction term for internal circuit delays.
The maximum ON-duty is
RT2
Du max =
2RT1
The oscillating frequency is:
1
fOSC
=
0.4 CT RT1 + 0.25 µ
+ 0.25 µ
RT2
1 –
2RT1
1
=
(Hz)
0.8 CT RT12 + 0.25µ × 2RT1
+ 0.25 µ
2RT1 − RT2
When RT1 = RT2, the maximum ON-duty is 50%, and:
1
fOSC
≈
0.8 CT RT1 + 0.25 µ × 2 + 0.25 µ
1
=
(Hz)
0.8 CT RT1 + 0.75 µ
This approximation is fairly close, but it should be checked in-circuit.
Rev.4.00 Jun 15, 2005 page 6 of 39
HA16107P/FP, HA16108P/FP
3. Programming of Maximum ON-Duty (Du Max)
The preceding equations should be used to program the deadband or maximum ON-duty. The following table gives
a summary.
Condition
RT1 > RT2
RT1 = RT2
RT1 < RT2
Triangle
waveform
Du max
Less than 50%
50%
Greater than 50%*
Note: In a primary-control switching regulator, Du Max > 50% is dangerous because the transformer will saturate.
Soft Start and Quick Shutdown
One purpose of the soft-start function is to protect the switching controller and power MOS FET from surges at power-
up. Another purpose is to let the secondary-side DC voltage rise smoothly.
When power goes off, the quick-shutdown function rapidly discharges the capacitor in the soft-start circuit (and at the
same time switches the PWM output off) to prepare for the next power-on.
The soft-start function in these ICs lets the PWM output develop smoothly from zero to the designated pulse width at
power-up. The soft-start voltage is the 3.8 V voltage value of an internal Zener diode, so the PWM output is able to
start widening gradually as soon as the soft-start function starts operating. The soft-start function will start promptly
even if CST is large.
The soft-start and quick-shutdown modes are selected automatically in the IC, under control of the UVL signal.
Rev.4.00 Jun 15, 2005 page 7 of 39
HA16107P/FP, HA16108P/FP
• Timing waveforms
Level determined by transformer
VIN
16.2 V
VIN
9.5 V
6.45 V
5 V
Vref
4 V
0 V
Vref
VST
VCT
CST discharge
4.2 V
3.8 V
2.2 V
V
VE/O
CT, VST
,
0 V
VE/O
VIN
0 V
Quick shutdown
(Time t)
VOUT
(PWM pulse)
Soft start
Normal operation
Vref
Vref
ST
9
from Vref
from UVL2
(Effective for
CST
quick shutdown)
+
+
−
10
Zener
diode
3.8 V
PWM comparator
VCT
10 µA
E/O
15
7
Note: The soft-start time constant is determined by CST and the constant-current value (typically 10 µA).
Rev.4.00 Jun 15, 2005 page 8 of 39
HA16107P/FP, HA16108P/FP
Vref Protection Functions: Overvoltage and Undervoltage
Vref overvoltage and undervoltage conditions are detected by the overvoltage detection circuit and UVL2 circuit.
PWM output shuts down when Vref ≥ 8 V. UVL2 detects undervoltage with hysteresis between approximately 4 V and
5 V. PWM output also shuts down below these voltages. It follows that PWM output will shut off whenever the Vref
pin is shorted to the power supply (VIN) or ground (GND). PWM output also shuts off when VIN is turned on or off.
The following diagram shows how these protection functions operate when power comes on and goes off (Vref < 6.45
V), and when a high external voltage is applied to the Vref pin (Vref > 6.45 V).
PWM output shut-
down region
PWM output
operating region
PWM
OUT
Power-off,
or shorted
to ground
Shorted to
power supply
PWM output
shut-down region
Power-up
Vref
0
4 V 5 V 6.45 V 8 V
10 V
Vref
OVP
UVL2
1. Current-Limiter Circuit
The current limiter pin (CL) is connected to the emitter of an npn transistor, as shown in the block diagram. The
threshold voltage is 240 mV typ. The switching speed of this circuit is approximately 100 ns from detection of
overcurrent to shut-down of PWM output. Switching speed increases with the strength of the signal input to the CL
pin.
Instead of simple pulse-by-pulse current limiting, in these ICs the current limiting circuit is linked to the timer-and-
latch or ON/OFF timer circuit, and also detects the degree of overcurrent. The overcurrent value is determined from
the point at which current limiting is triggered in the ON-duty cycle. With a large overcurrent (causing current
limiting to operate even at a small ON-duty), the IC automatically shortens the timer time.
Rev.4.00 Jun 15, 2005 page 9 of 39
HA16107P/FP, HA16108P/FP
Undervoltage Lockout and PWM Output
The undervoltage lockout function turns off the PWM pulse output when the controller’s supply voltage goes below a
designated value. These ICs have two undervoltage lockout circuits. The UVL1 circuit senses the supply voltage VIN.
The UVL2 circuit senses the Vref voltage. A feature of these ICs is that PWM output is turned on only when both
voltages are above designated values. Otherwise, the IC operates in standby mode.
The two built-in undervoltage lockout circuits make it possible to configure an extremely safe power supply system.
PWM output will shut down under a variety of abnormal conditions, such as if Vref is shorted to ground while VIN is
applied.
1
• UVL1 (VIN and Vref)
*
16.2 V
IIN
9.5 V
VIN
0
0
10 V
20 V
30 V
6.45 V
34 V
Notes: 1. Breakdown voltage of
the internal Zener
Vref
diode (Vz = 34 V typ).
2. Hysteresis characteristic.
2
*
VIN
10 V
20 V
30 V
• UVL2 (Vref and PWM output)
Vref
6.45 V
5 V
4 V
VIN
0
10 V
20 V
30 V
Operating region
OUT
VIN
0
10 V
20 V
30 V
PWM output shut-down region
• UVL1 and UVL2
VIN (UVL1)
Vref (UVL2)
PWM OUT
L
L
L
H
L
H
H
L
H
L
L
OUT
Standby mode
Note: Double circles indicate standby mode.
Rev.4.00 Jun 15, 2005 page 10 of 39
HA16107P/FP, HA16108P/FP
Timer Latch and ON/OFF Timer
The HA16107 has a built-in timer-latch function. The HA16108 has a built-in ON/OFF timer function.
The timer-latch function is an overvoltage protection function that combines latched shutdown of PWM output with a
timer function to vary the time until latched shutdown occurs according to the overcurrent value. A dedicated voltage
detection pin is provided in addition to Vref overvoltage protection.
The ON/OFF timer function is equivalent to the above timer-latch function without the latch. If overcurrent is detected
continuously, PWM output shuts down temporarily, then normal operation resumes. This process repeats, temporary
shutdown alternating with normal operation.
Both the timer-latch function in the HA16107 and the ON/OFF function in the HA16108 wait for an interval after
overcurrent detection before shutting down PWM output. The interval is determined by capacitor CTM and the value of
the charge/discharge current supplied internally from the IC. Normal operation therefore continues if a single
overcurrent spike is detected, while if continuous overcurrent is detected, the current and voltage droop curves for the
secondary-side output have sharp characteristics.
1. Use of Timer-Latch Pin (HA16107)
Timer-Latch Usage
See external circuit 1 in the following diagram. Under continuous overcurrent, the CML switch turns on,
charging CTM with 12 µA. PWM output shuts down when the voltage at pin 15 exceeds 7 V.
Overvoltage Protection Usage
See external circuit 2 in the diagram. This configuration is suitable when overvoltage is detected by an OVP
signal received through an optocoupler from the DC output on the secondary side of an AC/DC converter.
PWM output shuts down when the OVP signal allows the voltage at the TL pin to exceed 7 V. The shutdown is
latched. VIN must go below approximately 6.5 V (VINR2) to release the latched state.
• External circuit 1
• External circuit 2
VIN
16 µA
from CML
OVP with
latch timer
OVP signal
(from secondary)
15
TL
CTM
4 µA
HA16107
Latch
VTH
7.0 V
(PWM output shuts down)
B
VTL
A
0 V
t
OCL detected continuously
(activating pulse-by-pulse current limiter)
Notes: 1. Path A is followed if the OCL input stops before VTH is reached.
2. Path B is followed if OCL is detected continuously until the latch point is reached.
3. The latch function is cleared when VIN goes below approximately 7.0 V.
Rev.4.00 Jun 15, 2005 page 11 of 39
HA16107P/FP, HA16108P/FP
2. Use of ON/OFF Timer Pin (HA16108)
External Circuit
16 µA
from CML
OVP with
ION
16
+
latch timer
IOFF
4 µA
HA16108
ON/OFF Timer Operation
tOFF
tON
VTHH
7.0 V
VTHL
1.2 V
0 V
t
OCL detected
(PWM output on) output
shut down
PWM
OCL detected
(PWM output on)
Pulse-by-pulse current limiting
C × 5.8 V
(0.9 − Du) × 16 µA − 4 µA
tON
≈
C × 5.8 V
4 µA
tOFF
≈
Notes: 1. C is the capacitance of an external timing capacitor connected between this pin and ground.
2. Du is the ON-duty of the PWM output when overcurrent limiting is triggered.
3. The values of tON and tOFF for TL can be determined by the same equations as given for
the ON/OFF timer, except that 5.8 V (VTHH − VTHL) becomes VTHH = 7 V.
4. If the timer goes off during soft start or in the undervoltage lockout region, after recovery,
output will come on after the soft-start time or after the rise time to the undervoltage lockout
release point, which is determined by the time constant.
Rev.4.00 Jun 15, 2005 page 12 of 39
HA16107P/FP, HA16108P/FP
Absolute Maximum Ratings
(Ta = 25°C)
Item
Supply voltage
Symbol
Rating Value
Units
Notes
VIN
30
V
Output current (DC)
Output current (peak)
Current limiter voltage
Error amp input voltage
E/O output voltage
RT1 pin current
IO
±0.2
A
Iopeak
VCL
±2
A
+4, –1
Vref
V
VIEA
VIE/O
IRT1
IRT2
PT
V
Vref
V
500
µA
mA
mW
°C
°C
RT2 pin current
5
Power dissipation
680
1, 2
Operating temperature range
Storage temperature range
Topr
Tstg
–20 to +85
–55 to +125
Notes: 1. For the “FP” products (SOP package), this value is when mounted on a 40 by 40 by 1.6 mm glass epoxy
substrate. However, this value must be derated by 8.3 mW/°C from Ta = 45°C. When the wiring density is
10%, and 11.1 mW/°C from Ta = 64°C when the wiring density is 30%.
2. For the “P” products (DIP package), this value is valid up to 45°C, and must be derated by
8.3 mW/°C above 45°C.
3. In the case of SOP, use center 4 pins, (4), (5), (12), (13) for solder-mounting and connect the wide ground
pattern, because these pins are available for heat sink of this IC.
30% Wiring density
10% Wiring density
45°C 64°C
700
600
500
400
300
200
100
−20
0
20
40
60
80
100 120 140
Ambient temperature Ta (°C)
Rev.4.00 Jun 15, 2005 page 13 of 39
HA16107P/FP, HA16108P/FP
Electrical Characteristics
(Ta = 25°C, VIN = 18 V, fOSC = 100 kHz)
Section
Item
Output voltage
Line regulation
Load regulation
Symbol
Vref
Min
6.10
–
Typ
6.45
30
Max
6.80
60
Unit
V
Test Conditions
Note
Reference
voltage
Line
mV
mV
12 V ≤ VIN ≤ 30 V
0 mA ≤ IO ≤ 10 mA
Load
–
30
60
Temperature
stability
∆Vref/
∆Ta
–
40
–
ppm/
°C
Short circuit current
IOS
30
50
–
mA
V
Vref = 0 V
Over voltage protec-
tion (Vref OVP
voltage)
Vrovp
7.4
8.0
9.0
Triangle
wave
generator
Maximum frequency
Minimum frequency
Voltage stability
fmax
fmin
600
–
–
–
–
1
kHz
kHz
%
∆f/fo1
–
±1
±3
12 V ≤ VIN ≤ 30 V
fo1 = (fmax + fmin)/2
Temperature stability
Frequency accuracy
Minimum deadband
∆f/fo2
fOSC
tDB
–
270
–
±1
300
–
–
%
kHz
µs
–20°C ≤ Ta ≤ +85°C
fo2 = (fmax + fmin)/2
330
1.0
2.5
RT1 = RT2 = 27 kΩ
CT = 120 pF
PWM
comparator pulse width
Low level threshold
VTL
1.9
2.2
V
voltage
High level threshold
Differential threshold
VTH
3.8
1.7
–
4.2
2.0
±1
4.6
2.3
±3
V
V
∆VTH
∆DB1
Deadband width
initial accuracy
%
RT1 = RT2 = 27 kΩ
CT = 470 pF
Deadband width
voltage stability
∆DB2
∆DB3
–
–
±0.2
±1
±2.0
–
%
%
12 V ≤ VIN ≤ 30 V
(Dmax – Dmin)/2
Deadband width
–20°C ≤ Ta ≤ +85°C
temperature stability
(Dmax – Dmin)/2
Error amp
Input offset voltage
Input bias current
Input sink current
Output source current
VIO
–
–
2
10
2.0
–
mV
µA
µA
µA
V
IIB
0.8
140
140
–
Iosink
Iosource
VOH
80
80
VO = 2 V
VO = 5 V
IO = 10 µA
–
High level output
voltage
Vref –
1.5
–
Low level output
voltage
VOL
–
–
0.5
V
IO = 10 µA
Voltage gain
Band width
GV
–
–
55
15
–
–
–
–
dB
MHz
V
f = 10 kHz
BW
(–) Common mode
voltage
VCM
–
+
1.2
(+) Common mode
voltage
VCM
–
–
Vref –
1.5
V
Over-
current
detector
(+) Threshold voltage
(+) Bias current
VTH
IB+
VTH
IB–
toff
+
0.216
–
0.240
180
0.264
250
V
µA
V
VCL+ = 0 V
(–) Threshold voltage
(–) Bias current
–
–0.264 –0.240
–0.216
1350
–
1, 2
1, 2
–
–
950
100
µA
ns
VCL = –0.3 V
CL; open
Response time
VCL = +0.35 V
Notes: 1. Only applies to the HA16107P, HA16108P
2. The terminal should not be applied under –1.0 V.
Rev.4.00 Jun 15, 2005 page 14 of 39
HA16107P/FP, HA16108P/FP
Electrical Characteristics (cont.)
(Ta = 25°C, VIN = 18 V, fOSC = 100 kHz)
Section
Item
High level voltage
Sink current
Symbol
VSTH
Min
3.2
7
Typ
3.8
Max
4.4
Unit
V
Test Conditions
Isink = 1 mA
Note
Soft start
Isink
10
13
µA
V
VST = 2.0 V
Under
voltage
lockout 1
VIN high level thre-
shold voltage
VINTH
14.7
16.2
17.7
VIN low level thre-
shold voltage
VINTL
∆VTH
VrTH
VrTL
8.5
5.2
4.5
3.5
6.5
9.5
6.2
5.0
4.0
7.0
10.5
7.2
5.5
4.5
7.5
V
V
V
V
V
Threshold differential
voltage
(VINTH – VINTL)
Under
voltage
lockout 2
Vref high level thre-
shold voltage
Vref low level thre-
shold voltage
Timer
latch,
Latch threshold
voltage
VTHH
Latch threshold
voltage
ON/OFF
timer *2
VIN reset voltage
Reset voltage
VINR2
VTHL2
6.0
1.0
2.0
6.5
1.3
3.0
7.0
1.6
–
V
V
V
1
Differential threshold to ∆V
UVL low voltage
(VINTL – VINR2
Over current
)
Source current
(OCL mode)
Isource
8
2.5
–
12
4
16
µA
µA
detection mode
Sink current
(latch mode)
Isink
5.5
TL(ON/OFF)
terminal = 4 V
Output
Low voltage
High voltage
VOL1
VOH
1.7
–
2.2
–
V
V
Iosink = 0.2 A
VIN
–
Iosource = 0.2 A
2.2
Low voltage
VOL2
–
–
0.5
V
Iosink = 1 mA
(standby mode)
Rising time
tr
–
–
–
–
40
60
—
—
ns
ns
CL = 1000 pF
CL = 1000 pF
VIN = 14 V
Falling time
tf
Total
Standby current
Operation current
Ist
IIN1
160
16
250
20
µA
mA
VIN = 30 V,
CL = 1000 pF,
f = 100 kHz
Operation current
IIN2
–
12
16
mA
VIN = 30 V,
f = 100 kHz,
Output open
ON/OFF latch
current
IIN3
VZ
–
350
34
460
–
µA
VIN = 14 V
VIN – GND Zener
voltage
30
V
Notes: 1. Only applies to the HA16108P/FP.
2. Timer latch: HA16107P/FP.
ON/OFF timer: HA16108P/FP.
Rev.4.00 Jun 15, 2005 page 15 of 39
HA16107P/FP, HA16108P/FP
Note on Standby Current
In the test circuit shown in figure 1, the operating current at the start of PWM pulse output is the standby current.
If the resistance connected externally to the Vref pin (including RT2) is smaller than that of the test circuit, the apparent
standby current will increase.
↑
VIN
Ist
Vref
HA16107
Series
+
CIN
↑
IIN
Rref
Figure 1 Standby Current Test Circuit
Rev.4.00 Jun 15, 2005 page 16 of 39
HA16107P/FP, HA16108P/FP
Application Note
•
Case:
When DC power is applied directly as the power supply of the HA16107/HA16108, without using the transformer
backup coil.
•
Phenomenon:
The IC may not be activated in the case of a circuit in which VIN rises quickly (10 V/100 µs or faster), such as that
shown in figure 2.
•
•
Reason:
Because of the IC circuit configuration, the timer latch block operates first.
Remedy (counter measure):
Take remedial action such as configuring a time constant circuit as shown in figure 3, to keep the VIN rise speed
below 10 V/100 µs.
If the IC power supply consists of an activation resistance and backup coil, as in an AC/DC converter, The VIN rise
speed is usually around 1 V/100 µs, and there is no risk of this phenomenon occurring.
Output
Input
VIN
HA16107
Series
VIN
Feedback
GND
Figure 2 Example of Circuit with Fast VIN Rise Time
Input
Output
Time constant
circuit
R 51Ω
VIN
HA16107
Series
VIN
18 V
Feedback
1 µF
C
GND
Figure 3 Sample Remedial Circuit
Rev.4.00 Jun 15, 2005 page 17 of 39
HA16107P/FP, HA16108P/FP
Characteristic Curves
Operating Current vs. Power Supply Voltage
40
30
20
10
Ta = 25°C
RT1
CT = 470 pF
fOSC = 100 kHz
=
R
27 kΩ
=
T2
0
10
20
30
40
Power supply voltage (V)
Latch Current vs. Power Supply Voltage
2.0
1.5
1.0
0.5
Ta = 25°C
T1 = RT2 = 27 kΩ
R
CT =470 pF
fOSC = 100 kHz
0
10
20
30
40
Power supply voltage (V)
Rev.4.00 Jun 15, 2005 page 18 of 39
HA16107P/FP, HA16108P/FP
Standby Current vs. Power Supply Voltage
400
Ta = 25°C
T1 = RT2 = 27 k
R
Ω
CT =470 pF
300
200
100
fOSC = 100 kHz
0
4
8
12
16
20
Power supply voltage (V)
Output VOH vs. Reference Voltage
20
15
10
5
Ta = 25°C
IN = 20 V
V
CT = 470 pF
Vref
UVL2 Voltage
Vref
OVP Voltage
0
2
4
6
8
10
Reference voltage (V)
Rev.4.00 Jun 15, 2005 page 19 of 39
HA16107P/FP, HA16108P/FP
Reference Voltage vs. Power Supply Voltage
8
Ta = 25°C
RT1 = RT2 = 27 kΩ
CT =470 pF
6
4
2
fOSC = 100 kHz
0
10
20
30
Power supply voltage (V)
Output OFF Time vs. VCL
400
300
200
100
Ta = 25°C
RT1 = RT2 = 27 kΩ
CT =470 pF
VCL
fOSC = 100 kHz
CL = 100 pF
CL = unloaded
0
0.2
0.3
0.4
VCL (V)
Rev.4.00 Jun 15, 2005 page 20 of 39
HA16107P/FP, HA16108P/FP
Output ON Duty vs. Error Input Voltage
60
50
40
30
Ta = 25°C
T1 = RT2 = 27 kΩ
R
CT =470 pF
fOSC = 100 kHz
20
10
0
1
2
3
4
5
Error input voltage (V)
Rev.4.00 Jun 15, 2005 page 21 of 39
HA16107P/FP, HA16108P/FP
Reference Voltage and PWM Out vs. CL(+)
0
0.1
0.2
0.3
0.4
3.0
0
0.1
0.2
0.3
0.4
3.0
CL(+)
Reference Voltage and PWM Out vs. CL(−)
0
−0.1
−0.2
−0.3
−0.4
−1.0
0
−0.1
−0.2
−0.3
−0.4
−1.0
CL(−)
Rev.4.00 Jun 15, 2005 page 22 of 39
HA16107P/FP, HA16108P/FP
Timing Resistance vs. Deadband Duty
20
VIN
Ta
=
18V
=
25°C
15
10
5
CT
= 470 pF
f
OSC ≈ 100 kHz
RT1
R
T2
0
80
30
40
50
60
70
Deadband duty (%)
Temperature Fluctuation vs. Ambient Temperature
2000
1000
0
VIN
= 18V
RT1
=
R
= 27 kΩ
T2
CT
=
470 pF
100 kHz
fOSC
=
−1000
−2000
−20
85
0
25
50
75
Ambient temperature (°C)
Rev.4.00 Jun 15, 2005 page 23 of 39
HA16107P/FP, HA16108P/FP
Frequency Variance vs. Ambient Temperature
18V
10
VIN
RT1
=
=
R
= 27 kΩ
T2
CT
=
470 pF
= 100 kHz
5
0
fOSC
−5
−10
−20
0
25
50
75
85
Ambient temperature (°C)
Frequency Variance vs. Ambient Temperature
= 18V
10
5
VIN
RT1
=
R
= 27 kΩ
T2
CT
= 120 pF
fOSC = 300 kHz
0
−5
−10
−20
0
25
50
75
85
Ambient temperature (°C)
Rev.4.00 Jun 15, 2005 page 24 of 39
HA16107P/FP, HA16108P/FP
Frequency Variance vs. Ambient Temperature
18V
10
VIN
=
=
RT1
R
= 13 kΩ
T2
CT
=
120 pF
= 600 kHz
5
0
fOSC
−5
−10
−20
0
25
50
75
85
Ambient temperature (°C)
Output ON Duty Variance vs. Ambient Temperature
= 18V
10
5
VIN
0
f
f
=
=
100 kHz
300 kHz
−5
f
=
600 kHz
−10
−20
0
25
50
75
85
Ambient temperature (°C)
Rev.4.00 Jun 15, 2005 page 25 of 39
HA16107P/FP, HA16108P/FP
Oscillator Frequency vs. Timing Resistance
600
500
VIN = 18 V
Ta = 25°C
300
100
90
70
50
30
10
9
7
5
7
10
30
50
70
100
Timing resistance RT1 (= RT2) (kΩ)
Rev.4.00 Jun 15, 2005 page 26 of 39
HA16107P/FP, HA16108P/FP
Vout Output Rising Waveform
Test circuit
Ta
= 25°C
40
30
RT1
=
R
= 27 kΩ
T2
CT
= 470 pF
VIN
fOSC
=
100 kHz
Current probe
IO
20
TL
+
10
1 µF
OUT
CL
0
CL (+)
1000 pF
27 k
Ω
RT1
500
0
470 pF
CT
ST
CST
+
1 µF
RT2 Vref
27 k
−500
Ω
* Current probe: Tektronix AM503
200 ns/div
Vout Output Falling Waveform
40
30
20
10
0
500
0
−500
200 ns/div
Rev.4.00 Jun 15, 2005 page 27 of 39
HA16107P/FP, HA16108P/FP
HA16107
Operating waveform at the TL pin
When overcurrent is input at the point
VIN = 18V
Test circuit
R
T1 = RT2 = 27 kΩ
VIN
CT = 470 pF
where the duty cycle is 0%.
fOSC = 100 kHz
7
6
5
4
3
2
1
0
TL
+
OUT
SW
1 µF
CL
CL(+)
1000 pF
Clock
470 pF
B
RT1
CT
27 k
Ω
ST
CST
1 µF
+
RT2 Vref
27 kΩ
A
Triangle
wave
CL(+) when
input at a
duty of 0%
0.5 sec/div
CL(+) when
input at a
tON
tOFF
duty of 30%
Output pulse shutdown region
t1
SW ON SW OFF
t2
When overcurrent is input at the point
where the duty cycle is 30%.
t1
t2
Du =
× 100 (%)
7
A
Enlargement of section
6
5
4
3
2
1
0
b
c
a
VTL
B
CTL discharged at 4 µA
CTL discharged at 12 µA
t
B
Enlargement of section
A
VTL
CTL discharged at 4 µA
t
0.5 sec/div
tOFF
tON
a
to
to
b
c
: PWM pulse output is High
b
: The point where overcurrent
is detected
Output pulse shutdown region
SW ON SW OFF
b
: PWM pulse output is Low.
Rev.4.00 Jun 15, 2005 page 28 of 39
HA16107P/FP, HA16108P/FP
HA16108
Operating waveform at the ON/OFF pin
When overcurrent is input at the point
VIN = 18V
Test circuit
RT1 = RT2 = 27 k½
CT = 470 pF
VIN
where the duty cycle is 0%.
fOSC = 100kHz
7
6
ON/OFF
+
OUT
1 µF
CL
1000 pF
CL(+)
B
Clock
470 pF
5
4
RT1
CT
27 k½
ST
CST
1 µF
+
RT2
3
2
27 k½
A
1
0
Triangle
wave
CL(+) when
input at a
duty of 0%
0.5 sec/div
tON
tOFF
tON
tOFF
tON tOFF
CL(+) when
input at a
duty of 30%
t1
Output pulse shutdown region
SW ON
SW OFF
t
2
When overcurrent is input at the point
where the duty cycle is 30%.
t1
Du =
× 100 (%)
t
2
7
6
A
Enlargement of section
B
c
b
a
V TL
5
4
CTL discharged at 4 µA
CTL discharged at 12 µA
3
2
t
A
B
Enlargement of section
1
0
V TL
CTL discharged at 4 µA
0.5 sec/div
t
tON
tOFF
tON
tOFF
a
b
to
: PWM pulse output is High.
b
: The point where overcurrent
is detected.
Output pulse shutdown region
SW ON
SW OFF
to c : PWM pulse output is Low.
b
Rev.4.00 Jun 15, 2005 page 29 of 39
HA16107P/FP, HA16108P/FP
Error Amplifier Characteristic
60
40
20
0
0
45
AVO
φ
90
135
180
10 k 30 k 100 k 300 k 1 M
3 M 10 M 30 M 100 M
Input signal frequency fIN (Hz)
Examples of Drooping Characteristics of Power Supplies Using these Ics
5.0
ON
Pulse by pulse
Current limiter operation
Normal operation
Latch state here
A
2.5
B
A
B
Heavy load
Light load
OFF
0
1
2
3
4
IOUT (DC) (A)
HA16107 (Latch shut-down)
5.0
ON
Pulse by pulse
Current limiter operation
OFF
A
B
2.5
A
B
Heavy load
Light load
0
1
2
3
4
IOUT (DC) (A)
HA16108 (Intermittent operation by means of ON/OFF timer)
Rev.4.00 Jun 15, 2005 page 30 of 39
HA16107P/FP, HA16108P/FP
Operating Circuit Example
Flyback Transforrmer Application Example
•
(IC Vref used as system as reference voltage)
Schottky barrier diode
HRP 24
El-30
Trans former
Bridge Diode
Start-up Resistor
140 V
+
82 kΩ
1 W
5 V
OUTPUT
+
40T
6T
2SK1567
470 µF
51 Ω
−
HZP 16
−
1.5 Ω
23T
+
3 W
RFI
HRP 32
Current Sense
18.9 V
FILTER
50 V
22 µF
OVP
Detector
HZP 16
TL
AC
INPUT
Timerlatch
Capacitor
VIN
+
16 V
1 µF
E/O −
IN(−)
NC
OUT
CL(+)
VE
330
kΩ
110 Ω
51 Ω
Current
Sense
L.P.F.
510 kΩ
68
kΩ
Phase
Comp.
4700 pF
CL(−)
GND
27 kΩ
IN(+)
3.225 V
RT1
470 pF
ST
Soft Start
Cap.
−
CT
fosc = 100 kHz,
Dumax = 50%
1 µF
+
16 V
33kΩ 33kΩ
Vref
RT2
Frequency,
Max, Duty
Setting
27 kΩ
−
1 µF
16 V
+
HA16107P/FP
6.45 V
Rev.4.00 Jun 15, 2005 page 31 of 39
HA16107P/FP, HA16108P/FP
• Forward Transformer Application Example
Rev.4.00 Jun 15, 2005 page 32 of 39
HA16107P/FP, HA16108P/FP
• When OVP signal is inserted at CL(+) pin
VIN
RB
OVP detector
VIN
OUT
CL(+)
TL
+
1 µF
When the OVP detection Zener diode turns on, latch shutdown of the output
is performed after the elapse of the time determined by the capacitance
connected the TL pin.
Rev.4.00 Jun 15, 2005 page 33 of 39
HA16107P/FP, HA16108P/FP
Application
1. Use of Error Amplifier for Flyback Transformer Primary-Side Control
In this example, the fact that the transformers winding ratio and voltage ratio in Figure 4 are mutually proportional is
made use of in a flyback transformer type AC-DC converter. As fluctuation of output voltage V2 also appears in IC
power supply voltage V3, this is divided by a resistance and amplified by an error amplifier. An advantage of this
method is that a photocoupler need not be used, making it possible to configure a power supply with a small number of
parts (this example cannot be applied to a forward transformer).
•V1(input voltage)
Commercial AC input
Output
Start-up
N1
N3
resistance
To switch element
V3(IC power supply voltage)
V2(output voltage)
N2
R4
C1
R1
R3
Flyback
transformer
−
R2
R1 + R2
1
2
14
× V3 =
Vref
E/O
15
Error amp.
+
R2
N3
N2
Where V3 =
× V2,
11
2.5V
Figure 4 Error Amplifier Peripheral Circuitry Diagram
<Determining External Constants around Error Amplifier>
1. Detrrrmining DC Characteristics
In Figure 4, the relational expression in the box is satisfied, and therefore parameters are determined based on this.
The absolute value of the number of transformer windings is determined based on the equation N1:N2:N3 = V1:V2:V3,
taking primary inductance into consideration.
Next, IC operating voltage V3 is made around 11V to 18V, taking the UVL voltage into consideration. If V3 is too
large, the power consumption of the IC will increase, causing heat emission problems. If V3 is too small, on the
other hand, there will be problems with defective power supply start-up.
2. Determining Error Amplifier Gain vs. Frequency Characteristic
Taking the configuration in Figure 4, the error amplifier gain characteristic with respect to fluctuation of output
voltage V2 is as shown in Figure 5.
G1
G2
R6 ≠ 0
R6 = 0
f1 fAC
f2
fOSC
Frequency f (Hz)
Figure 5 Error Amplifier Characteristic
Rev.4.00 Jun 15, 2005 page 34 of 39
HA16107P/FP, HA16108P/FP
In Figure 5, the parameters are given by the following equations.
Gain
G1 = V3/V2 × R3/R1
G2 = V3/V2 × R4/R1
Corner frequencies
f1 = 1/(2π C1 R3)
f2 = 1/(2π C1 R4)
Where R3>>R4 (10:1 or above)
G1 is made around 30 to 50 dB, taking both regulation and stability into consideration.
f1 is made a lower value than commercial frequency ripple fAC, thus preventing hunting (a system instability
phenomenon).
Next, G2 is set to 0 dB or less as a guideline, so that there is no gain in IC operating frequency fOSC (several tens to
several hundreds of kHz). f2 should be set to a value that is substantially smaller than fOSC, and that is appropriate for
the power supply response speed (several kHz). In the case of a bridge type rectification circuit, the commercial
frequency ripple is twice the input frequency (with a 50 Hz commercial frequency, fAC = 100 Hz).
2. External Constant Design for Current Detection Section (HA16107, HA16108, HA16666)
In the above IC models, which incorporate a current detection function, a low-pass filter such as shown in Figure 6 must
be inserted between switch element current detection resistance RCS and the current detection pin of the IC.
140V
Input voltage VB
Floating capacitance
CX
Output
From PWM
output pin
of IC
Switch element
power MOS FET
To current
detection pin
of IC
ID
RA
V11
Current detection resistance
V12
RB
RCS
CA
Several hundred mΩ
to several Ω
Filter (LPF)
Figure 6 Current Detection Circuit
Rev.4.00 Jun 15, 2005 page 35 of 39
HA16107P/FP, HA16108P/FP
The reason for this is that, when the switch element is on in each cycle, there is an impulse current associated with
charging of transformer floating capacitance CX, and IC current detection malfunctions (see Figure 7).
VTH
V11
V12
Figure 7 Current Detection Waveform
<Setting Numeric Values>
If the switch element current to be detected is designated ID, and the current detection resistance RCS, then the following
equation is satisfied using the parameters in Figure 6.
ID × RCS = ((RA + RB)/RB) VTH
VTH is the detection level voltage of the IC (240 mV in the case of the HA16107, for example). RA and RB are set to
values on the order of several hundred Ω to several kΩ, so that RCS is not affected.
Next, the filter cutoff frequency is set according to the following equation.
fC = 1/(2π CA (RA/RB))
fC can be found with the following guideline, using IC operating frequency fOSC, power supply rating on-duty D, and
power MOS element turn-on time tON
.
fosc/D ≤ fC ≤ 1/(100 × tON
)
Value 100 in the above equation provides a margin for noise, ringing, and so forth.
<Actual Example>
In an SW power supply using an HA16107, with a 100 kHz operating frequency and a D value of 30%, the relevant
values were as follows: VB = 140 V, CX = 80 pF, tON = 10 ns. Thus, when RCS = 1 Ω, the V11 level peak value reaches
the following figure.
V11 (peak) = RCS × ID peak
= RCS × (VB × CX)/tON
= 1Ω × (140 V × 80 pF)/10 ns
= 1.12 (V)
A filter with the following constants was then inserted.
RA = RB = 1 kΩ, CA = 1000 pF
At this time, the detectable drain current is 0.48 (A), and the filter cutoff frequency is 318 (kHz). Note that increasing a
filter time constant is effective against noise, but if the value is too large, error will arise in the switch element current
detection level.
Rev.4.00 Jun 15, 2005 page 36 of 39
HA16107P/FP, HA16108P/FP
3. IC Heat Emission Problem and Countermeasures (HA16107 Series, HA16114 Series)
While the above ICs can directly drive a power MOS FET gate, if the method of use is not thoroughly investigated,
there will be a tendency for the gate drive power to increase and a problem of heat emission by the IC may occur.
This section should therefore be noted and appropriate measures taken to prevent this kind of problem.
1. Power MOS FET Drive Characteristics
When power MOS FET drive is performed, in order to lower the on-resistance sufficiently, overdrive is normally
performed with a voltage considerably higher than 5 V, for example, such as the 15 V power supply voltage of the
IC.
At this time, the power that should be supplied from the IC to the power MOS FET is determined by gate load Qg in
Figure 9.
2. IC Heat-Emission Power Calculation (Figure 9)
The power that contributes to IC heat emission is calculated by means of the following equation.
Pd = VIN IQ + 2Qg VIN f
Where
VIN : Power supply voltage of IC
IQ : Operating current of IC (unloaded)
Qg : Above-mentioned gate load
f
: Operating frequency of IC
The coefficient, 2, indicates that gate discharging also contributes to heat emission.
4. Power MOS FET Gate Resistance Design (HA16107 Series, HA16114 Series)
There are the following three purposes in connecting a gate resistance, and the circuit is generally of the kind shown in
Figure 8.
(1) To suppress peak current due to gate charging
(2) To protect IC output pins
(3) To provide drive appropriate to power MOS FET input characteristics
DG
To transformer
Power
MOS FET
OUT
RG1
RG2
CS
IC
output pin
RCS
Figure 8 Gate Drive Circuit
Rev.4.00 Jun 15, 2005 page 37 of 39
HA16107P/FP, HA16108P/FP
This gate resistance RG is given by the following equation.
RG = (VG/IG) – (VG × tON)/Qg, RG = RG1 + RG2
IG : Gate input peak current
VG : Gate drive voltage wave high value (equal to power supply voltage of IC)
tON : Power MOS FET turn-on time
tOFF : Power MOS FET turn-off time
Qg : Gate charge according to Figure 9
VDS
VDS
(V)
VGS
(V)
VGS
Qg (nc)
Figure 9 Power MOS FET Dynamic Input Characteristics
Refer to the power MOS FET catalog for information on tON and Qg.
By dividing RG into RG1 and RG2, it is possible for speed to be slowed when the power MOS FET is on, and
increased when off.
Power MOS FET on and off times when mounted, tON’ and tOFF’, are as follows.
tON’ = tON + Qg(RG1 + RG2)/VG
tOFF’ = tOFF + Qg ⋅ RG2/VG
<Actual Example>
When driving a power MOS FET and 2SK1567 with an HA16107, etc.
(RG1 = 100 Ω, RG2 = 20 Ω, VG = 15 V)
t
ON’ = 70 ns + 36 nc ⋅ (100 Ω + 20 Ω)/(15 V) = 360 (ns)
tOFF’ = 135 ns + 36 nc ⋅ (20 Ω)/(15 V) = 183 (ns)
Generally, the gate resistance values in the case of this circuit configuration are on the order of 100 to 470 Ω for RG1
and 10 to 47 Ω for RG2.
Rev.4.00 Jun 15, 2005 page 38 of 39
HA16107P/FP, HA16108P/FP
Package Dimensions
As of January, 2003
19.20
20.00 Max
Unit: mm
16
1
9
8
1.3
1.11 Max
7.62
+ 0.13
− 0.05
0.25
2.54 ± 0.25
0.48 ± 0.10
0° − 15°
Package Code
JEDEC
JEITA
DP-16
Conforms
Conforms
1.07 g
Mass (reference value)
JEITA Package Code
P-SOP16-5.5x10.06-1.27
RENESAS Code
PRSP0016DH-A
Previous Code
FP-16DA
MASS[Typ.]
0.24g
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
*1
D
F
16
9
bp
b1
Index mark
Dimension in Millimeters
Reference
Symbol
Min
Nom
10.06
5.5
Max
10.5
Terminal cross section
D
E
1
8
bp
A 2
A 1
A
*3
e
0.00
0.34
0.17
0.10
0.20
2.20
0.50
Z
x
M
L1
b
0.42
0.40
0.22
0.20
p
b
1
c
0.27
c
1
θ
H E
e
0
°
8°
7.50
7.80
1.27
8.00
y
x
0.12
0.15
0.80
0.90
L
y
Z
Detail F
L
0.50
0.70
1.15
L
1
Rev.4.00 Jun 15, 2005 page 39 of 39
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits,
(ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
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evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater
use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
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© 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
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