H8/3835U [RENESAS]
Single-Chip Microcomputer; 单片机
| 型号： | H8/3835U |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Single-Chip Microcomputer |
| 文件： | 总497页 (文件大小：1170K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Hitachi Single-Chip Microcomputer
H8/3834U Series
HD6433833U
HD6473834U, HD6433834U
HD6433835U
HD6433836U
HD6473837U, HD6433837U
Hardware Manual
ADE-602-089
Preface
The H8/300L Series of single-chip microcomputers has the high-speed H8/300L CPU at its core,
with many necessary peripheral functions on-chip. The H8/300L CPU instruction set is
compatible with the H8/300 CPU.
The H8/3834U Series has a system-on-a-chip architecture that includes such peripheral functions
as an LCD controller/driver, five types of timers, a 14-bit PWM, a three-channel serial
communication interface, and an A/D converter. This makes it ideal for use in systems requiring
an LCD display.
This manual describes the hardware of the H8/3834U Series. For details on the H8/3834U Series
instruction set, refer to the H8/300L Series Programming Manual.
Contents
Section 1 Overview..........................................................................................................
1
1
5
6
6
8
1.1
1.2
1.3
Overview.........................................................................................................................
Internal Block Diagram ..................................................................................................
Pin Arrangement and Functions .....................................................................................
1.3.1 Pin Arrangement.................................................................................................
1.3.2 Pin Functions ......................................................................................................
Section 2 CPU................................................................................................................... 13
2.1
Overview......................................................................................................................... 13
2.1.1 Features............................................................................................................... 13
2.1.2 Address Space..................................................................................................... 14
2.1.3 Register Configuration........................................................................................ 14
Register Descriptions...................................................................................................... 15
2.2.1 General Registers................................................................................................ 15
2.2.2 Control Registers ................................................................................................ 15
2.2.3 Initial Register Values......................................................................................... 17
Data Formats................................................................................................................... 17
2.3.1 Data Formats in General Registers ..................................................................... 18
2.3.2 Memory Data Formats........................................................................................ 19
Addressing Modes .......................................................................................................... 20
2.4.1 Addressing Modes .............................................................................................. 20
2.4.2 Effective Address Calculation ............................................................................ 22
Instruction Set................................................................................................................. 26
2.5.1 Data Transfer Instructions .................................................................................. 28
2.5.2 Arithmetic Operations ........................................................................................ 30
2.5.3 Logic Operations ................................................................................................ 31
2.5.4 Shift Operations.................................................................................................. 31
2.5.5 Bit Manipulations ............................................................................................... 33
2.5.6 Branching Instructions........................................................................................ 37
2.5.7 System Control Instructions ............................................................................... 39
2.5.8 Block Data Transfer Instruction ......................................................................... 40
Basic Operational Timing............................................................................................... 42
2.6.1 Access to On-Chip Memory (RAM, ROM) ....................................................... 42
2.6.2 Access to On-Chip Peripheral Modules ............................................................. 43
CPU States...................................................................................................................... 45
2.7.1 Overview............................................................................................................. 45
2.7.2 Program Execution State ................................................................................... 46
2.7.3 Program Halt State.............................................................................................. 46
2.7.4 Exception-Handling State................................................................................... 46
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Memory Map .................................................................................................................. 47
2.8.1 Memory Map ...................................................................................................... 47
2.8.2 LCD RAM Address Relocation.......................................................................... 52
Application Notes........................................................................................................... 53
2.9.1 Notes on Data Access......................................................................................... 53
2.9.2 Notes on Bit Manipulation.................................................................................. 55
2.9.3 Notes on Use of the EEPMOV Instruction......................................................... 61
Section 3 Exception Handling...................................................................................... 63
3.1
3.2
Overview......................................................................................................................... 63
Reset ............................................................................................................................ 63
3.2.1 Overview............................................................................................................. 63
3.2.2 Reset Sequence................................................................................................... 63
3.2.3 Interrupt Immediately after Reset....................................................................... 65
Interrupts......................................................................................................................... 66
3.3.1 Overview............................................................................................................. 66
3.3.2 Interrupt Control Registers ................................................................................. 68
3.3.3 External Interrupts .............................................................................................. 77
3.3.4 Internal Interrupts ............................................................................................... 78
3.3.5 Interrupt Operations............................................................................................ 79
3.3.6 Interrupt Response Time..................................................................................... 84
Application Notes........................................................................................................... 85
3.4.1 Notes on Stack Area Use.................................................................................... 85
3.4.2 Notes on Rewriting Port Mode Registers ........................................................... 86
3.3
3.4
Section 4 Clock Pulse Generators............................................................................... 89
4.1
Overview......................................................................................................................... 89
4.1.1 Block Diagram.................................................................................................... 89
4.1.2 System Clock and Subclock ............................................................................... 89
System Clock Generator................................................................................................. 90
Subclock Generator ........................................................................................................ 93
Prescalers........................................................................................................................ 96
Note on Oscillators ......................................................................................................... 97
4.2
4.3
4.4
4.5
Section 5 Power-Down Modes..................................................................................... 99
5.1
Overview......................................................................................................................... 99
5.1.1 System Control Registers ................................................................................... 102
Sleep Mode..................................................................................................................... 105
5.2.1 Transition to Sleep Mode.................................................................................... 105
5.2.2 Clearing Sleep Mode .......................................................................................... 105
Standby Mode................................................................................................................. 106
5.2
5.3
5.3.1 Transition to Standby Mode ............................................................................... 106
5.3.2 Clearing Standby Mode...................................................................................... 106
5.3.3 Oscillator Settling Time after Standby Mode is Cleared.................................... 106
5.3.4 Transition to Standby Mode and Port Pin States ................................................ 107
Watch Mode.................................................................................................................... 108
5.4.1 Transition to Watch Mode .................................................................................. 108
5.4.2 Clearing Watch Mode......................................................................................... 108
5.4.3 Oscillator Settling Time after Watch Mode is Cleared....................................... 108
Subsleep Mode................................................................................................................ 109
5.5.1 Transition to Subsleep Mode .............................................................................. 109
5.5.2 Clearing Subsleep Mode..................................................................................... 109
Subactive Mode .............................................................................................................. 110
5.6.1 Transition to Subactive Mode............................................................................. 110
5.6.2 Clearing Subactive Mode.................................................................................... 110
5.6.3 Operating Frequency in Subactive Mode ........................................................... 110
Active (medium-speed) Mode ........................................................................................ 111
5.7.1 Transition to Active (medium-speed) Mode....................................................... 111
5.7.2 Clearing Active (medium-speed) Mode ............................................................. 111
5.7.3 Operating Frequency in Active (medium-speed) Mode ..................................... 111
Direct Transfer................................................................................................................ 112
5.8.1 Direct Transfer Overview ................................................................................... 112
5.8.2 Calculation of Direct Transfer Time before Transition ...................................... 113
5.4
5.5
5.6
5.7
5.8
Section 6 ROM.................................................................................................................. 117
6.1
Overview......................................................................................................................... 117
6.1.1 Block Diagram.................................................................................................... 117
H8/3834U PROM Mode................................................................................................. 118
6.2.1 Setting to PROM Mode ..................................................................................... 118
6.2.2 Socket Adapter Pin Arrangement and Memory Map ......................................... 118
H8/3834U Programming ................................................................................................ 121
6.3.1 Writing and Verifying......................................................................................... 121
6.3.2 Programming Precautions................................................................................... 124
H8/3837U PROM Mode................................................................................................. 125
6.4.1 Setting to PROM Mode ...................................................................................... 125
6.4.2 Socket Adapter Pin Arrangement and Memory Map ......................................... 125
H8/3837U Programming ................................................................................................ 128
6.5.1 Writing and Verifying......................................................................................... 128
6.5.2 Programming Precautions................................................................................... 133
Reliability of Programmed Data..................................................................................... 134
6.2
6.3
6.4
6.5
6.6
Section 7 RAM ................................................................................................................. 135
7.1
Overview......................................................................................................................... 135
7.1.1 Block Diagram.................................................................................................... 135
Section 8 I/O Ports........................................................................................................... 137
8.1 Overview ............................................................................................................................ 137
8.2
Port 1 ............................................................................................................................ 139
8.2.1 Overview............................................................................................................. 139
8.2.2 Register Configuration and Description ............................................................. 139
8.2.3 Pin Functions ...................................................................................................... 143
8.2.4 Pin States ............................................................................................................ 145
8.2.5 MOS Input Pull-Up............................................................................................. 145
Port 2 ............................................................................................................................ 146
8.3.1 Overview............................................................................................................. 146
8.3.2 Register Configuration and Description ............................................................. 146
8.3.3 Pin Functions ...................................................................................................... 150
8.3.4 Pin States ............................................................................................................ 150
Port 3 ............................................................................................................................ 151
8.4.1 Overview............................................................................................................. 151
8.4.2 Register Configuration and Description ............................................................. 151
8.4.3 Pin Functions ...................................................................................................... 155
8.4.4 Pin States ............................................................................................................ 157
8.4.5 MOS Input Pull-Up............................................................................................. 157
Port 4 ............................................................................................................................ 158
8.5.1 Overview............................................................................................................. 158
8.5.2 Register Configuration and Description ............................................................. 158
8.5.3 Pin Functions ...................................................................................................... 160
8.5.4 Pin States ............................................................................................................ 161
Port 5 ............................................................................................................................ 162
8.6.1 Overview............................................................................................................. 162
8.6.2 Register Configuration and Description ............................................................. 162
8.6.3 Pin Functions ...................................................................................................... 165
8.6.4 Pin States ............................................................................................................ 166
8.6.5 MOS Input Pull-Up............................................................................................. 166
Port 6 ............................................................................................................................ 167
8.7.1 Overview............................................................................................................. 167
8.7.2 Register Configuration and Description ............................................................. 167
8.7.3 Pin Functions ...................................................................................................... 169
8.7.4 Pin States ............................................................................................................ 169
8.7.5 MOS Input Pull-Up............................................................................................. 170
Port 7 ............................................................................................................................ 171
8.3
8.4
8.5
8.6
8.7
8.8
8.8.1 Overview............................................................................................................. 171
8.8.2 Register Configuration and Description ............................................................. 171
8.8.3 Pin Functions ...................................................................................................... 173
8.8.4 Pin States ............................................................................................................ 173
Port 8 ............................................................................................................................ 174
8.9.1 Overview............................................................................................................. 174
8.9.2 Register Configuration and Description ............................................................. 174
8.9.3 Pin Functions ...................................................................................................... 176
8.9.4 Pin States ............................................................................................................ 176
8.9
8.10 Port 9 ............................................................................................................................ 177
8.10.1 Overview............................................................................................................. 177
8.10.2 Register Configuration and Description ............................................................. 177
8.10.3 Pin Functions ...................................................................................................... 179
8.10.4 Pin States ............................................................................................................ 180
8.11 Port A ............................................................................................................................ 181
8.11.1 Overview............................................................................................................. 181
8.11.2 Register Configuration and Description ............................................................. 181
8.11.3 Pin Functions ...................................................................................................... 183
8.11.4 Pin States ............................................................................................................ 184
8.12 Port B ............................................................................................................................ 185
8.12.1 Overview............................................................................................................. 185
8.12.2 Register Configuration and Description ............................................................. 185
8.13 Port C ............................................................................................................................ 186
8.13.1 Overview............................................................................................................. 186
8.13.2 Register Configuration and Description ............................................................. 186
Section 9 Timers............................................................................................................... 187
9.1
9.2
Overview......................................................................................................................... 187
Timer A........................................................................................................................... 188
9.2.1 Overview............................................................................................................. 188
9.2.2 Register Descriptions.......................................................................................... 190
9.2.3 Timer Operation.................................................................................................. 192
9.2.4 Timer A Operation States ................................................................................... 193
Timer B........................................................................................................................... 194
9.3.1 Overview............................................................................................................. 194
9.3.2 Register Descriptions.......................................................................................... 195
9.3.3 Timer Operation.................................................................................................. 197
9.3.4 Timer B Operation States ................................................................................... 198
Timer C........................................................................................................................... 199
9.4.1 Overview............................................................................................................. 199
9.4.2 Register Descriptions.......................................................................................... 201
9.3
9.4
9.4.3 Timer Operation.................................................................................................. 204
9.4.4 Timer C Operation States ................................................................................... 205
Timer F ........................................................................................................................... 206
9.5.1 Overview............................................................................................................. 206
9.5.2 Register Descriptions.......................................................................................... 208
9.5.3 Interface with the CPU ....................................................................................... 215
9.5.4 Timer Operation.................................................................................................. 219
9.5.5 Application Notes............................................................................................... 222
Timer G........................................................................................................................... 224
9.6.1 Overview............................................................................................................. 224
9.6.2 Register Descriptions.......................................................................................... 226
9.6.3 Noise Canceller Circuit....................................................................................... 230
9.6.4 Timer Operation.................................................................................................. 231
9.6.5 Application Notes............................................................................................... 235
9.6.6 Sample Timer G Application.............................................................................. 239
9.5
9.6
Section 10 Serial Communication Interface............................................................. 241
10.1 Overview......................................................................................................................... 241
10.2 SCI1................................................................................................................................ 242
10.2.1 Overview........................................................................................................... 242
10.2.2 Register Descriptions........................................................................................ 244
10.2.3 Operation .......................................................................................................... 249
10.2.4 Interrupts........................................................................................................... 253
10.2.5 Application Notes............................................................................................. 253
10.3 SCI2................................................................................................................................ 254
10.3.1 Overview........................................................................................................... 254
10.3.2 Register Descriptions........................................................................................ 256
10.3.3 Operation .......................................................................................................... 262
10.3.4 Interrupts........................................................................................................... 269
10.3.5 Application Notes............................................................................................. 269
10.4 SCI3................................................................................................................................ 270
10.4.1 Overview........................................................................................................... 270
10.4.2 Register Descriptions........................................................................................ 273
10.4.3 Operation .......................................................................................................... 291
10.4.4 Operation in Asynchronous Mode.................................................................... 295
10.4.5 Operation in Synchronous Mode...................................................................... 303
10.4.6 Multiprocessor Communication Function........................................................ 310
10.4.7 Interrupts........................................................................................................... 316
10.4.8 Application Notes............................................................................................. 317
Section 11 14-Bit PWM ................................................................................................. 323
11.1 Overview......................................................................................................................... 323
11.1.1 Features............................................................................................................. 323
11.1.2 Block Diagram.................................................................................................. 323
11.1.3 Pin Configuration.............................................................................................. 324
11.1.4 Register Configuration...................................................................................... 324
11.2 Register Descriptions...................................................................................................... 325
11.2.1 PWM Control Register (PWCR) ...................................................................... 325
11.2.2 PWM Data Registers U and L (PWDRU, PWDRL) ........................................ 326
11.3 Operation ........................................................................................................................ 327
Section 12 A/D Converter.............................................................................................. 329
12.1 Overview......................................................................................................................... 329
12.1.1 Features............................................................................................................. 329
12.1.2 Block Diagram.................................................................................................. 329
12.1.3 Pin Configuration.............................................................................................. 330
12.1.4 Register Configuration...................................................................................... 330
12.2 Register Descriptions...................................................................................................... 331
12.2.1 A/D Result Register (ADRR) ........................................................................... 331
12.2.2 A/D Mode Register (AMR).............................................................................. 331
12.2.3 A/D Start Register (ADSR) .............................................................................. 333
12.3 Operation ........................................................................................................................ 334
12.3.1 A/D Conversion Operation ............................................................................... 334
12.3.2 Start of A/D Conversion by External Trigger Input ......................................... 334
12.4 Interrupts......................................................................................................................... 335
12.5 Typical Use ..................................................................................................................... 335
12.6 Application Notes........................................................................................................... 338
Section 13 LCD Controller/Driver.............................................................................. 339
13.1 Overview......................................................................................................................... 339
13.1.1 Features............................................................................................................. 339
13.1.2 Block Diagram.................................................................................................. 340
13.1.3 Pin Configuration.............................................................................................. 341
13.1.4 Register Configuration...................................................................................... 341
13.2 Register Descriptions...................................................................................................... 342
13.2.1 LCD Port Control Register (LPCR) ................................................................. 342
13.2.2 LCD Control Register (LCR) ........................................................................... 344
13.3 Operation ........................................................................................................................ 346
13.3.1 Settings Prior to LCD Display.......................................................................... 346
13.3.2 Relation of LCD RAM to Display.................................................................... 347
13.3.3 Connection to HD66100................................................................................... 348
13.3.4 Operation in Power-Down Modes .................................................................... 356
13.3.5 Boosting the LCD Driver Power Supply .......................................................... 357
Section 14 Electrical Characteristics.......................................................................... 359
14.1 H8/3834U Series Absolute Maximum Ratings .............................................................. 359
14.2 H8/3833U and H8/3834U Electrical Characteristics...................................................... 360
14.2.1 Power Supply Voltage and Operating Range.................................................... 360
14.2.2 DC Characteristics............................................................................................ 362
14.2.3 AC Characteristics ............................................................................................ 367
14.2.4 A/D Converter Characteristics.......................................................................... 370
14.2.5 LCD Characteristics.......................................................................................... 371
14.3 H8/3835U, H8/3836U, and H8/3837U Electrical Characteristics.................................. 372
14.3.1 Power Supply Voltage and Operating Range.................................................... 372
14.3.2 DC Characteristics............................................................................................ 374
14.3.3 AC Characteristics ............................................................................................ 379
14.3.4 A/D Converter Characteristics.......................................................................... 382
14.3.5 LCD Characteristics.......................................................................................... 383
14.4 Operation Timing............................................................................................................ 384
14.5 Output Load Circuit........................................................................................................ 389
Appendix A CPU Instruction Set.................................................................................. 391
A.1
A.2
A.3
Instructions ..................................................................................................................... 391
Operation Code Map....................................................................................................... 399
Number of Execution States ........................................................................................... 401
Appendix B On-Chip Registers..................................................................................... 408
B.1
I/O Registers (1) ............................................................................................................. 408
B.2
I/O Registers (2) ............................................................................................................. 411
Appendix C I/O Port Block Diagrams........................................................................ 454
C.1
C.2
C.3
C.4
C.5
C.6
C.7
C.8
C.9
Schematic Diagram of Port 1.......................................................................................... 454
Schematic Diagram of Port 2.......................................................................................... 459
Schematic Diagram of Port 3.......................................................................................... 462
Schematic Diagram of Port 4.......................................................................................... 468
Schematic Diagram of Port 5.......................................................................................... 471
Schematic Diagram of Port 6.......................................................................................... 472
Schematic Diagram of Port 7.......................................................................................... 473
Schematic Diagram of Port 8.......................................................................................... 474
Schematic Diagram of Port 9.......................................................................................... 475
C.10 Schematic Diagram of Port A......................................................................................... 476
C.11 Schematic Diagram of Port B......................................................................................... 477
C.12 Schematic Diagram of Port C......................................................................................... 477
Appendix D Port States in the Different Processing States .................................. 478
Appendix E Product Code Lineup ............................................................................... 479
Appendix F Package Dimensions ................................................................................ 481
Section 1 Overview
1.1 Overview
The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built
around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip.
Within the H8/300L Series, the H8/3834U Series features an on-chip liquid crystal display (LCD)
controller/driver. Other on-chip peripheral functions include five timers, a 14-bit pulse width
modulator (PWM), three serial communication interface channels, and an analog-to-digital (A/D)
converter. Together these functions make the H8/3834U Series ideally suited for embedded control
of systems requiring an LCD display. The H8/3834U Series, in particular, features low-voltage
A/D converter operation (V = AV = 2.7 V to 5.5 V), enabling these devices to be used in
CC
CC
low-voltage, single power supply systems. On-chip memory is 24 kbytes of ROM and 1 kbyte of
RAM in the H8/3833U, 32 kbytes of ROM and 1 kbyte of RAM in the H8/3834U, 40 kbytes of
ROM and 2 kbytes of RAM in the H8/3835U, 48 kbytes of ROM and 2 kbytes of RAM in the
H8/3836U, and 60 kbytes of ROM and 2 kbytes of RAM in the H8/3837U.
The H8/3834U and H8/3837U both include a ZTAT™ version*, featuring a user-programmable
on-chip PROM.
Table 1-1 summarizes the features of the H8/3834U Series.
Note: * ZTAT is a trademark of Hitachi, Ltd.
Table 1-1 Features
Item
Description
CPU
High-speed H8/300L CPU
• General-register architecture
General registers: Sixteen 8-bit registers (can be used as eight 16-bit
registers)
• Operating speed
— Max. operating speed: 5 MHz
— Add/subtract: 0.4 µs (operating at 5 MHz)
— Multiply/divide: 2.8 µs (operating at 5 MHz)
— Can run on 32.768 kHz subclock
• Instruction set compatible with H8/300 CPU
— Instruction length of 2 bytes or 4 bytes
— Basic arithmetic operations between registers
— MOV instruction for data transfer between memory and registers
1
Table 1-1 Features (cont)
Item
Description
CPU
Typical instructions
• Multiply (8 bits × 8 bits)
• Divide (16 bits ÷ 8 bits)
• Bit accumulator
• Register-indirect designation of bit position
• 13 external interrupt pins: IRQ4 to IRQ0, WKP7 to WKP0
• 20 internal interrupt sources
Interrupts
Clock pulse generators Two on-chip clock pulse generators
• System clock pulse generator: 1 to 10 MHz
• Subclock pulse generator: 32.768 kHz
Power-down modes
Six power-down modes
• Sleep mode
• Standby mode
• Watch mode
• Subsleep mode
• Subactive mode
• Active (medium-speed) mode
Large on-chip memory
Memory
• H8/3833U: 24-kbyte ROM, 1-kbyte RAM
• H8/3834U: 32-kbyte ROM, 1-kbyte RAM
• H8/3835U: 40-kbyte ROM, 2-kbyte RAM
• H8/3836U: 48-kbyte ROM, 2-kbyte RAM
• H8/3837U: 60-kbyte ROM, 2-kbyte RAM
• I/O pins: 71
I/O ports
Timers
• Input pins: 13
Five on-chip timers
• Timer A: 8-bit timer
Count-up timer with selection of eight internal clock signals divided from
the system clock (ø)* and four clock signals divided from the watch clock
(øw)*
2
Table 1-1 Features (cont)
Item
Description
Timers
• Timer B: 8-bit timer
— Count-up timer with selection of seven internal clock signals or event
input from external pin
— Auto-reloading
• Timer C: 8-bit timer
— Count-up/count-down timer with selection of seven internal clock
signals or event input from external pin
— Auto-reloading
• Timer F: 16-bit timer
— Can be used as two independent 8-bit timers.
— Count-up timer with selection of four internal clock signals or event
input from external pin
— Compare-match function with toggle output
• Timer G: 8-bit timer
— Count-up timer with selection of four internal clock signals
— Input capture function with built-in noise canceller circuit
Note: * ø and øw are defined in section 4, Clock Pulse Generators.
Three channels on chip
Serial communication
interface
• SCI1: synchronous serial interface
Choice of 8-bit or 16-bit data transfer
• SCI2: 8-bit synchronous serial interface
Automatic transfer of 32-byte data segments
• SCI3: 8-bit synchronous or asynchronous serial interface
Built-in function for multiprocessor communication
Pulse-division PWM output for reduced ripple
14-bit PWM
• Can be used as a 14-bit D/A converter by connecting to an external
low-pass filter.
A/D converter
• Successive approximations using a resistance ladder
• Resolution: 8 bits
• 12-channel analog input port
• Conversion time: 31/ø or 62/ø per channel
3
Table 1-1 Features (cont)
Item
Specification
LCD controller/driver
Up to 40 segment pins and 4 common pins
• Choice of four duty cycles (static, 1/2, 1/3, 1/4)
• Segments can be expanded externally
• Segment pins can be switched to general-purpose ports in groups of
four
Product lineup
Product Code
Mask ROM
Version
ZTAT
Version
Package
ROM/RAM Size
HD6433833UH
HD6433833UF
HD6433833UX
—
—
—
100-pin QFP (FP-100B)
100-pin QFP (FP-100A)
100-pin TQFP (TFP-100B)
ROM: 24 kbytes
RAM: 1 kbyte
HD6433834UH HD6473834UH 100-pin QFP (FP-100B)
HD6433834UF HD6473834UF 100-pin QFP (FP-100A)
HD6433834UX HD6473834UX 100-pin TQFP (TFP-100B)
ROM: 32 kbytes
RAM: 1 kbyte
HD6433835UH
HD6433835UF
HD6433835UX
HD6433836UH
HD6433836UF
HD6433836UX
—
—
—
—
—
—
100-pin QFP (FP-100B)
100-pin QFP (FP-100A)
100-pin TQFP (TFP-100B)
100-pin QFP (FP-100B)
100-pin QFP (FP-100A)
100-pin TQFP (TFP-100B)
ROM: 40 kbytes
RAM: 2 kbytes
ROM: 48 kbytes
RAM: 2 kbytes
HD6433837UH HD6473837UH 100-pin QFP (FP-100B)
HD6433837UF HD6473837UF 100-pin QFP (FP-100A)
HD6433837UX HD6473837UX 100-pin TQFP (TFP-100B)
ROM: 60 kbytes
RAM: 2 kbytes
4
1.2 Internal Block Diagram
Figure 1-1 shows a block diagram of the H8/3834U Series.
P10/TMOW
LCD
driver
power
supply
V1
V2
V3
P11/TMOFL
P12/TMOFH
P13/TMIG
CPU
H8/300L
Port 1
P14/PWM
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
Data bus (lower)
P15/IRQ1/TMIB
P16/IRQ2/TMIC
P17/IRQ3/TMIF
Port A
P97/SEG40/CL1
P96/SEG39/CL2
P95/SEG38/DO
P94/SEG37/M
P93/SEG36
P20/IRQ4/ADTRG
ROM
RAM
P21/UD
P22
P23
Port 2
Port 9
P24
P92/SEG35
P25
LCD controller
SCI1
Timer A
Timer B
Timer C
P91/SEG34
P26
P90/SEG33
P27
P30/SCK1
P31/SI1
P87/SEG32
P86/SEG31
P85/SEG30
P84/SEG29
P83/SEG28
P82/SEG27
P81/SEG26
P80/SEG25
SCI2
P32/SO1
P33/SCK2
P34/SI2
Port 3
Port 4
Port 5
Port 8
P35/SO2
P36/STRB
P37/CS
Timer F
Timer G
SCI3
P40/SCK3
P41/RXD
P42/TXD
P43/IRQ0
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
14-bit PWM
Port 7
A/D converter
P50/WKP0 /SEG1
P51/WKP1 /SEG2
P52/WKP2 /SEG3
P53/WKP3 /SEG4
P54/WKP4 /SEG5
P55/WKP5 /SEG6
P56/WKP6 /SEG7
P57/WKP7 /SEG8
Port B
Port C
P67/SEG16
P66/SEG15
P65/SEG14
P64/SEG13
P63/SEG12
P62/SEG11
P61/SEG10
P60/SEG9
Port 6
Figure 1-1 Block Diagram
5
1.3 Pin Arrangement and Functions
1.3.1 Pin Arrangement
The H8/3834U Series pin arrangement is shown in figures 1-2 and 1-3.
PC3/AN11
AVSS
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P97/SEG40/CL1
P96/SEG39/CL2
P95/SEG38/D0
P94/SEG37/M
P93/SEG36
P92/SEG35
P91/SEG34
P90/SEG33
P87/SEG32
P86/SEG31
P85/SEG30
P84/SEG29
P83/SEG28
P82/SEG27
P81/SEG26
P80/SEG25
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
P67/SEG16
2
TEST
3
X2
4
X1
5
VSS
6
OSC1
7
OSC2
8
RES
9
MD0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P20/IRQ4/ADTRG
P21/UD
P22
P23
P24
P25
P26
P27
P30/SCK1
P31/SI1
P32/SO1
P33/SCK2
P34/SI2
P35/SO2
P36/STRB
Figure 1-2 Pin Arrangement (FP-100B, TFP-100B: Top View)
6
PC0 /AN8
PC1 /AN9
PC2 /AN10
PC3 /AN11
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P10 /TMOW
VCC
2
3
P97 /SEG40 /CL1
P96 /SEG39 /CL2
P95 /SEG38 /DO
P94 /SEG37 /M
P93 /SEG36
P92 /SEG35
P91 /SEG34
P90 /SEG33
P87 /SEG32
P86 /SEG31
P85 /SEG30
P84 /SEG29
P83 /SEG28
P82 /SEG27
P81 /SEG26
P80 /SEG25
P77 /SEG24
P76 /SEG23
P75 /SEG22
P74 /SEG21
P73 /SEG20
P72 /SEG19
P71 /SEG18
P70 /SEG17
P67 /SEG16
P66 /SEG15
P65 /SEG14
P64 /SEG13
4
AV
5
SS
TEST
X2
6
7
X1
8
V
9
SS
OSC1
OSC2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
RES
MD0
P20 /IRQ4 /ADTRG
P21 /UD
P22
P23
P24
P25
P26
P27
P30 /SCK1
P31 /SI1
P32 /SO1
P33 /SCK2
P34 /SI2
P35 /SO2
P36 /STRB
P37 /CS
V
SS
Figure 1-3 Pin Arrangement (FP-100A: Top View)
7
1.3.2 Pin Functions
Table 1-2 outlines the pin functions of the H8/3834U Series.
Table 1-2 Pin Functions
Pin No.
Type
Symbol
FP-100B FP-100A
I/O
Name and Functions
Power
source pins
VCC
31, 76
6, 27
89
34, 79
9, 30
92
Input
Power supply: All VCC pins should
be connected to the system power
supply (+5 V)
VSS
Input
Input
Ground: All VSS pins should be
connected to the system power supply
(0 V)
AVCC
Analog power supply: This is the
power supply pin for the A/D converter.
When the A/D converter is not used,
connect this pin to the system power
supply (+5 V).
AVSS
2
5
Input
Input
Analog ground: This is the A/D
converter ground pin. It should be
connected to the system power supply
(0 V).
V1,
V2,
V3
30,
29,
28
33,
32,
31
LCD power supply: These are power
supply pins for the LCD controller/
driver. A built-in resistor divider is
provided for the power supply, so
these pins are normally left open.
Power supply conditions are
VCC ≥ V1 ≥ V2 ≥ V3 ≥ VSS.
Clock pins
OSC1
OSC2
7
8
10
Input
System clock: This pin connects to a
crystal or ceramic oscillator, or can be
used to input an external clock.
See section 4, Clock Pulse
11
Output
Generators, for a typical connection
diagram.
X1
X2
5
4
8
7
Input
Subclock: This pin connects to a
32.768-kHz crystal oscillator.
See section 4, Clock Pulse
Generators, for a typical connection
diagram.
Output
8
Table 1-2 Pin Functions (cont)
Pin No.
FP-100B FP-100A
Type
Symbol
I/O
Name and Functions
System
control
RES
9
12
13
6
Input
Reset: When this pin is driven low,
the chip is reset
MD0
10
3
Input
Input
Mode: This pin controls system
clock oscillation in the reset state
TEST
Test: This is a test pin, not for use in
application systems. It should be
connected to VSS
.
Interrupt
pins
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
88
82
83
84
11
91
85
86
87
14
Input
Input
External interrupt request 0 to 4:
These are input pins for external
interrupts for which there is a choice
between rising and falling edge
sensing
WKP7 to
WKP0
43 to
36
46 to
39
Wakeup interrupt request 0 to 7:
These are input pins for external
interrupts that are detected at the
falling edge
Timer pins TMOW
77
82
83
12
80
85
86
15
Output Clock output: This is an output pin
for waveforms generated by the timer
A output circuit
TMIB
TMIC
UD
Input
Input
Input
Timer B event counter input: This is
an event input pin for input to the
timer B counter
Timer C event counter input: This is
an event input pin for input to the
timer C counter
Timer C up/down select: This pin
selects whether the timer C counter is
used for up- or down-counting. At
high level it selects up-counting, and
at low level down-counting.
TMIF
84
87
Input
Timer F event counter input: This is
an event input pin for input to the
timer F counter
9
Table 1-2 Pin Functions (cont)
Pin No.
FP-100B FP-100A
Type
Symbol
I/O
Name and Functions
Timer pins TMOFL
78
79
80
81
81
82
83
84
Output Timer FL output: This is an output
pin for waveforms generated by the
timer FL output compare function
TMOFH
Output Timer FH output: This is an output
pin for waveforms generated by the
timer FH output compare function
TMIG
Input
Timer G capture input: This is an
input pin for the timer G input capture
function
14-bit
PWM
Output 14-bit PWM output: This is an output
pin for waveforms generated by the
14-bit PWM
PWM pin
I/O ports
PB7 to
PB0
97 to
90
100 to
93
Input
Input
Input
I/O
Port B: This is an 8-bit input port
PC3 to
PC0
1, 100 to 4 to
98
Port C: This is a 4-bit input port
1
P43
88
91
Port 4 (bit 3): This is a 1-bit input
port
P42 to
P40
87 to
85
90 to
88
Port 4 (bits 2 to 0): This is a 3-bit I/O
port. Input or output can be
designated for each bit by means of
port control register 4 (PCR4).
PA3 to
PA0
32 to
35
35 to
38
I/O
I/O
I/O
I/O
Port A: This is a 4-bit I/O port. Input
or output can be designated for each
bit by means of port control register A
(PCRA).
P17 to
P10
84 to
77
87 to
80
Port 1: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 1
(PCR1).
P27 to
P20
18 to
11
21 to
14
Port 2: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 2
(PCR2).
P37 to
P30
26 to
19
29 to
22
Port 3: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 3
(PCR3).
10
Table 1-2 Pin Functions (cont)
Pin No.
FP-100B FP-100A
Type
Symbol
I/O
Name and Functions
I/O ports
P57 to
P50
43 to
36
46 to
39
I/O
Port 5: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 5
(PCR5).
P67 to
P60
51 to
44
54 to
47
I/O
Port 6: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 6
(PCR6).
P77 to
P70
59 to
52
62 to
55
I/O
Port 7: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 7
(PCR7).
P87 to
P80
67 to
60
70 to
63
I/O
Port 8: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 8
(PCR8).
P97 to
P90
75 to
68
78 to
71
I/O
Port 9: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register 9
(PCR9).
Serial
communi-
cation
interface
(SCI)
SI1
20
21
19
23
24
22
26
23
24
22
26
27
25
29
Input
SCI1 receive data input:
This is the SCI1 data input pin
SO1
SCK1
SI2
Output SCI1 send data output:
This is the SCI1 data output pin
I/O
SCI1 clock I/O :
This is the SCI1 clock I/O pin
Input
SCI2 receive data input:
This is the SCI2 data input pin
SO2
SCK2
CS
Output SCI2 send data output:
This is the SCI2 data output pin
I/O
SCI2 clock I/O :
This is the SCI2 clock I/O pin
Input
SCI2 chip select input:
This pin controls the start of SCI2
transfers
STRB
25
28
Output SCI2 strobe output: This pin outputs
a strobe pulse each time a byte of
data is transferred
11
Table 1-2 Pin Functions (cont)
Pin No.
FP-100B FP-100A
Type
Symbol
I/O
Name and Functions
Serial
communi-
cation
interface
(SCI)
RXD
86
87
85
89
90
88
Input
SCI3 receive data input:
This is the SCI3 data input pin
TXD
Output SCI3 send data output:
This is the SCI3 data output pin
SCK3
I/O
SCI3 clock I/O :
This is the SCI3 clock I/O pin
A/D
converter
AN11 to
AN0
1, 100 to 4 to 1
Input
Analog input channels 0 to 11:
These are analog data input channels
to the A/D converter
90
100 to
93
ADTRG
11
14
Input
A/D converter trigger input:
This is the external trigger input pin to
the A/D converter
LCD
controller/
driver
COM4 to
COM1
35 to
32
38 to
35
Output LCD common output:
These are LCD common output pins
SEG40 to 75 to
SEG1
78 to
39
Output LCD segment output:
These are LCD segment output pins
36
CL1
75
78
Output LCD latch clock:
This is the display data latch clock
output pin for external segment
expansion
CL2
74
77
Output LCD shift clock:
This is the display data shift clock
output pin for external segment
expansion
DO
M
73
72
76
75
Output LCD serial data output:
This is the serial display data output
pin for external segment expansion
Output LCD alternating signal output:
This is the LCD alternating signal
output pin for external segment
expansion
12
Section 2 CPU
2.1 Overview
The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit
registers. Its concise, optimized instruction set is designed for high-speed operation.
2.1.1 Features
Features of the H8/300L CPU are listed below.
•
General-register architecture
Sixteen 8-bit general registers, also usable as eight 16-bit general registers
•
Instruction set with 55 basic instructions, including:
— Multiply and divide instructions
— Powerful bit-manipulation instructions
•
Eight addressing modes
— Register direct
— Register indirect
— Register indirect with displacement
— Register indirect with post-increment or pre-decrement
— Absolute address
— Immediate
— Program-counter relative
— Memory indirect
•
•
64-kbyte address space
High-speed operation
— All frequently used instructions are executed in two to four states
— High-speed arithmetic and logic operations
8- or 16-bit register-register add or subtract: 0.4 µs*
8 × 8-bit multiply:
16 ÷ 8-bit divide:
2.8 µs*
2.8 µs*
•
Low-power operation modes
SLEEP instruction for transfer to low-power operation
Note: * These values are at ø = 5 MHz.
13
2.1.2 Address Space
The H8/300L CPU supports an address space of up to 64 kbytes for storing program code and
data.
See 2.8, Memory Map, for details of the memory map.
2.1.3 Register Configuration
Figure 2-1 shows the register structure of the H8/300L CPU. There are two groups of registers: the
general registers and control registers.
General registers (Rn)
7
0 7
0
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
SP: Stack Pointer
(SP)
Control registers (CR)
15
0
PC
7 6 5 4 3 2 1 0
CCR I U H U N Z V C
PC: Program Counter
CCR: Condition Code Register
Carry flag
Overflow flag
Zero flag
Negative flag
Half-carry flag
Interrupt mask bit
User bit
User bit
Figure 2-1 CPU Registers
14
2.2 Register Descriptions
2.2.1 General Registers
All the general registers can be used as both data registers and address registers.
When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes
(R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers.
When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7).
R7 also functions as the stack pointer (SP), used implicitly by hardware in exception processing
and subroutine calls. When it functions as the stack pointer, as indicated in figure 2-2, SP (R7)
points to the top of the stack.
Lower address side [H'0000]
Unused area
SP
(R7)
Stack area
Upper address side [H'FFFF]
Figure 2-2 Stack Pointer
2.2.2 Control Registers
The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code
register (CCR).
Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU
will execute. All instructions are fetched 16 bits (1 word) at a time, so the least significant bit of
the PC is ignored (always regarded as 0).
15
Condition Code Register (CCR): This 8-bit register contains internal status information,
including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and
carry (C) flags. These bits can be read and written by software (using the LDC, STC, ANDC,
ORC, and XORC instructions). The N, Z, V, and C flags are used as branching conditions for
conditional branching (Bcc) instructions.
Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1
automatically at the start of exception handling. The interrupt mask bit may be read and written
by software. For further details, see section 3.3, Interrupts.
Bit 6—User Bit (U): Can be used freely by the user.
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0
otherwise.
The H flag is used implicitly by the DAA and DAS instructions.
When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 11, and is cleared to 0 otherwise.
Bit 4—User Bit (U): Can be used freely by the user.
Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an
instruction.
Bit 2—Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero
result.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.
Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
•
•
•
Add instructions, to indicate a carry
Subtract instructions, to indicate a borrow
Shift and rotate instructions, to store the value shifted out of the end bit
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave some or all of the flag bits unchanged.
Refer to the H8/300L Series Programming Manual for the action of each instruction on the flag
bits.
16
2.2.3 Initial Register Values
When the CPU is reset, the program counter (PC) is initialized to the value stored at address
H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general
registers are not initialized. In particular, the stack pointer (R7) is not initialized. To prevent
program crashes the stack pointer should be initialized by software, by the first instruction
executed after a reset.
2.3 Data Formats
The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word)
data.
•
Bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand
(n = 0, 1, 2, ..., 7).
•
•
All arithmetic and logic instructions except ADDS and SUBS can operate on byte data.
The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions operate on word data.
•
The DAA and DAS instructions perform decimal arithmetic adjustments on byte data in
packed BCD form. Each nibble of the byte is treated as a decimal digit.
17
2.3.1 Data Formats in General Registers
Data of all the sizes above can be stored in general registers as shown in figure 2-3.
Data Type Register No.
Data Format
7
0
1-bit data
RnH
RnL
7
6
5
4
3
2
1
0
don’t care
7
0
1-bit data
don’t care
7
6
5
4
3
2
1
0
7
0
Byte data
RnH MSB
LSB
don’t care
7
0
Byte data
RnL
don’t care
MSB
LSB
15
0
Word data
4-bit BCD data
Rn
MSB
LSB
7
4
3
0
Upper digit
Lower digit
RnH
RnL
don’t care
7
4
3
0
Upper digit
Lower digit
4-bit BCD data
Notation:
don’t care
RnH: Upper byte of general register
RnL: Lower byte of general register
MSB: Most significant bit
LSB: Least significant bit
Figure 2-3 Register Data Formats
18
2.3.2 Memory Data Formats
Figure 2-4 indicates the data formats in memory. For access by the H8/300L CPU, word data
stored in memory must always begin at an even address. In word access the least significant bit of
the address is regarded as 0. If an odd address is specified, the access is performed at the
preceding even address. This rule affects the MOV.W instruction, and also applies to instruction
fetching.
Data Type
Address
Data Format
7
0
1-bit data
Byte data
Address n
Address n
7
6
5
4
3
2
1
0
MSB
MSB
LSB
Upper 8 bits
Lower 8 bits
Even address
Odd address
Word data
Byte data (CCR) on stack
Word data on stack
LSB
MSB
MSB
CCR
LSB
LSB
Even address
Odd address
CCR*
MSB
Even address
Odd address
LSB
CCR: Condition code register
Note: * Ignored on return
Figure 2-4 Memory Data Formats
When the stack is accessed using R7 as an address register, word access should always be
performed. When the CCR is pushed on the stack, two identical copies of the CCR are pushed to
make a complete word. When they are restored, the lower byte is ignored.
19
2.4 Addressing Modes
2.4.1 Addressing Modes
The H8/300L CPU supports the eight addressing modes listed in table 2-1. Each instruction uses a
subset of these addressing modes.
Table 2-1 Addressing Modes
No.
1
Address Modes
Symbol
Rn
Register direct
2
Register indirect
@Rn
3
Register indirect with displacement
@(d:16, Rn)
4
Register indirect with post-increment
Register indirect with pre-decrement
@Rn+
@–Rn
5
6
7
8
Absolute address
Immediate
@aa:8 or @aa:16
#xx:8 or #xx:16
@(d:8, PC)
Program-counter relative
Memory indirect
@@aa:8
1. Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general
register containing the operand.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
2. Register Indirect—@Rn: The register field of the instruction specifies a 16-bit general
register containing the address of the operand in memory.
3. Register Indirect with Displacement—@(d:16, Rn): The instruction has a second word
(bytes 3 and 4) containing a displacement which is added to the contents of the specified
general register to obtain the operand address in memory.
This mode is used only in MOV instructions. For the MOV.W instruction, the resulting
address must be even.
20
4. Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn:
•
Register indirect with post-increment—@Rn+
The @Rn+ mode is used with MOV instructions that load registers from memory.
The register field of the instruction specifies a 16-bit general register containing the
address of the operand. After the operand is accessed, the register is incremented by 1 for
MOV.B or 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register
must be even.
•
Register indirect with pre-decrement—@–Rn
The @–Rn mode is used with MOV instructions that store register contents to memory.
The register field of the instruction specifies a 16-bit general register which is
decremented by 1 or 2 to obtain the address of the operand in memory. The register retains
the decremented value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For
MOV.W, the original contents of the register must be even.
5. Absolute Address—@aa:8 or @aa:16: The instruction specifies the absolute address of the
operand in memory.
The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and
bit manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP,
and JSR instructions can use 16-bit absolute addresses.
For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range
is H'FF00 to H'FFFF (65280 to 65535).
6. Immediate—#xx:8 or #xx:16: The instruction contains an 8-bit operand (#xx:8) in its
second byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. Only MOV.W
instructions can contain 16-bit immediate values.
The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data.
Some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte
of the instruction, specifying a bit number.
7. Program-Counter Relative—@(d:8, PC): This mode is used in the Bcc and BSR
instructions. An 8-bit displacement in byte 2 of the instruction code is sign-extended to 16
bits and added to the program counter contents to generate a branch destination address. The
possible branching range is –126 to +128 bytes (–63 to +64 words) from the current address.
The displacement should be an even number.
21
8. Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
second byte of the instruction code specifies an 8-bit absolute address. The word located at
this address contains the branch destination address.
The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is
from H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the
address area is also used as a vector area. See 3.3, Interrupts, for details on the vector area.
If an odd address is specified as a branch destination or as the operand address of a MOV.W
instruction, the least significant bit is regarded as 0, causing word access to be performed at
the address preceding the specified address. See 2.3.2, Memory Data Formats, for further
information.
2.4.2 Effective Address Calculation
Table 2-2 shows how effective addresses are calculated in each of the addressing modes.
Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX,
CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6).
Data transfer instructions can use all addressing modes except program-counter relative (7) and
memory indirect (8).
Bit manipulation instructions use register direct (1), register indirect (2), or absolute addressing (5)
to specify a byte operand, and 3-bit immediate addressing (6) to specify a bit position in that byte.
The BSET, BCLR, BNOT, and BTST instructions can also use register direct addressing (1) to
specify the bit position.
22
23
24
25
2.5 Instruction Set
The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2-3.
Table 2-3 Instruction Set
Function
Instructions
Number
Data transfer
MOV, PUSH*1, POP*1
1
Arithmetic operations
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS,
SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG
14
Logic operations
Shift
AND, OR, XOR, NOT
4
8
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR,
ROTXL, ROTXR
Bit manipulation
BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR,
BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST
14
Branch
Bcc*2, JMP, BSR, JSR, RTS
RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP
EEPMOV
5
System control
Block data transfer
8
1
Total: 55
Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @–SP.
POP Rn is equivalent to MOV.W @SP+, Rn.
2. Bcc is a conditional branch instruction in which cc represents a condition code.
The following sections give a concise summary of the instructions in each category, and indicate
the bit patterns of their object code. The notation used is defined next.
26
Notation
Rd
General register (destination)
General register (source)
General register
Rs
Rn
(EAd), <EAd>
Destination operand
Source operand
(EAs), <EAs>
CCR
N
Condition code register
N (negative) flag of CCR
Z (zero) flag of CCR
V (overflow) flag of CCR
C (carry) flag of CCR
Program counter
Stack pointer
Z
V
C
PC
SP
#IMM
disp
+
Immediate data
Displacement
Addition
–
Subtraction
×
Multiplication
÷
Division
AND logical
OR logical
Exclusive OR logical
Move
→
~
Logical negation (logical complement)
3-bit length
:3
:8
8-bit length
:16
16-bit length
( ), < >
Contents of operand indicated by effective address
27
2.5.1 Data Transfer Instructions
Table 2-4 describes the data transfer instructions. Figure 2-5 shows their object code formats.
Table 2-4 Data Transfer Instructions
Instruction
Size*
Function
MOV
B/W
(EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general
register and memory, or moves immediate data to a general register.
The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:16, @–Rn, and @Rn+
addressing modes are available for byte or word data. The @aa:8
addressing mode is available for byte data only.
The @–R7 and @R7+ modes require word operands. Do not specify
byte size for these two modes.
POP
W
W
@SP+ → Rn
Pops a 16-bit general register from the stack. Equivalent to MOV.W
@SP+, Rn.
PUSH
Rn → @–SP
Pushes a 16-bit general register onto the stack. Equivalent to MOV.W
Rn, @–SP.
Notes: * Size: Operand size
B:
Byte
W:
Word
Certain precautions are required in data access. See 2.9.1, Notes on Data Access, for details.
28
15
15
15
8
8
8
7
7
7
0
0
0
MOV
op
rm
rn
rn
rn
Rm→Rn
op
rm
@Rm←→Rn
op
op
rm
rm
@(d:16, Rm)←→Rn
disp
15
15
15
8
8
8
7
7
7
0
0
0
@Rm+→Rn, or
Rn →@–Rm
rn
rn
op
rn
abs
@aa:8←→Rn
@aa:16←→Rn
op
abs
15
15
8
7
0
0
op
rn
IMM
#xx:8→Rn
8
7
op
rn
#xx:16→Rn
IMM
15
8
7
0
PUSH, POP
@SP+→Rn, or
Rn→@–SP
op
1
1
1
rn
Notation:
op: Operation field
rm, rn: Register field
disp: Displacement
abs:
Absolute address
IMM: Immediate data
Figure 2-5 Data Transfer Instruction Codes
29
2.5.2 Arithmetic Operations
Table 2-5 describes the arithmetic instructions.
Table 2-5 Arithmetic Instructions
Instruction
Size*
Function
ADD
SUB
B/W
Rd ± Rs → Rd, Rd + #IMM → Rd
Performs addition or subtraction on data in two general registers, or
addition on immediate data and data in a general register. Immediate
data cannot be subtracted from data in a general register. Word
data can be added or subtracted only when both words are in general
registers.
ADDX
SUBX
B
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry or borrow on byte data in
two general registers, or addition or subtraction on immediate data and
data in a general register.
INC
B
Rd ± 1 → Rd
DEC
Increments or decrements a general register
ADDS
SUBS
W
Rd ± 1 → Rd, Rd ± 2 → Rd
Adds or subtracts immediate data to or from data in a general register.
The immediate data must be 1 or 2.
DAA
DAS
B
Rd decimal adjust → Rd
Decimal-adjusts (adjusts to packed BCD) an addition or subtraction
result in a general register by referring to the CCR
MULXU
DIVXU
CMP
B
Rd × Rs → Rd
Performs 8-bit × 8-bit unsigned multiplication on data in two general
registers, providing a 16-bit result
B
Rd ÷ Rs → Rd
Performs 16-bit ÷ 8-bit unsigned division on data in two general
registers, providing an 8-bit quotient and 8-bit remainder
B/W
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immediate data, and the result is stored in the CCR.
Word data can be compared only between two general registers.
NEG
B
0 – Rd → Rd
Obtains the two’s complement (arithmetic complement) of data in a
general register
Notes: * Size: Operand size
B:
Byte
W:
Word
30
2.5.3 Logic Operations
Table 2-6 describes the four instructions that perform logic operations.
Table 2-6 Logic Operation Instructions
Instruction
Size*
Function
AND
B
Rd Rs → Rd, Rd #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data
OR
B
B
B
Rd Rs → Rd, Rd #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data
XOR
NOT
Rd Rs → Rd, Rd #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data
~ Rd → Rd
Obtains the one’s complement (logical complement) of general register
contents
Notes: * Size: Operand size
B: Byte
2.5.4 Shift Operations
Table 2-7 describes the eight shift instructions.
Table 2-7 Shift Instructions
Instruction
Size*
Function
SHAL
SHAR
B
Rd shift → Rd
Performs an arithmetic shift operation on general register contents
Rd shift → Rd
SHLL
SHLR
B
B
B
Performs a logical shift operation on general register contents
Rd rotate → Rd
ROTL
ROTR
Rotates general register contents
Rd rotate through carry → Rd
ROTXL
ROTXR
Rotates general register contents through the C (carry) bit
Notes: * Size: Operand size
B: Byte
31
Figure 2-6 shows the instruction code format of arithmetic, logic, and shift instructions.
15
15
15
15
15
15
15
8
8
8
8
8
8
8
7
7
7
7
7
7
7
0
0
0
0
0
0
0
ADD, SUB, CMP,
ADDX, SUBX (Rm)
op
op
op
rm
rm
rm
rn
rn
rn
ADDS, SUBS, INC, DEC,
DAA, DAS, NEG, NOT
op
MULXU, DIVXU
ADD, ADDX, SUBX,
CMP (#XX:8)
op
op
rn
IMM
IMM
rn
rn
AND, OR, XOR (Rm)
AND, OR, XOR (#xx:8)
rn
SHAL, SHAR, SHLL, SHLR,
ROTL, ROTR, ROTXL, ROTXR
op
Notation:
op: Operation field
rm, rn: Register field
IMM: Immediate data
Figure 2-6 Arithmetic, Logic, and Shift Instruction Codes
32
2.5.5 Bit Manipulations
Table 2-8 describes the bit-manipulation instructions. Figure 2-7 shows their object code formats.
Table 2-8 Bit-Manipulation Instructions
Instruction
Size*
Function
BSET
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BCLR
BNOT
BTST
B
B
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory to 0. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
~ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory. The bit number
is specified by 3-bit immediate data or the lower three bits of a general
register.
~ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory and sets or clears
the Z flag accordingly. The bit number is specified by 3-bit immediate
data or the lower three bits of a general register.
BAND
B
B
C
(<bit-No.> of <EAd>) → C
ANDs the C flag with a specified bit in a general register or memory,
and stores the result in the C flag.
BIAND
C
[~ (<bit-No.> of <EAd>)] → C
ANDs the C flag with the inverse of a specified bit in a general register
or memory, and stores the result in the C flag.
The bit number is specified by 3-bit immediate data.
BOR
B
B
C
(<bit-No.> of <EAd>) → C
ORs the C flag with a specified bit in a general register or memory, and
stores the result in the C flag.
BIOR
C
[~ (<bit-No.> of <EAd>)] → C
ORs the C flag with the inverse of a specified bit in a general register or
memory, and stores the result in the C flag.
The bit number is specified by 3-bit immediate data.
Notes: * Size: Operand size
B: Byte
33
Table 2-8 Bit-Manipulation Instructions (cont)
Instruction
Size*
Function
BXOR
B
C
(<bit-No.> of <EAd>) → C
XORs the C flag with a specified bit in a general register or memory,
and stores the result in the C flag.
BIXOR
B
C
[~(<bit-No.> of <EAd>)] → C
XORs the C flag with the inverse of a specified bit in a general register
or memory, and stores the result in the C flag.
The bit number is specified by 3-bit immediate data.
(<bit-No.> of <EAd>) → C
BLD
B
B
Copies a specified bit in a general register or memory to the C flag.
~ (<bit-No.> of <EAd>) → C
BILD
Copies the inverse of a specified bit in a general register or memory to
the C flag.
The bit number is specified by 3-bit immediate data.
C → (<bit-No.> of <EAd>)
BST
B
B
Copies the C flag to a specified bit in a general register or memory.
~ C → (<bit-No.> of <EAd>)
BIST
Copies the inverse of the C flag to a specified bit in a general register or
memory.
The bit number is specified by 3-bit immediate data.
Notes: * Size: Operand size
B: Byte
Certain precautions are required in bit manipulation. See 2.9.2, Notes on Bit Manipulation, for
details.
34
BSET, BCLR, BNOT, BTST
15
15
15
8
8
8
7
7
7
0
0
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
op
IMM
rn
rn
Operand: register direct (Rn)
Bit No.: register direct (Rm)
op
rm
0
op
op
rn
IMM
0
0
0
0
0
0
0
Operand: register indirect (@Rn)
Bit No.: immediate (#xx:3)
0
15
15
15
8
8
8
7
7
7
0
op
op
rn
0
0
0
0
0
0
0
Operand: register indirect (@Rn)
Bit No.: register direct (Rm)
rm
0
0
op
abs
Operand: absolute (@aa:8)
Bit No.: immediate (#xx:3)
op
IMM
0
0
0
0
0
0
0
op
op
abs
Operand: absolute (@aa:8)
Bit No.: register direct (Rm)
rm
0
0
BAND, BOR, BXOR, BLD, BST
15
15
8
8
7
7
0
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
op
IMM
rn
0
op
op
rn
IMM
0
0
0
0
0
0
0
Operand: register indirect (@Rn)
Bit No.: immediate (#xx:3)
0
15
8
7
0
op
op
abs
Operand: absolute (@aa:8)
Bit No.: immediate (#xx:3)
IMM
0
0
0
0
Notation:
op:
rm, rn: Register field
abs: Absolute address
IMM: Immediate data
Operation field
Figure 2-7 Bit Manipulation Instruction Codes
35
BIAND, BIOR, BIXOR, BILD, BIST
15
15
8
8
7
7
0
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
op
IMM
rn
0
op
op
rn
0
0
0
0
0
0
0
Operand: register indirect (@Rn)
Bit No.: immediate (#xx:3)
IMM
0
15
8
7
0
op
op
abs
Operand: absolute (@aa:8)
Bit No.: immediate (#xx:3)
IMM
0
0
0
0
Notation:
op:
rm, rn: Register field
abs: Absolute address
IMM: Immediate data
Operation field
Figure 2-7 Bit Manipulation Instruction Codes (cont)
36
2.5.6 Branching Instructions
Table 2-9 describes the branching instructions. Figure 2-8 shows their object code formats.
Table 2-9 Branching Instructions
Instruction
Size
Function
Bcc
—
Branches to the designated address if condition cc is true. The branching
conditions are given below.
Mnemonic
BRA (BT)
BRN (BF)
BHI
Description
Always (true)
Never (false)
High
Condition
Always
Never
C
C
Z = 0
Z = 1
BLS
Low or same
Carry clear (high or same)
Carry set (low)
Not equal
BCC (BHS)
BCS (BLO)
BNE
C = 0
C = 1
Z = 0
Z = 1
V = 0
V = 1
N = 0
N = 1
BEQ
Equal
BVC
Overflow clear
Overflow set
Plus
BVS
BPL
BMI
Minus
BGE
Greater or equal
Less than
N
N
Z
Z
V = 0
BLT
V = 1
BGT
Greater than
Less or equal
(N V) = 0
(N V) = 1
BLE
JMP
BSR
—
—
Branches unconditionally to a specified address
Branches to a subroutine at a specified displacement from the current
address
JSR
RTS
—
—
Branches to a subroutine at a specified address
Returns from a subroutine
37
15
15
15
8
8
8
7
7
7
0
op
cc
disp
Bcc
0
op
rm
0
0
0
0
JMP (@Rm)
0
op
abs
JMP (@aa:16)
15
15
15
15
8
7
7
7
7
0
0
op
abs
JMP (@@aa:8)
BSR
8
8
8
op
disp
0
op
rm
0
0
0
0
JSR (@Rm)
0
op
abs
JSR (@aa:16)
15
15
8
7
0
0
op
abs
JSR (@@aa:8)
RTS
8
7
op
Notation:
op: Operation field
cc: Condition field
rm: Register field
disp: Displacement
abs: Absolute address
Figure 2-8 Branching Instruction Codes
38
2.5.7 System Control Instructions
Table 2-10 describes the system control instructions. Figure 2-9 shows their object code formats.
Table 2-10 System Control Instructions
Instruction
RTE
Size*
—
Function
Returns from an exception-handling routine
SLEEP
—
Causes a transition from active mode to a power-down mode. See
section 5, Power-Down Modes, for details
LDC
B
Rs → CCR, #IMM → CCR
Moves immediate data or general register contents to the condition code
register
STC
B
B
B
B
—
CCR → Rd
Copies the condition code register to a specified general register
CCR #IMM → CCR
ANDC
ORC
XORC
NOP
Logically ANDs the condition code register with immediate data
CCR #IMM → CCR
Logically ORs the condition code register with immediate data
CCR #IMM → CCR
Logically exclusive-ORs the condition code register with immediate data
PC + 2 → PC
Only increments the program counter
Notes: * Size: Operand size
B: Byte
39
15
15
15
8
8
8
7
7
7
0
0
0
op
RTE, SLEEP, NOP
LDC, STC (Rn)
op
rn
ANDC, ORC,
XORC, LDC (#xx:8)
op
IMM
Notation:
op: Operation field
rn: Register field
IMM: Immediate data
Figure 2-9 System Control Instruction Codes
2.5.8 Block Data Transfer Instruction
Table 2-11 describes the block data transfer instruction. Figure 2-10 shows its object code format.
Table 2-11 Block Data Transfer Instruction
Instruction
Size
Function
If R4L ≠ 0 then
repeat
EEPMOV
—
@R5+ → @R6+
R4L – 1 → R4L
R4L = 0
until
else next;
Moves a data block according to parameters set in general registers R4L,
R5, and R6.
R4L: Size of block (bytes)
R5: Starting source address
R6: Starting destination address
Execution of the next instruction starts as soon as the block transfer is
completed.
Certain precautions are required in using the EEPMOV instruction. See 2.9.3, Notes on Use of the
EEPMOV Instruction, for details.
40
15
8
7
0
op
op
Notation:
op: Operation field
Figure 2-10 Block Data Transfer Instruction Code
41
2.6 Basic Operational Timing
CPU operation is synchronized by a system clock (ø) or a subclock (ø
). For details on these
SUB
clock signals see section 4, Clock Pulse Generators. The period from a rising edge of ø or ø
to
SUB
the next rising edge is called one state. A bus cycle consists of two states or three states. The
cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
2.6.1 Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing
access in byte or word size. Figure 2-11 shows the on-chip memory access cycle.
Bus cycle
T1 state
T2 state
ø or øSUB
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2-11 On-Chip Memory Access Cycle
42
2.6.2 Access to On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits,
so access is by byte size only. This means that for accessing word data, two instructions must be
used. Figures 2-12 and 2-13 show the on-chip peripheral module access cycle.
Two-state access to on-chip peripheral modules
Bus cycle
T1 state
T2 state
ø or øSUB
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2-12 On-Chip Peripheral Module Access Cycle (2-State Access)
43
Three-state access to on-chip peripheral modules
Bus cycle
T1 state
T2 state
Address
T3 state
ø or øSUB
Internal
address bus
Internal
read signal
Internal
data bus
Read data
(read access)
Internal
write signal
Internal
data bus
Write data
(write access)
Figure 2-13 On-Chip Peripheral Module Access Cycle (3-State Access)
44
2.7 CPU States
2.7.1 Overview
There are four CPU states: the reset state, program execution state, program halt state, and
exception-handling state. The program execution state includes active (high-speed or medium-
speed) mode and subactive mode. In the program halt state there are a sleep mode, standby mode,
watch mode, and sub-sleep mode. These states are shown in figure 2-14.
Figure 2-15 shows the state transitions.
CPU state
Reset state
The CPU is initialized.
Program
execution state
Active
(high speed) mode
The CPU executes successive program
instructions at high speed,
synchronized by the system clock
Active
(medium speed) mode
The CPU executes successive
program instructions at
reduced speed, synchronized
by the system clock
Subactive mode
The CPU executes
successive program
instructions at reduced
speed, synchronized
by the subclock
Low-power
modes
Program halt state
Sleep mode
Standby mode
Watch mode
A state in which some
or all of the chip
functions are stopped
to conserve power
Subsleep mode
Exception-
handling state
A transient state in which the CPU changes
the processing flow due to a reset or an interrupt
Note: See section 5, Power-Down Modes, for details on the modes and their transitions.
Figure 2-14 CPU Operation States
45
Reset cleared
Reset occurs
Reset state
Exception-handling state
Reset
occurs
Interrupt
source
Reset
occurs
Exception- Exception-
handling
request
handling
complete
Program halt state
Program execution state
SLEEP instruction executed
Figure 2-15 State Transitions
2.7.2 Program Execution State
In the program execution state the CPU executes program instructions in sequence.
There are three modes in this state, two active modes (high speed and medium speed) and one
subactive mode. Operation is synchronized with the system clock in active mode (high speed and
medium speed), and with the subclock in subactive mode. See section 5, Power-Down Modes for
details on these modes.
2.7.3 Program Halt State
In the program halt state there are four modes: sleep mode, standby mode, watch mode, and
subsleep mode. See section 5, Power-Down Modes for details on these modes.
2.7.4 Exception-Handling State
The exception-handling state is a transient state occurring when exception handling is started by a
reset or interrupt and the CPU changes its normal processing flow. In exception handling caused
by an interrupt, SP (R7) is referenced and the PC and CCR values are saved on the stack.
For details on interrupt handling, see section 3, Exception Handling.
46
2.8 Memory Map
2.8.1 Memory Map
Figure 2-16 (a) shows the H8/3833U memory map. Figure 2-16 (b) shows the H8/3834U memory
map. Figure 2-16 (c) shows the H8/3835U memory map. Figure 2-16 (d) shows the H8/3836U
memory map. Figure 2-16 (e) shows the H8/3837U memory map.
H'0000
Interrupt vector area
H'0029
H'002A
24 kbytes
(24,576 bytes)
On-chip ROM
H'5FFF
Reserved
H'F740
*
LCD RAM (64 bytes)
H'F77F
Reserved
H'FB80
On-chip RAM
1,024 bytes
H'FF7F
H'FF80
H'FF9F
H'FFA0
32-byte serial data buffer
Internal I/O registers
(96 bytes)
H'FFFF
Note: * The LCD RAM addresses are the addresses after a reset.
Figure 2-16 (a) H8/3833U Memory Map
47
H'0000
Interrupt vector area
On-chip ROM
H'0029
H'002A
32 kbytes
(32,768 bytes)
H'7FFF
Reserved
H'F740
H'F77F
*
LCD RAM (64 bytes)
Reserved
H'FB80
On-chip RAM
1,024 bytes
H'FF7F
H'FF80
H'FF9F
H'FFA0
32-byte serial data buffer
Internal I/O registers
(96 bytes)
H'FFFF
Note: * The LCD RAM addresses are the addresses after a reset.
Figure 2-16 (b) H8/3834U Memory Map
48
H'0000
Interrupt vector area
On-chip ROM
H'0029
H'002A
40 kbytes
(40,960 bytes)
H'9FFF
Reserved
H'F740
LCD RAM* (64 bytes)
H'F77F
H'F780
2,048 bytes
On-chip RAM
H'FF7F
H'FF80
32-byte serial data buffer
H'FF9F
H'FFA0
Internal I/O registers
(96 bytes)
H'FFFF
Note: *The LCD RAM addresses are the addresses after a reset.
Figure 2-16 (c) H8/3835U Memory Map
49
H'0000
Interrupt vector area
H'0029
H'002A
48 kbytes
(49,152 bytes)
On-chip ROM
H'BFFF
H'F740
Reserved
LCD RAM* (64 bytes)
H'F77F
H'F780
2,048 bytes
On-chip RAM
H'FF7F
H'FF80
32-byte serial data buffer
H'FF9F
H'FFA0
Internal I/O registers
(96 bytes)
H'FFFF
Note: *The LCD RAM addresses are the addresses after a reset.
Figure 2-16 (d) H8/3836U Memory Map
50
H'0000
Interrupt vector area
H'0029
H'002A
60 kbytes
(60,928 bytes)
On-chip ROM
H'EDFF
H'F740
Reserved
LCD RAM* (64 bytes)
H'F77F
H'F780
On-chip RAM
2,048 bytes
H'FF7F
H'FF80
32-byte serial data buffer
H'FF9F
H'FFA0
Internal I/O registers
(96 bytes)
H'FFFF
Note: *The LCD RAM addresses are the addresses after a reset.
Figure 2-16 (e) H8/3837U Memory Map
51
2.8.2 LCD RAM Address Relocation
After a reset, the LCD RAM area is located at addresses H'F740 to H'F77F. However, this area
can be relocated by setting the LCD RAM relocation register (RLCTR) bits. The LCD RAM
relocation register is explained below.
LCD RAM relocation register (RLCTR: H'FFCF)
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
0
RLCT1 RLCT0
Initial value
Read/Write
0
0
—
—
—
—
—
—
R/W
R/W
RLCTR is an 8-bit read/write register that selects the LCD RAM address space. Upon reset,
RLCTR is initialized to H'FC.
Bits 7 to 2: Reserved bits
Bits 7 to 2 are reserved; they are always read as 1, and cannot be modified.
Bits 1 and 0: LCD RAM relocation select (RLCT1, RLCT0)
Bits 1 and 0 select the LCD RAM address space.
Bit 1
Bit 0
RLCT1
RLCT0
Description
0
0
1
1
0
1
0
1
H'F740 toH'F77F
H'F940 to H'F97F*2
H'FB40 to H'FB7F*2
H'FD40 to H'FD7F*1, 2
(initial value)
Notes: 1. In devices with 1,024-byte RAM, if RLCT1 to 0 are set to
11, on-chip RAM addresses H'FB80 to H'FD7F become
inaccessible.
2. In devices with 2,048-byte RAM, if RLCT1 to 0 are set to
any value except 00, these on-chip RAM addresses
become inaccessible.
52
2.9 Application Notes
2.9.1 Notes on Data Access
1. The address space of the H8/300L CPU includes empty areas in addition to the RAM,
registers, and ROM areas available to the user. If these empty areas are mistakenly accessed
by an application program, the following results will occur.
Data transfer from CPU to empty area:
The transferred data will be lost. This action may also cause the CPU to misoperate.
Data transfer from empty area to CPU:
Unpredictable data is transferred.
2. Internal data transfer to or from on-chip modules other than the ROM and RAM areas makes
use of an 8-bit data width. If word access is attempted to these areas, the following results
will occur.
Word access from CPU to I/O register area:
Upper byte: Will be written to I/O register.
Lower byte: Transferred data will be lost.
Word access from I/O register to CPU:
Upper byte: Will be written to upper part of CPU register.
Lower byte: Unpredictable data will be written to lower part of CPU register.
Byte size instructions should therefore be used when transferring data to or from I/O registers
other than the on-chip ROM and RAM areas. Figure 2-17 shows the data size and number of
states in which on-chip peripheral modules can be accessed.
53
Access
Word Byte
States
H'0000
Interrupt vector area
(42 bytes)
H'0029
H'002A
o
o
2
32 kbytes*2
On-chip ROM
H'7FFF*2
—
—
—
Reserved
H'F740
H'F77F
LCD RAM*1 (64 bytes)
Reserved
o
o
2
—
—
—
H'FB80*3
1,024 bytes*3
On-chip RAM
o
o
2
H'FF7F
H'FF80
H'FF9F
H'FFA0
32-byte serial data buffer
×
×
o
o
2
2
Internal I/O registers
(96 bytes)
H'FFA8
H'FFAD
×
×
o
o
3
2
H'FFFF
o : Access possible
× : Not possible
Notes: The above example is a description of the H8/3834U.
1. The indicated addresses for the LCD RAM area are initial values after system reset.
2. The H8/3833U has 24 kbytes of on-chip ROM, and its ending address is H'5FFF.
The H8/3835U has 40 kbytes of on-chip ROM, and its ending address is H'9FFF.
The H8/3836U has 48 kbytes of on-chip ROM, and its ending address is H'BFFF.
The H8/3837U has 60 kbytes of on-chip ROM, and its ending address is H'EDFF.
3. The H8/3833U has 1,024 bytes of on-chip RAM and its starting address is H'FB80.
The H8/3835U, H8/3836U, and H8/3837U each have 2,048 bytes of on-chip RAM, and
their starting address is H'F780.
Figure 2-17 Data Size and Number of States for Access to and from
On-Chip Peripheral Modules
54
2.9.2 Notes on Bit Manipulation
The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data,
then write the data byte again. Special care is required when using these instructions in cases
where two registers are assigned to the same address, in the case of registers that include write-
only bits, and when the instruction accesses an I/O.
Order of Operation
Operation
1
2
3
Read
Modify
Write
Read byte data at the designated address
Modify a designated bit in the read data
Write the altered byte data to the designated address
1. Bit manipulation in two registers assigned to the same address
Example 1
Figure 2-18 shows an example in which two timer registers share the same address. When a bit
manipulation instruction accesses the timer load register and timer counter of a reloadable timer,
since these two registers share the same address, the following operations take place.
Order of Operation
Operation
1
2
3
Read
Modify
Write
Timer counter data is read (one byte)
The CPU modifies (sets or resets) the bit designated in the instruction
The altered byte data is written to the timer load register
The timer counter is counting, so the value read is not necessarily the same as the value in the
timer load register. As a result, bits other than the intended bit in the timer load register may be
modified to the timer counter value.
R
Count clock
Timer counter
R: Read
W: Write
Reload
W
Timer load register
Internal bus
Figure 2-18 Timer Configuration Example
55
Example 2
Here a BSET instruction is executed designating port 3.
P3 and P3 are designated as input pins, with a low-level signal input at P3 and a high-level
7
6
7
signal at P3 . The remaining pins, P3 to P3 , are output pins and output low-level signals. In
6
5
0
this example, the BSET instruction is used to change pin P3 to high-level output.
0
[A: Prior to executing BSET]
P37
P36
P35
P34
P33
P32
P31
P30
Input/output
Pin state
Input
Input
Output Output Output Output Output Output
Low
level
High
level
Low
Low
Low
Low
Low
Low
level
level
level
level
level
level
PCR3
PDR3
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
[B: BSET instruction executed]
BSET #0 @PDR3
,
The BSET instruction is executed designating port 3.
[C: After executing BSET]
P37
P36
P35
P34
P33
P32
P31
P30
Input/output
Pin state
Input
Input
Output Output Output Output Output Output
Low
level
High
level
Low
Low
Low
Low
Low
High
level
level
level
level
level
level
PCR3
PDR3
0
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
[D: Explanation of how BSET operates]
When the BSET instruction is executed, first the CPU reads port 3.
Since P3 and P3 are input pins, the CPU reads the pin states (low-level and high-level input).
7
6
P3 to P3 are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a
5
0
value of H'80, but the value read by the CPU is H'40.
Next, the CPU sets bit 0 of the read data to 1, changing the PDR3 data to H'41. Finally, the CPU
writes this value (H'41) to PDR3, completing execution of BSET.
56
As a result of this operation, bit 0 in PDR3 becomes 1, and P3 outputs a high-level signal.
0
However, bits 7 and 6 of PDR3 end up with different values.
To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit
manipulation on the data in the work area, then write this data to PDR3.
[A: Prior to executing BSET]
MOV. B #80, R0L
MOV. B R0L, @RAM0
MOV. B R0L, @PDR3
The PDR3 value (H'80) is written to a work area in memory
(RAM0) as well as to PDR3.
P37
P36
P35
P34
P33
P32
P31
P30
Input/output
Pin state
Input
Input
Output Output Output Output Output Output
Low
level
High
level
Low
Low
Low
Low
Low
Low
level
level
level
level
level
level
PCR3
PDR3
RAM0
0
1
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
[B: BSET instruction executed]
BSET #0 @RAM0
,
The BSET instruction is executed designating the PDR3
work area (RAM0).
57
[C: After executing BSET]
MOV. B @RAM0, R0L
MOV. B R0L, @PDR3
The work area (RAM0) value is written to PDR3.
P37
P36
P35
P34
P33
P32
P31
P30
Input/output
Pin state
Input
Input
Output Output Output Output Output Output
Low
level
High
level
Low
Low
Low
Low
Low
High
level
level
level
level
level
level
PCR3
PDR3
RAM0
0
1
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
1
2. Bit manipulation in a register containing a write-only bit
Example 3
In this example, the port 3 control register PCR3 is accessed by a BCLR instruction.
As in the examples above, P3 and P3 are input pins, with a low-level signal input at P3 and a
7
6
7
high-level signal at P3 . The remaining pins, P3 to P3 , are output pins that output low-level
6
5
0
signals. In this example, the BCLR instruction is used to change pin P3 to an input port. It is
0
assumed that a high-level signal will be input to this input pin.
[A: Prior to executing BCLR]
P37
P36
P35
P34
P33
P32
P31
P30
Input/output
Pin state
Input
Input
Output Output Output Output Output Output
Low
level
High
level
Low
Low
Low
Low
Low
Low
level
level
level
level
level
level
PCR3
PDR3
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
[B: BCLR instruction executed]
BCLR #0 @PCR3
,
The BCLR instruction is executed designating PCR3.
58
[C: After executing BCLR]
P37
P36
P35
P34
P33
P32
P31
P30
Input/output
Pin state
Output Output Output Output Output Output Output Input
Low
High
level
Low
Low
Low
Low
Low
High
level
level
level
level
level
level
level
PCR3
PDR3
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
0
[D: Explanation of how BCLR operates]
When the BCLR instruction is executed, first the CPU reads PCR3. Since PCR3 is a write-only
register, the CPU reads a value of H'FF, even though the PCR3 value is actually H'3F.
Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. Finally, this value
(H'FE) is written to PCR3 and BCLR instruction execution ends.
As a result of this operation, bit 0 in PCR3 becomes 0, making P3 an input port. However, bits 7
0
and 6 in PCR3 change to 1, so that P3 and P3 change from input pins to output pins.
7
6
To avoid this problem, store a copy of the PCR3 data in a work area in memory. Perform the bit
manipulation on the data in the work area, then write this data to PCR3.
[A: Prior to executing BCLR]
MOV. B #3F, R0L
MOV. B R0L, @RAM0
MOV. B R0L, @PCR3
The PCR3 value (H'3F) is written to a work area in memory
(RAM0) as well as to PCR3.
P37
P36
P35
P34
P33
P32
P31
P30
Input/output
Pin state
Input
Input
Output Output Output Output Output Output
Low
level
High
level
Low
Low
Low
Low
Low
Low
level
level
level
level
level
level
PCR3
PDR3
RAM0
0
1
0
0
0
0
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
59
[B: BCLR instruction executed]
BCLR #0 @RAM0
,
The BCLR instruction is executed designating the PCR3
work area (RAM0).
[C: After executing BCLR]
MOV. B @RAM0, R0L
MOV. B R0L, @PCR3
The work area (RAM0) value is written to PCR3.
P37
P36
P35
P34
P33
P32
P31
P30
Input/output
Pin state
Input
Input
Output Output Output Output Output Output
Low
level
High
level
Low
Low
Low
Low
Low
High
level
level
level
level
level
level
PCR3
PDR3
RAM0
0
1
0
0
0
0
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
0
0
The tables below list registers that share the same address, and registers that contain write-only
bits.
Registers with shared addresses
Register Name
Abbreviation
TCB/TLB
TCC/TLC
PDR1
Address
H'FFB3
H'FFB5
H'FFD4
H'FFD5
H'FFD6
H'FFD7
H'FFD8
H'FFD9
H'FFDA
H'FFDB
H'FFDC
H'FFDD
Timer counter B and timer load register B
Timer counter C and timer load register C
Port data register 1*
Port data register 2*
PDR2
Port data register 3*
PDR3
Port data register 4*
PDR4
Port data register 5*
PDR5
Port data register 6*
PDR6
Port data register 7*
PDR7
Port data register 8*
PDR8
Port data register 9*
PDR9
Port data register A*
PDRA
Note: * These port registers are used also for pin input.
60
Registers with write-only bits
Register Name
Abbreviation
PCR1
Address
H'FFE4
H'FFE5
H'FFE6
H'FFE7
H'FFE8
H'FFE9
H'FFEA
H'FFEB
H'FFEC
H'FFED
H'FFB6
H'FFD0
H'FFD1
H'FFD2
Port control register 1
Port control register 2
Port control register 3
Port control register 4
Port control register 5
Port control register 6
Port control register 7
Port control register 8
Port control register 9
Port control register A
Timer control register F
PWM control register
PWM data register U
PWM data register L
PCR2
PCR3
PCR4
PCR5
PCR6
PCR7
PCR8
PCR9
PCRA
TCRF
PWCR
PWDRU
PWDRL
2.9.3 Notes on Use of the EEPMOV Instruction
•
The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes
specified by R4L from the address specified by R5 to the address specified by R6.
→
→
R5
←
←
R6
R5 + R4L
R6 + R4L
•
When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not
exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of
the instruction.
→
→
R5
←
←
R6
R5 + R4L
H'FFFF
Not allowed
R6 + R4L
61
Section 3 Exception Handling
3.1 Overview
Exception handling is performed in the H8/3834U Series when a reset or interrupt occurs. Table
3-1 shows the priorities of these two types of exception handling.
Table 3-1 Exception Handling Types and Priorities
Priority
Exception Source
Reset
Time of Start of Exception Handling
High
Exception handling starts as soon as the reset state is cleared
Interrupt
When an interrupt is requested, exception handling starts
after execution of the present instruction or the exception
handling in progress is completed
Low
3.2 Reset
3.2.1 Overview
A reset is the highest-priority exception. The internal state of the CPU and the registers of the on-
chip peripheral modules are initialized.
3.2.2 Reset Sequence
As soon as the RES pin goes low, all processing is stopped and the H8/3834U enters the reset
state.
To make sure the chip is reset properly, observe the following precautions.
•
•
At power on: Hold the RES pin low until the clock pulse generator output stabilizes.
Resetting during operation: Hold the RES pin low for at least 10 system clock cycles.
If the MD0 pin is at the high level, reset exception handling begins when the RES pin is held low
for a given period, then returned to the high level. If the MD0 pin is low, however, when the RES
pin is held low for a given period and then returned to high level, the reset is not cleared
immediately. First the MD0 pin must go from low to high, then after 8,192 clock cycles the reset
is cleared and reset exception handling begins.
63
Reset exception handling takes place as follows.
•
The CPU internal state and the registers of on-chip peripheral modules are initialized, with
the I bit of the condition code register (CCR) set to 1.
•
The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after
which the program starts executing from the address indicated in PC.
When system power is turned on or off, the RES pin should be held low.
Figures 3-1 and 3-2 show the reset sequence.
Reset cleared
Program initial
instruction prefetch
Vector fetch
Internal
processing
RES
MD0
High
ø
Internal
address bus
(1)
(2)
Internal read
signal
Internal write
signal
Internal data
bus (16-bit)
(2)
(3)
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) First instruction of program
Figure 3-1 Reset Sequence (when MD0 Pin is High)
64
Reset cleared
Vector fetch
Program initial
instruction prefetch
Internal
processing
RES
MD0
ø
8,192 clock
cycles
Internal
address bus
(1)
(2)
Internal read
signal
Internal write
signal
Internal data
bus (16-bit)
(2)
(3)
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) First instruction of program
Figure 3-2 Reset Sequence (when MD0 Pin is Low)
3.2.3 Interrupt Immediately after Reset
After a reset, if an interrupt were to be accepted before the stack pointer (SP: R7) was initialized,
PC and CCR would not be pushed onto the stack correctly, resulting in program runaway. To
prevent this, immediately after reset exception handling all interrupts are masked. For this reason,
the initial program instruction is always executed immediately after a reset. This instruction
should initialize the stack pointer (e.g. MOV.W #xx: 16, SP).
65
3.3 Interrupts
3.3.1 Overview
The interrupt sources include 13 external interrupts (WKP to WKP , IRQ to IRQ ), and 20
0
7
0
4
internal interrupts from on-chip peripheral modules. Table 3-2 shows the interrupt sources, their
priorities, and their vector addresses. When more than one interrupt is requested, the interrupt
with the highest priority is processed.
The interrupts have the following features:
•
Both internal and external interrupts can be masked by the I bit of CCR. When this bit is set
to 1, interrupt request flags are set but interrupts are not accepted.
•
The external interrupt pins IRQ to IRQ can each be set independently to either rising edge
0
4
sensing or falling edge sensing.
Table 3-2 Interrupt Sources and Priorities
Priority
Interrupt Source
RES
Interrupt
Reset
IRQ0
Vector Number
Vector Address
H'0000 to H'0001
H'0008 to H'0009
H'000A to H'000B
H'000C to H'000D
H'000E to H'000F
H'0010 to H'0011
H'0012 to H'0013
High
0
4
5
6
7
8
9
IRQ0
IRQ1
IRQ1
IRQ2
IRQ2
IRQ3
IRQ3
IRQ4
IRQ4
WKP0
WKP1
WKP2
WKP3
WKP4
WKP5
WKP6
WKP7
SCI1
WKP0
WKP1
WKP2
WKP3
WKP4
WKP5
WKP6
WKP7
Low
SCI1 transfer complete 10
H'0014 to H'0015
66
Table 3-2 Interrupt Sources and Priorities (cont)
Vector
Priority
Interrupt Source
Timer A
Interrupt
Number Vector Address
High
Timer A overflow
11
12
13
14
H'0016 to H'0017
H'0018 to H'0019
H'001A to H'001B
H'001C to H'001D
Timer B
Timer B overflow
Timer C
Timer C overflow or underflow
Timer FL compare match
Timer FL overflow
Timer FH compare match
Timer FH overflow
Timer G input capture
Timer G overflow
Timer FL
Timer FH
Timer G
SCI2
15
16
17
18
H'001E to H'001F
H'0020 to H'0021
H'0022 to H'0023
H'0024 to H'0025
SCI2 transfer complete
SCI2 transfer abort
SCI3 transmit end
SCI3 transmit data empty
SCI3 receive data full
SCI3 overrun error
SCI3 framing error
SCI3 parity error
SCI3
A/D converter
A/D conversion end
Direct transfer
19
20
H'0026 to H'0027
H'0028 to H'0029
(SLEEP instruction
executed)
Low
Note: Vector addresses H'0002 to H'0007 are reserved and cannot be used.
67
3.3.2 Interrupt Control Registers
Table 3-3 lists the registers that control interrupts.
Table 3-3 Interrupt Control Registers
Register Name
Abbreviation
IEGR
R/W
Initial Value
H'E0
Address
H'FFF2
H'FFF3
H'FFF4
H'FFF6
H'FFF7
H'FFF9
IRQ edge select register
Interrupt enable register 1
Interrupt enable register 2
Interrupt request register 1
Interrupt request register 2
Wakeup interrupt request register
R/W
IENR1
IENR2
IRR1
R/W
H'00
R/W
H'00
R/W*
R/W*
R/W*
H'20
IRR2
H'00
IWPR
H'00
Note: * Write is enabled only for writing of 0 to clear a flag.
1. IRQ edge select register (IEGR)
Bit
7
—
1
6
—
1
5
—
1
4
IEG4
0
3
IEG3
0
2
IEG2
0
1
0
IEG0
0
IEG1
0
Initial value
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
IEGR is an 8-bit read/write register, used to designate whether pins IRQ to IRQ are set to rising
0
4
edge sensing or falling edge sensing.
Bits 7 to 5: Reserved bits
Bits 7 to 5 are reserved; they are always read as 1, and cannot be modified.
Bit 4: IRQ edge select (IEG4)
4
Bit 4 selects the input sensing of pin IRQ /ADTRG.
4
Bit 4
IEG4
Description
0
1
Falling edge of IRQ4/ADTRG pin input is detected
Rising edge of IRQ4/ADTRG pin input is detected
(initial value)
68
Bit 3: IRQ edge select (IEG3)
3
Bit 3 selects the input sensing of pin IRQ /TMIF.
3
Bit 3
IEG3
Description
0
1
Falling edge of IRQ3/TMIF pin input is detected
Rising edge of IRQ3/TMIF pin input is detected
(initial value)
(initial value)
(initial value)
(initial value)
Bit 2: IRQ edge select (IEG2)
2
Bit 2 selects the input sensing of pin IRQ /TMIC.
2
Bit 2
IEG2
Description
0
1
Falling edge of IRQ2/TMIC pin input is detected
Rising edge of IRQ2/TMIC pin input is detected
Bit 1: IRQ edge select (IEG1)
1
Bit 1 selects the input sensing of pin IRQ /TMIB.
1
Bit 1
IEG1
Description
0
1
Falling edge of IRQ1/TMIB pin input is detected
Rising edge of IRQ1/TMIB pin input is detected
Bit 0: IRQ edge select (IEG0)
0
Bit 0 selects the input sensing of pin IRQ .
0
Bit 0
IEG0
Description
0
1
Falling edge of IRQ0 pin input is detected
Rising edge of IRQ0 pin input is detected
69
2. Interrupt enable register 1 (IENR1)
Bit
7
IENTA
0
6
5
4
IEN4
0
3
IEN3
0
2
IEN2
0
1
IEN1
0
0
IEN0
0
IENS1 IENWP
Initial value
Read/Write
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IENR1 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7: Timer A interrupt enable (IENTA)
Bit 7 enables or disables timer A overflow interrupt requests.
Bit 7
IENTA
Description
0
1
Disables timer A interrupts
Enables timer A interrupts
(initial value)
(initial value)
(initial value)
Bit 6: SCI1 interrupt enable (IENS1)
Bit 6 enables or disables SCI1 transfer complete interrupt requests.
Bit 6
IENS1
Description
0
1
Disables SCI1 interrupts
Enables SCI1 interrupts
Bit 5: Wakeup interrupt enable (IENWP)
Bit 5 enables or disables WKP to WKP interrupt requests.
7
0
Bit 5
IENWP
Description
0
1
Disables interrupt requests from WKP7 to WKP0
Enables interrupt requests from WKP7 to WKP0
70
Bits 4 to 0: IRQ to IRQ interrupt enable (IEN4 to IEN0)
4
0
Bits 4 to 0 enable or disable IRQ to IRQ interrupt requests.
4
0
Bit n
IENn
Description
0
1
Disables interrupt request IRQn
Enables interrupt request IRQn
(initial value)
(n = 4 to 0)
3. Interrupt Enable Register 2 (IENR2)
Bit
7
IENDT
0
6
5
4
3
2
1
0
IENAD IENS2 IENTG IENTFH IENTFL IENTC IENTB
Initial value
Read/Write
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IENR2 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7: Direct transfer interrupt enable (IENDT)
Bit 7 enables or disables direct transfer interrupt requests.
Bit 7
IENDT
Description
0
1
Disables direct transfer interrupt requests
Enables direct transfer interrupt requests
(initial value)
Bit 6: A/D converter interrupt enable (IENAD)
Bit 6 enables or disables A/D converter interrupt requests.
Bit 6
IENAD
Description
0
1
Disables A/D converter interrupt requests
Enables A/D converter interrupt requests
(initial value)
71
Bit 5: SCI2 interrupt enable (IENS2)
Bit 5 enables or disables SCI2 transfer complete and transfer abort interrupt requests.
Bit 5
IENS2
Description
0
1
Disables SCI2 interrupts
Enables SCI2 interrupts
(initial value)
(initial value)
(initial value)
(initial value)
Bit 4: Timer G interrupt enable (IENTG)
Bit 4 enables or disables timer G input capture and overflow interrupt requests.
Bit 4
IENTG
Description
0
1
Disables timer G interrupts
Enables timer G interrupts
Bit 3: Timer FH interrupt enable (IENTFH)
Bit 3 enables or disables timer FH compare match and overflow interrupt requests.
Bit 3
IENTFH
Description
0
1
Disables timer FH interrupts
Enables timer FH interrupts
Bit 2: Timer FL interrupt enable (IENTFL)
Bit 2 enables or disables timer FL compare match and overflow interrupt requests.
Bit 2
IENTFL
Description
0
1
Disables timer FL interrupts
Enables timer FL interrupts
72
Bit 1: Timer C interrupt enable (IENTC)
Bit 1 enables or disables timer C overflow or underflow interrupt requests.
Bit 1
IENTC
Description
0
1
Disables timer C interrupts
Enables timer C interrupts
(initial value)
Bit 0: Timer B interrupt enable (IENTB)
Bit 0 enables or disables timer B overflow or underflow interrupt requests.
Bit 0
IENTB
Description
0
1
Disables timer B interrupts
Enables timer B interrupts
(initial value)
SCI3 interrupt control is covered in 10.4.2, in the description of serial control register 3.
4. Interrupt request register 1 (IRR1)
Bit
7
IRRTA
0
6
5
—
1
4
3
2
1
0
IRRS1
0
IRRI4
0
IRRI3
0
IRRI2
0
IRRI1
0
IRRI0
0
Initial value
Read/Write
R/W*
R/W*
—
R/W*
R/W*
R/W*
R/W*
R/W*
Note: * Only a write of 0 for flag clearing is possible.
IRR1 is an 8-bit read/write register, in which the corresponding bit is set to 1 when a timer A,
SCI1, or IRQ to IRQ interrupt is requested. The flags are not cleared automatically when an
4
0
interrupt is accepted. It is necessary to write 0 to clear each flag.
Bit 7: Timer A interrupt request flag (IRRTA)
Bit 7
IRRTA
Description
0
Clearing conditions:
(initial value)
When IRRTA = 1, it is cleared by writing 0
1
Setting conditions:
When the timer A counter value overflows (goes from H'FF to H'00)
73
Bit 6: SCI1 interrupt request flag (IRRS1)
Bit 6
IRRS1
Description
0
Clearing conditions:
(initial value)
When IRRS1 = 1, it is cleared by writing 0
1
Setting conditions:
When an SCI1 transfer is completed
Bit 5: Reserved bit
Bit 5 is reserved; it is always read as 1, and cannot be modified.
Bits 4 to 0: IRQ to IRQ interrupt request flags (IRRI4 to IRRI0)
4
0
Bit n
IRRIn
Description
0
Clearing conditions:
(initial value)
When IRRIn = 1, it is cleared by writing 0 to IRRIn.
1
Setting conditions:
IRRIn is set when pin IRQn is set to interrupt input, and the designated signal
edge is detected.
(n = 4 to 0)
5. Interrupt request register 2 (IRR2)
Bit
7
6
5
4
3
2
1
0
IRRDT IRRAD IRRS2 IRRTG IRRTFH IRRTFL IRRTC IRRTB
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Note: * Only a write of 0 for flag clearing is possible.
IRR2 is an 8-bit read/write register, in which the corresponding bit is set to 1 when a direct
transfer, A/D converter, SCI2, timer G, timer FH, timer FL, timer C, or timer B interrupt is
requested. The flags are not cleared automatically when an interrupt is accepted. It is necessary
to write 0 to clear each flag.
74
Bit 7: Direct transfer interrupt request flag (IRRDT)
Bit 7
IRRDT
Description
0
Clearing conditions:
(initial value)
When IRRDT = 1, it is cleared by writing 0
1
Setting conditions:
When DTON = 1 and a direct transfer is made immediately after a SLEEP instruction
is executed
Bit 6: A/D converter interrupt request flag (IRRAD)
Bit 6
IRRAD
Description
0
Clearing conditions:
When IRRAD = 1, it is cleared by writing 0
(initial value)
(initial value)
(initial value)
1
Setting conditions:
When A/D conversion is completed and ADSF is reset
Bit 5: SCI2 interrupt request flag (IRRS2)
Bit 5
IRRS2
Description
0
Clearing conditions:
When IRRS2 = 1, it is cleared by writing 0
1
Setting conditions:
When an SCI2 transfer is completed or aborted
Bit 4: Timer G interrupt request flag (IRRTG)
Bit 4
IRRTG
Description
0
Clearing conditions:
When IRRTG = 1, it is cleared by writing 0
1
Setting conditions:
When pin TMIG is set to TMIG input and the designated signal edge is detected
75
Bit 3: Timer FH interrupt request flag (IRRTFH)
Bit 3
IRRTFH
Description
0
Clearing conditions:
(initial value)
When IRRTFH = 1, it is cleared by writing 0
1
Setting conditions:
When counter FH matches output compare register FH in 8-bit timer mode, or when
16-bit counter F (TCFL, TCFH) matches output compare register F (OCRFL,
OCRFH) in 16-bit timer mode
Bit 2: Timer FL interrupt request flag (IRRTFL)
Bit 2
IRRTFL
Description
0
Clearing conditions:
(initial value)
When IRRTFL = 1, it is cleared by writing 0
1
Setting conditions:
When counter FL matches output compare register FL in 8-bit timer mode
Bit 1: Timer C interrupt request flag (IRRTC)
Bit 1
IRRTC
Description
0
Clearing conditions:
(initial value)
When IRRTC = 1, it is cleared by writing 0
1
Setting conditions:
When the timer C counter value overflows (goes from H'FF to H'00) or underflows
(goes from H'00 to H'FF)
Bit 0: Timer B interrupt request flag (IRRTB)
Bit 0
IRRTB
Description
0
Clearing conditions:
(initial value)
When IRRTB = 1, it is cleared by writing 0
1
Setting conditions:
When the timer B counter value overflows (goes from H'FF to H'00)
76
6. Wakeup interrupt request register (IWPR)
Bit
7
6
5
4
3
2
1
0
IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Note: * Only a write of 0 for flag clearing is possible.
IWPR is an 8-bit read/write register, in which the corresponding bit is set to 1 when pins WKP7 to
WKP0 are set to wakeup input and a pin receives a falling edge input. The flags are not cleared
automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag.
Bits 7 to 0: Wakeup interrupt request flags (WKPF7 to WKPF0)
Bit n
IWPFn
Description
0
Clearing conditions:
When IWPFn = 1, it is cleared by writing 0 to IWPFn.
1
Setting conditions:
IWPFn is set when pin WKPn is set to wakeup interrupt input, and a falling edge input
is detected at the pin.
(n = 7 to 0)
3.3.3 External Interrupts
There are 13 external interrupts, WKP to WKP and IRQ to IRQ .
0
7
0
4
1. Interrupts WKP to WKP
0
7
Interrupts WKP to WKP are requested by falling edge inputs at pins WKP to WKP . When
0
7
0
7
these pins are designated as WKP to WKP pins in port mode register 5 (PMR5) and falling edge
0
7
input is detected, the corresponding bit in the wakeup interrupt request register (IWPR) is set to 1,
requesting an interrupt. Wakeup interrupt requests can be disabled by clearing the IENWP bit in
IENR1 to 0. It is also possible to mask all interrupts by setting the CCR I bit to 1.
When an interrupt exception handling request is received for interrupts WKP0 to WKP7, the CCR
I bit is set to 1. The vector number for interrupts WKP0 to WKP7 is 9. Since all eight interrupts
are assigned the same vector number, the interrupt source must be determined by the exception
handling routine.
77
2. Interrupts IRQ to IRQ
0
4
Interrupts IRQ to IRQ are requested by into pins inputs to IRQ to IRQ . These interrupts are
0
4
0
4
detected by either rising edge sensing or falling edge sensing, depending on the settings of bits
IEG0 to IEG4 in the edge select register (IEGR).
When these pins are designated as pins IRQ to IRQ in port mode registers 1 and 2 (PMR1 and
0
4
PMR2) and the designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an
interrupt. Interrupts IRQ to IRQ can be disabled by clearing bits IEN0 to IEN4 in IENR1 to 0.
0
4
All interrupts can be masked by setting the I bit in CCR to 1.
When IRQ to IRQ interrupt exception handling is initiated, the I bit is set to 1. Vector numbers
0
4
4 to 8 are assigned to interrupts IRQ to IRQ . The order of priority is from IRQ (high) to IRQ
4
0
4
0
(low). Table 3-2 gives details.
3.3.4 Internal Interrupts
There are 20 internal interrupts that can be requested by the on-chip peripheral modules. When a
peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1.
Individual interrupt requests can be disabled by clearing the corresponding bit in IENR1 or IENR2
to 0. All interrupts can be masked by setting the I bit in CCR to 1. When an internal interrupt
request is accepted, the I bit is set to 1. Vector numbers 10 to 20 are assigned to these interrupts.
Table 3-2 shows the order of priority of interrupts from on-chip peripheral modules.
78
3.3.5 Interrupt Operations
Interrupts are controlled by an interrupt controller. Figure 3-3 shows a block diagram of the
interrupt controller. Figure 3-4 shows the flow up to interrupt acceptance.
Interrupt controller
External or
internal
interrupts
Interrupt
request
External
interrupts or
internal
interrupt
enable
signals
I
CCR (CPU)
Figure 3-3 Block Diagram of Interrupt Controller
Interrupt operation is described as follows.
•
When an interrupt condition is met while the interrupt enable register bit is set to 1, an
interrupt request signal is sent to the interrupt controller.
•
•
When the interrupt controller receives an interrupt request, it sets the interrupt request flag.
From among the interrupts with interrupt request flags set to 1, the interrupt controller selects
the interrupt request with the highest priority and holds the others pending. (Refer to
table 3-2 for a list of interrupt priorities.)
79
•
•
The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request
is accepted; if the I bit is 1, the interrupt request is held pending.
If the interrupt is accepted, after processing of the current instruction is completed, both PC
and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3-5.
The PC value pushed onto the stack is the address of the first instruction to be executed upon
return from interrupt handling.
•
•
The I bit of CCR is set to 1, masking all further interrupts.
The vector address corresponding to the accepted interrupt is generated, and the interrupt
handling routine located at the address indicated by the contents of the vector address is
executed.
Notes:
1. When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits
in an interrupt request register, always do so while interrupts are masked (I = 1).
2. If the above clear operations are performed while I = 0, and as a result a conflict arises
between the clear instruction and an interrupt request, exception processing for the interrupt
will be executed after the clear instruction has been executed.
80
Program execution state
No
IRRIO = 1
Yes
No
IENO = 1
Yes
No
No
IRRI1 = 1
Yes
IEN1 = 1
Yes
No
No
IRRI2 = 1
Yes
IEN2 = 1
Yes
No
No
IRRDT = 1
Yes
IENDT = 1
Yes
No
I = 0
Yes
PC contents saved
CCR contents saved
I ← 1
Branch to interrupt
handling routine
Notation:
PC: Program counter
CCR: Condition code register
I: I bit of CCR
Figure 3-4 Flow up to Interrupt Acceptance
81
SP – 4
SP – 3
SP – 2
SP – 1
SP (R7)
SP (R7)
SP + 1
SP + 2
SP + 3
SP + 4
CCR
CCR*
PCH
PCL
Even address
Stack area
Prior to start of interrupt
exception handling
After completion of interrupt
exception handling
PC and CCR
saved to stack
Notation:
PCH: Upper 8 bits of program counter (PC)
PCL: Lower 8 bits of program counter (PC)
CCR: Condition code register
SP: Stack pointer
1. PC shows the address of the first instruction to be executed upon
return from the interrupt handling routine.
Notes:
2. Register contents must always be saved and restored by word access,
starting from an even-numbered address.
* Ignored on return from interrupt.
Figure 3-5 Stack State after Completion of Interrupt Exception Handling
Figure 3-6 shows a typical interrupt sequence where the program area is in the on-chip ROM and
the stack area is in the on-chip RAM.
82
Figure 3-6 Interrupt Sequence
83
3.3.6 Interrupt Response Time
Table 3-4 shows the number of wait states after an interrupt request flag is set until the first
instruction of the interrupt handler is executed.
Table 3-4 Interrupt Wait States
Item
States
Waiting time for completion of executing instruction*
Saving of PC and CCR to stack
Vector fetch
1 to 13
4
2
Instruction fetch
4
Internal processing
4
Total
15 to 27
Note: * Not including EEPMOV instruction.
84
3.4 Application Notes
3.4.1 Notes on Stack Area Use
When word data is accessed in the H8/3834U Series, the least significant bit of the address is
regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7)
should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @–SP) or POP Rn (MOV.W
@SP+, Rn) to save or restore register values.
Setting an odd address in SP may cause a program to crash. An example is shown in figure 3-7.
→
PCH
PCL
SP
R1L
PCL
H'FEFC
H'FEFD
→
SP
→
SP
H'FEFF
MOV. B R1L, @–R7
Stack accessed beyond SP Contents of PCH are lost
BSR instruction
SP set to H'FEFF
Notation:
PCH: Upper byte of program counter
PCL: Lower byte of program counter
R1L: General register R1L
SP: Stack pointer
Figure 3-7 Operation when Odd Address is Set in SP
When CCR contents are saved to the stack during interrupt exception handling or restored when
RTE is executed, this also takes place in word size. Both the upper and lower bytes of word data
are saved to the stack; on return, the even address contents are restored to CCR while the odd
address contents are ignored.
85
3.4.2 Notes on Rewriting Port Mode Registers
When a port mode register is rewritten to switch the functions of external interrupt pins, the
following points should be observed.
When an external interrupt pin function is switched by rewriting the port mode register that
controls these pins (IRQ to IRQ , and WKP to WKP ), the interrupt request flag may be set to 1
4
0
7
0
at the time the pin function is switched, even if no valid interrupt is input at the pin. Be sure to
clear the interrupt request flag to 0 after switching pin functions. Table 3-5 shows the conditions
under which interrupt request flags are set to 1 in this way.
Table 3-5 Conditions under which Interrupt Request Flag is Set to 1
Interrupt Request
Flags Set to 1
Conditions
IRR1
IRRI4
IRRI3
IRRI2
IRRI1
IRRI0
• When PMR2 bit IRQ4 is changed from 0 to 1 while pin IRQ4 is low and
IEGR bit IEG4 = 0.
• When PMR2 bit IRQ4 is changed from 1 to 0 while pin IRQ4 is low and
IEGR bit IEG4 = 1.
• When PMR1 bit IRQ3 is changed from 0 to 1 while pin IRQ3 is low and
IEGR bit IEG3 = 0.
• When PMR1 bit IRQ3 is changed from 1 to 0 while pin IRQ3 is low and
IEGR bit IEG3 = 1.
• When PMR1 bit IRQ2 is changed from 0 to 1 while pin IRQ2 is low and
IEGR bit IEG2 = 0.
• When PMR1 bit IRQ2 is changed from 1 to 0 while pin IRQ2 is low and
IEGR bit IEG2 = 1.
• When PMR1 bit IRQ1 is changed from 0 to 1 while pin IRQ1 is low and
IEGR bit IEG1 = 0.
• When PMR1 bit IRQ1 is changed from 1 to 0 while pin IRQ1 is low and
IEGR bit IEG1 = 1.
• When PMR2 bit IRQ0 is changed from 0 to 1 while pin IRQ0 is low and
IEGR bit IEG0 = 0.
• When PMR2 bit IRQ0 is changed from 1 to 0 while pin IRQ0 is low and
IEGR bit IEG0 = 1.
86
Table 3-5 Conditions under which Interrupt Request Flag is Set to 1 (cont)
Interrupt Request
Flags Set to 1
Conditions
IWPR IWPF7
When PMR5 bit WKP7 is changed from 0 to 1 while pin WKP7 is low
When PMR5 bit WKP6 is changed from 0 to 1 while pin WKP6 is low
When PMR5 bit WKP5 is changed from 0 to 1 while pin WKP5 is low
When PMR5 bit WKP4 is changed from 0 to 1 while pin WKP4 is low
When PMR5 bit WKP3 is changed from 0 to 1 while pin WKP3 is low
When PMR5 bit WKP2 is changed from 0 to 1 while pin WKP2 is low
When PMR5 bit WKP1 is changed from 0 to 1 while pin WKP1 is low
When PMR5 bit WKP0 is changed from 0 to 1 while pin WKP0 is low
IWPF6
IWPF5
IWPF4
IWPF3
IWPF2
IWPF1
IWPF0
Figure 3-8 shows the procedure for setting a bit in a port mode register and clearing the interrupt
request flag.
When switching a pin function, mask the interrupt before setting the bit in the port mode register.
After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the
interrupt request flag from 1 to 0. If the instruction to clear the flag is executed immediately after
the port mode register access without executing an intervening instruction, the flag will not be
cleared.
An alternative method is to avoid the setting of interrupt request flags when pin functions are
switched by keeping the pins at the high level so that the conditions in table 3-5 do not occur.
Interrupts masked. (Another possibility
is to disable the relevant interrupt in
interrupt enable register 1.)
←
CCR I bit
1
Set port mode register bit
After setting the port mode register bit,
first execute at least one instruction
(e.g., NOP), then clear the interrupt
request flag to 0
Execute NOP instruction
Clear interrupt request flag to 0
←
Interrupt mask cleared
CCR I bit
0
Figure 3-8 Port Mode Register Setting and Interrupt Request Flag
Clearing Procedure
87
Section 4 Clock Pulse Generators
4.1 Overview
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a
system clock pulse generator and a subclock pulse generator. The system clock pulse generator
consists of a system clock oscillator and system clock dividers. The subclock pulse generator
consists of a subclock oscillator circuit and a subclock divider.
4.1.1 Block Diagram
Figure 4-1 shows a block diagram of the clock pulse generators.
øOSC/2
øOSC
OSC1
OSC2
System clock
oscillator
System clock
divider (1/2)
ø
øOSC/16
System clock
divider (1/8)
(fOSC
)
ø/2
to
ø/8192
Prescaler S
(13 bits)
System clock pulse generator
øW
øW/2
øW
Subclock
divider
(1/2, 1/4, 1/8)
)
X1
X2
øW/4
øW/8
Subclock
oscillator
øSUB
(fW
øW /2
øW /4
øW /8
to
Prescaler W
(5 bits)
Subclock pulse generator
øW /128
Figure 4-1 Block Diagram of Clock Pulse Generators
4.1.2 System Clock and Subclock
The basic clock signals that drive the CPU and on-chip peripheral modules are ø and ø
. Four
SUB
of the clock signals have names: ø is the system clock, ø
is the subclock, ø
is the oscillator
SUB
OSC
clock, and ø is the watch clock.
W
The clock signals available for use by peripheral modules are ø/2, ø/4, ø/8, ø/16, ø/32, ø/64, ø/128,
ø/256, ø/512, ø/1024, ø/2048, ø/4096, ø/8192, ø , ø /2, ø /4, ø /8, ø /16, ø /32, ø /64, and
W
W
W
W
W
W
W
ø /128. The clock requirements differ from one module to another.
W
89
4.2 System Clock Generator
Clock pulse can be supplied to the system clock divider either by connecting a crystal or ceramic
oscillator, or by providing external clock input.
1. Connecting a crystal oscillator
Figure 4-2 shows a typical method of connecting a crystal oscillator.
C1
OSC1
Rf
Rf = 1 MΩ ±20%
C1 = C2 = 12 pF ±20%
OSC2
C2
Figure 4-2 Typical Connection to Crystal Oscillator
Figure 4-3 shows the equivalent circuit of a crystal oscillator. An oscillator having the
characteristics given in table 4-1 should be used.
CS
LS
RS
OSC1
OSC2
C0
Figure 4-3 Equivalent Circuit of Crystal Oscillator
Table 4-1 Crystal Oscillator Parameters
Frequency (MHz)
Rs max (Ω)
2
4
8
10
30
500
7
100
50
Co max (pF)
90
2. Connecting a ceramic oscillator
Figure 4-4 shows a typical method of connecting a ceramic oscillator.
C1
OSC1
Rf
Rf = 1 MΩ ±20%
C1 = 30 pF ±10%
C2 = 30 pF ±10%
OSC2
C2
Ceramic oscillator: Murata
Figure 4-4 Typical Connection to Ceramic Oscillator
3. Notes on board design
When generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention
to the following points.
Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely
affected by induction currents. (See figure 4-5.)
The board should be designed so that the oscillator and load capacitors are located as close as
possible to pins OSC and OSC .
1
2
To be avoided
Signal A Signal B
C2
OSC1
OSC2
C1
Figure 4-5 Board Design of Oscillator Circuit
91
4. External clock input method
Connect an external clock signal to pin OSC1, and leave pin OSC open. Figure 4-6 shows a
2
typical connection.
OSC1
OSC2
External clock input
Open
Figure 4-6 External Clock Input (Example)
Frequency
Oscillator Clock (øOSC)
Duty cycle
45% to 55%
92
4.3 Subclock Generator
1. Connecting a 32.768-kHz crystal oscillator
Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal
oscillator, as shown in figure 4-7. Follow the same precautions as noted under 4.2.3 for the
system clock.
C1
X1
X2
C1 = C2 = 15 pF (typ.)
C2
Figure 4-7 Typical Connection to 32.768-kHz Crystal Oscillator (Subclock)
Figure 4-8 shows the equivalent circuit of the 32.768-kHz crystal oscillator.
CS
LS
RS
X1
X2
C0
C0 = 1.5 pF typ
RS = 14 kΩ typ
fW = 32.768 kHz
Crystal oscillator: MX38T
(Nihon Denpa Kogyo)
Figure 4-8 Equivalent Circuit of 32.768-kHz Crystal Oscillator
93
2. Inputting an external clock
(1) Circuit configuration
An external clock is input to the X pin. The X pin should be left open.
1
2
An example of the connection in this case is shown in figure 4-9.
External clock input
X1
X2
Open
Figure 4-9 Example of Connection when Inputting an External Clock
(2) External clock
Input a square waveform to the X pin. When using the CPU, timer A, timer C, timer G, or an
1
LCD, with a subclock (øw) clock selected, do not stop the clock supply to the X pin.
1
txH
VIH
VIL
txr
txf
txL
Figure 4-10 External Subclock Timing
The DC characteristics and timing of an external clock input to the X pin are shown in table 4-2.
1
94
Table 4-2 DC Characteristics and Timing
(V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C,
CC
CC
SS
SS
a
unless otherwise specified, including subactive mode)
Values
Typ
Applicable Test
Item
Symbol Pin
Conditions Min
Max
Unit Notes
Input high voltage
Input low voltage
VIH
VIL
txr
X1
VCC –0.3
–0.3
—
—
—
VCC +0.3
0.3
V
Figure 4.10
External subclock
rise time
—
100
ns
Figure 4.10
External subclock
fall time
txf
—
—
100
—
External subclock
oscillation frequency
fx
—
32.768
—
kHz
µs
External subclock
high width
txH
txL
12.0
12.0
—
Figure 4.10
External subclock
low width
—
—
µs
3. Pin connection when not using subclock
When the subclock is not used, connect pin X to V and leave pin X open, as shown in
1
CC
2
figure 4-11.
VCC
X1
X2
Open
Figure 4-11 Pin Connection when not Using Subclock
95
4.4 Prescalers
The H8/3834U Series is equipped with two on-chip prescalers having different input clocks
(prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock (ø) as its
input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules.
Prescaler W is a 5-bit counter using a 32.768-kHz signal divided by 4 (ø /4) as its input clock.
W
Its prescaled outputs are used by timer A as a time base for timekeeping.
1. Prescaler S (PSS)
Prescaler S is a 13-bit counter using the system clock (ø) as its input clock. It is incremented once
per clock period.
Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state.
In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse
generator stops. Prescaler S also stops and is initialized to H'0000.
The CPU cannot read or write prescaler S.
The output from prescaler S is shared by timer A, timer B, timer C, timer F, timer G, SCI1, SCI2,
SCI3, the A/D converter, LCD controller, and 14-bit PWM. The divider ratio can be set separately
for each on-chip peripheral function.
In active (medium-speed) mode the clock input to prescaler S is ø
2. Prescaler W (PSW)
/16.
OSC
Prescaler W is a 5-bit counter using a 32.768 kHz signal divided by 4 (ø /4) as its input clock.
W
Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state.
Even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler W continues
functioning so long as clock signals are supplied to pins X and X .
1
2
Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register A (TMA).
Output from prescaler W can be used to drive timer A, in which case timer A functions as a time
base for timekeeping.
96
4.5 Note on Oscillators
Oscillator characteristics of both the masked ROM and ZTAT™ versions are closely related to
board design and should be carefully evaluated by the user, referring to the examples shown in this
section. Oscillator circuit constants will differ depending on the oscillator element, stray
capacitance in its interconnecting circuit, and other factors. Suitable constants should be
determined in consultation with the oscillator element manufacturer. Design the circuit so that the
oscillator element never receives voltages exceeding its maximum rating.
97
Section 5 Power-Down Modes
5.1 Overview
The H8/3834U Series has seven modes of operation after a reset. These include six power-down
modes, in which power dissipation is significantly reduced.
Table 5-1 gives a summary of the seven operation modes. All but the active (high-speed) mode
are power-down modes.
Table 5-1 Operation Modes
Operating Mode
Description
Active (high-speed) mode
The CPU runs on the system clock, executing program
instructions at high speed
Active (medium-speed) mode
Subactive mode
Sleep mode
The CPU runs on the system clock, executing program
instructions at reduced speed
The CPU runs on the subclock, executing program instructions
at reduced speed
The CPU halts. On-chip peripheral modules continue to
operate on the system clock.
Subsleep mode
Watch mode
The CPU halts. Timer A, timer C, timer G, and the LCD
controller/driver continue to operate on the subclock.
The CPU halts. The time-base function of timer A and the LCD
controller/driver continue to operate on the subclock.
Standby mode
The CPU and all on-chip peripheral modules stop operating
In this section the two active modes (high-speed and medium-speed) are referred to collectively as
active mode.
99
Figure 5-1 shows the transitions among these operation modes. Table 5-2 indicates the internal
states in each mode.
Program execution state
LSON = 0, MSON = 0
Program halt state
Reset state
Program halt state
Active (high-speed)
mode
*
4
SSBY = 1,
TMA3 = 0,
LSON = 0
*
1
SSBY = 0,
LSON = 0
*
3
Standby mode
Sleep mode
LSON = 0,
MSON = 1
*
3
*
4
Active
(medium-speed)
mode
*
1
SSBY = 1,
TMA3 = 1
Watch mode
SSBY = 0,
LSON = 1,
TMA3 = 1
*
1
LSON = 1,
TMA3 = 1
SLEEP
instruction
Subactive mode
Subsleep mode
*
2
Power-down mode
: Transition caused by exception handling
A transition between different modes cannot be made to occur simply because an interrupt request is
generated. Make sure that the interrupt is accepted and interrupt handling is performed.
Details on the mode transition conditions are given in the explanations of each mode, in sections 5.2
through 5.8.
Notes: 1. Timer A interrupt, IRQ0 interrupt, WKP0 to WKP7 interrupts
2. Timer A interrupt, timer C interrupt, timer G interrupt, IRQ0 to IRQ 4 interrupts,
WKP0 to WKP7 interrupts
3. All interrupts
4. IRQ0 interrupt, IRQ1 interrupt, WKP0 to WKP7 interrupts
Figure 5-1 Operation Mode Transition Diagram
100
Table 5-2 Internal State in Each Operation Mode
Active Mode
High
Speed
Medium
Speed
Sleep
Mode
Watch
Mode
Subactive Subsleep Standby
Function
Mode
Mode
Mode
System clock oscillator Functions Functions Functions Halted
Subclock oscillator
Halted
Halted
Halted
Functions Functions Functions Functions Functions Functions Functions
CPU
operation
Instructions Functions Functions Halted
Halted
Functions Halted
Retained
Halted
RAM
Retained
Retained
Retained
Registers
I/O
Retained*1
External IRQ0
Functions Functions Functions Functions Functions Functions Functions
interrupts
IRQ1
Retained*6
IRQ2
IRQ3
Retained*6
IRQ4
WKP0
Functions Functions Functions Functions Functions Functions Functions
WKP1
WKP2
WKP3
WKP4
WKP5
WKP6
WKP7
Peripheral Timer A
Functions Functions Functions Functions*5 Functions*5 Functions*5 Retained
module
functions
Timer C
Timer B
Retained
Retained
Retained
Functions/ Functions/
Retained*2 Retained*2
Timer F
Timer G
Retained
Retained
Functions/ Functions/
Retained*3 Retained*3
SCI1
SCI2
SCI3
PWM
A/D
Functions Functions Functions Retained
Reset
Retained
Retained
Retained
Reset
Reset
Reset
Functions Functions Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Functions Functions Functions Retained
LCD
Functions Functions Functions Functions/ Functions/ Functions/ Retained
Retained*4 Retained*4 Retained*4
Notes: 1. Register contents held; high-impedance output.
2. Functions only if external clock or øW/4 internal clock is selected; otherwise halted and retained.
3. Functions only if øW/2 internal clock is selected; otherwise halted and retained.
4. Functions only if øW or øW/2 internal clock is selected; otherwise halted and retained.
5. Functions when timekeeping time-base function is selected.
6. External interrupt requests are ignored. The interrupt request register contents are not affected.
101
5.1.1 System Control Registers
The operation mode is selected using the system control registers described in table 5-3.
Table 5-3 System Control Register
Name
Abbreviation
SYSCR1
R/W
R/W
R/W
Initial Value
H'07
Address
H'FFF0
H'FFF1
System control register 1
System control register 2
SYSCR2
H'E0
1. System control register 1 (SYSCR1)
Bit
7
SSBY
0
6
STS2
0
5
STS1
0
4
3
2
1
—
1
0
STS0
0
LSON
0
—
1
—
1
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
—
—
—
SYSCR1 is an 8-bit read/write register for control of the power-down modes.
Bit 7: Software standby (SSBY)
This bit designates transition to standby mode or watch mode.
Bit 7
SSBY
Description
0
• When a SLEEP instruction is executed in active mode, a transition
is made to sleep mode.
(initial value)
• When a SLEEP instruction is executed in subactive mode, a transition is made to
subsleep mode.
1
• When a SLEEP instruction is executed in active mode, a transition is made to
standby mode or watch mode.
• When a SLEEP instruction is executed in subactive mode, a transition is made to
watch mode.
Bits 6 to 4: Standby timer select 2 to 0 (STS2 to STS0)
These bits designate the time the CPU and peripheral modules wait for stable clock operation after
exiting from standby mode or watch mode to active mode due to an interrupt. The designation
should be made according to the clock frequency so that the waiting time is at least 10 ms.
102
Bit 6
Bit 5
Bit 4
STS2
STS1
STS0
Description
0
0
0
0
1
0
0
1
1
*
0
1
0
1
*
Wait time = 8,192 states
Wait time = 16,384 states
Wait time = 32,768 states
Wait time = 65,536 states
Wait time = 131,072 states
(initial value)
Note: * Don’t care
Bit 3: Low speed on flag (LSON)
This bit chooses the system clock (ø) or subclock (ø
) as the CPU operating clock when watch
SUB
mode is cleared. The resulting operation mode depends on the combination of other control bits
and interrupt input.
Bit 3
LSON
Description
0
1
The CPU operates on the system clock (ø)
(initial value)
The CPU operates on the subclock (øSUB
)
Bits 2 to 0: Reserved bits
These bits are reserved; they are always read as 1, and cannot be modified.
2. System control register 2 (SYSCR2)
Bit
7
—
1
6
—
1
5
—
1
4
3
2
1
0
NESEL DTON MSON
SA1
0
SA0
0
Initial value
Read/Write
0
0
0
—
—
—
R/W
R/W
R/W
R/W
R/W
SYSCR2 is an 8-bit read/write register for power-down mode control.
Bits 7 to 5: Reserved bits
These bits are reserved; they are always read as 1, and cannot be modified.
Bit 4: Noise elimination sampling frequency select (NESEL)
This bit selects the frequency at which the watch clock signal (ø ) generated by the subclock
W
pulse generator is sampled, in relation to the oscillator clock (ø
) generated by the system clock
OSC
pulse generator. When ø
= 2 to 10 MHz, clear NESEL to 0.
OSC
103
Bit 4
NESEL
Description
0
1
Sampling rate is øOSC/16
Sampling rate is øOSC/4
Bit 3: Direct transfer on flag (DTON)
This bit designates whether or not to make direct transitions among active (high-speed), active
(medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which
the transition is made after the SLEEP instruction is executed depends on a combination of this
and other control bits.
Bit 3
DTON
Description
0
When a SLEEP instruction is executed in active mode, a transition
is made to standby mode, watch mode, or sleep mode.
(initial value)
When a SLEEP instruction is executed in subactive mode, a transition is made to
watch mode or subsleep mode.
1
When a SLEEP instruction is executed in active (high-speed) mode, a direct
transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1.
When a SLEEP instruction is executed in active (medium-speed) mode, a direct
transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and LSON =
0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1.
When a SLEEP instruction is executed in subactive mode, a direct transition is made
to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 0, or to
active (medium-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 1.
Bit 2: Medium speed on flag (MSON)
After standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active
(medium-speed) mode.
Bit 2
MSON
Description
0
1
Operation is in active (high-speed) mode
Operation is in active (medium-speed) mode
(initial value)
104
Bits 1 and 0: Subactive mode clock select (SA1 and SA0)
These bits select the CPU clock rate (ø /2, ø /4, or ø /8) in subactive mode. SA1 and SA0
W
W
W
cannot be modified in subactive mode.
Bit 1
SA1
Bit 0
SA0
Description
øW/8
0
0
1
0
1
*
(initial value)
øW/4
øW/2
Note: * Don’t care
5.2 Sleep Mode
5.2.1 Transition to Sleep Mode
The system goes from active mode to sleep mode when a SLEEP instruction is executed while the
SSBY and LSON bits in system control register 1 (SYSCR1) are cleared to 0. In sleep mode CPU
operation is halted but the on-chip peripheral functions other than PWM are operational. The
CPU register contents are retained.
5.2.2 Clearing Sleep Mode
Sleep mode is cleared by an interrupt (timer A, timer B, timer C, timer F, timer G, IRQ to IRQ ,
0
4
WKP to WKP , SCI1, SCI2, SCI3, A/D converter) or by input at the RES pin.
0
7
•
Clearing by interrupt
When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts.
Operation resumes in active (high-speed) mode if MSON = 0 in SYSCR2, or active (medium-
speed) mode if MSON = 1. Sleep mode is not cleared if the I bit of the condition code register
(CCR) is set to 1 or the particular interrupt is disabled in the interrupt enable register.
•
Clearing by RES input
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.
105
5.3 Standby Mode
5.3.1 Transition to Standby Mode
The system goes from active mode to standby mode when a SLEEP instruction is executed while
the SSBY bit in SYSCR1 is set to 1, the LSON bit is cleared to 0, and bit TMA3 in timer
register A (TMA) is cleared to 0. In standby mode the clock pulse generator stops, so the CPU
and on-chip peripheral modules stop functioning. As long as a minimum required voltage is
applied, the CPU register contents and data in the on-chip RAM will be retained. The I/O ports go
to the high-impedance state.
5.3.2 Clearing Standby Mode
Standby mode is cleared by an interrupt (IRQ , IRQ , WKP to WKP ) or by input at the RES
0
1
0
7
pin.
•
Clearing by interrupt
When an interrupt is requested, the system clock pulse generator starts. After the time set in bits
STS2–STS0 in SYSCR1 has elapsed, a stable system clock signal is supplied to the entire chip,
standby mode is cleared, and interrupt exception handling starts. Operation resumes in active
(high-speed) mode if MSON = 0 in SYSCR2, or active (medium-speed) mode if MSON = 1.
Standby mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in
the interrupt enable register.
•
Clearing by RES input
When the RES pin goes low, the system clock pulse generator starts and standby mode is cleared.
After the pulse generator output has stabilized, if the RES pin is driven high, the CPU starts reset
exception handling.
Since system clock signals are supplied to the entire chip as soon as the system clock pulse
generator starts functioning, the RES pin should be kept at the low level until the pulse generator
output stabilizes.
5.3.3 Oscillator Settling Time after Standby Mode is Cleared
Bits STS2 to STS0 in SYSCR1 should be set as follows.
•
When a crystal oscillator is used
The table below gives settings for various operating frequencies. Set bits STS2 to STS0 for a
waiting time of at least 10 ms.
106
•
When an external clock is used
Any values may be set. Normally the minimum time (STS2 = STS1 = STS0 = 0) should be set.
Table 5-3 Clock Frequency and Settling Time (times are in ms)
STS2
STS1
STS0
Waiting Time
8,192 states
5 MHz
1.6
4 MHz
2.0
2 MHz
4.1
1 MHz
8.2
0.5 MHz
16.4
0
0
0
0
1
0
0
1
1
*
0
1
0
1
*
16,384 states
32,768 states
65,536 states
131,072 states
3.2
4.1
8.2
16.4
32.8
65.5
131.1
32.8
6.6
8.2
16.4
32.8
65.5
65.5
13.1
26.2
16.4
32.8
131.1
262.1
Note: * Don’t care
5.3.4 Transition to Standby Mode and Port Pin States
The system goes from active (high-speed or medium-speed) mode to standby mode when a
SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit is cleared
to 0, and bit TMA3 in TMA is cleared to 0. Port pins (except those with their MOS pull-up turned
on) enter high-impedance state when the transition to standby mode is made. This timing is
shown in figure 5-2.
φ
Internal
data bus
SLEEP instruction fetch
Next instruction fetch
SLEEP instruction
execution
Internal
processing
Output
High-impedance
Standby mode
Port pins
Active (high-speed or medium-speed) mode
Figure 5-2 Transition to Standby Mode and Port Pin States
107
5.4 Watch Mode
5.4.1 Transition to Watch Mode
The system goes from active or subactive mode to watch mode when a SLEEP instruction is
executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1.
In watch mode, operation of on-chip peripheral modules other than timer A and the LCD
controller is halted. The LCD controller can be selected to operate or to halt. As long as a
minimum required voltage is applied, the contents of CPU registers and some registers of the on-
chip peripheral modules, and the on-chip RAM contents, are retained. I/O ports keep the same
states as before the transition.
5.4.2 Clearing Watch Mode
Watch mode is cleared by an interrupt (timer A, IRQ , WKP to WKP ) or by a low input at the
0
0
7
RES pin.
•
Clearing by interrupt
Watch mode is cleared when an interrupt is requested. The mode to which a transition is made
depends on the settings of LSON in SYSCR1 and MSON in SYSCR2. If both LSON and MSON
are cleared to 0, transition is to active (high-speed) mode; if LSON = 0 and MSON = 1, transition
is to active (medium-speed) mode; if LSON = 1, transition is to subactive mode. When the
transition is to active mode, after the time set in SYSCR1 bits STS2 to STS0 has elapsed, a stable
clock signal is supplied to the entire chip, watch mode is cleared, and interrupt exception handling
starts. Watch mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is
disabled in the interrupt enable register.
•
Clearing by RES input
Clearing by RES pin is the same as for standby mode; see 5.3.2, Clearing Standby Mode.
5.4.3 Oscillator Settling Time after Watch Mode is Cleared
The waiting time is the same as for standby mode; see 5.3.3, Oscillator Settling Time after
Standby Mode is Cleared.
108
5.5 Subsleep Mode
5.5.1 Transition to Subsleep Mode
The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed
while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in
TMA is set to 1.
In subsleep mode, operation of on-chip peripheral modules other than timer A, timer C, timer G,
and the LCD controller is halted. As long as a minimum required voltage is applied, the contents
of CPU registers and some registers of the on-chip peripheral modules, and the on-chip RAM
contents, are retained. I/O ports keep the same states as before the transition.
5.5.2 Clearing Subsleep Mode
Subsleep mode is cleared by an interrupt (timer A, timer C, timer G, IRQ to IRQ , WKP to
0
4
0
WKP ) or by a low input at the RES pin.
7
•
Clearing by interrupt
When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts.
Subsleep mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in
the interrupt enable register.
•
Clearing by RES input
Clearing by RES pin is the same as for standby mode; see 5.3.2, Clearing Standby Mode.
109
5.6 Subactive Mode
5.6.1 Transition to Subactive Mode
Subactive mode is entered from watch mode if a timer A, IRQ , or WKP to WKP interrupt is
0
0
7
requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode, subactive mode is
entered if a timer A, timer C, timer G, IRQ to IRQ , or WKP to WKP interrupt is requested.
0
4
0
7
A transition to subactive mode does not take place if the I bit of CCR is set to 1 or the particular
interrupt is disabled in the interrupt enable register.
5.6.2 Clearing Subactive Mode
Subactive mode is cleared by a SLEEP instruction or by a low input at the RES pin.
•
Clearing by SLEEP instruction
If a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and TMA3 bit in
TMA is set to 1, subactive mode is cleared and watch mode is entered. If a SLEEP instruction is
executed while SSBY = 0 and LSON = 1 in SYSCR1 and TMA3 = 1 in TMA, subsleep mode is
entered. Direct transfer to active mode is also possible; see 5.8, Direct Transfer, below.
•
Clearing by RES pin
Clearing by RES pin is the same as for standby mode; see 5.3.2, Clearing Standby Mode.
5.6.3 Operating Frequency in Subactive Mode
The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices
are ø /2, ø /4, and ø /8.
W
W
W
110
5.7 Active (medium-speed) Mode
5.7.1 Transition to Active (medium-speed) Mode
If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition
to active (medium-speed) mode results from IRQ , IRQ , or WKP to WKP interrupts in standby
0
1
0
7
mode, timer A, IRQ , or WKP to WKP interrupts in watch mode, or any interrupt in sleep
0
0
7
mode. A transition to active (medium-speed) mode does not take place if the I bit of CCR is set to
1 or the particular interrupt is disabled in the interrupt enable register.
5.7.2 Clearing Active (medium-speed) Mode
Active (medium-speed) mode is cleared by a SLEEP instruction or by a low input at the RES pin.
•
Clearing by SLEEP instruction
A transition to standby mode takes place if a SLEEP instruction is executed while the SSBY bit in
SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and TMA3 bit in TMA is cleared to
0. The system goes to watch mode if the SSBY bit in SYSCR1 is set to 1 and TMA3 bit in TMA
is set to 1 when a SLEEP instruction is executed. Sleep mode is entered if both SSBY and LSON
are cleared to 0 when a SLEEP instruction is executed. Direct transfer to active (high-speed)
mode or to subactive mode is also possible. See 5.8, Direct Transfer, below for details.
•
Clearing by RES pin
When the RES pin goes low, the CPU enters the reset state and active (medium-speed) mode is
cleared.
5.7.3 Operating Frequency in Active (medium-speed) Mode
In active (medium-speed) mode, the CPU is clocked at 1/8 the frequency in active (high-speed)
mode.
111
5.8 Direct Transfer
5.8.1 Direct Transfer Overview
The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed)
mode, and subactive mode. A direct transfer is a transition among these three modes without the
stopping of program execution. A direct transfer can be made by executing a SLEEP instruction
while the DTON bit in SYSCR2 is set to 1. After the mode transition, direct transfer interrupt
exception handling starts.
If the direct transfer interrupt is disabled in interrupt enable register 2 (IENR2), a transition is
made instead to sleep mode or watch mode. Note that if a direct transition is attempted while the I
bit in CCR is set to 1, sleep mode or watch mode will be entered, and it will be impossible to clear
the resulting mode by means of an interrupt.
•
Direct transfer from active (high-speed) mode to active (medium-speed) mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON
bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON bit in
SYSCR2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode.
•
Direct transfer from active (medium-speed) mode to active (high-speed) mode
When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and
LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON
bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep mode.
•
Direct transfer from active (high-speed) mode to subactive mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON
bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and TMA3 bit in TMA is set
to 1, a transition is made to subactive mode via watch mode.
•
Direct transfer from subactive mode to active (high-speed) mode
When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set
to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, the
DTON bit in SYSCR2 is set to 1, and TMA3 bit in TMA is set to 1, a transition is made directly to
active (high-speed) mode via watch mode after the waiting time set in SYSCR1 bits STS2 to
STS0 has elapsed.
112
•
Direct transfer from active (medium-speed) mode to subactive mode
When a SLEEP instruction is executed in active (medium-speed) while the SSBY and LSON bits
in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and TMA3 bit in TMA is set to 1, a
transition is made to subactive mode via watch mode.
•
Direct transfer from subactive mode to active (medium-speed) mode
When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set
to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, the DTON bit
in SYSCR2 is set to 1, and TMA3 bit in TMA is set to 1, a transition is made directly to active
(medium-speed) mode via watch mode after the waiting time set in SYSCR1 bits STS2 to STS0
has elapsed.
5.8.2 Calculation of Direct Transfer Time before Transition
•
Time required before direct transfer from active (high-speed) mode to active (medium-speed)
mode
A direct transfer is made from active (high-speed) mode to active (medium-speed) mode when a
SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in
SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON bit in SYSCR2 is
set to 1. A direct transfer time, that is, the time from SLEEP instruction execution to interrupt
exception handling completion is calculated by expression (1) below.
Direct transfer time = (number of states for SLEEP instruction execution + number of states for
internal processing) × tcyc before transition + number of states for interrupt
exception handling execution × tcyc after transition
...... (1)
Example: Direct transfer time for the H8/3834U Series
= (2 + 1) × 2tosc + 14 × 16tosc = 230 tosc
Notation:
tosc: OSC clock cycle time
tcyc: System clock (φ) cycle time
•
Time required before direct transfer from active (medium-speed) mode to active (high-speed)
mode
A direct transfer is made from active (medium-speed) mode to active (high-speed) mode when a
SLEEP instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in
SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in
SYSCR2 is set to 1. A direct transfer time, that is, the time from SLEEP instruction execution to
interrupt exception handling completion is calculated by expression (2) below.
113
Direct transfer time = (number of states for SLEEP instruction execution + number of states for
internal processing) × tcyc before transition + number of states for interrupt
exception handling execution × tcyc after transition
...... (2)
Example: Direct transfer time for the H8/3834U Series
= (2 + 1) × 16tosc + 14 × 2tosc = 76 tosc
Notation:
tosc: OSC clock cycle time
tcyc: System clock (φ) cycle time
•
Time required before direct transfer from subactive mode to active (high-speed) mode
A direct transfer is made from subactive mode to active (high-speed) mode when a SLEEP
instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit
in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, the DTON bit in SYSCR2 is
set to 1, and the TMA3 bit in TMA is set to 1. A direct transfer time, that is, the time from
SLEEP instruction execution to interrupt exception handling completion is calculated by
expression (3) below.
Direct transfer time = (number of states for SLEEP instruction execution + number of states for
internal processing) × tsubcyc before transition + (wait time designated by
STS2 to STS0 bits in SCR + number of states for interrupt exception
handling execution) × tcyc after transition
...... (3)
Example: Direct transfer time for the H8/3834U Series
(when CPU clock frequency is φw/8 and wait time is 8192 states)
= (2 + 1) × 8tw + (8192 + 14) × 2tosc = 24tw + 16412tosc
Notation:
tosc: OSC clock cycle time
tw: Watch clock cycle time
tcyc: System clock (φ) cycle time
tsubcyc: Subclock (φSUB) cycle time
•
Time required before direct transfer from subactive mode to active (medium-speed) mode
A direct transfer is made from subactive mode to active (medium-speed) mode when a SLEEP
instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit
in SYSCR1 is cleared to 0, the MSON and DTON bits in SYSCR2 are set to 1, and the TMA3 bit
in TMA is set to 1. A direct transfer time, that is, the time from SLEEP instruction execution to
interrupt exception handling completion is calculated by expression (4) below.
Direct transfer time = (number of states for SLEEP instruction execution + number of states for
internal processing) × tsubcyc before transition + (wait time designated by
114
STS2 to STS0 bits in SCR + number of states for interrupt exception
handling execution) × tcyc after transition
...... (4)
Example: Direct transfer time for the H8/3834U Series
(when CPU clock frequency is φw/8 and wait time is 8192 states)
= (2 + 1) × 8tw + (8192 + 14) × 16tosc = 24tw + 131296tosc
Notation:
tosc: OSC clock cycle time
tw: Watch clock cycle time
tcyc: System clock (φ) cycle time
tsubcyc: Subclock (φSUB) cycle time
115
Section 6 ROM
6.1 Overview
The H8/3833U has 24 kbytes of on-chip ROM, while the H8/3834U has 32 kbytes, the H8/3835U
has 40 kbytes, the H8/3836U has 48 kbytes, and the H8/3837U has 60 kbytes. The ROM is
connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data
and word data. The ZTAT™ versions of the H8/3834U and H8/3837U each have 32 kbytes and
60 kbytes of PROM.
6.1.1 Block Diagram
Figure 6-1 shows a block diagram of the on-chip ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'0000
H'0002
H'0000
H'0002
H'0001
H'0003
On-chip ROM
H'7FFE
H'7FFE
H'7FFF
Even-numbered
address
Odd-numbered
address
Figure 6-1 ROM Block Diagram (H8/3834U)
117
6.2 H8/3834U PROM Mode
6.2.1 Setting to PROM Mode
If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a
microcontroller and allows the PROM to be programmed in the same way as the standard
HN27C256 EPROM. Table 6-1 shows how to set the chip to PROM mode.
Table 6-1 Setting to PROM Mode
Pin Name
TEST
Setting
High level
Low level
PB4/AN4
PB5/AN5
PB6/AN6
High level
6.2.2 Socket Adapter Pin Arrangement and Memory Map
A standard PROM programmer can be used to program the PROM. A socket adapter is required
for conversion to 28 pins, as listed in table 6-2.
Figure 6-2 shows the pin-to-pin wiring of the socket adapter. Figure 6-3 shows a memory map.
Table 6-2 Socket Adapter
Package
Socket Adapter
HS3834ESH01H
HS3834ESF01H
HS3834ESN01H
100-pin (FP-100B)
100-pin (FP-100A)
100-pin (TFP-100B)
118
H8/3834U
EPROM socket
FP-100A
12
47
48
49
50
51
52
53
54
70
69
68
67
66
65
64
63
55
91
57
58
59
60
61
62
56
34, 79
92
6
FP-100B
9
Pin
RES
P60
P61
P62
P63
P64
P65
P66
P67
P87
P86
P85
P84
P83
P82
P81
P80
P70
P43
P72
P73
P74
P75
P76
P77
P71
VCC
AVCC
TEST
X1
Pin
HN27C256
VPP
EO0
EO1
EO2
EO3
EO4
EO5
EO6
EO7
EA0
EA1
EA2
EA3
EA4
EA5
EA6
EA7
EA8
EA9
EA10
EA11
EA12
EA13
EA14
CE
1
44
45
46
47
48
49
50
51
67
66
65
64
63
62
61
60
52
88
54
55
56
57
58
59
53
31, 76
89
3
11
12
13
15
16
17
18
19
10
9
8
7
6
5
4
3
25
24
21
23
2
26
27
20
22
28
OE
VCC
8
5
99
13
81
82
83
9, 30
5
96
10
78
79
80
6, 27
2
PB6
MD0
P11
P12
P13
VSS
AVSS
PB4
PB5
P14
P15
P16
VSS
14
97
98
84
85
86
94
95
81
82
83
Note: Pins not indicated in the figure should be left open.
Figure 6-2 Socket Adapter Pin Correspondence (with HN27C256)
119
Address in MCU mode
H'0000
Address in PROM mode
H'0000
On-chip PROM
H'7FFF
H'7FFF
Figure 6-3 H8/3834U Memory Map in PROM Mode
Note: When programming with a PROM programmer, be sure to specify addresses from H'0000 to
H'7FFF.
120
6.3 H8/3834U Programming
The write, verify, and other modes are selected as shown in table 6-3 in H8/3834U PROM mode.
Table 6-3 Mode Selection in H8/3834U PROM Mode
Pin
Mode
CE
L
OE
H
VPP
VPP
VPP
VPP
VCC
VCC
VCC
VCC
EO7 to EO0
Data input
EA14 to EA0
Address input
Address input
Address input
Write
Verify
H
L
Data output
High impedance
Programming disabled
H
H
Notation:
L:
H:
Low level
High level
V
V
PP: VPP level
CC: VCC level
The specifications for writing and reading the on-chip PROM are identical to those for the
standard HN27C256 EPROM.
6.3.1 Writing and Verifying
An efficient, high-performance programming method is available for writing and verifying the
PROM data. This method achieves high speed without voltage stress on the device and without
lowering the reliability of written data. H'FF data is written in unused address areas.
The basic flow of this high-performance programming method is shown in figure 6-4. Table 6-4
and table 6-5 give the electrical characteristics in programming mode. Figure 6-5 shows a
write/verify timing diagram.
121
Start
Set write/verify mode
VCC = 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V
Address = 0
n = 0
n + 1→ n
Yes
n < 25
No
Write time tPW = 1 ms ± 5%
No Go
Verify
Go
Address + 1→ address
Write time tOPW = 3n ms
No
Last address?
Yes
Set read mode
VCC = 5.0 V ± 0.5 V, VPP = VCC
No
All
Error
addresses read?
Yes
End
Figure 6-4 High-Performance Programming Flowchart
122
Table 6-4 DC Characteristics
(Conditions: V = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V, V = 0 V, T = 25°C ±5°C)
CC
PP
SS
a
Test
Item
Symbol Min
Typ
Max
Unit Conditions
Input high-
level voltage OE, CE
EO7 to EO0, EA14 to EA0, VIH
2.4
–0.3
2.4
—
—
VCC + 0.3 V
Input low-
level voltage OE, CE
EO7 to EO0, EA14 to EA0, VIL
—
—
—
—
0.8
—
V
V
V
Output high- EO7 to EO0
level voltage
VOH
VOL
IOH = –200 µA
IOL = 0.8 mA
Output low-
level voltage
EO7 to EO0
0.45
2
Input leakage EO7 to EO0, EA14 to EA0, |ILI|
—
µA VIN
=
current
OE, CE
5.25 V/0.5 V
VCC current
VPP current
ICC
IPP
—
—
—
—
40
40
mA
mA
Table 6-5 AC Characteristics
(Conditions: V = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V, T = 25°C ±5°C)
CC
PP
a
Item
Symbol
tAS
Min
2
Typ
—
Max
—
Unit
µs
Test Conditions
Address setup time
OE setup time
Figure 6-5*1
tOES
tDS
2
—
—
µs
Data setup time
2
—
—
µs
Address hold time
Data hold time
tAH
0
—
—
µs
tDH
2
—
—
µs
*2
Data output disable time
VPP setup time
tDF
0
—
130
—
ns
tVPS
tPW
2
—
µs
Programming pulse width
0.95
2.85
1.0
—
1.05
78.7
ms
ms
*3
CE pulse width for overwrite
programming
tOPW
VCC setup time
tVCS
tOE
2
0
—
—
—
µs
ns
Data output delay time
500
Notes: 1. Input pulse level: 0.8 V to 2.2 V
Input rise time/fall time ≤ 20 ns
Timing reference levels Input: 1.0 V, 2.0 V
Output: 0.8 V, 2.0 V
2. tDF is defined at the point at which the output is floating and the output level cannot be
read.
3. tOPW is defined by the value given in figure 6-4 high-performance programming flow chart.
123
Write
Verify
Address
Data
tAH
tAS
Input data
Output data
tDS
tDH
tDF
VPP
VCC
VPP
VCC
CE
tVPS
VCC+1
VCC
tVCS
tPW
tOES
tOE
OE
tOPW
*
Note: *tOPW is defined by the value given in figure 6-4 high-performance programming flow chart.
Figure 6-5 PROM Write/Verify Timing
6.3.2 Programming Precautions
•
Use the specified programming voltage and timing.
The programming voltage in PROM mode (V ) is 12.5 V. Use of a higher voltage can
PP
permanently damage the chip. Be especially careful with respect to PROM programmer
overshoot.
Setting the PROM programmer to Hitachi specifications for the HN27C256 will result in a
correct V of 12.5 V.
PP
•
•
Make sure the index marks on the PROM programmer socket, socket adapter, and chip are
properly aligned. If they are not, the chip may be destroyed by excessive current flow.
Before programming, be sure that the chip is properly mounted in the PROM programmer.
Avoid touching the socket adapter or chip during programming, since this may cause contact
faults and write errors.
124
6.4 H8/3837U PROM Mode
6.4.1 Setting to PROM Mode
If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a
microcontroller and allows the PROM to be programmed in the same way as the standard
HN27C101 EPROM. Table 6-6 shows how to set the chip to PROM mode.
Table 6-6 Setting to PROM Mode
Pin Name
TEST
Setting
High level
Low level
PB4/AN4
PB5/AN5
PB6/AN6
High level
6.4.2 Socket Adapter Pin Arrangement and Memory Map
A standard PROM programmer can be used to program the PROM. A socket adapter is required
for conversion to 32 pins, as listed in table 6-7.
Figure 6-6 shows the pin-to-pin wiring of the socket adapter. Figure 6-7 shows a memory map.
Table 6-7 Socket Adapter
Package
Socket Adapter
HS3836ESH01H
HS3836ESF01H
HS3836ESN01H
100-pin (FP-100B)
100-pin (FP-100A)
100-pin (TFP-100B)
125
H8/3837U
EPROM socket
HN27C101 (32 pins)
FP-100A
12
47
48
49
50
51
52
53
54
70
69
68
67
66
65
64
63
55
91
57
58
59
60
61
84
85
62
56
83
34, 79
92
6
FP-100B
9
Pin
RES
P60
P61
P62
P63
P64
P65
P66
P67
P87
P86
P85
P84
P83
P82
P81
P80
P70
P43
P72
P73
P74
P75
P76
P14
P15
P77
P71
P13
VCC
AVCC
TEST
X1
Pin
VPP
1
44
45
46
47
48
49
50
51
67
66
65
64
63
62
61
60
52
88
54
55
56
57
58
81
82
59
53
80
31, 76
89
3
EO0
EO1
EO2
EO3
EO4
EO5
EO6
EO7
EA0
EA1
EA2
EA3
EA4
EA5
EA6
EA7
EA8
EA9
EA10
EA11
EA12
EA13
EA14
EA15
EA16
CE
13
14
15
17
18
19
20
21
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
22
24
31
32
OE
PGM
VCC
8
5
PB6
MD0
P11
P12
P16
VSS
AVSS
PB4
PB5
99
13
81
82
86
9, 30
5
96
10
78
79
83
6, 27
2
16
VSS
97
98
94
95
Note: Pins not indicated in the figure should be left open.
Figure 6-6 Socket Adapter Pin Correspondence (with HN27C101)
126
Address in
MCU mode
Address in
PROM mode
H'0000
H'0000
On-chip PROM
H'EDFF
H'EDFF
Missing area *
H'1FFFF
Note: * If read in PROM mode, this address area returns unpredictable output data.
When programming with a PROM programmer, be sure to specify addresses
from H'0000 to H'EDFF.
If address H'EE00 and higher addresses are programmed by mistake, it may
become impossible to program the PROM or verify the programmed data.
When programming, assign H'FF data to this address area (H'EE00 to H'1FFFF).
Figure 6-7 H8/3837U Memory Map in PROM Mode
127
6.5 H8/3837U Programming
The write, verify, and other modes are selected as shown in table 6-8 in H8/3837U PROM mode.
Table 6-8 Mode Selection in H8/3837U PROM Mode
Pin
Mode
Write
Verify
CE
L
OE
H
L
PGM
VPP
VPP
VPP
VPP
VCC
VCC
VCC
VCC
EO7 to EO0
Data input
EA16 to EA0
Address input
Address input
Address input
L
L
H
L
Data output
High impedance
Programming
disabled
L
L
L
H
L
H
L
H
H
H
H
Notation
L:
Low level
H: High level
VPP: VPP level
VCC: VCC level
The specifications for writing and reading the on-chip PROM are identical to those for the
standard HN27C101 EPROM. Page programming is not supported, however. The PROM writer
must not be set to page mode. A PROM programmer that provides only page programming mode
cannot be used. When selecting a PROM programer, check that it supports a byte-by-byte high-
speed, high-reliability programming method. Be sure to set the address range to H'0000 to
H'EDFF.
6.5.1 Writing and Verifying
An efficient, high-speed, high-reliability method is available for writing and verifying the PROM
data. This method achieves high speed without voltage stress on the device and without lowering
the reliability of written data. The basic flow of this high-speed, high-reliability programming
method is shown in figure 6-8.
128
Start
Set write/verify mode
VCC = 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V
Address = 0
n = 0
n + 1 → n
Yes
n<25
No
Write time tPW = 0.2 ms ± 5%
No Go
Verify
Address + 1 → address
Go
Write time tOPW = 0.2n ms
No
Last address?
Yes
Set read mode
VCC = 5.0 V ± 0.25 V, VPP = VCC
No
All addresses
Error
read?
Yes
End
Figure 6-8 High-Speed, High-Reliability Programming Flow Chart
129
Table 6-9 and table 6-10 give the electrical characteristics in programming mode.
Table 6-9 DC Characteristics (preliminary)
(Conditions: V = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V, V = 0 V, T = 25°C ±5°C)
CC
PP
SS
a
Test
Item
Symbol Min Typ Max
Unit Conditions
Input high-
level voltage OE, CE, PGM
EO7 to EO0, EA16 to EA0 VIH
2.4
–0.3
2.4
—
—
—
—
—
—
VCC + 0.3 V
Input low-
level voltage OE, CE, PGM
EO7 to EO0, EA16 to EA0 VIL
0.8
—
V
V
V
Output high- EO7 to EO0
level voltage
VOH
VOL
IOH = –200 µA
IOL = 0.8 mA
Output low-
level voltage
EO7 to EO0
0.45
2
Input leakage EO7 to EO0, EA16 to EA0 |ILI|
—
µA Vin = 5.25 V/
0.5 V
current
OE, CE, PGM
VCC current
VPP current
ICC
IPP
—
—
—
—
40
40
mA
mA
130
Table 6-10 AC Characteristics
(Conditions: V = 6.0 V ±0.25 V, V = 12.5 V ±0.3 V, T = 25°C ±5°C)
CC
PP
a
Test
Item
Symbol
tAS
Min
2
Typ
Max
—
Unit
µs
Conditions
Address setup time
OE setup time
—
Figure 6-9*1
tOES
tDS
2
—
—
µs
Data setup time
2
—
—
µs
Address hold time
Data hold time
tAH
0
—
—
µs
tDH
2
—
—
µs
*2
Data output disable time
VPP setup time
tDF
—
2
—
130
—
ns
tVPS
tPW
—
µs
Programming pulse width
0.19
0.19
0.20
—
0.21
5.25
ms
ms
*3
PGM pulse width for overwrite
programming
tOPW
VCC setup time
tVCS
tCES
tOE
2
2
0
—
—
—
—
µs
µs
ns
CE setup time
—
Data output delay time
200
Notes: 1. Input pulse level: 0.45 V to 2.4 V
Input rise time/fall time ≤ 20 ns
Timing reference levels Input: 0.8 V, 2.0 V
Output: 0.8 V, 2.0 V
2. tDF is defined at the point at which the output is floating and the output level cannot be
read.
3. tOPW is defined by the value given in figure 6-8 high-speed, high-reliability programming
flow chart.
131
Figure 6-9 shows a write/verify timing diagram.
Write
Verify
Address
tAH
tAS
Data
Input data
Output data
tDF
tDS
tDH
VPP
VCC
VPP
VCC
CE
tVPS
VCC +1
VCC
tVCS
tCES
PGM
OE
tPW
tOES
tOE
tOPW
*
Note: * tOPW is defined by the value given in figure 6-8 high-speed, high-reliability
programming flow chart.
Figure 6-9 PROM Write/Verify Timing
132
6.5.2 Programming Precautions
• Use the specified programming voltage and timing.
The programming voltage in PROM mode (V ) is 12.5 V. Use of a higher voltage can
PP
permanently damage the chip. Be especially careful with respect to PROM programmer
overshoot.
Setting the PROM programmer to Hitachi specifications for the HN27C101 will result in
correct V of 12.5 V.
PP
•
Make sure the index marks on the PROM programmer socket, socket adapter, and chip are
properly aligned. If they are not, the chip may be destroyed by excessive current flow. Before
programming, be sure that the chip is properly mounted in the PROM programmer.
•
•
•
Avoid touching the socket adapter or chip while programming, since this may cause contact
faults and write errors.
Select the programming mode carefully. The chip cannot be programmed in page
programming mode.
When programming with a PROM programmer, be sure to specify addresses from H'0000 to
H'EDFF. If address H'EE00 and higher addresses are programmed by mistake, it may become
impossible to program the PROM or verify the programmed data. When programming, assign
H'FF data to the address area from H'EE00 to H'1FFFF.
133
6.6 Reliability of Programmed Data
A highly effective way of assuring data retention characteristics after programming is to screen the
chips by baking them at a temperature of 150°C. This quickly eliminates PROM memory cells
prone to initial data retention failure.
Figure 6-10 shows a flowchart of this screening procedure.
Write program and verify contents
Bake at high temperature with power off
125°C to 150°C, 24 hrs to 48 hrs
Read and check program
Install
Figure 6-10 Recommended Screening Procedure
If write errors occur repeatedly while the same PROM programmer is being used, stop
programming and check for problems in the PROM programmer and socket adapter, etc.
Please notify your Hitachi representative of any problems occurring during programming or in
screening after high-temperature baking.
134
Section 7 RAM
7.1 Overview
The H8/3833U and H8/3834U have 1 kbyte of high-speed static RAM on-chip, while the
H8/3835U, H8/3836U, and H8/3837U each have 2 kbytes. The RAM is connected to the CPU by
a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data.
7.1.1 Block Diagram
Figure 7-1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'FB80
H'FB82
H'FB80
H'FB82
H'FB81
H'FB83
On-chip RAM
H'FF7E
H'FF7E
H'FF7F
Even-numbered
address
Odd-numbered
address
Figure 7-1 RAM Block Diagram (H8/3834U)
135
Section 8 I/O Ports
8.1 Overview
The H8/3834U Series is provided with eight 8-bit I/O ports, one 4-bit I/O port, one 3-bit I/O port,
one 8-bit input-only port, one 4-bit input-only port, and one 1-bit input-only port. Table 8-1
indicates the functions of each port.
Each port has of a port control register (PCR) that controls input and output, and a port data
register (PDR) for storing output data. Input or output can be assigned to individual bits.
See 2.9.2, Notes on Bit Manipulation, for information on executing bit-manipulation instructions
to write data in PCR or PDR.
Ports 5, 6, 7, 8, 9, and A double as LCD segment pins and common pins. The choice of pin
functions can be made in 4-bit groupings.
Block diagrams of each port are given in Appendix C.
Table 8-1 Port Functions
Function
Switching
Port
Description
Pins
Other Functions
Register
Port 1 • 8-bit I/O port
P17 to P15/
External interrupts 3 to 1
Timer event input TMIF, TMIC,
TMIB
PMR1
TCRF,
TMC,
TMB
• Input pull-up MOS IRQ3 to IRQ1/
option
TMIF, TMIC,
TMIB
P14/PWM
P13/TMIG
14-bit PWM output
PMR1
PMR1
PMR1
Timer G input capture
Timer F output compare
P12, P11/
TMOFH, TMOFL
P10/TMOW
P27 to P22
P21/UD
Timer A clock output
None
PMR1
Port 2 • 8-bit I/O port
• Open drain output
option
Timer C count-up/down selection
PMR2
P20/IRQ4/
ADTRG
External interrupt 4 and A/D
converter external trigger
PMR2
AMR
• High-current port
137
Table 8-1 Port Functions (cont)
Function
Switching
Register
Port
Description
Pins
Other Functions
Port 3 • 8-bit I/O port
P37/CS
SCI2 chip select input (CS),
strobe output (STRB), data
output (SO2), data input (SI2),
clock input/output (SCK2)
PMR3
• Input pull-up MOS P36/STRB
option
• High-current port
P35/SO2
P34/SI2
P33/SCK2
P32/SO1
P31/SI1
P30/SCK1
SCI1 data output (SO1), data
input (SI1), clock input/output
(SCK1)
PMR3
PMR2
Port 4 • 1-bit input-only port
• 3-bit I/O port
P43/IRQ0
External interrupt 0
P42/TXD
P41/RXD
P40/SCK3
SCI3 data output (TXD), data
input (RXD), clock input/output
(SCK3)
SCR3
SMR3
Port 5 • 8-bit I/O port
P57 to P50/
• Wakeup input (WKP7 to WKP0)
PMR5
LPCR
• Input pull-up MOS WKP7 to WKP0/ • Segment output (SEG8 to SEG1)
option
SEG8 to SEG1
Port 6 • 8-bit I/O port
P67 to P60/
Segment output (SEG16 to SEG9)
LPCR
• Input pull-up MOS SEG16 to SEG9
option
Port 7 • 8-bit I/O port
P77 to P70/
SEG24 to SEG17
Segment output (SEG24 to SEG17)
Segment output (SEG32 to SEG25)
LPCR
LPCR
Port 8 • 8-bit I/O port
Port 9 • 8-bit I/O port
P87 to P80/
SEG32 to SEG25
P97/SEG40/CL1 • Segment output (SEG40 to SEG37) LPCR
P96/SEG39/CL2 • Latch clock (CL1), for external
P95/SEG38/DO
P94/SEG37/M
P93 to P90/
segment expansion, shift clock
(CL2), display data port (DO),
and alternating signal (M)
SEG36 to SEG33 • Segment output (SEG36 to SEG33)
Port A • 4-bit I/O port
Port B • 8-bit input port
Port C • 4-bit input port
PA3 to PA0/
COM4 to COM1
Common output (COM4 to COM1)
A/D converter analog input
A/D converter analog input
LPCR
AMR
AMR
PB7 to PB0/
AN7 to AN0
PC3 to PC0/
AN11 to AN8
138
8.2 Port 1
8.2.1 Overview
Port 1 is an 8-bit I/O port. Figure 8-1 shows its pin configuration.
P17/IRQ3/TMIF
P16/IRQ2/TMIC
P15/IRQ1/TMIB
P14/PWM
Port 1
P13/TMIG
P12/TMOFH
P11/TMOFL
P10/TMOW
Figure 8-1 Port 1 Pin Configuration
8.2.2 Register Configuration and Description
Table 8-2 shows the port 1 register configuration.
Table 8-2 Port 1 Registers
Name
Abbrev.
PDR1
R/W
R/W
W
Initial Value
H'00
Address
H'FFD4
H'FFE4
H'FFE0
H'FFC8
Port data register 1
Port control register 1
Port pull-up control register 1
Port mode register 1
PCR1
H'00
PUCR1
PMR1
R/W
R/W
H'00
H'00
139
1. Port data register 1 (PDR1)
Bit
7
6
5
P15
0
4
3
P13
0
2
P12
0
1
P11
0
0
P17
0
P16
0
P14
0
P10
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR1 is an 8-bit register that stores data for pins P1 through P1 . If port 1 is read while PCR1
7
0
bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states. If port 1 is
read while PCR1 bits are cleared to 0, the pin states are read.
Upon reset, PDR1 is initialized to H'00.
2. Port control register 1 (PCR1)
Bit
7
6
5
4
3
2
1
0
PCR17 PCR16 PCR15 PCR14 PCR13 PCR12
PCR11 PCR10
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
PCR1 is an 8-bit register for controlling whether each of the port 1 pins P1 to P1 functions as an
7
0
input pin or output pin. Setting a PCR1 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCR1 and in PDR1 are valid only
when the corresponding pin is designated in PMR1 as a general I/O pin.
Upon reset, PCR1 is initialized to H'00.
PCR1 is a write-only register. All bits are read as 1.
3. Port pull-up control register 1 (PUCR1)
Bit
7
6
5
4
3
2
1
0
PUCR17 PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR1 controls whether the MOS pull-up of each port 1 pin is on or off. When a PCR1 bit is
cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS pull-up for the
corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR1 is initialized to H'00.
140
4. Port mode register 1 (PMR1)
Bit
7
IRQ3
0
6
IRQ2
0
5
IRQ1
0
4
PWM
0
3
2
1
0
TMIG TMOFH TMOFL TMOW
Initial value
Read/Write
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PMR1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins.
Upon reset, PMR1 is initialized to H'00.
Bit 7: P1 /IRQ /TMIF pin function switch (IRQ3)
7
3
This bit selects whether pin P1 /IRQ /TMIF is used as P1 or as IRQ /TMIF.
7
3
7
3
Bit 7
IRQ3
Description
0
1
Functions as P17 I/O pin
(initial value)
(initial value)
(initial value)
Functions as IRQ3/TMIF input pin
Note: Rising or falling edge sensing can be designated for IRQ3/TMIF.
For details on TMIF pin settings, see 9.5.2 (3), timer control register F (TCRF).
Bit 6: P1 /IRQ /TMIC pin function switch (IRQ2)
6
2
This bit selects whether pin P1 /IRQ /TMIC is used as P1 or as IRQ /TMIC.
6
2
6
2
Bit 6
IRQ2
Description
0
1
Functions as P16 I/O pin
Functions as IRQ2/TMIC input pin
Note: Rising or falling edge sensing can be designated for IRQ2/TMIC.
For details on TMIC pin settings, see 9.4.2 (1), timer mode register C (TMC).
Bit 5: P1 /IRQ /TMIB pin function switch (IRQ1)
5
1
This bit selects whether pin P1 /IRQ /TMIB is used as P1 or as IRQ /TMIB.
5
1
5
1
Bit 5
IRQ1
Description
0
1
Functions as P15 I/O pin
Functions as IRQ1/TMIB input pin
Note: Rising or falling edge sensing can be designated for IRQ1/TMIB.
For details on TMIB pin settings, see 9.3.2 (1), timer mode register B (TMB).
141
Bit 4: P1 /PWM pin function switch (PWM)
4
This bit selects whether pin P1 /PWM is used as P1 or as PWM.
4
4
Bit 4
PWM
Description
0
1
Functions as P14 I/O pin
(initial value)
(initial value)
(initial value)
(initial value)
Functions as PWM output pin
Bit 3: P1 /TMIG pin function switch (TMIG)
3
This bit selects whether pin P1 /TMIG is used as P1 or as TMIG.
3
3
Bit 3
TMIG
Description
0
1
Functions as P13 I/O pin
Functions as TMIG input pin
Bit 2: P1 /TMOFH pin function switch (TMOFH)
2
This bit selects whether pin P1 /TMOFH is used as P1 or as TMOFH.
2
2
Bit 2
TMOFH
Description
0
1
Functions as P12 I/O pin
Functions as TMOFH output pin
Bit 1: P1 /TMOFL pin function switch (TMOFL)
1
This bit selects whether pin P1 /TMOFL is used as P1 or as TMOFL.
1
1
Bit 1
TMOFL
Description
0
1
Functions as P11 I/O pin
Functions as TMOFL output pin
142
Bit 0: P1 /TMOW pin function switch (TMOW)
0
This bit selects whether pin P1 /TMOW is used as P1 or as TMOW.
0
0
Bit 0
TMOW
Descrition
0
1
Functions as P10 I/O pin
(initial value)
Functions as TMOW output pin
8.2.3 Pin Functions
Table 8-3 shows the port 1 pin functions.
Table 8-3 Port 1 Pin Functions
Pin
Pin Functions and Selection Method
P17/IRQ3/TMIF The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in TCRF,
and bit PCR17 in PCR1.
IRQ3
PCR17
0
1
0
1
*
CKSL2 to CKSL0
Pin function
*
Not 0**
0**
P17 input pin P17 output pin IRQ3 input pin IRQ3/TMIF
input pin
Note: When using as TMIF input pin, clear bit IEN3 in IENR1 to 0, disabling
IRQ3 interrupts.
P16/IRQ2/TMIC The pin function depends on bit IRQ2 in PMR1, bits TMC2 to TMC0 in TMC, and
bit PCR16 in PCR1.
IRQ2
PCR16
0
1
0
1
*
TMC2 to TMC0
Pin function
*
Not 111
111
P16 input pin P16 output pin IRQ2 input pin IRQ2/TMIC
input pin
Note: When using as TMIC input pin, clear bit IEN2 in IENR1 to 0, disabling
IRQ2 interrupts.
Note: * Don’t care
143
Table 8-3 Port 1 Pin Functions (cont)
Pin
Pin Functions and Selection Method
P15/IRQ1/ TMIB The pin function depends on bit IRQ1 in PMR1, bits TMB2 to TMB0 in TMB, and
bit PCR15 in PCR1.
IRQ1
PCR15
0
1
0
1
*
TMB2 to TMB0
Pin function
*
Not 111
111
P15 input pin P15 output pin IRQ1 input pin IRQ1/TMIB
input pin
Note: When using as TMIB input pin, clear bit IEN1 in IENR1 to 0, disabling
IRQ1 interrupts.
P14/PWM
The pin function depends on bit PWM in PMR1 and bit PCR14 in PCR1.
PWM
PCR14
0
1
0
1
*
Pin function
P14 input pin P14 output pin
PWM output pin
P13/TMIG
The pin function depends on bit TMIG in PMR1 and bit PCR13 in PCR1.
TMIG
PCR13
0
1
0
1
*
Pin function
P13 input pin P13 output pin
TMIG input pin
P12/TMOFH
P11/TMOFL
P10/TMOW
Note: * Don’t care
The pin function depends on bit TMOFH in PMR1 and bit PCR12 in PCR1.
TMOFH
PCR12
0
1
0
1
*
Pin function
P12 input pin P12 output pin
TMOFH output pin
The pin function depends on bit TMOFL in PMR1 and bit PCR11 in PCR1.
TMOFL
PCR11
0
1
0
1
*
Pin function
P11 input pin P11 output pin
TMOFL output pin
The pin function depends on bit TMOW in PMR1 and bit PCR10 in PCR1.
TMOW
PCR10
0
1
0
1
*
Pin function
P10 input pin P10 output pin
TMOW output pin
144
8.2.4 Pin States
Table 8-4 shows the port 1 pin states in each operating mode.
Table 8-4 Port 1 Pin States
Pins
Reset
Sleep
Subsleep Standby
Retains High-
Watch
Subactive Active
P17/IRQ3/TMIF High-
Retains
Retains Functional Functional
P16/IRQ2/TMIC impedance previous previous
impedance* previous
P15/IRQ1/TMIB
P14/PWM
state
state
state
P13/TMIG
P12/TMOFH
P11/TMOFL
P10/TMOW
Note: * A high-level signal is output when the MOS pull-up is in the on state.
8.2.5 MOS Input Pull-Up
Port 1 has a built-in MOS input pull-up function that can be controlled by software. When a
PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS input pull-up
for that pin. The MOS input pull-up function is in the off state after a reset.
PCR1n
PUCR1n
0
1
*
0
1
MOS input pull-up
Off
On
Off
Note: * Don’t care
n = 7 to 0
145
8.3 Port 2
8.3.1 Overview
Port 2 is an 8-bit I/O port. Figure 8-2 shows its pin configuration.
P27
P26
P25
P24
Port 2
P23
P22
P21/UD
P20/IRQ4/ADTRG
Figure 8-2 Port 2 Pin Configuration
8.3.2 Register Configuration and Description
Table 8-5 shows the port 2 register configuration.
Table 8-5 Port 2 Registers
Name
Abbrev.
PDR2
PCR2
PMR2
PMR4
R/W
R/W
W
Initial Value
H'00
Address
H'FFD5
H'FFE5
H'FFC9
H'FFCB
Port data register 2
Port control register 2
Port mode register 2
Port mode register 4
H'00
R/W
R/W
H'C0
H'00
146
1. Port data register 2 (PDR2)
Bit
7
P27
0
6
P26
0
5
P25
0
4
P24
0
3
P23
0
2
P22
0
1
P21
0
0
P20
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR2 is an 8-bit register that stores data for pins P2 through P2 . If port 2 is read while PCR2
7
0
bits are set to 1, the values stored in PDR2 are read, regardless of the actual pin states. If port 2 is
read while PCR2 bits are cleared to 0, the pin states are read.
Upon reset, PDR2 is initialized to H'00.
2. Port control register 2 (PCR2)
Bit
7
6
5
4
3
2
1
0
PCR27 PCR26 PCR25 PCR24 PCR23 PCR22
PCR21 PCR20
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
PCR2 is an 8-bit register for controlling whether each of the port 2 pins P2 to P2 functions as an
7
0
input pin or output pin. Setting a PCR2 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCR2 and in PDR2 are valid only
when the corresponding pin is designated in PMR2 as a general I/O pin.
Upon reset, PCR2 is initialized to H'00.
PCR2 is a write-only register. All bits are read as 1.
3. Port mode register 2 (PMR2)
Bit
7
—
1
6
—
1
5
POF2
0
4
3
IRQ0
0
2
POF1
0
1
UD
0
0
IRQ4
0
NCS
0
Initial value
Read/Write
—
—
R/W
R/W
R/W
R/W
R/W
R/W
PMR2 is an 8-bit read/write register, controlling the selection of pin functions for pins P2 ,
0
P2 ,and P4 , controlling the PMOS on/off option for pins P3 /SO and P3 /SO , and controlling
1
3
5
2
2
1
the TMIG input noise canceller.
Upon reset, PMR2 is initialized to H'C0.
147
Bits 7 to 6: Reserved bits
Bits 7 to 6 are reserved; they are always read as 1, and cannot be modified.
Bit 5: P3 /SO pin PMOS control (POF2)
5
2
This bit controls the PMOS transistor in the P3 /SO pin output buffer.
5
2
Bit 5
POF2
Description
0
1
CMOS output
(initial value)
(initial value)
(initial value)
(initial value)
NMOS open-drain output
Bit 4: TMIG noise canceller select (NCS)
This bit controls the noise canceller circuit for input capture at pin TMIG.
Bit 4
NCS
Description
0
1
Noise canceller function not selected
Noise canceller function selected
Bit 3: P4 /IRQ pin function switch (IRQ0)
3
0
This bit selects whether pin P4 /IRQ is used as P4 or as IRQ .
3
0
3
0
Bit 3
IRQ0
Description
0
1
Functions as P43 input pin
Functions as IRQ0 input pin
Bit 2: P3 /SO pin PMOS control (POF1)
2
1
This bit controls the PMOS transistor in the P3 /SO pin output buffer.
2
1
Bit 2
POF1
Description
0
1
CMOS output
NMOS open-drain output
148
Bit 1: P2 /UD pin function switch (UD)
1
This bit selects whether pin P2 /UD is used as P2 or as UD.
1
1
Bit 1
UD
Description
0
1
Functions as P21 I/O pin
Functions as UD input pin
(initial value)
Bit 0: P2 /IRQ /ADTRG pin function switch (IRQ4)
0
4
This bit selects whether pin P2 /IRQ /ADTRG is used as P2 or as IRQ /ADTRG.
0
4
0
4
Bit 0
IRQ4
Description
Functions as P20 I/O pin
Functions as IRQ4/ADTRG input pin
0
1
(initial value)
Note: See 12.3.2, Start of A/D Conversion by External Trigger Input, for the ADTRG pin setting.
4. Port mode register 4 (PMR4)
Bit
7
6
5
4
3
2
1
0
NMOD7 NMOD6 NMOD5 NMOD4 NMOD3 NMOD2 NMOD1 NMOD0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PMR4 is an 8-bit read/write register, used to select CMOS output or NMOS open drain output for
each port 2 pin.
Upon reset, PMR4 is initialized to H'00.
Bit n: NMOS open-drain output select (NMODn)
This bit selects CMOS output or NMOS open-drain output when pin P2 is used as an output pin.
n
Bit n
NMODn
Description
0
1
CMOS output
NMOS open-drain output
(n = 7 to 0)
149
8.3.3 Pin Functions
Table 8-6 shows the port 2 pin functions.
Table 8-6 Port 2 Pin Functions
Pin
Pin Functions and Selection Method
Input or output is selected as follows by the bit settings in PCR2.
P27 to P22
(n = 2 to 7)
PCR2n
0
1
Pin function
P2n input pin
P2n output pin
P21/UD
The pin function depends on bit UD in PMR2 and bit PCR21 in PCR2.
UD
0
1
PCR21
0
1
*
Pin function
P21 input pin P21 output pin
UD input pin
P20/IRQ4/ADTRG The pin function depends on bit IRQ4 in PMR2, bit TRGE in AMR, and bit
PCR20 in PCR2.
IRQ4
PCR20
0
1
0
1
*
TRGE
*
0
1
Pin function
P20 input pin P20 output pin
IRQ4
input pin
IRQ4/ADTRG
input pin
Note: When using as ADTRG input pin, clear bit IEN4 in IENR1 to 0,
disabling IRQ4 interrupts.
Note: * Don’t care
8.3.4 Pin States
Table 8-7 shows the port 2 pin states in each operating mode.
Table 8-7 Port 2 Pin States
Pins
Reset
Sleep
Subsleep Standby
Retains High-
Watch Subactive Active
P27 to P22 High-
Retains
Retains Functional Functional
P21/UD
P20/IRQ4/
ADTRG
impedance previous previous
state state
impedance previous
state
150
8.4 Port 3
8.4.1 Overview
Port 3 is an 8-bit I/O port, configured as shown in figure 8-3.
P37/CS
P36/STRB
P35/SO2
P34/SI2
Port 3
P33/SCK2
P32/SO1
P31/SI1
P30/SCK1
Figure 8-3 Port 3 Pin Configuration
8.4.2 Register Configuration and Description
Table 8-8 shows the port 3 register configuration.
Table 8-8 Port 3 Registers
Name
Abbrev.
PDR3
R/W
R/W
W
Initial Value
H'00
Address
H'FFD6
H'FFE6
H'FFE1
H'FFCA
Port data register 3
Port control register 3
Port pull-up control register 3
Port mode register 3
PCR3
H'00
PUCR3
PMR3
R/W
R/W
H'00
H'00
151
1. Port data register 3 (PDR3)
Bit
7
P37
0
6
P36
0
5
P35
0
4
P34
0
3
P33
0
2
P32
0
1
P31
0
0
P30
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR3 is an 8-bit register that stores data for port 3 pins P3 to P3 . If port 3 is read while PCR3
7
0
bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is
read while PCR3 bits are cleared to 0, the pin states are read.
Upon reset, PDR3 is initialized to H'00.
2. Port control register 3 (PCR3)
Bit
7
6
5
4
3
2
1
0
PCR37 PCR36 PCR35 PCR34 PCR33 PCR32
PCR31 PCR30
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
PCR3 is an 8-bit register for controlling whether each of the port 3 pins P3 to P3 functions as an
7
0
input pin or output pin. Setting a PCR3 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCR3 and in PDR3 are valid only
when the corresponding pin is designated in PMR3 as a general I/O pin.
Upon reset, PCR3 is initialized to H'00.
PCR3 is a write-only register. All bits are read as 1.
3. Port pull-up control register 3 (PUCR3)
Bit
7
6
5
4
3
2
1
0
PUCR37 PUCR36 PUCR35 PUCR34 PUCR33 PUCR32 PUCR31 PUCR30
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR3 controls whether the MOS pull-up of each port 3 pin is on or off. When a PCR3 bit is
cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for the
corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR3 is initialized to H'00.
152
4. Port mode register 3 (PMR3)
Bit
7
CS
0
6
STRB
0
5
4
SI2
0
3
SCK2
0
2
1
SI1
0
0
SCK1
0
SO2
0
SO1
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins.
Upon reset, PMR3 is initialized to H'00.
Bit 7: P3 /CS pin function switch (CS)
7
This bit selects whether pin P3 /CS is used as P3 or as CS.
7
7
Bit 7
CS
Description
0
1
Functions as P37 I/O pin
Functions as CS input pin
(initial value)
(initial value)
(initial value)
Bit 6: P3 /STRB pin function switch (STRB)
6
This bit selects whether pin P3 /STRB is used as P3 or as STRB.
6
6
Bit 6
STRB
Description
0
1
Functions as P36 I/O pin
Functions as STRB output pin
Bit 5: P35/SO2 pin function switch (SO2)
This bit selects whether pin P35/SO is used as P35 or as SO .
2
2
Bit 5
SO2
Description
0
1
Functions as P35 I/O pin
Functions as SO2 output pin
153
Bit 4: P3 /SI pin function switch (SI2)
4
2
This bit selects whether pin P3 /SI is used as P3 or as SI .
4
2
4
2
Bit 4
SI2
Description
0
1
Functions as P34 I/O pin
Functions as SI2 input pin
(initial value)
(initial value)
(initial value)
(initial value)
Bit 3: P3 /SCK pin function switch (SCK2)
3
2
This bit selects whether pin P3 /SCK is used as P3 or as SCK .
3
2
3
2
Bit 3
SCK2
Description
Functions as P33 I/O pin
Functions as SCK2 I/O pin
0
1
Bit 2: P3 /SO pin function switch (SO1)
2
1
This bit selects whether pin P3 /SO is used as P3 or as SO .
2
1
2
1
Bit 2
SO1
Description
0
1
Functions as P32 I/O pin
Functions as SO1 output pin
Bit 1: P3 /SI pin function switch (SI1)
1
1
This bit selects whether pin P3 /SI is used as P3 or as SI .
1
1
1
1
Bit 1
SI1
Description
0
1
Functions as P31 I/O pin
Functions as SI1 input pin
154
Bit 0: P3 /SCK pin function switch (SCK1)
0
1
This bit selects whether pin P3 /SCK is used as P3 or as SCK .
0
1
0
1
Bit 0
SCK1
Description
Functions as P30 I/O pin
Functions as SCK1 I/O pin
0
1
(initial value)
8.4.3 Pin Functions
Table 8-9 shows the port 3 pin functions.
Table 8-9 Port 3 Pin Functions
Pin
Pin Functions and Selection Method
The pin function depends on bit CS in PMR3 and bit PCR37 in PCR3.
P37/CS
CS
0
1
PCR37
0
1
*
Pin function
P37 input pin P37 output pin
CS input pin
P36/STRB
The pin function depends on bit STRB in PMR3 and bit PCR36 in PCR3.
STRB
PCR36
0
1
0
1
*
Pin function
P36 input pin P36 output pin
STRB output pin
P35/SO2
The pin function depends on bit SO2 in PMR3 and bit PCR35 in PCR3.
SO2
0
1
PCR35
0
1
*
Pin function
P35 input pin P35 output pin
SO2 output pin
P34/SI2
The pin function depends on bit SI2 in PMR3 and bit PCR34 in PCR3.
SI2
0
1
PCR34
0
1
*
Pin function
P34 input pin P34 output pin
SI2 input pin
Note: * Don’t care
155
Table 8-9 Port 3 Pin Functions (cont)
Pin
Pin Functions and Selection Method
P33/SCK2
The pin function depends on bit SCK2 in PMR3, bits CKS2 to 0 in SCR2, and
bit PCR33 in PCR3.
SCK2
CKS2 to CKS0
PCR33
0
1
*
Not 111
111
0
1
*
*
Pin function P33 input pin P33 output pin SCK2 output pin SCK2 input pin
The pin function depends on bit SO1 in PMR3 and bit PCR32 in PCR3.
P32/SO1
SO1
0
1
PCR32
0
1
*
Pin function P32 input pin P32 output pin
SO1 output pin
P31/SI1
The pin function depends on bit SI1 in PMR3 and bit PCR31 in PCR3.
SI1
0
1
PCR31
0
1
*
Pin function P31 input pin P31 output pin
SI1 input pin
P30/SCK1
The pin function depends on bit SCK1 in PMR3, bit CKS3 in SCR1, and bit
PCR30 in PCR3.
SCK1
CKS3
PCR30
0
1
*
0
1
0
1
*
*
Pin function P30 input pin P30 output pin SCK1 output pin SCK1 input pin
Note: * Don’t care
156
8.4.4 Pin States
Table 8-10 shows the port 3 pin states in each operating mode.
Table 8-10 Port 3 Pin States
Pins
Reset
Sleep
Subsleep Standby
Retains High-
Watch Subactive Active
P37/CS
High-
Retains
Retains Functional Functional
P36/STRB
P35/SO2
P34/SI2
impedance previous previous
state state
impedance* previous
state
P33/SCK2
P32/SO1
P31/SI1
P30/SCK1
Note: * A high-level signal is output when the MOS pull-up is in the on state.
8.4.5 MOS Input Pull-Up
Port 3 has a built-in MOS input pull-up function that can be controlled by software. When a
PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for
that pin. The MOS pull-up function is in the off state after a reset.
PCR3n
PUCR3n
0
1
*
0
1
MOS input pull-up
Note: * Don’t care
Off
On
Off
(n = 7 to 0)
157
8.5 Port 4
8.5.1 Overview
Port 4 consists of a 3-bit I/O port and a 1-bit input port, and is configured as shown in figure 8-4.
P43/IRQ0
P42/TXD
Port 4
P41/RXD
P40/SCK3
Figure 8-4 Port 4 Pin Configuration
8.5.2 Register Configuration and Description
Table 8-11 shows the port 4 register configuration.
Table 8-11 Port 4 Registers
Name
Abbrev.
PDR4
R/W
R/W
W
Initial Value
H'F8
Address
H'FFD7
H'FFE7
Port data register 4
Port control register 4
PCR4
H'F8
158
1. Port data register 4 (PDR4)
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
P43
1
2
P42
0
1
P41
0
0
P40
0
Initial value
Read/Write
—
—
—
—
R
R/W
R/W
R/W
PDR4 is an 8-bit register that stores data for port 4 pins P4 to P4 . If port 4 is read while PCR4
2
0
bits are set to 1, the values stored in PDR4 are read, regardless of the actual pin states. If port 4 is
read while PCR4 bits are cleared to 0, the pin states are read.
Upon reset, PDR4 is initialized to H'F8.
2. Port control register 4 (PCR4)
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
1
0
PCR42 PCR41 PCR40
Initial value
Read/Write
0
0
0
—
—
—
—
—
W
W
W
PCR4 controls whether each of the port 4 pins P4 to P4 functions as an input pin or output pin.
2
0
Setting a PCR4 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0
makes the pin an input pin. The settings in PCR4 and in PDR4 are valid only when the
corresponding pin is designated in SCR3 as a general I/O pin.
Upon reset, PCR4 is initialized to H'F8.
PCR4 is a write-only register. All bits are read as 1.
159
8.5.3 Pin Functions
Table 8-12 shows the port 4 pin functions.
Table 8-12 Port 4 Pin Functions
Pin
Pin Functions and Selection Method
The pin function depends on the IRQ0 bit setting in PMR2.
P43/IRQ0
IRQ0
0
1
Pin function
P43 input pin
IRQ0 input pin
P42/TXD
P41/RXD
P40/SCK3
The pin function depends on bit TE in SCR3 and bit PCR42 in PCR4.
UD
0
1
PCR42
0
1
*
Pin function
P42 input pin P42 output pin
TXD output pin
The pin function depends on bit RE in SCR3 and bit PCR41 in PCR4.
RE
0
1
PCR41
0
1
*
Pin function
P41 input pin P41 output pin
RXD input pin
The pin function depends on bits CKE1 and CKE0 in SCR3, bit COM in SMR,
and bit PCR40 in PCR4.
CKE1
CKE0
COM
0
1
*
*
*
0
1
0
1
*
PCR40
0
1
*
Pin function P40 input pin P40 output pin SCK3 output pin SCK3 input pin
Note: * Don’t care
160
8.5.4 Pin States
Table 8-13 shows the port 4 pin states in each operating mode.
Table 8-13 Port 4 Pin States
Pins
Reset
Sleep
Subsleep Standby
Retains High-
Watch Subactive Active
P43/IRQ0
P42/TXD
P41/RXD
P40/SCK3
High-
Retains
Retains Functional Functional
impedance previous previous
state state
impedance previous
state
161
8.6 Port 5
8.6.1 Overview
Port 5 is an 8-bit I/O port, configured as shown in figure 8-5.
P57/WKP7 /SEG8
P56/WKP6 /SEG7
P55/WKP5 /SEG6
P54/WKP4 /SEG5
P53/WKP3 /SEG4
P52/WKP2 /SEG3
P51/WKP1 /SEG2
P50/WKP0 /SEG1
Port 5
Figure 8-5 Port 5 Pin Configuration
8.6.2 Register Configuration and Description
Table 8-14 shows the port 5 register configuration.
Table 8-14 Port 5 Registers
Name
Abbrev.
PDR5
R/W
R/W
W
Initial Value
H'00
Address
H'FFD8
H'FFE8
H'FFE2
H'FFCC
Port data register 5
Port control register 5
Port pull-up control register 5
Port mode register 5
PCR5
H'00
PUCR5
PMR5
R/W
R/W
H'00
H'00
162
1. Port data register 5 (PDR5)
Bit
7
P57
0
6
P56
0
5
P55
0
4
P54
0
3
P53
0
2
P52
0
1
P51
0
0
P50
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR5 is an 8-bit register that stores data for port 5 pins P5 to P5 . If port 5 is read while PCR5
7
0
bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is
read while PCR5 bits are cleared to 0, the pin states are read.
Upon reset, PDR5 is initialized to H'00.
2. Port control register 5 (PCR5)
Bit
7
6
5
4
3
2
1
0
PCR57 PCR56 PCR55 PCR54 PCR53 PCR52
PCR51 PCR50
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
PCR5 is an 8-bit register for controlling whether each of the port 5 pins P5 to P5 functions as an
7
0
input pin or output pin. Setting a PCR5 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCR5 and in PDR5 are valid only
when the corresponding pin is designated as a general I/O pin in PMR5 and in bits SGS3 to SGS0
of LPCR.
Upon reset, PCR5 is initialized to H'00.
PCR5 is a write-only register. All bits are read as 1.
3. Port pull-up control register 5 (PUCR5)
Bit
7
6
5
4
3
2
1
0
PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR5 controls whether the MOS pull-up of each port 5 pin is on or off. When a PCR5 bit is
cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for the
corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR5 is initialized to H'00.
163
4. Port mode register 5 (PMR5)
Bit
7
WKP7
0
6
WKP6
0
5
WKP5
0
4
WKP4
0
3
WKP3
0
2
WKP2
0
1
WKP1
0
0
WKP0
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PMR5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins.
Upon reset, PMR5 is initialized to H'00.
Bit n: P5 /WKP /SEG pin function switch (WKPn)
n+1
n
n
When pin P5 /WKP /SEG
is not used as a SEG pin, this bit selects whether it is used as
n+1
n
n
n+1
P5 or as WKP .
n
n
Bit n
WKPn
Description
0
1
Functions as P5n I/O pin
(initial value)
(n = 7 to 0)
Functions as WKPn input pin
Note: For information on use as a SEG pin, see 13.2.1, LCD Port Control Register (LPCR).
n+1
164
8.6.3 Pin Functions
Table 8-15 shows the port 5 pin functions.
Table 8-15 Port 5 Pin Functions
Pin
Pin Functions and Selection Method
P57/WKP7/
SEG8to P54/
WKP4/SEG5
The pin function depends on bit WKPn in PMR5, bit PCR5n in PCR5, and bits
SGS3 to SGS0 in LPCR.
(n = 7 to 4)
SGS3 to SGS0
WKPn
0***
1***
0
1
*
*
PCR5n
0
1
*
Pin function P5n input pin P5n output pin WKPn input pin SEGn+1 output pin
P53/WKP3/
The pin function depends on bit WKPn in PMR5, bit PCR5n in PCR5, and bits
SEG4 to P50/
WKP0/SEG1
SGS3 to SGS0 in LPCR.
(n = 3 to 0)
SGS3 to SGS0
WKPn
0*** or 1**0
1**1
0
1
*
*
PCR5n
0
1
*
Pin function P5n input pin P5n output pin WKPn input pin SEGn+1 output pin
Note: * Don’t care
165
8.6.4 Pin States
Table 8-16 shows the port 5 pin states in each operating mode.
Table 8-16 Port 5 Pin States
Pins
Reset
Sleep
Subsleep Standby
Retains High-
Watch
Subactive Active
P57/WKP7/
High-
Retains
Retains Functional Functional
SEG8 to P50/ impedance previous previous
WKP0/SEG1 state state
impedance* previous
state
Note: * A high-level signal is output when the MOS pull-up is in the on state.
8.6.5 MOS Input Pull-Up
Port 5 has a built-in MOS input pull-up function that can be controlled by software. When a
PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for
that pin. The MOS pull-up function is in the off state after a reset.
PCR5n
PUCR5n
0
1
*
0
1
MOS input pull-up
Note: * Don’t care
Off
On
Off
(n = 7 to 0)
166
8.7 Port 6
8.7.1 Overview
Port 6 is an 8-bit I/O port, configured as shown in figure 8-6.
P67/SEG16
P66/SEG15
P65/SEG14
P64/SEG13
P63/SEG12
P62/SEG11
P61/SEG10
P60/SEG9
Port 6
Figure 8-6 Port 6 Pin Configuration
8.7.2 Register Configuration and Description
Table 8-17 shows the port 6 register configuration.
Table 8-17 Port 6 Registers
Name
Abbrev.
PDR6
R/W
R/W
W
Initial Value
H'00
Address
H'FFD9
H'FFE9
H'FFE3
Port data register 6
Port control register 6
Port pull-up control register 6
PCR6
H'00
PUCR6
R/W
H'00
167
1. Port data register 6 (PDR6)
Bit
7
P67
0
6
P66
0
5
P65
0
4
P64
0
3
P63
0
2
P62
0
1
P61
0
0
P60
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR6 is an 8-bit register that stores data for port 6 pins P6 to P6 . If port 6 is read while PCR6
7
0
bits are set to 1, the values stored in PDR6 are read, regardless of the actual pin states. If port 6 is
read while PCR6 bits are cleared to 0, the pin states are read.
Upon reset, PDR6 is initialized to H'00.
2. Port control register 6 (PCR6)
Bit
7
6
5
4
3
2
1
0
PCR67 PCR66 PCR65 PCR64 PCR63 PCR62
PCR61 PCR60
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
PCR6 is an 8-bit register for controlling whether each of the port 6 pins P6 to P6 functions as an
7
0
input pin or output pin. Setting a PCR6 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCR6 and in PDR6 are valid only
when the corresponding pin is designated in bits SGS3 to SGS0 in LPCR as a general I/O pin.
Upon reset, PCR6 is initialized to H'00.
PCR6 is a write-only register. All bits are read as 1.
3. Port pull-up control register 6 (PUCR6)
Bit
7
6
5
4
3
2
1
0
PUCR67 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR6 controls whether the MOS pull-up of each port 6 pin is on or off. When a PCR6 bit is
cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for the
corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR6 is initialized to H'00.
168
8.7.3 Pin Functions
Table 8-18 shows the port 6 pin functions.
Table 8-18 Port 6 Pin Functions
Pin
Pin Functions and Selection Method
P67/SEG16 to
P64/SEG13
The pin function depends on bit PCR6n in PCR6 and bits SGS3 to SGS0 in
LPCR.
(n = 7 to 4)
SGS3 to SGS0
PCR6n
00** or 010*
011* or 1***
*
0
1
Pin function
P6n input pin P6n output pin
SEGn+9 output pin
P63/SEG12
to P60/SEG9
The pin function depends on bit PCR6n in PCR6 and bits SGS3 to SGS0 in
LPCR.
(n = 3 to 0)
SGS3 to SGS0
PCR6n
00**, 010* or 0110
0111 or 1***
*
0
1
Pin function
P6n input pin P6n output pin
SEGn+9 output pin
Note: * Don’t care
8.7.4 Pin States
Table 8-19 shows the port 6 pin states in each operating mode.
Table 8-19 Port 6 Pin States
Pins
Reset
Sleep
Subsleep Standby
Retains High-
Watch
Subactive Active
P67/SEG16 to
P60/SEG9
High-
Retains
Retains Functional Functional
impedance previous previous
state state
impedance* previous
state
Note: * A high-level signal is output when the MOS pull-up is in the on state.
169
8.7.5 MOS Input Pull-Up
Port 6 has a built-in MOS input pull-up function that can be controlled by software. When a
PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for
that pin. The MOS pull-up function is in the off state after a reset.
PCR6n
PUC6n
0
1
*
0
1
MOS input pull-up
Note: * Don’t care
Off
On
Off
(n = 7 to 0)
170
8.8 Port 7
8.8.1 Overview
Port 7 is an 8-bit I/O port, configured as shown in figure 8-7.
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
Port 7
Figure 8-7 Port 7 Pin Configuration
8.8.2 Register Configuration and Description
Table 8-20 shows the port 7 register configuration.
Table 8-20 Port 7 Registers
Name
Abbrev.
PDR7
R/W
R/W
W
Initial Value
H'00
Address
H'FFDA
H'FFEA
Port data register 7
Port control register 7
PCR7
H'00
171
1. Port data register 7 (PDR7)
Bit
7
P77
0
6
P76
0
5
P75
0
4
P74
0
3
P73
0
2
P72
0
1
P71
0
0
P70
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR7 is an 8-bit register that stores data for port 7 pins P7 to P7 . If port 7 is read while PCR7
7
0
bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is
read while PCR7 bits are cleared to 0, the pin states are read.
Upon reset, PDR7 is initialized to H'00.
2. Port control register 7 (PCR7)
Bit
7
6
5
4
3
2
1
0
PCR77 PCR76 PCR75 PCR74 PCR73 PCR72
PCR71 PCR70
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
PCR7 is an 8-bit register for controlling whether each of the port 7 pins P7 to P7 functions as an
7
0
input pin or output pin. Setting a PCR7 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCR7 and in PDR7 are valid only
when the corresponding pin is designated in bits SGS3 to SGS0 in LPCR as a general I/O pin.
Upon reset, PCR7 is initialized to H'00.
PCR7 is a write-only register. All bits are read as 1.
172
8.8.3 Pin Functions
Table 8-21 shows the port 7 pin functions.
Table 8-21 Port 7 Pin Functions
Pin
Pin Functions and Selection Method
P77/SEG24 to
P74/SEG21
The pin function depends on bit PCR7n in PCR7 and bits SGS3 to SGS0 in
LPCR.
(n = 7 to 4)
SGS3 to SGS0
PCR7n
00**
01** or 1***
*
0
1
Pin function
P7n input pin P7n output pin
SEGn+17 output pin
P73/SEG20 to
P70/SEG17
The pin function depends on bit PCR7n in PCR7 and bits SGS3 to SGS0 in
LPCR.
(n = 3 to 0)
SGS3 to SGS0
PCR7n
00** or 0100
0101, 011* or 1***
*
0
1
Pin function
P7n input pin P7n output pin
SEGn+17 output pin
Note: * Don’t care
8.8.4 Pin States
Table 8-22 shows the port 7 pin states in each operating mode.
Table 8-22 Port 7 Pin States
Pins
Reset
Sleep
Subsleep Standby
Watch
Subactive Active
P77/SEG24 to
P70/SEG17
High-
Retains
Retains
High-
impedance
Retains Functional Functional
previous
state
impedance previous previous
state state
173
8.9 Port 8
8.9.1 Overview
Port 8 is an 8-bit I/O port configured as shown in figure 8-9.
P87/SEG32
P86/SEG31
P85/SEG30
P84/SEG29
P83/SEG28
P82/SEG27
P81/SEG26
P80/SEG25
Port 8
Figure 8-8 Port 8 Pin Configuration
8.9.2 Register Configuration and Description
Table 8-23 shows the port 8 register configuration.
Table 8-23 Port 8 Registers
Name
Abbrev.
PDR8
R/W
R/W
W
Initial Value
H'00
Address
H'FFDB
H'FFEB
Port data register 8
Port control register 8
PCR8
H'00
174
1. Port data register 8 (PDR8)
Bit
7
P87
0
6
P86
0
5
P85
0
4
P84
0
3
P83
0
2
P82
0
1
P81
0
0
P80
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR8 is an 8-bit register that stores data for port 8 pins P8 to P8 . If port 8 is read while PCR8
7
0
bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is
read while PCR8 bits are cleared to 0, the pin states are read.
Upon reset, PDR8 is initialized to H'00.
2. Port control register 8 (PCR8)
Bit
7
6
5
4
3
2
1
0
PCR87 PCR86 PCR85 PCR84 PCR83 PCR82
PCR81 PCR80
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
PCR8 is an 8-bit register for controlling whether each of the port 8 pins P8 to P8 functions as an
7
0
input or output pin. Setting a PCR8 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCR8 and in PDR8 are valid only
when the corresponding pin is designated in bits SGS3 to SGS0 in LPCR as a general I/O pin.
Upon reset, PCR8 is initialized to H'00.
PCR8 is a write-only register. All bits are read as 1.
175
8.9.3 Pin Functions
Table 8-24 shows the port 8 pin functions.
Table 8-24 Port 8 Pin Functions
Pin
Pin Functions and Selection Method
P87/SEG32 to
P84/SEG29
The pin function depends on bit PCR8n in PCR8 and bits SGS3 to SGS0 in
LPCR.
(n = 7 to 4)
SGS3 to SGS0
PCR8n
000*
001*, 01** or 1***
*
0
1
Pin function
P8n input pin P8n output pin
SEGn+25 output pin
P83/SEG28 to
P80/SEG25
The pin function depends on bit PCR8n in PCR8 and bits SGS3 to SGS0 in
LPCR.
(n = 3 to 0)
SGS3 to SGS0
PCR8n
000* or 0010
0011, 01** or 1***
*
0
1
Pin function
P8n input pin P8n output pin
SEGn+25 output pin
Note: * Don’t care
8.9.4 Pin States
Table 8-25 shows the port 8 pin states in each operating mode.
Table 8-25 Port 8 Pin States
Pins
Reset
Sleep
Subsleep Standby
Watch
Subactive Active
P87/SEG32 to
P80/SEG25
High-
Retains
Retains
High-
impedance
Retains Functional Functional
previous
state
impedance previous previous
state state
176
8.10 Port 9
8.10.1 Overview
Port 9 is an 8-bit I/O port configured as shown in figure 8-9.
P97/SEG40 /CL1
P96/SEG39 /CL2
P95/SEG38 /DO
P94/SEG37 /M
P93/SEG36
Port 9
P92/SEG35
P91/SEG34
P90/SEG33
Figure 8-9 Port 9 Pin Configuration
8.10.2 Register Configuration and Description
Table 8-26 shows the port 9 register configuration.
Table 8-26 Port 9 Registers
Name
Abbrev.
PDR9
R/W
R/W
W
Initial Value
H'00
Address
H'FFDC
H'FFEC
Port data register 9
Port control register 9
PCR9
H'00
177
1. Port data register 9 (PDR9)
Bit
7
P97
0
6
P96
0
5
P95
0
4
P94
0
3
P93
0
2
P92
0
1
P91
0
0
P90
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR9 is an 8-bit register that stores data for port 9 pins P9 to P9 . If port 9 is read while PCR9
7
0
bits are set to 1, the values stored in PDR9 are read, regardless of the actual pin states. If port 9 is
read while PCR9 bits are cleared to 0, the pin states are read.
Upon reset, PDR9 is initialized to H'00.
2. Port control register 9 (PCR9)
Bit
7
6
5
4
3
2
1
0
PCR97 PCR96 PCR95 PCR94 PCR93 PCR92
PCR91 PCR90
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
PCR9 is an 8-bit register for controlling whether each of the port 9 pins P9 to P9 functions as an
7
0
input or output pin. Setting a PCR9 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCR9 and in PDR9 are valid only
when the corresponding pin is designated in bits SGS3 to SGS0 in LPCR as a general I/O pin.
Upon reset, PCR9 is initialized to H'00.
PCR9 is a write-only register. All bits are read as 1.
178
8.10.3 Pin Functions
Table 8-27 shows the port 9 pin functions.
Table 8-27 Port 9 Pin Functions
Pin
Pin Functions and Selection Method
P97/SEG40/CL1
The pin function depends on bit PCR97 in PCR9, and bits SGX and SGS3 to
SGS0 in LPCR.
SGS3 to SGS0
SGX
0000
0
Not 0000
*
1
*
0
PCR97
0
1
*
Pin function P97 input pin P97 output pin SEG40 output pin CL1 output pin
P96/SEG39/CL2
P95/SEG38/DO
P94/SEG37/M
The pin function depends on bit PCR96 in PCR9, and bits SGX and SGS3 to
SGS0 in LPCR.
SGS3 to SGS0
SGX
0000
0
Not 0000
*
1
*
0
PCR96
0
1
*
Pin function P96 input pin P96 output pin SEG39 output pin CL2 output pin
The pin function depends on bit PCR95 in PCR9, and bits SGX and SGS3 to
SGS0 in LPCR.
SGS3 to SGS0
SGX
0000
0
Not 0000
*
1
*
0
PCR95
0
1
*
Pin function P95 input pin P95 output pin SEG38 output pin DO output pin
The pin function depends on bit PCR94 in PCR9, and bits SGX and SGS3 to
SGS0 in LPCR.
SGS3 to SGS0
SGX
0000
0
Not 0000
*
1
*
0
PCR94
0
1
*
Pin function P94 input pin P94 output pin SEG37 output pin M output pin
Note: * Don’t care
179
Table 8-27 Port 9 Pin Functions (cont)
Pin
Pin Functions and Selection Method
93/SEG36 to
P90/SEG33
The pin function depends on bit PCR9n in PCR9 and bits SGS3 to SGS0 in
LPCR.
(n = 3 to 0)
SGS3 to SGS0
PCR9n
0000
Not 0000
0
1
*
Pin function P9n input pin P9n output pin
SEGn+33 output pin
Note: * Don’t care
8.10.4 Pin States
Table 8-28 shows the port 9 pin states in each operating mode.
Table 8-28 Port 9 Pin States
Pins
Reset
Sleep
Subsleep Standby
Watch
Subactive Active
P97/SEG40/CL1 High-
Retains
Retains
High-
Retains Functional Functional
P96/SEG39/CL2 impedance previous previous
impedance
previous
state
P95/SEG38/DO
P94/SEG37/M
P93/SEG36 to
P90/SEG33
state
state
180
8.11 Port A
8.11.1 Overview
Port A is a 4-bit I/O port, configured as shown in figure 8-10.
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
Port A
Figure 8-10 Port A Pin Configuration
8.11.2 Register Configuration and Description
Table 8-29 shows the port A register configuration.
Table 8-29 Port A Registers
Name
Abbrev.
PDRA
R/W
R/W
W
Initial Value
H'F0
Address
H'FFDD
H'FFED
Port data register A
Port control register A
PCRA
H'F0
181
1. Port data register A (PDRA)
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
2
1
0
PA3
0
PA2
0
PA1
0
PA0
0
Initial value
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
PDRA is an 8-bit register that stores data for port A pins PA to PA . If port A is read while
3
0
PCRA bits are set to 1, the values stored in PDRA are read, regardless of the actual pin states. If
port A is read while PCRA bits are cleared to 0, the pin states are read.
Upon reset, PDRA is initialized to H'F0.
2. Port control register A (PCRA)
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
2
1
0
PCRA3 PCRA2 PCRA1 PCRA0
Initial value
Read/Write
0
0
0
0
—
—
—
—
W
W
W
W
PCRA is an 8-bit register for controlling whether each of the port A pins PA to PA functions as
3
0
an input or output pin. Setting a PCRA bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCRA and in PDRA are valid only
when the corresponding pin is designated in LPCR as a general I/O pin.
Upon reset, PCRA is initialized to H'F0.
PCRA is a write-only register. All bits are read as 1.
182
8.11.3 Pin Functions
Table 8-30 gives the port A pin functions.
Table 8-30 Port A Pin Functions
Pin
Pin Functions and Selection Method
PA3/COM4
The pin function depends on bit PCRA3 in PCRA and bits DTS1, DTS0, CMX,
SGX, and SGS3 to SGS0 in LPCR.
CMX
DTS1,DTS0 ** Not 11 ** Not 11
SGX
*
0
*
0
1
*
Not 11
11
0
1
*
0
1
*
1
*
1
*
SGS3 to SGS0 0000 Not 0000 0000 Not 0000 0000 Not 0000 0000 Not 0000
PCRA3
0
1
*
Pin function
PA3 input pin PA3 output pin
COM4 output pin
PA2/COM3
The pin function depends on bit PCRA2 in PCRA and bits DTS1, DTS0, CMX,
SGX, and SGS3 to SGS0 in LPCR.
CMX
DTS1,DTS0 ** 00 or 01 ** 00 or 01
SGX
*
0
*
0
1
*
00 or 01
Not 00 or 01
0
1
*
0
1
*
1
*
1
*
SGS3 to SGS0 0000 Not 0000 0000 Not 0000 0000 Not 0000 0000 Not 0000
PCRA2
0
1
*
Pin function
PA2 input pin PA2 output pin
COM3 output pin
PA1/COM2
The pin function depends on bit PCRA1 in PCRA and bits DTS1, DTS0, CMX,
SGX, and SGS3 to SGS0 in LPCR.
CMX
DTS1,DTS0 **
SGX
*
0
*
**
0
0
1
*
00
00
00
Not 00
0
1
*
1
*
1
*
1
*
SGS3 to SGS0 0000 Not 0000 0000 Not 0000 0000 Not 0000 0000 Not 0000
PCRA1
0
1
*
Pin function
PA1 input pin PA1 output pin
COM2 output pin
Note: * Don’t care
183
Table 8-30 Port A Pin Functions (cont)
Pin
Pin Functions and Selection Method
PA0/COM1
The pin function depends on bit PCRA0 in PCRA, and bits SGX and SGS3 to
SGS0 in LPCR.
SGS3 to SGS0
SGX
0000
0
0000
1
Not 0000
*
PCRA0
0
1
*
Pin function
PA0 input pin PA0 output pin
COM1 output pin
Note: * Don’t care
8.11.4 Pin States
Table 8-31 shows the port A pin states in each operating mode.
Table 8-31 Port A Pin States
Pins
Reset
Sleep
Subsleep Standby
Retains High-
Watch Subactive Active
PA3/COM4 High-
Retains
Retains Functional Functional
PA2/COM3 impedance previous previous
impedance previous
state
PA1/COM2
PA0/COM1
state
state
184
8.12 Port B
8.12.1 Overview
Port B is an 8-bit input-only port, configured as shown in figure 8-11.
PB7/AN7
PB6/AN6
PB5/AN5
PB4/AN4
Port B
PB3/AN3
PB2/AN2
PB1/AN1
PB0/AN0
Figure 8-11 Port B Pin Configuration
8.12.2 Register Configuration and Description
Table 8-32 shows the port B register configuration.
Table 8-32 Port B Register
Name
Abbrev.
R/W
Address
Port data register B
PDRB
R
H'FFDE
Port Data Register B (PDRB)
Bit
7
6
5
4
3
2
1
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Read/Write
R
R
R
R
R
R
R
R
Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input
channel for the A/D converter by AMR bits CH3 to CH0, that pin reads 0 regardless of the input
voltage.
185
8.13 Port C
8.13.1 Overview
Port C is a 4-bit input-only port, configured as shown in figure 8-12.
PC3 /AN11
PC2 /AN10
Port C
PC1 /AN9
PC0 /AN8
Figure 8-12 Port C Pin Configuration
8.13.2 Register Configuration and Description
Table 8-33 shows the port C register configuration.
Table 8-33 Port C Register
Name
Abbrev.
R/W
Address
Port data register C
PDRC
R
H'FFDF
Port Data Register C (PDRC)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
PC3
PC2
PC1
PC0
Read/Write
—
—
—
—
R
R
R
R
Reading PDRC always gives the pin states. However, if a port C pin is selected as an analog input
channel for the A/D converter by AMR bits CH3 to CH0, that pin reads 0 regardless of the input
voltage.
186
Section 9 Timers
9.1 Overview
The H8/3834U Series provides five timers (timers A, B, C, F, and G) on-chip.
Table 9-1 outlines the functions of timers A, B, C, F, and G.
Table 9-1 Timer Functions
Event
Waveform
Name
Functions
Internal Clock
Input Pin Output Pin Remarks
Timer A • 8-bit timer
• Interval timer
ø/8 to ø/8192
(8 choices)
—
—
—
—
• 8-bit timer
• Time base
øW/128
(choice of 4
overflow periods)
• 8-bit timer
• clock output
ø/4 to ø/32,
øW/4 to øW/32
(8 choices)
—
TMOW
—
Timer B • 8-bit timer
• Interval timer
ø/4 to ø/8192
(7 choices)
TMIB
TMIC
• Event counter
Timer C • 8-bit timer
• Interval timer
ø/4 to ø/8192,
øW/4 (7 choices)
—
Counting
direction can
be controlled by
software or
hardware
• Event counter
• Choice of up- or down-
counting
Timer F • 16-bit timer
• Event counter
ø/2 to ø/32
(4 choices)
TMIF
TMOFL
TMOFH
• Can be used as two
independent 8-bit timers
• Output compare
Timer G • 8-bit timer
ø/2 to ø/64, øW/2 TMIG
(4 choices)
—
• Counter clear
designation
possible
• Input capture
• Interval timer
• Built-in noise
canceller
circuit for input
capture
187
9.2 Timer A
9.2.1 Overview
Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock
time-base function is available when a 32.768-kHz crystal oscillator is connected. A clock signal
divided from 32.768 kHz or from the system clock can be output at the TMOW pin.
1. Features
Features of timer A are given below.
•
Choice of eight internal clock sources (ø/8192, ø/4096, ø/2048, ø/512, ø/256, ø/128, ø/32,
ø/8).
•
Choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms) when timer A is used as a clock
time base (using a 32.768 kHz crystal oscillator).
•
•
An interrupt is requested when the counter overflows.
Any of eight clock signals can be output from pin TMOW: 32.768 kHz divided by 32, 16, 8,
or 4 (1 kHz, 2 kHz, 4 kHz, 8 kHz), or the system clock divided by 32, 16, 8, or 4.
188
2. Block diagram
Figure 9-2-1 shows a block diagram of timer A.
øW
TMA
1/4
PSW
øW/4
øW/32
øW/16
øW/8
øW/4
øW/128
TMOW
TCA
ø/32
ø/16
ø/8
ø/8192, ø/4096, ø/2048,
ø/512, ø/256, ø/128,
ø/32, ø/8
ø/4
ø
PSS
IRRTA
Notation:
TMA: Timer mode register A
TCA: Timer counter A
IRRTA: Timer A overflow interrupt request flag (interrupt request register 1)
PSW: Prescaler W
PSS:
Prescaler S
Note: Can be selected only when the prescaler W output (øW/128) is used as the TCA input clock.
Figure 9-2-1 Block Diagram of Timer A
3. Pin configuration
Table 9-2-1 shows the timer A pin configuration.
Table 9-2-1 Pin Configuration
Name
Abbrev. I/O
Function
Clock output TMOW
Output Output of waveform generated by timer A output circuit
189
4. Register configuration
Table 9-2-2 shows the register configuration of timer A.
Table 9-2-2 Timer A Registers
Name
Abbrev.
TMA
R/W
R/W
R
Initial Value
H'10
Address
H'FFB0
H'FFB1
Timer mode register A
Timer counter A
TCA
H'00
9.2.2 Register Descriptions
1. Timer mode register A (TMA)
Bit
7
TMA7
0
6
TMA6
0
5
TMA5
0
4
—
1
3
2
1
0
TMA0
0
TMA3
0
TMA2
0
TMA1
0
Initial value
Read/Write
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
TMA is an 8-bit read/write register for selecting the prescaler, input clock, and output clock.
Upon reset, TMA is initialized to H'10.
Bits 7 to 5: Clock output select (TMA7 to TMA5)
Bits 7 to 5 choose which of eight clock signals is output at the TMOW pin. The system clock
divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. A 32.768 kHz signal
divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode.
Bit 7
Bit 6
Bit 5
TMA7
TMA6
TMA5
Clock Output
ø/32
0
0
1
0
1
0
1
0
1
0
1
0
1
(initial value)
ø/16
ø/8
ø/4
1
øW/32
øW/16
øW/8
øW/4
190
Bit 4: Reserved bit
Bit 4 is reserved; it is always read as 1, and cannot be modified.
Bits 3 to 0: Internal clock select (TMA3 to TMA0)
Bits 3 to 0 select the clock input to TCA. The selection is made as follows.
Description
Bit 3
Bit 2
Bit 1
Bit 0
Prescaler and Divider Ratio
or Overflow Period
TMA3 TMA2 TMA1 TMA0
Function
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PSS, ø/8192
PSS, ø/4096
PSS, ø/2048
PSS, ø/512
(initial value) Interval timer
PSS, ø/256
PSS, ø/128
PSS, ø/32
PSS, ø/8
Clock time
base
1
PSW, 1 s
PSW, 0.5 s
PSW, 0.25 s
PSW, 0.03125 s
PSW and TCA are reset
191
2. Timer counter A (TCA)
Bit
7
TCA7
0
6
TCA6
0
5
TCA5
0
4
TCA4
0
3
TCA3
0
2
TCA2
0
1
TCA1
0
0
TCA0
0
Initial value
Read/Write
R
R
R
R
R
R
R
R
TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock
source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A
(TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive
mode. When TCA overflows, the IRRTA bit in interrupt request register 1 (IRR1) is set to 1.
TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11.
Upon reset, TCA is initialized to H'00.
9.2.3 Timer Operation
1. Interval timer operation
When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit
interval timer.
Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval
timing resume immediately. The clock input to timer A is selected by bits TMA2 to TMA0 in
TMA; any of eight internal clock signals output by prescaler S can be selected.
After the count value in TCA reaches H'FF, the next clock signal input causes timer A to overflow,
setting bit IRRTA to 1 in interrupt request register 1 (IRR1). If IENTA = 1 in interrupt enable
register 1 (IENR1), a CPU interrupt is requested.*
At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A functions as
an interval timer that generates an overflow output at intervals of 256 input clock pulses.
Note: * For details on interrupts, see 3.3, Interrupts.
192
2. Real-time clock time base operation
When bit TMA3 in TMA is set to 1, timer A functions as a real-time clock time base by counting
clock signals output by prescaler W.
The overflow period of timer A is set by bits TMA1 and TMA0 in TMA. A choice of four
periods is available. In time base operation (TMA3 = 1), setting bit TMA2 to 1 clears both TCA
and prescaler W to their initial values of H'00.
3. Clock output
Setting bit TMOW in port mode register 1 (PMR1) to 1 causes a clock signal to be output at pin
TMOW. Eight different clock output signals can be selected by means of bits TMA7 to TMA5 in
TMA. The system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode.
A 32.768 kHz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and
subactive mode.
9.2.4 Timer A Operation States
Table 9-2-3 summarizes the timer A operation states.
Table 9-2-3 Timer A Operation States
Sub-
Sub-
Operation Mode
Reset Active
Sleep
Watch
active
sleep
Standby
TCA Interval
Reset Functions Functions Halted
Halted
Halted
Halted
Clock time base Reset Functions Functions Functions Functions Functions Halted
Reset Functions Retained Retained Functions Retained Retained
TMA
Note: When real-time clock time base function is selected as the internal clock of TCA in active
mode or sleep mode, the internal clock is not synchronous with the system clock, so it is
synchronized by a synchronizing circuit. This may result in a maximum error of 1/ø (s) in the
count cycle.
193
9.3 Timer B
9.3.1 Overview
Timer B is an 8-bit timer that increments each time a clock pulse is input. This timer has two
operation modes, interval and auto reload.
1. Features
Features of timer B are given below.
•
Choice of seven internal clock sources (ø/8192, ø/2048, ø/512, ø/256, ø/64, ø/16, ø/4) or an
external clock (can be used to count external events).
•
An interrupt is requested when the counter overflows.
2. Block Diagram
Figure 9-3-1 shows a block diagram of timer B.
TMB
TCB
TLB
PSS
ø
TMIB
IRRTB
Notation:
TMB:
TCB:
TLB:
Timer mode register B
Timer counter B
Timer load register B
IRRTB: Timer B overflow interrupt request flag
PSS: Prescaler S
Figure 9-3-1 Block Diagram of Timer B
194
3. Pin configuration
Table 9-3-1 shows the timer B pin configuration.
Table 9-3-1 Pin Configuration
Name
Abbrev.
I/O
Function
Timer B event input
TMIB
Input
Event input to TCB
4. Register configuration
Table 9-3-2 shows the register configuration of timer B.
Table 9-3-2 Timer B Registers
Name
Abbrev.
TMB
R/W
R/W
R
Initial Value
H'78
Address
H'FFB2
H'FFB3
H'FFB3
Timer mode register B
Timer counter B
Timer load register B
TCB
H'00
TLB
W
H'00
9.3.2 Register Descriptions
1. Timer mode register B (TMB)
Bit
7
TMB7
0
6
—
1
5
—
1
4
—
1
3
—
1
2
TMB2
0
1
0
TMB0
0
TMB1
0
Initial value
Read/Write
R/W
—
—
—
—
R/W
R/W
R/W
TMB is an 8-bit read/write register for selecting the auto-reload function and input clock.
Upon reset, TMB is initialized to H'78.
Bit 7: Auto-reload function select (TMB7)
Bit 7 selects whether timer B is used as an interval timer or auto-reload timer.
Bit 7
TMB7
Description
0
1
Interval timer function selected
Auto-reload function selected
(initial value)
195
Bits 6 to 3: Reserved bits
Bits 6 to 3 are reserved; they always read 1, and cannot be modified.
Bits 2 to 0: Clock select (TMB2 to TMB0)
Bits 2 to 0 select the clock input to TCB. For external event counting, either the rising or falling
edge can be selected.
Bit 2
Bit 1
Bit 0
TMB2
TMB1
TMB0
Description
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Internal clock: ø/8192
Internal clock: ø/2048
Internal clock: ø/512
Internal clock: ø/256
Internal clock: ø/64
(initial value)
Internal clock: ø/16
Internal clock: ø/4
External event (TMIB): rising or falling edge*
Note: * The edge of the external event signal is selected by bit IEG1 in the IRQ edge select
register (IEGR). See 3.3.2, Interrupt Control Registers, for details on the IRQ edge select
register. Be sure to set bit IRQ1 in port mode register 1 (PMR1) to 1 before setting bits
TMB2 to TMB0 to 111.
2. Timer counter B (TCB)
Bit
7
TCB7
0
6
TCB6
0
5
TCB5
0
4
TCB4
0
3
TCB3
0
2
TCB2
0
1
TCB1
0
0
TCB0
0
Initial value
Read/Write
R
R
R
R
R
R
R
R
TCB is an 8-bit read-only up-counter, which is incremented by internal clock or external event
input. The clock source for input to this counter is selected by bits TMB2 to TMB0 in timer mode
register B (TMB). TCB values can be read by the CPU at any time.
When TCB overflows from H'FF to H'00 or to the value set in TLB, the IRRTB bit in interrupt
request register 2 (IRR2) is set to 1.
TCB is allocated to the same address as timer load register B (TLB).
Upon reset, TCB is initialized to H'00.
196
3. Timer load register B (TLB)
Bit
7
TLB7
0
6
TLB6
0
5
TLB5
0
4
TLB4
0
3
TLB3
0
2
TLB2
0
1
TLB1
0
0
TLB0
0
Initial value
Read/Write
W
W
W
W
W
W
W
W
TLB is an 8-bit write-only register for setting the reload value of timer counter B.
When a reload value is set in TLB, the same value is loaded into timer counter B (TCB) as well,
and TCB starts counting up from that value. When TCB overflows during operation in auto-
reload mode, the TLB value is loaded into TCB. Accordingly, overflow periods can be set within
the range of 1 to 256 input clocks.
The same address is allocated to TLB as to TCB.
Upon reset, TLB is initialized to H'00.
9.3.3 Timer Operation
1. Interval timer operation
When bit TMB7 in timer mode register B (TMB) is cleared to 0, timer B functions as an 8-bit
interval timer.
Upon reset, TCB is cleared to H'00 and bit TMB7 is cleared to 0, so up-counting and interval
timing resume immediately. The clock input to timer B is selected from seven internal clock
signals output by prescaler S, or an external clock input at pin TMIB. The selection is made by
bits TMB2 to TMB0 of TMB.
After the count value in TCB reaches H'FF, the next clock signal input causes timer B to overflow,
setting bit IRRTB to 1 in interrupt request register 2 (IRR2). If IENTB = 1 in interrupt enable
register 2 (IENR2), a CPU interrupt is requested.*
At overflow, TCB returns to H'00 and starts counting up again.
During interval timer operation (TMB7 = 0), when a value is set in timer load register B (TLB),
the same value is set in TCB.
Note: * For details on interrupts, see 3.3, Interrupts.
197
2. Auto-reload timer operation
Setting bit TMB7 in TMB to 1 causes timer B to function as an 8-bit auto-reload timer. When a
reload value is set in TLB, the same value is loaded into TCB, becoming the value from which
TCB starts its count.
After the count value in TCB reaches H'FF, the next clock signal input causes timer B to overflow.
The TLB value is then loaded into TCB, and the count continues from that value. The overflow
period can be set within a range from 1 to 256 input clocks, depending on the TLB value.
The clock sources and interrupts in auto-reload mode are the same as in interval mode.
In auto-reload mode (TMB7 = 1), when a new value is set in TLB, the TLB value is also set in
TCB.
3. Event counter operation
Timer B can operate as an event counter, counting rising or falling edges of an external event
signal input at pin TMIB. External event counting is selected by setting bits TMB2 to TMB0 in
timer mode register B to all 1s (111).
When timer B is used to count external event input, bit IRQ1 in port mode register 1 (PMR1)
should be set to 1, and bit IEN1 in interrupt enable register 1 (IENR1) should be cleared to 0 to
disable IRQ interrupt requests.
1
9.3.4 Timer B Operation States
Table 9-3-3 summarizes the timer B operation states.
Table 9-3-3 Timer B Operation States
Sub-
Sub-
Operation Mode
Reset Active
Sleep
Watch
active
sleep
Standby
Halted
TCB Interval
Reset Functions
Functions Halted
Functions Halted
Halted
Halted
Halted
Halted
Auto reload Reset Functions
Reset Functions
Halted
TMB
Retained
Retained Retained Retained Retained
198
9.4 Timer C
9.4.1 Overview
Timer C is an 8-bit timer that increments or decrements each time a clock pulse is input. This
timer has two operation modes, interval and auto reload.
1. Features
The main features of timer C are given below.
•
Choice of seven internal clock sources (ø/8192, ø/2048, ø/512, ø/64, ø/16, ø/4, ø /4) or an
W
external clock (can be used to count external events).
•
•
•
An interrupt is requested when the counter overflows.
Can be switched between up- and down-counting by software or hardware.
When ø /4 is selected as the internal clock source, or when an external clock is selected,
W
timer C can function in subactive mode and subsleep mode.
199
2. Block diagram
Figure 9-4-1 shows a block diagram of timer C.
TMC
UD
TCC
TLC
PSS
ø
TMIC
øW/4
IRRTC
Notation:
TMC: Timer mode register C
TCC: Timer counter C
TLC:
Timer load register C
IRRTC: Timer C overflow interrupt request flag
PSS: Prescaler S
Figure 9-4-1 Block Diagram of Timer C
3. Pin configuration
Table 9-4-1 shows the timer C pin configuration.
Table 9-4-1 Pin Configuration
Name
Abbrev.
TMIC
UD
I/O
Function
Timer C event input
Timer C up/down control
Input
Input
Event input to TCC
Selection of counting direction
200
4. Register configuration
Table 9-4-2 shows the register configuration of timer C.
Table 9-4-2 Timer C Registers
Name
Abbrev.
TMC
R/W
R/W
R
Initial Value
H'18
Address
H'FFB4
H'FFB5
H'FFB5
Timer mode register C
Timer counter C
Timer load register C
TCC
H'00
TLC
W
H'00
9.4.2 Register Descriptions
1. Timer mode register C (TMC)
Bit
7
TMC7
0
6
TMC6
0
5
TMC5
0
4
—
1
3
—
1
2
TMC2
0
1
0
TMC0
0
TMC1
0
Initial value
Read/Write
R/W
R/W
R/W
—
—
R/W
R/W
R/W
TMC is an 8-bit read/write register for selecting the auto-reload function, counting direction, and
input clock.
Upon reset, TMC is initialized to H'18.
Bit 7: Auto-reload function select (TMC7)
Bit 7 selects whether timer C is used as an interval timer or auto-reload timer.
Bit 7
TMC7
Description
0
1
Interval timer function selected
Auto-reload function selected
(initial value)
201
Bits 6 and 5: Counter up/down control (TMC6 and TMC5)
These bits select the counting direction of timer counter C (TCC), or allow hardware to control the
counting direction using pin UD.
Bit 6
Bit 5
TMC6
TMC5
Description
0
0
1
0
1
*
TCC is an up-counter
TCC is a down-counter
(initial value)
TCC up/down control is determined by input at pin UD. TCC is a down-
counter if the UD input is high, and an up-counter if the UD input is low.
Note: * Don’t care
Bits 4 and 3: Reserved bits
Bits 4 and 3 are reserved; they are always read as 1, and cannot be modified.
Bits 2 to 0: Clock select (TMC2 to TMC0)
Bits 2 to 0 select the clock input to TCC. For external clock counting, either the rising or falling
edge can be selected.
Bit 2
Bit 1
Bit 0
TMC2
TMC1
TMC0
Description
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Internal clock: ø/8192
Internal clock: ø/2048
Internal clock: ø/512
Internal clock: ø/64
(initial value)
Internal clock: ø/16
Internal clock: ø/4
Internal clock: øW/4
External event (TMIC): rising or falling edge*
Note: * The edge of the external event signal is selected by bit IEG2 in the IRQ edge select
register (IEGR). See 3.3.2, Interrupt Control Registers, for details on the IRQ edge select
register. Be sure to set bit IRQ2 in port mode register 1 (PMR1) to 1 before setting bits
TMC2 to TMC0 to 111.
202
2. Timer counter C (TCC)
Bit
7
TCC7
0
6
TCC6
0
5
TCC5
0
4
TCC4
0
3
TCC3
0
2
TCC2
0
1
TCC1
0
0
TCC0
0
Initial value
Read/Write
R
R
R
R
R
R
R
R
TCC is an 8-bit read-only up-/down-counter, which is incremented or decremented by internal or
external clock input. The clock source for input to this counter is selected by bits TMC2 to TMC0
in timer mode register C (TMC). TCC values can be read by the CPU at any time.
When TCC overflows (from H'FF to H'00 or to the value set in TLC) or underflows (from H'00 to
H'FF or to the value set in TLC), the IRRTC bit in interrupt request register 2 (IRR2) is set to 1.
TCC is allocated to the same address as timer load register C (TLC).
Upon reset, TCC is initialized to H'00.
3. Timer load register C (TLC)
Bit
7
TLC7
0
6
TLC6
0
5
TLC5
0
4
TLC4
0
3
TLC3
0
2
TLC2
0
1
TLC1
0
0
TLC0
0
Initial value
Read/Write
W
W
W
W
W
W
W
W
TLC is an 8-bit write-only register for setting the reload value of TCC.
When a reload value is set in TLC, the same value is loaded into timer counter C (TCC) as well,
and TCC starts counting up or down from that value. When TCC overflows or underflows during
operation in auto-reload mode, the TLC value is loaded into TCC. Accordingly, overflow and
underflow periods can be set within the range of 1 to 256 input clocks.
The same address is allocated to TLC as to TCC.
Upon reset, TLC is initialized to H'00.
203
9.4.3 Timer Operation
1. Interval timer operation
When bit TMC7 in timer mode register C (TMC) is cleared to 0, timer C functions as an 8-bit
interval timer.
Upon reset, timer counter C (TCC) is initialized to H'00 and TMC to H'18, so counting and
interval timing resume immediately. The clock input to timer C is selected from seven internal
clock signals output by prescalers S and W, or an external clock input at pin TMIC. The selection
is made by bits TMC2 to TMC0 in TMC.
Either software or hardware can control whether TCC counts up or down. The selection is made
by TMC bits TMC6 and TMC5.
After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to
overflow (underflow), setting bit IRRTC to 1 in interrupt request register 2 (IRR2). If IENTC = 1
in interrupt enable register 2 (IENR2), a CPU interrupt is requested.*
At overflow or underflow, TCC returns to H'00 or H'FF and starts counting up or down again.
During interval timer operation (TMC7 = 0), when a value is set in timer load register C (TLC),
the same value is set in TCC.
Note: * For details on interrupts, see 3.3, Interrupts.
2. Auto-reload timer operation
Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When a
reload value is set in TLC, the same value is loaded into TCC, becoming the value from which
TCC starts its count.
After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to
overflow (underflow). The TLC value is then loaded TCC, and the count continues from that
value. The overflow (underflow) period can be set within a range from 1 to 256 input clocks,
depending on the TLC value.
204
The clock sources, up/down control, and interrupts in auto-reload mode are the same as in interval
mode.
In auto-reload mode (TMC7 = 1), when a new value is set in TLC, the TLC value is also set in TCC.
3. Event counter operation
Timer C can operate as an event counter, counting an event signal input at pin TMIC. External
event counting is selected by setting TMC bits TMC2 to TMC0 to all 1s (111). TCC counts up or
down at the rising or falling edge of the input at pin TMIC.
When timer C is used to count external event inputs, bit IRQ2 in port mode register 1 (PMR1)
should be set to 1, and bit IEN2 in interrupt enable register 1 (IENR1) should be cleared to 0 to
disable IRQ2 interrupt requests.
4. TCC up/down control by hardware
The counting direction of timer C can be controlled by input at pin UD. When bit TMC6 in TMC
is set to 1, high-level input at the UD pin selects down-counting, while low-level input selects up-
counting.
When using input at pin UD for this control function, set the UD bit in port mode register 2
(PMR2) to 1.
9.4.4 Timer C Operation States
Table 9-4-3 summarizes the timer C operation states.
Table 9-4-3 Timer C Operation States
Sub-
Sub-
Operation Mode Reset Active
Sleep
Watch
active
sleep
Standby
TCC Interval Reset Functions Functions Halted
Functions/ Functions/ Halted
Halted* Halted*
TCC Auto reload Reset Functions Functions Halted
TMC Reset Functions Retained Retained
Functions/ Functions/ Halted
Halted* Halted*
Functions Retained
Retained
Note: When øW/4 is selected as the internal clock of TCC in active mode or sleep mode, the
internal clock is not synchronous with the system clock, so it is synchronized by a
synchronizing circuit. This may result in a maximum error of 1/ø (s) in the count cycle.
* When timer C is operated in subactive mode or subsleep mode, either an external clock or
the øW/4 internal clock must be selected. The counter will not operate in these modes if
another clock is selected. If the internal øW/4 clock is selected when øW/8 is being used
as the subclock øSUB, the lower 2 bits of the counter will operate on the same cycle, with
the least significant bit not being counted.
205
9.5 Timer F
9.5.1 Overview
Timer F is a 16-bit timer with an output compare function. Compare match signals can be used to
reset the counter, request an interrupt, or toggle the output. Timer F can also be used for external
event counting, and can operate as two independent 8-bit timers, timer FH and timer FL.
1. Features
Features of timer F are given below.
•
•
Choice of four internal clock sources (ø/32, ø/16, ø/4, ø/2) or an external clock (can be used
as an external event counter).
Output from pin TMOFH is toggled by one compare match signal (the initial value of the
toggle output can be set).
•
•
•
Counter can be reset by the compare match signal.
Two interrupt sources: counter overflow and compare match.
Can operate as two independent 8-bit timers (timer FH and timer FL) in 8-bit mode.
Timer FH
— 8-bit timer (clocked by timer FL overflow signals when timer F operates as a 16-bit timer).
— Choice of four internal clocks (ø/32, ø/16, ø/4, ø/2).
— Output from pin TMOFH is toggled by one compare match signal (the initial value of the
toggle output can be set).
— Counter can be reset by the compare match signal.
— Two interrupt sources: counter overflow and compare match.
Timer FL
— 8-bit timer/event counter
— Choice of four internal clocks (ø/32, ø/16, ø/4, ø/2) or event input at pin TMIF.
— Output from pin TMOFL is toggled by one compare match signal (the initial value of the
toggle output can be set).
— Counter can be reset by the compare match signal.
— Two interrupt sources: counter overflow and compare match.
206
2. Block diagram
Figure 9-5-1 shows a block diagram of timer F.
ø
PSS
IRRTFL
TCRF
TCFL
TMIF
Toggle
TMOFL
Compare circuit
OCRFL
circuit
TCFH
Compare circuit
OCRFH
Toggle
circuit
TMOFH
Match
TCSRF
IRRTFH
Notation:
TCRF:
Timer control register F
TCSRF: Timer control status register F
TCFH:
TCFL:
8-bit timer counter FH
8-bit timer counter FL
OCRFH: Output compare register FH
OCRFL: Output compare register FL
IRRTFH: Timer FH interrupt request flag
IRRTFL: Timer FL interrupt request flag
PSS:
Prescaler S
Figure 9-5-1 Block Diagram of Timer F
207
3. Pin configuration
Table 9-5-1 shows the timer F pin configuration.
Table 9-5-1 Pin Configuration
Name
Abbrev.
TMIF
I/O
Function
Timer F event input
Timer FH output
Timer FL output
Input
Output
Output
Event input to TCFL
Timer FH output
Timer FL output
TMOFH
TMOFL
4. Register configuration
Table 9-5-2 shows the register configuration of timer F.
Table 9-5-2 Timer F Registers
Name
Abbrev.
TCRF
R/W
W
Initial Value
H'00
Address
H'FFB6
H'FFB7
H'FFB8
H'FFB9
H'FFBA
H'FFBB
Timer control register F
Timer control/status register F
8-bit timer counter FH
8-bit timer counter FL
Output compare register FH
Output compare register FL
TCSRF
TCFH
R/W
R/W
R/W
R/W
R/W
H'00
H'00
TCFL
H'00
OCRFH
OCRFL
H'FF
H'FF
9.5.2 Register Descriptions
1. 16-bit timer counter (TCF)
8-bit timer counter (TCFH)
8-bit timer counter (TCFL)
TCF
Bit
15
0
14
0
13
0
12
0
11
0
10
0
9
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Initial value
0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCFH TCFL
208
TCF is a 16-bit read/write up-counter consisting of two cascaded 8-bit timer counters, TCFH and
TCFL. TCF can be used as a 16-bit counter, with TCFH as the upper 8 bits and TCFL as the
lower 8 bits of the counter, or TCFH and TCFL can be used as independent 8-bit counters.
TCFH and TCFL can be read and written by the CPU, but in 16-bit mode, data transfer with the
CPU takes place via a temporary register (TEMP). For details see 9.5.3, Interface with the CPU.
Upon reset, TCFH and TCFL are each initialized to H'00.
•
16-bit mode (TCF)
16-bit mode is selected by clearing bit CKSH2 to 0 in timer control register F (TCRF). The TCF
input clock is selected by TCRF bits CKSL2 to CKSL0.
Timer control status register F (TCSRF) can be set so that counter TCF will be cleared by
compare match.
When TCF overflows from H'FFFF to H'0000, the overflow flag (OVFH) in TCSRF is set to 1. If
bit OVIEH in TCSRF is set to 1 when an overflow occurs, bit IRRTFH in interrupt request register
2 (IRR2) will be set to 1; and if bit IENTFH in interrupt enable register 2 (IENR2) is set to 1, a
CPU interrupt will be requested.
•
8-bit mode (TCFH, TCFL)
When bit CKSH2 in timer control register F (TCRF) is set to 1, timer F functions as two separate
8-bit counters, TCFH and TCFL. The TCFH (TCFL) input clock is selected by TCRF bits
CKSH2 to CKSH0 (CKSL2 to CKSL0).
TCFH (TCFL) can be cleared by a compare match signal. This designation is made in bit
CCLRH (CCLRL) in TCSRF.
When TCFH (TCFL) overflows from H'FF to H'00, the overflow flag OVFH (OVFL) in TCSRF is
set to 1. If bit OVIEH (OVIEL) in TCSRF is set to 1 when an overflow occurs, bit IRRTFH
(IRRTHL) in interrupt request register 2 (IRR2) will be set to 1; and if bit IENTFH (IENTFL) in
interrupt enable register 2 (IENR2) is set to 1, a CPU interrupt will be requested.
209
2. 16-bit output compare register (OCRF)
8-bit output compare register (OCRFH)
8-bit output compare register (OCRFL)
OCRF
Bit
15
1
14
1
13
1
12
1
11
1
10
1
9
8
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
Initial value
1
1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
OCRFH OCRFL
OCRF is a 16-bit read/write output compare register consisting of two 8-bit read/write registers
OCRFH and OCRFL. It can be used as a 16-bit output compare register, with OCRFH as the
upper 8 bits and OCRFL as the lower 8 bits of the register, or OCRFH and OCRFL can be used as
independent 8-bit registers.
OCRFH and OCRFL can be read and written by the CPU, but in 16-bit mode, data transfer with
the CPU takes place via a temporary register (TEMP). For details see 9.5.3, Interface with the
CPU.
Upon reset, OCRFH and OCRFL are each initialized to H'FF.
•
16-bit mode (OCRF)
16-bit mode is selected by clearing bit CKSH2 to 0 in timer control register F (TCRF). The
OCRF contents are always compared with the 16-bit timer counter (TCF). When the contents
match, the compare match flag (CMFH) in TCSRF is set to 1. Also, IRRTFH in interrupt request
register 2 (IRR2) is set to 1. If bit IENTFH in interrupt enable register 2 (IENR2) is set to 1, a
CPU interrupt is requested.
Output for pin TMOFH can be toggled by compare match. The output level can also be set to
high or low by bit TOLH of timer control register F (TCRF).
•
8-bit mode (OCRFH, OCRFL)
Setting bit CKSH2 in TCRF to 1 results in two independent output compare registers, OCRFH
and OCRFL.
The OCRFH contents are always compared with TCFH, and the OCRFL contents are always
compared with TCFL. When the contents match, the compare match flag (CMFH or CMFL) in
TCSRF is set to 1. Also, bit IRRTFH (IRRTFL) in interrupt request register 2 (IRR2) set to 1. If
bit IENTFH (IENTFL) in interrupt enable register 2 (IENR2) is set to 1 at this time, a CPU
interrupt is requested.
210
The output at pin TMOFH (TMOFL) can be toggled by compare match. The output level can also
be set to high or low by bit TOLH (TOLL) of the timer control register (TCRF).
3. Timer control register F (TCRF)
Bit
7
TOLH
0
6
5
4
3
2
1
0
CKSH2 CKSH1 CKSH0 TOLL
CKSL2 CKSL1 CKSL0
Initial value
Read/Write
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
TCRF is an 8-bit write-only register. It is used to switch between 16-bit mode and 8-bit mode, to
select among four internal clocks and an external clock, and to select the output level at pins
TMOFH and TMOFL.
Upon reset, TCRF is initialized to H'00.
Bit 7: Toggle output level H (TOLH)
Bit 7 sets the output level at pin TMOFH. The setting goes into effect immediately after this bit is
written.
Bit 7
TOLH
Description
Low level
0
1
(initial value)
High level
Bits 6 to 4: Clock select H (CKSH2 to CKSH0)
Bits 6 to 4 select the input to TCFH from four internal clock signals or the overflow of TCFL.
Bit 6
Bit 5
Bit 4
CKSH2 CKSH1 CKSH0 Description
0
*
*
16-bit mode selected. TCFL overflow signals are
counted.
(initial value)
1
1
1
1
0
0
1
1
0
1
0
1
Internal clock: ø/32
Internal clock: ø/16
Internal clock: ø/4
Internal clock: ø/2
Note: * Don’t care
211
Bit 3: Toggle output level L (TOLL)
Bit 3 sets the output level at pin TMOFL. The setting goes into effect immediately after this bit is
written.
Bit 3
TOLL
Description
Low level
0
1
(initial value)
High level
Bits 2 to 0: Clock select L (CKSL2 to CKSL0)
Bits 2 to 0 select the input to TCFL from four internal clock signals or external event input.
Bit 2
Bit 1
Bit 0
CKSL2 CKSL1 CKSL0 Description
0
*
*
External event (TMIF). Rising or falling edge is
counted (see note).
(initial value)
1
1
1
1
0
0
1
1
0
1
0
1
Internal clock: ø/32
Internal clock: ø/16
Internal clock: ø/4
Internal clock: ø/2
* Don’t care
Note: The edge of the external event signal is selected by bit IEG3 in the IRQ edge select register
(IEGR). See 3.3.2, Interrupt Control Registers, for details on the IRQ edge select register.
Note that switching the TMIF pin function by changing bit IRQ3 in port mode register 1
(PMR1) from 0 to 1 or from 1 to 0 while the TMIF pin is at the low level may cause the timer
F counter to be incremented.
4. Timer control/status register F (TCSRF)
Bit
7
OVFH
0
6
5
4
3
2
CMFL
0
1
0
CMFH OVIEH CCLRH OVFL
OVIEL CCLRL
Initial value
Read/Write
0
0
0
0
0
0
*
*
*
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Only 0 can be written, to clear flag.
TCSRF is an 8-bit read/write register. It is used for counter clear selection, overflow and compare
match indication, and enabling of interrupts caused by timer overflow.
Upon reset, TCSRF is initialized to H'00.
212
Bit 7: Timer overflow flag H (OVFH)
Bit 7 is a status flag indicating TCFH overflow (H'FF to H'00). This flag is set by hardware and
cleared by software. It cannot be set by software.
Bit 7
OVFH
Description
0
Clearing conditions:
(initial value)
After reading OVFH = 1, cleared by writing 0 to OVFH
1
Setting conditions:
Set when the value of TCFH goes from H'FF to H'00
Bit 6: Compare match flag H (CMFH)
Bit 6 is a status flag indicating a compare match between TCFH and OCRFH. This flag is set by
hardware and cleared by software. It cannot be set by software.
Bit 6
CMFH
Description
0
Clearing conditions:
(initial value)
After reading CMFH = 1, cleared by writing 0 to CMFH
1
Setting conditions:
Set when the TCFH value matches OCRFH value
Bit 5: Timer overflow interrupt enable H (OVIEH)
Bit 5 enables or disables TCFH overflow interrupts.
Bit 5
OVIEH
Description
0
1
TCFH overflow interrupt disabled
TCFH overflow interrupt enabled
(initial value)
213
Bit 4: Counter clear H (CCLRH)
In 16-bit mode, bit 4 selects whether or not TCF is cleared when a compare match occurs between
TCF and OCRF.
In 8-bit mode, bit 4 selects whether or not TCFH is cleared when a compare match occurs between
TCFH and OCRFH.
Bit 4
CCLRH
Description
0
16-bit mode: TCF clearing by compare match disabled
8-bit mode: TCFH clearing by compare match disabled
(initial value)
1
16-bit mode: TCF clearing by compare match enabled
8-bit mode: TCFH clearing by compare match enabled
Bit 3: Timer overflow flag L (OVFL)
Bit 3 is a status flag indicating TCFL overflow (H'FF to H'00). This flag is set by hardware and
cleared by software. It cannot be set by software.
Bit 3
OVFL
Description
0
Clearing conditions:
(initial value)
After reading OVFL = 1, cleared by writing 0 to OVFL
1
Setting conditions:
Set when the value of TCFL goes from H'FF to H'00
Bit 2: Compare match flag L (CMFL)
Bit 2 is a status flag indicating a compare match between TCFL and OCRFL. This flag is set by
hardware and cleared by software. It cannot be set by software.
Bit 2
CMFL
Description
0
Clearing conditions:
(initial value)
After reading CMFL = 1, cleared by writing 0 to CMFL
1
Setting conditions:
Set when the TCFL value matches the OCRFL value
214
Bit 1: Timer overflow interrupt enable L (OVIEL)
Bit 1 enables or disables TCFL overflow interrupts.
Bit 1
OVIEL
Description
0
1
TCFL overflow interrupt disabled
TCFL overflow interrupt enabled
(initial value)
Bit 0: Counter clear L (CCLRL)
Bit 0 selects whether or not TCFL is cleared when a compare match occurs between TCFL and
OCRFL.
Bit 0
CCLRL
Description
0
1
TCFL clearing by compare match disabled
TCFL clearing by compare match enabled
(initial value)
9.5.3 Interface with the CPU
TCF and OCRF are 16-bit read/write registers, whereas the data bus between the CPU and on-chip
peripheral modules has an 8-bit width. For this reason, when the CPU accesses TCF or OCRF, it
makes use of an 8-bit temporary register (TEMP).
In 16-bit mode, when reading or writing TCF or writing OCRF, always use two consecutive byte
size MOV instructions, and always access the upper byte first. Data will not be transferred
properly if only the upper byte or only the lower byte is accessed. In 8-bit mode there is no such
restriction on the order of access.
•
Write access
When the upper byte is written, the upper-byte data is loaded into the TEMP register. Next when
the lower byte is written, the data in TEMP goes to the upper byte of the register, and the lower-
byte data goes directly to the lower byte of the register. Figure 9-5-2 shows a TCF write operation
when H'AA55 is written to TCF.
215
•
Read access
When the upper byte of TCF is read, the upper-byte data is sent directly to the CPU, and the lower
byte is loaded into TEMP. Next when the lower byte is read, the lower byte in TEMP is sent to the
CPU.
When the upper byte of OCRF is read, the upper-byte data is sent directly to the CPU. Next when
the lower byte is read, the lower-byte data is sent directly to the CPU.
Figure 9-5-3 shows a TCF read operation when H'AAFF is read from TCF.
216
Upper byte write
Internal data bus
CPU
(H'AA)
TEMP
(H'AA)
TCFH
TCFL
(
)
(
)
Lower byte write
Internal data bus
CPU
(H'55)
TEMP
(H'AA)
TCFH
(H'AA)
TCFL
(H'55)
Figure 9-5-2 TCF Write Operation (CPU → TCF)
217
Upper byte read
Internal data bus
CPU
(H'AA)
TEMP
(H'FF)
TCFH
(H'AA)
TCFL
(H'FF)
Lower byte read
Internal data bus
CPU
(H'FF)
TEMP
(H'FF)
TCFH
TCFL
(AB)*
(00) *
Note: *Becomes H'AB00 if counter is incremented once.
Figure 9-5-3 TCF Read Operation (TCF → CPU)
218
9.5.4 Timer Operation
Timer F is a 16-bit timer/counter that increments with each input clock. When the value set in
output compare register F matches the count in timer F, the timer can be cleared, an interrupt can
be requested, and the port output can be toggled. Timer F can also be used as two independent
8-bit timers.
1. Timer F operation
Timer F can operate in either 16-bit timer mode or 8-bit timer mode. These modes are described
below.
•
16-bit timer mode
Timer F operates in 16-bit timer mode when the CKSH2 bit in timer control register F (TCRF) is
cleared to 0.
A reset initializes timer counter F (TCF) to H'0000, output compare register F (OCRF) to H'FFFF,
and timer control register F (TCRF) and timer control status register F (TCSRF) to H'00. Timer F
begins counting external event input signals (TMIF). The edge of the external event signal is
selected by the IEG3 bit in the IRQ edge select register (IEGR).
Instead of counting external events, timer F can be switched by bits CKSL2 to CKSL0 in TCRF to
count one of four internal clocks output by prescaler S.
TCF is continuously compared with the contents of OCRF. When these two values match, the
CMFH bit in TCSRF is set to 1. At this time if IENTFH of IENR2 is 1, a CPU interrupt is
requested and the output at pin TMOFH is toggled. If the CCLRH bit in TCSRF is 1, timer F is
cleared. The output at pin TMOFH can also be set by the TOLH bit in TCRF.
If timer F overflows (from H'FFFF to H'0000), the OVFH bit in TCSRF is set to 1. At this time, if
the OVIEH bit in TCSRF and the IENTFH bit in IENR2 are both 1, a CPU interrupt is requested.
219
•
8-bit timer mode
When the CKSH2 bit in TCRF is set to 1, timer F operates as two independent 8-bit timers, TCFH
and TCFL. The input clock of TCFH/TCFL is selected by bits CKSH2 to CKSH0/CKSL2 to
CKSL0 in TCRF.
When TCFH/TCFL and the contents of OCRFH/OCRFL match, the CMFH/CMFL bit in TCSRF
is set to 1. If the IENTFH/IENTFL bit in IENR2 is 1, a CPU interrupt is requested and the output
at pin TMOFH/TMOFL is toggled. If the CCLRH/CCLRL bit in TCRF is 1, TCFH/TCFL is
cleared. The output at pin TMOFH/TMOFL can also be set by the TOLH/TOLL bit in TCRF.
When TCFH/TCFL overflows from H'FF to H'00, the OVFH/OVFL bit in TCSRF is set to 1. At
this time, if the OVIEH/OVIEL bit in TCSRF and the IENTFH/IENTFL bit in IENR2 are both 1,
a CPU interrupt is requested.
2. TCF count timing
TCF is incremented by each pulse of the input clock (internal or external clock).
•
Internal clock
The settings of bits CKSH2 to CKSH0 or bits CKSL2 to CKSL0 in TCRF select one of four
internal clock signals divided from the system clock (ø), namely, ø/32, ø/16, ø/4, or ø/2.
•
External clock
External clock input is selected by clearing bit CKSL2 to 0 in TCRF. Either rising or falling edges
of the clock input can be counted. The edge is selected by bit IEG3 in IEGR. An external clock
pulse width of at least two system clock cycles (ø) is necessary; otherwise the counter will not
operate properly.
220
3. TMOFH and TMOFL output timing
The outputs at pins TMOFH and TMOFL are the values set in bits TOLH and TOLL in TCRF.
When a compare match occurs, the output value is inverted. Figure 9-5-4 shows the output
timing.
ø
TMIF
(when IEG3 = 1)
Count input
clock
TCF
N
N + 1
N
N + 1
OCRF
N
N
Compare match
signal
TMOFH, TMOFL
Figure 9-5-4 TMOFH, TMOFL Output Timing
4. TCF clear timing
TCF can be cleared at compare match with OCRF.
5. Timer overflow flag (OVF) set timing
OVF is set to 1 when TCF overflows (goes from H'FFFF to H'0000).
6. Compare match flag set timing
The compare match flags (CMFH or CMFL) are set to 1 when a compare match occurs between
TCF and OCRF. A compare match signal is generated in the final state in which the values match
(when TCF changes from the matching count value to the next value). When TCF and OCRF
match, a compare match signal is not generated until the next counter clock pulse.
221
7. Timer F operation states
Table 9-5-3 summarizes the timer F operation states.
Table 9-5-3 Timer F Operation States
Sub-
Sub-
Operation Mode Reset Active
Sleep
Watch
active
sleep
Standby
TCF
Reset Functions
Reset Functions
Reset Functions
Reset Functions
Functions Halted
Halted
Halted
Halted
OCRF
TCRF
TCSRF
Retained
Retained
Retained
Retained Retained Retained Retained
Retained Retained Retained Retained
Retained Retained Retained Retained
9.5.5 Application Notes
The following conflicts can arise in timer F operation.
1. 16-bit timer mode
The output at pin TMOFH toggles when all 16 bits match and a compare match signal is
generated. If the compare match signal occurs at the same time as new data is written in TCRF by
a MOV instruction, however, the new value written in bit TOLH will be output at pin TMOFH.
The TMOFL output in 16-bit mode is indeterminate, so this output should not be used. Use the
pin as a general input or output port.
If an OCRFL write occurs at the same time as a compare match signal, the compare match signal
is inhibited. If a compare match occurs between the written data and the counter value, however, a
compare match signal will be generated at that point. The compare match signal is output in
synchronization with the TCFL clock, so if this clock is stopped no compare match signal will be
generated, even if a compare match occurs.
Compare match flag CMFH is set when all 16 bits match and a compare match signal is
generated; bit CMFL is set when the setting conditions are met for the lower 8 bits.
The overflow flag (OVFH) is set when TCF overflows; bit OVFL is set if the setting conditions
are met when the lower 8 bits overflow. If a write to TCFL occurs at the same time as an overflow
signal, the overflow signal is not output.
222
2. 8-bit timer mode
TCFH and OCRFH
The output at pin TMOFH toggles when there is a compare match. If the compare match signal
occurs at the same time as new data is written in TCRF by a MOV instruction, however, the new
value written in bit TOLH will be output at pin TMOFH.
If an OCRFH write occurs at the same time as a compare match signal, the compare match signal
is inhibited. If a compare match occurs between the written data and the counter value, however, a
compare match signal will be generated at that point. The compare match signal is output in
synchronization with the TCFH clock.
If a TCFH write occurs at the same time as an overflow signal, the overflow signal is not output.
TCFL and OCRFL
The output at pin TMOFL toggles when there is a compare match. If the compare match signal
occurs at the same time as new data is written in TCRF by a MOV instruction, however, the new
value written in bit TOLL will be output at pin TMOFL.
If an OCRFL write occurs at the same time as a compare match signal, the compare match signal
is inhibited. If a compare match occurs between the written data and the counter value, however,
a compare match signal will be generated at that point. The compare match signal is output in
synchronization with the TCFL clock, so if this clock is stopped no compare match signal will be
generated, even if a compare match occurs.
If a TCFL write occurs at the same time as an overflow signal, the overflow signal is not output.
223
9.6 Timer G
9.6.1 Overview
Timer G is an 8-bit timer, with input capture functions for separately capturing the rising edge and
falling edge of pulses input at the input capture pin (input capture input signal). Timer G has a
built-in noise canceller circuit that can eliminate high-frequency noise from the input capture
signal, enabling accurate measurement of its duty cycle. When timer G is not used for input
capture, it functions as an 8-bit interval timer.
1. Features
Features of timer G are given below.
•
•
Choice of four internal clock sources (ø/64, ø/32, ø/2, ø /2)
W
Input capture function
Separate input capture registers are provided for the rising and falling edges.
Counter overflow detection
•
•
Can detect whether overflow occurred when the input capture signal was high or low.
Choice of counter clear triggers
The counter can be cleared at the rising edge, falling edge, or both edges of the input capture
signal.
•
Two interrupt sources
Interrupts can be requested by input capture and by overflow. For input capture, the rising or
falling edge can be selected.
•
•
Built-in noise-canceller circuit
The noise canceller circuit can eliminate high-frequency noise in the input capture signal.
Operates in subactive and subsleep modes
When ø /2 is selected as the internal clock source, timer G can operate in the subactive and
W
subsleep modes.
224
2. Block diagram
Figure 9-6-1 shows a block diagram of timer G.
PSS
ø
TMG
ICRGF
TCG
Level
sense
circuit
øW/2
Edge
sense
circuit
Noise
canceller
circuit
TMIG
NCS
ICRGR
IRRTG
Notation:
TMG:
TCG:
Timer mode register G
Timer counter G
ICRGF: Input capture register GF
ICRGR: Input capture register GR
IRRTG: Timer G interrupt request flag
NCS:
PSS:
Noise canceller select
Prescaler S
Figure 9-6-1 Block Diagram of Timer G
3. Pin configuration
Table 9-6-1 shows the timer G pin configuration.
Table 9-6-1 Pin Configuration
Name
Abbrev.
I/O
Function
Timer G capture input
Timer G capture input
TMIG
Input
225
4. Register configuration
Table 9-6-2 shows the register configuration of timer G.
Table 9-6-2 Timer G Registers
Name
Abbrev.
TMG
R/W
R/W
—
Initial Value
H'00
Address
H'FFBC
—
Timer mode register G
Timer counter G
TCG
H'00
Input capture register GF
Input capture register GR
ICRGF
ICRGR
R
H'00
H'FFBD
H'FFBE
R
H'00
9.6.2 Register Descriptions
1. Timer counter G (TCG)
Bit
7
TCG7
0
6
TCG6
0
5
TCG5
0
4
TCG4
0
3
2
1
0
TCG0
0
TCG3
0
TCG2
0
TCG1
0
Initial value
Read/Write
—
—
—
—
—
—
—
—
Timer counter G (TCG) is an 8-bit up-counter which is incremented by an input clock. The input
clock signal is selected by bits CKS1 and CKS0 in timer mode register G (TMG).
To use TCG as an input capture timer, set bit TMIG to 1 in PMR1; to use TCG as an interval
timer, clear bit TMIG to 0.* When TCG is used as an input capture timer, the TCG value can be
cleared at the rising edge, falling edge, or both edges of the input capture signal, depending on
settings in TMG.
When TCG overflows (goes from H'FF to H'00), if the timer overflow interrupt enable bit (OVIE)
is set to 1 in TMG, bit IRRTG in interrupt request register 2 (IRR2) is set to 1. If in addition bit
IENTG in interrupt enable register 2 (IENR2) is set to 1, a CPU interrupt is requested. Details on
interrupts are given in 3.3, Interrupts.
TCG cannot be read or written by the CPU.
Upon reset, TCG is initialized to H'00.
Note: * An input capture signal may be generated when TMIG is rewritten.
226
2. Input capture register GF (ICRGF)
Bit
7
6
5
4
3
2
1
0
ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
ICRGF is an 8-bit read-only register. When the falling edge of the input capture signal is
detected, the TCG value at that time is transferred to ICRGF. If the input capture interrupt select
bit (IIEGS) is set to 1 in TMG, bit IRRTG in interrupt request register 2 (IRR2) is set to 1. If in
addition bit IENTG in interrupt enable register 2 (IENR2) is set to 1, a CPU interrupt is requested.
Details on interrupts are given in 3.3, Interrupts.
To ensure proper input capture when the noise canceller is not used, the pulse width of the input
capture signal should be at least 2ø or 2ø
Upon reset, ICRGF is initialized to H'00.
3. Input capture register GR (ICRGR)
.
SUB
Bit
7
6
5
4
3
2
1
0
ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
ICRGR is an 8-bit read-only register. When the rising edge of the input capture signal is detected,
the TCG value at that time is sent to ICRGR. If the IIEGS bit is cleared to 0 in TMG, bit IRRTG
in interrupt request register 2 (IRR2) is set to 1. If in addition bit IENTG in interrupt enable
register 2 (IENR2) is set to 1, a CPU interrupt is requested. Details on interrupts are given in 3.3,
Interrupts.
To ensure proper input capture when the noise canceller is not used, the pulse width of the input
capture signal should be at least 2ø or 2ø
.
SUB
Upon reset, ICRGR is initialized to H'00.
227
4. Timer mode register G (TMG)
Bit
7
6
5
OVIE
0
4
3
2
1
CKS1
0
0
CKS0
0
OVFH
0
OVFL
0
IIEGS CCLR1 CCLR0
Initial value
Read/Write
0
0
0
R/W*
R/W*
R/W
R/W
R/W
R/W
R/W
R/W
Note: * Only 0 can be written, to clear flag.
TMG is an 8-bit read/write register. It controls the choice of four input clocks, counter clear
selection, and edge selection for input capture interrupt requests. It also indicates overflow status
and enables or disables overflow interrupt requests.
Upon reset, TMG is initialized to H'00.
Bit 7: Timer overflow flag H (OVFH)
Bit 7 is a status flag indicating that TCG overflowed (from H'FF to H'00) when the input capture
signal was high. This flag is set by hardware and cleared by software. It cannot be set by
software.
Bit 7
OVFH
Description
0
Clearing conditions:
(initial value)
After reading OVFH = 1, cleared by writing 0 to OVFH
1
Setting conditions:
Set when the value of TCG overflows from H'FF to H'00
Bit 6: Timer overflow flag L (OVFL)
Bit 6 is a status flag indicating that TCG overflowed (from H'FF to H'00) when the input capture
signal was low, or in interval timer operation. This flag is set by hardware and cleared by
software. It cannot be set by software.
Bit 6
OVFL
Description
0
Clearing conditions:
(initial value)
After reading OVFL = 1, cleared by writing 0 to OVFL
1
Setting conditions:
Set when the value of TCG overflows from H'FF to H'00
228
Bit 5: Timer overflow interrupt enable (OVIE)
Bit 5 enables or disables TCG overflow interrupts.
Bit 5
OVIE
Description
0
1
TCG overflow interrupt disabled
TCG overflow interrupt enabled
(initial value)
Bit 4: Input capture interrupt edge select (IIEGS)
Bit 4 selects the input signal edge at which input capture interrupts are requested.
Bit 4
IIEGS
Description
0
1
Interrupts are requested at the rising edge of the input capture signal
Interrupts are requested at the falling edge of the input capture signal
(initial value)
Bits 3, 2: Counter clear 1, 0 (CCLR1, CCLR0)
Bits 3 and 2 designate whether TCG is cleared at the rising, falling, or both edges of the input
capture signal, or is not cleared.
Bit 3
Bit 2
CCLR1 CCLR0 Description
0
0
1
1
0
1
0
1
TCG is not cleared
(initial value)
TCG is cleared at the falling edge of the input capture signal
TCG is cleared at the rising edge of the input capture signal
TCG is cleared at both edges of the input capture signal
Bits 1, 0: Clock select (CKS1, CKS0)
Bits 1 and 0 select the clock input to TCG from four internal clock signals.
Bit 1
Bit 0
CKS1
CKS0
Description
0
0
1
1
0
1
0
1
Internal clock: ø/64
Internal clock: ø/32
Internal clock: ø/2
Internal clock: øW/2
(initial value)
229
9.6.3 Noise Canceller Circuit
The noise canceller circuit built into the H8/3834U Series is a digital low-pass filter that rejects
high-frequency pulse noise in the input at the input capture pin. The noise canceller circuit is
enabled by the noise canceller select (NCS) bit in port mode register 2 (PMR2)*.
Figure 9-6-2 shows a block diagram of the noise canceller circuit.
Sampling clock
C
C
C
C
C
Input capture
signal
D
Q
D
Q
D
Q
D
Q
D
Q
Match
detection
circuit
Noise
canceller
output
latch
latch
latch
latch
latch
∆t
Sampling clock
∆ t: Selected by bits CKS1, CKS0.
Figure 9-6-2 Block Diagram of Noise Canceller Circuit
The noise canceller consists of five latch circuits connected in series, and a match detection
circuit. When the noise canceller function is disabled (NCS = 0), the system clock is selected as
the sampling clock. When the noise canceller is enabled (NCS = 1), the internal clock selected by
bits CKS1 and CKS0 in TMG becomes the sampling clock. The input signal is sampled at the
rising edge of this clock pulse. Data is considered correct when the outputs of all five latch
circuits match. If they do not match, the previous value is retained. Upon reset, the noise
canceller output is initialized after the falling edge of the input capture signal has been sampled
five times. Accordingly, after the noise canceller function is enabled, pulses that have a pulse
width five times greater than the sampling clock will be recognized as input capture signals.
If the noise canceller circuit is not used, the input capture signal pulse width must be at least 2ø or
2ø
in order to ensure proper input capture operation.
SUB
230
Note: * Rewriting the NCS bit may cause an internal input capture signal to be generated.
Figure 9-6-3 shows a typical timing diagram for the noise canceller circuit. In this example, a
high-level input at the input capture pin is rejected as noise because its pulse width is less than five
sampling clock ø cycles.
Input capture
input signal
Sampling
clock
Noise canceller
output
Rejected as noise
Figure 9-6-3 Noise Canceller Circuit Timing (Example)
9.6.4 Timer Operation
Timer G is an 8-bit timer with input capture and interval timer functions.
1. Timer G functions
Timer G is an 8-bit timer/counter that functions as an input capture timer or an interval timer.
These two functions are described below.
•
Input capture timer operation
Timer G functions as an input capture timer when bit TMIG of port mode register 1 (PMR1) is
set to 1.*
At reset, timer mode register G (TMG), timer counter G (TCG), input capture register GF
(ICRGF), and input capture register GR (ICRGR) are all initialized to H'00.
Immediately after reset, TCG begins counting an internal clock with a frequency of ø divided by
64 (ø/64). Three other internal clocks can be selected using bits CKS1 and CKS0 of TMG.
At the rising edge/falling edge of the input capture signal input to pin TMIG, the value of TCG is
copied into ICRGR/ICRGF. If the input edge is the same as the edge selected by the IIEGS bit of
TMG, then bit IRRTG is set to 1 in IRR2. If bit IENTG is also set to 1 in IENR2, a CPU interrupt
is requested. For details on interrupts, see section 3.3, Interrupts.
231
TCG can be cleared to 0 at the rising edge, falling edge, or both edges of the input capture signal
as determined with bits CCLR1 and CCLR0 of TMG. If TCG overflows while the input capture
signal is high, bit OVFH of TMG is set. If TCG overflows while the input capture signal is low,
bit OVFL of TMG is set. When either of these bits is set, if bit OVIE of TMG is currently set to 1,
then bit IRRTG is set to 1 in IRR2. If bit IENTG is also set to 1 in IENR2, then timer G requests a
CPU interrupt. For further details see 3.3, Interrupts.
Timer G has a noise canceller circuit that rejects high-frequency pulse noise in the input to pin
TMIG. See 9.6.3, Noise Canceller Circuit, for details.
Note: * Rewriting the TMIG bit may cause an internal input capture signal to be generated.
•
Interval timer operation
Timer G functions as an interval timer when bit TMIG is cleared to 0 in PMR1. Following a reset,
TCG starts counting cycles of the ø/64 internal clock. This is one of four internal clock sources
that can be selected by bits CKS1 and CKS0 of TMG. TCG counts up according to the selected
clock source. When it overflows from H'FF to H'00, bit OVFL of TMG is set to 1. If bit OVIE of
TMG is currently set to 1, then bit IRRTG is set to 1 in IRR2. If bit IENTG is also set to 1 in
IENR2, then timer G requests a CPU interrupt. For further details see 3.3, Interrupts.
2. Count timing
TCG is incremented by input pulses from an internal clock. TMG bits CKS1 and CKS0 select
one of four internal clocks (ø/64, ø/32, ø/2, ø /2) derived by dividing the system clock (ø) or the
W
watch clock (ø ).
W
232
3. Timing of internal input capture signals
Timing with noise canceller function disabled
•
Separate internal input capture signals are generated from the rising and falling edges of the
external input signal.
Figure 9-6-4 shows the timing of these signals.
External input
capture signal
Internal input
capture signal F
Internal input
capture signal R
Figure 9-6-4 Input Capture Signal Timing (Noise Canceller Function Disabled)
•
Timing with noise canceller function enabled
When input capture noise cancelling is enabled, the external input capture signal is routed via the
noise canceller circuit, so the internal signals are delayed from the input edge by five sampling
clock cycles. Figure 9-6-5 shows the timing.
External input
capture signal
Sampling clock
Noise canceller
circuit output
Internal input
capture signal R
Figure 9-6-5 Input Capture Signal Timing (Noise Canceller Function Enabled)
233
4. Timing of input capture
Figure 9-6-6 shows the input capture timing in relation to the internal input capture signal.
Internal input
capture signal
TCG
N –1
N
N +1
Input capture
register
H'XX
N
Figure 9-6-6 Input Capture Timing
5. TCG clear timing
TCG can be cleared at the rising edge, falling edge, or both edges of the external input capture
signal. Figure 9-6-7 shows the timing for clearing at both edges.
External input
capture signal
Internal input
capture signal F
Internal input
capture signal R
TCG
N
H'00
N
H'00
Figure 9-6-7 TCG Clear Timing
234
6. Timer G operation states
Table 9-6-3 summarizes the timer G operation states.
Table 9-6-3 Timer G Operation States
Sub-
Sub-
Operation Mode Reset Active
Sleep
Watch
active
sleep
Standby
TCG
Input
capture
Reset Functions* Functions* Halted
Functions/ Functions/ Halted
Halted* Halted*
Interval Reset Functions* Functions* Retained Functions/ Functions/ Halted
Halted* Halted*
ICRGF
ICRGR
TMG
Reset Functions* Functions* Retained Functions/ Functions/ Retained
Halted* Halted*
Reset Functions* Functions* Retained Functions/ Functions/ Retained
Halted* Halted*
Reset Functions Retained
Retained Functions Retained
Retained
Note: * In active mode and sleep mode, if ø /2 is selected as the TCG internal clock, since the
W
system clock and internal clock are not synchronized with each other, a synchronization
circuit is used. This may result in a count cycle error of up to 1/ø (s). In subactive mode
and subsleep mode, if ø /2 is selected as the TCG internal clock, regardless of the
W
subclock ø/SUB (ø /2, ø /4, ø /8) TCG and the noise canceller circuit run on an internal
W
W
W
clock of ø /2. If any other internal clock is chosen, TCG and the noise canceller circuit
W
will not run, and the input capture function will not operate.
9.6.5 Application Notes
1. Input clock switching and TCG operation
Depending on when the input clock is switched, there will be cases in which TCG is incremented
in the process. Table 9-6-4 shows the relation between internal clock switchover timing (selected
in bits CKS1 and CKS0) and TCG operation. If an internal clock (derived from the system clock
ø or subclock ø
) is used, an increment pulse is generated when a falling edge of the internal
SUB
clock is detected. For this reason, in a case like No. 3 in table 9-6-4, where the clock is switched
at a time such that the clock signal goes from high level before switching to low level after
switching, the switchover is seen as a falling edge of the clock pulse, causing TCG to be
incremented.
235
Table 9-6-4 Internal Clock Switching and TCG Operation
Clock Level Before
and After Modifying
No. Bits CKS1 and CKS0
TCG Operation
1
2
3
Goes from low level to
low level
Clock before
switching
Clock after
switching
Count clock
TCG
N +1
N
CKS bits modified
Goes from low level to
high level
Clock before
switching
Clock after
switching
Count clock
N
N +1
N +2
TCG
CKS bits modified
Goes from high level to
low level
Clock before
switching
Clock after
switching
*
Count clock
TCG
N
N +1
N +2
CKS bits modified
4
Goes from high level to
high level
Clock before
switching
Clock after
switching
Count clock
TCG
N
N +1
N +2
CKS bits modified
Note: * The switchover is seen as a falling edge of the clock pulse, and TCG is incremented.
236
2. Note on rewriting port mode registers
When a port mode register setting is modified to enable or disable the input capture function or
input capture noise canceling function, note the following points.
•
Switching the function of the input capture pin
When the function of the input capture pin is switched by modifying the TMIG bit in port mode
register 1 (PMR1) an input capture edge may be recognized even though no valid signal edge has
been input. This occurs under the conditions listed in table 9-6-5.
Table 9-6-5 False Input Capture Edges Generating by Switching of Input Capture Pin Function
Input Capture Edge Conditions
Rising edge
recognized
TMIG pin level is high, and TMIG bit is changed from 0 to 1
TMIG pin level is high and NCS bit is changed from 0 to 1, then TMIG bit is
changed from 0 to 1 before noise canceller circuit completes five samples
Falling edge
recognized
TMIG pin level is high, and TMIG bit is changed from 1 to 0
TMIG pin level is low and NCS bit is changed from 0 to 1, then TMIG bit is
changed from 0 to 1 before noise canceller circuit completes five samples
TMIG pin level is high and NCS bit is changed from 0 to 1, then TMIG bit is
changed from 1 to 0 before noise canceller circuit completes five samples
Note: When pin P13 is not used for input capture, the input capture signal input to timer G is low.
•
Switching the input capture noise canceling function
When modifying the NCS bit in port mode register 2 (PMR2) to enable or disable the input
capture noise canceling function, first clear the TMIG bit to 0. Otherwise an input capture edge
may be recognized even though no valid signal edge has been input. This occurs under the
conditions listed in table 9-6-6.
Table 9-6-6 False Input Capture Edges Generating by Switching of Noise Canceling Function
Input Capture Edge Conditions
Rising edge
recognized
TMIG bit is set to 1 and TMIG pin level changes from low to high, then NCS
bit is changed from 1 to 0 before noise canceller circuit completes five
samples
Falling edge
recognized
TMIG bit is set to 1 and TMIG pin level changes from high to low, then NCS
bit is changed from 1 to 0 before noise canceller circuit completes five
samples
237
If switching of the pin function generates a false input capture edge matching the edge selected by
the input capture interrupt edge select bit (IIEGS), the interrupt request flag will be set to 1,
making it necessary to clear this flag to 0 before using the interrupt function. Figure 9-6-8 shows
the procedure for modifying port mode register settings and clearing the interrupt request flag. The
first step is to mask interrupts before modifying the port mode register. After modifying the port
mode register setting, wait long enough for an input capture edge to be recognized (at least two
system clocks when noise canceling is disabled; at least five sampling clocks when noise
canceling is enabled), then clear the interrupt request flag to 0 (assuming it has been set to 1). An
alternative procedure is to avoid having the interrupt request flag set when the pin function is
switched, either by controlling the level of the input capture pin so that it does not satisfy the
conditions in tables 9-6-5 and 9-6-6, or by setting the IIEGS bit of TMG to select the edge
opposite to the falsely generated edge.
Disable interrupts (or disable by clearing interrupt
Set I bit to 1 in CCR
enable bit in interrupt enable register 2)
Modify port mode register
Modify port mode register setting, wait for input
capture edge to be recognized (at least two
system clocks when noise canceling is disabled;
at least five sampling clocks when noise canceling
Wait for TMIG to be recognized
is enabled), then clear interrupt request flag to 0
Clear interrupt request flag to 0
Clear I bit to 0 in CCR
Enable interrupts
Figure 9-6-8 Procedure for Modifying Port Mode Register and Clearing Interrupt
Request Flag
238
9.6.6 Sample Timer G Application
The absolute values of the high and low widths of the input capture signal can be measured by
using timer G. The CCLR1 and CCLR0 bits of TMG should be set to 1. Figure 9-6-9 shows an
example of this operation.
Input capture
signal
H'FF
Input capture
register GF
Input capture
register GR
H'00
TCG
Counter cleared
Figure 9-6-9 Sample Timer G Application
239
Section 10 Serial Communication Interface
10.1 Overview
The H8/3834U Series is provided with a three-channel serial communication interface (SCI).
Table 10-1-1 summarizes the functions and features of the three SCI channels.
Table 10-1-1 Serial Communication Interface Functions
Channel
Functions
Features
• Choice of 8 internal clocks (ø/1024 to ø/2) or
external clock
SCI1
Synchronous serial transfer
• Choice of 8-bit or 16-bit data length
• Continuous clock output
• Open drain output possible
• Interrupt requested at completion of transfer
• Choice of 7 internal clocks (ø/256 to ø/2) or
external clock
SCI2
SCI3
Synchronous serial transfer
• Automatic transfer of up to 32 bytes
of data (send, receive, or simultaneous
send/receive)
• Open drain output possible
• Interrupt requested at completion of
transfer or error
• Chip select input
• Strobe pulse output
Synchronous serial transfer
• 8-bit data transfer
• Built-in baud rate generator
• Receive error detection
• Break detection
• Send, receive, or simultaneous
send/receive
• Interrupt requested at completion of transfer
or error
Asynchronous serial transfer
• Multiprocessor communication function
• Choice of 7-bit or 8-bit data length
• Choice of 1-bit or 2-bit stop bit length
• Odd or even parity
241
10.2 SCI1
10.2.1 Overview
Serial communication interface 1 (SCI1) performs synchronous serial transfer of 8-bit or 16-bit
data.
1. Features
•
•
Choice of 8-bit or 16-bit data length
Choice of eight internal clock sources (ø/1024, ø/256, ø/64, ø/32, ø/16, ø/8, ø/4, ø/2) or an
external clock
•
Interrupt requested at completion of transfer
242
2. Block diagram
Figure 10-2-1 shows a block diagram of SCI1.
PSS
ø
SCR1
SCK1
Transmit/receive
control circuit
SCSR1
Transfer bit counter
SDRU
SI1
SDRL
SO1
IRRS1
Notation:
SCR1: Serial control register 1
SCSR1: Serial control/status register 1
SDRU: Serial data register U
SDRL: Serial data register L
IRRS1: SCI1 interrupt request flag
PSS:
Prescaler S
Figure 10-2-1 SCI1 Block Diagram
243
3. Pin configuration
Table 10-2-1 shows the SCI1 pin configuration.
Table 10-2-1 Pin Configuration
Name
Abbrev.
SCK1
SI1
I/O
Function
SCI1 clock pin
SCI1 data input pin
SCI1 data output pin
I/O
SCI1 clock input or output
SCI1 receive data input
SCI1 transmit data output
Input
Output
SO1
4. Register configuration
Table 10-2-2 shows the SCI1 register configuration.
Table 10-2-2 SCI1 Registers
Name
Abbrev.
SCR1
R/W
R/W
R/W
R/W
R/W
Initial Value
H'00
Address
H'FFA0
H'FFA1
H'FFA2
H'FFA3
Serial control register 1
Serial control status register 1
Serial data register U
Serial data register L
SCSR1
SDRU
SDRL
H'80
Not fixed
Not fixed
10.2.2 Register Descriptions
1. Serial control register 1 (SCR1)
Bit
7
SNC1
0
6
SNC0
0
5
—
4
—
3
2
1
0
CKS0
0
CKS3
0
CKS2
0
CKS1
0
Initial value
Read/Write
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCR1 is an 8-bit read/write register for selecting the operation mode, the transfer clock source,
and the prescaler division ratio.
Upon reset, SCR1 is initialized to H'00. Writing to this register during a transfer stops the
transfer.
244
Bits 7 and 6: Operation mode select 1, 0 (SNC1, SNC0)
Bits 7 and 6 select the operation mode.
Bit 7
Bit 6
SNC1
SNC0
Description
0
0
1
1
0
1
0
1
8-bit synchronous transfer mode
16-bit synchronous transfer mode
Continuous clock output mode*1
Reserved*2
(initial value)
Notes: 1. Pins SI1 and SO1 should be used as general input or output ports.
2. Don’t set bits SNC1 and SNC0 to 11.
Bits 5 and 4: Reserved bits
Bits 5 and 4 are reserved, but they can be written and read.
Bit 3: Clock source select (CKS3)
Bit 3 selects the clock source and sets pin SCK as an input or output pin.
1
Bit 3
CKS3
Description
0
1
Clock source is prescaler S, and pin SCK1 is output pin
Clock source is external clock, and pin SCK1 is input pin
(initial value)
245
Bits 2 to 0: Clock select (CKS2 to CKS 0)
When CKS3 = 0, bits 2 to 0 select the prescaler division ratio and the serial clock cycle.
Serial Clock Cycle
Bit 2
Bit 1
Bit 0
CKS2
CKS1
CKS0
Prescaler Division
ø = 5 MHz
204.8 µs
51.2 µs
12.8 µs
6.4 µs
3.2 µs
1.6 µs
0.8 µs
—
ø = 2.5 MHz
409.6 µs
102.4 µs
25.6 µs
12.8 µs
6.4 µs
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ø/1024 (initial value)
ø/256
ø/64
ø/32
ø/16
ø/8
3.2 µs
ø/4
1.6 µs
ø/2
0.8 µs
2. Serial control/status register 1 (SCSR1)
Bit
7
—
1
6
5
4
—
0
3
—
0
2
—
0
1
0
SOL
0
ORER
0
—
0
STF
0
Initial value
Read/Write
—
R/W
R/(W)*
—
—
—
R/W
R/W
Note: * Only a write of 0 for flag clearing is possible.
SCSR1 is an 8-bit read/write register indicating operation status and error status.
Upon reset, SCSR1 is initialized to H'80.
Bit 7: Reserved bit
Bit 7 is reserved; it is always read as 1, and cannot be modified.
246
Bit 6: Extended data bit (SOL)
Bit 6 sets the SO output level. When read, SOL returns the output level at the SO pin. After
1
1
completion of a transmission, SO continues to output the value of the last bit of transmitted data.
1
The SO output can be changed by writing to SOL before or after a transmission. The SOL bit
1
setting remains valid only until the start of the next transmission. To control the level of the SO
1
pin after transmission ends, it is necessary to write to the SOL bit at the end of each transmission.
Do not write to this register while transmission is in progress, because that may cause a
malfunction.
Bit 6
SOL
Description
0
Read
Write
Read
Write
SO1 pin output level is low
(initial value)
SO1 pin output level changes to low
SO1 pin output level is high
1
SO1 pin output level changes to high
Bit 5: Overrun error flag (ORER)
When an external clock is used, bit 5 indicates the occurrence of an overrun error. If a clock pulse
is input after transfer completion, this bit is set to 1 indicating an overrun. If noise occurs during a
transfer, causing an extraneous pulse to be superimposed on the normal serial clock, incorrect data
may be transferred.
Bit 5
ORER
Description
0
Clearing conditions:
(initial value)
After reading ORER = 1, cleared by writing 0 to ORER
1
Setting conditions:
Set if a clock pulse is input after transfer is complete, when an external clock is used
Bits 4 to 2: Reserved bits
Bits 4 to 2 are reserved; they are always read as 0, and cannot be modified.
Bit 1: Reserved bit
Bit 1 is reserved; it should always be cleared to 0.
247
Bit 0: Start flag (STF)
Bit 0 controls the start of a transfer. Setting this bit to 1 causes SCI1 to start transferring data.
During the transfer or while waiting for the first clock pulse, this bit remains set to 1. It is cleared
to 0 upon completion of the transfer. It can therefore be used as a busy flag.
Bit 0
STF
Description
0
Read: Indicates that transfer is stopped
Write: Invalid
(initial value)
1
Read: Indicates transfer in progress
Write: Starts a transfer operation
3. Serial data register U (SDRU)
Bit
7
6
5
4
3
2
1
0
SDRU7 SDRU6 SDRU5 SDRU4 SDRU3 SDRU2 SDRU1 SDRU0
Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SDRU is an 8-bit read/write register. It is used as the data register for the upper 8 bits in 16-bit
transfer (SDRL is used for the lower 8 bits).
Data written to SDRU is output to SDRL starting from the least significant bit (LSB). This data is
then replaced by LSB-first data input at pin SI1, which is shifted in the direction from the most
significant bit (MSB) toward the LSB.
SDRU must be written or read only after data transmission or reception is complete. If this
register is written or read while a data transfer is in progress, the data contents are not guaranteed.
The SDRU value upon reset is not fixed.
248
4. Serial data register L (SDRL)
Bit
7
6
5
4
3
2
1
0
SDRL7 SDRL6 SDRL5 SDRL4 SDRL3 SDRL2 SDRL1 SDRL0
Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SDRL is an 8-bit read/write register. It is used as the data register in 8-bit transfer, and as the data
register for the lower 8 bits in 16-bit transfer (SDRU is used for the upper 8 bits).
In 8-bit transfer, data written to SDRL is output from pin SO starting from the least significant
1
bit (LSB). This data is than replaced by LSB-first data input at pin SI , which is shifted in the
1
direction from the most significant bit (MSB) toward the LSB.
In 16-bit transfer, operation is the same as for 8-bit transfer, except that input data is fed in via
SDRU.
SDRL must be written or read only after data transmission or reception is complete. If this
register is read or written while a data transfer is in progress, the data contents are not guaranteed.
The SDRL value upon reset is not fixed.
10.2.3 Operation
Data can be sent and received in an 8-bit or 16-bit format, synchronized to an internal or external
serial clock. Overrun errors can be detected when an external clock is used.
1. Clock
The serial clock can be selected from a choice of eight internal clocks and an external clock.
When an internal clock source is selected, pin SCK becomes the clock output pin. When
1
continuous clock output mode is selected (SCR1 bits SNC1 and SNC0 are set to 10), the clock
signal (ø/1024 to ø/2) selected in bits CKS2 to CKS0 is output continuously from pin SCK .
1
When an external clock is used, pin SCK is the clock input pin.
1
2. Data transfer format
Figure 10-2-2 shows the data transfer format. Data is sent and received starting from the least
significant bit, in LSB-first format. Transmit data is output from one falling edge of the serial
clock until the next falling edge. Receive data is latched at the rising edge of the serial clock.
249
SCK1
SO1/SI1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Figure 10-2-2 Transfer Format
3. Data transfer operations
Transmitting
A transmit operation is carried out as follows.
— Set bit SO in port mode register 3 (PMR3) to 1, making pin P3 /SO the SO output pin.
•
1
2
1
1
Also set bit SCK1 in PMR3 to 1, making pin P3 /SCK the SCK I/O pin. If necessary, set
0
1
1
bit POF1 in port mode register 2 (PMR2) for NMOS open drain output at pin SO .
1
— Clear bit SNC1 in SCR1 to 0, and set bit SNC0 to 1 or 0, designating 8- or 16-bit
synchronous transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing data to
SCR1 initializes the internal state of SCI1.
— Write transmit data in SDRL and SDRU, as follows.
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL
— Set the SCSR1 start flag (STF) to 1. SCI1 starts operating and outputs transmit data at pin
SO .
1
— After data transmission is complete, bit IRRS1 in interrupt request register 1 (IRR1) is
set to 1.
When an internal clock is used, a serial clock is output from pin SCK in synchronization with the
1
transmit data. After data transmission is complete, the serial clock is not output until the next time
the start flag is set to 1. During this time, pin SO continues to output the value of the last bit
1
transmitted.
250
When an external clock is used, data is transmitted in synchronization with the serial clock input
at pin SCK . After data transmission is complete, an overrun occurs if the serial clock continues
1
to be input; no data is transmitted and the SCSR1 overrun error flag (bit ORER) is set to 1.
While transmission is stopped, the output value of pin SO can be changed by rewriting bit SOL
1
in SCSR1.
•
Receiving
A receive operation is carried out as follows.
— Set bit SI1 in port mode register 3 (PMR3) to 1, making pin P3 /SI the SI input pin. Also
1
1
1
set bit SCK1 in PMR3 to 1, making pin P3 /SCK the SCK I/O pin.
0
1
1
— Clear bit SNC1 in SCR1 to 0, and set bit SNC0 to 1 or 0, designating 8- or 16-bit
synchronous transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing data to
SCR1 initializes the internal state of SCI1.
— Set the SCSR1 start flag (STF) to 1. SCI1 starts operating and receives data at pin SI .
1
— After data reception is complete, bit IRRS1 in interrupt request register 1 (IRR1) is set to 1.
— Read the received data from SDRL and SDRU, as follows.
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL
— After data reception is complete, an overrun occurs if the serial clock continues to be input;
no data is received and the SCSR1 overrun error flag (bit ORER) is set to 1.
251
•
Simultaneous transmit/receive
A simultaneous transmit/receive operation is carried out as follows.
— Set bits SO , SI , and SCK1 in PMR3 to 1, making pin P3 /SO the SO output pin, pin
1
1
2
1
1
P3 /SI the SI input pin, and pin P3 /SCK the SCK I/O pin. If necessary, set bit POF1 in
1
1
1
0
1
1
port mode register 2 (PMR2) for NMOS open drain output at pin SO .
1
— Clear bit SNC1 in SCR1 to 0, and set bit SNC0 to 1 or 0, designating 8- or 16-bit
synchronous transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing data to
SCR1 initializes the internal state of SCI1.
— Write transmit data in SDRL and SDRU, as follows.
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL
— Set the SCSR1 start flag (STF) to 1. SCI1 starts operating. Transmit data is output at pin
SO . Receive data is input at pin SI .
1
1
— After data transmission and reception are complete, bit IRRS1 in IRR1 is set to 1.
— Read the received data from SDRL and SDRU, as follows.
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL
When an internal clock is used, a serial clock is output from pin SCK in synchronization with the
1
transmit data. After data transmission is complete, the serial clock is not output until the next time
the start flag is set to 1. During this time, pin SO continues to output the value of the last bit
1
transmitted.
When an external clock is used, data is transmitted and received in synchronization with the serial
clock input at pin SCK . After data transmission and reception are complete, an overrun occurs if
1
the serial clock continues to be input; no data is transmitted or received and the SCSR1 overrun
error flag (bit ORER) is set to 1.
While transmission is stopped, the output value of pin SO can be changed by rewriting bit SOL
1
in SCSR1.
252
10.2.4 Interrupts
SCI1 can generate an interrupt at the end of a data transfer.
When an SCI1 transfer is complete, bit IRRS1 in interrupt request register 1 (IRR1) is set to 1.
SCI1 interrupt requests can be enabled or disabled by bit IENS1 of interrupt enable register 1
(IENR1).
For further details, see 3.3, Interrupts.
10.2.5 Application Notes
When an external clock is input at pin SCK , bit STF in SCSR1 must first be set to 1 to start data
1
transfer before inputting the external clock.
253
10.3 SCI2
10.3.1 Overview
Serial communication interface 2 (SCI2) has a 32-bit data buffer for synchronous serial transfer of
up to 32 bytes of data in one operation.
1. Features
Features of SCI are listed below.
•
•
Automatic transfer of up to 32 bytes of data
Choice of seven internal clock sources (ø/256, ø/64, ø/32, ø/16, ø/8, ø/4, ø/2) or an external
clock
•
•
Interrupts requested at completion of transfer or when an error occurs
Gaps of 56, 24, or 8 internal clock cycles can be inserted between successive bytes of
transferred data.
•
•
Transfer can be started by chip select input.
A strobe pulse can be output for each byte transferred.
254
2. Block diagram
Figure 10-3-1 shows a block diagram of SCI2.
PSS
SCK2
STAR
EDAR
SCR2
STRB
Transmit/receive
control circuit
CS
SCSR2
SO2
Serial data buffer
SI2
IRRS2
Notation:
STAR: Start address register
EDAR: End address register
IRRS2: SCI2 interrupt request flag (IRR2)
PSS:
Prescaler S
Figure 10-3-1 SCI2 Block Diagram
255
3. Pin configuration
Table 10-3-1 shows the SCI2 pin configuration.
Table 10-3-1 Pin Configuration
Name
Abbrev.
SCK2
SI2
I/O
Function
SCI2 clock pin
I/O
SCI2 clock input/output
SCI2 receive data input
SCI2 transmit data output
SCI2 strobe signal output
SCI2 chip select input
SCI2 data input pin
SCI2 data output pin
SCI2 strobe pin
SCI2 chip select pin
Input
Output
Output
Input
SO2
STRB
CS
4. Register configuration
Table 10-3-2 shows the SCI2 register configuration.
Table 10-3-2 SCI2 Registers
Name
Abbrev.
STAR
EDAR
SCR2
SCSR2
—
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
H'E0
Address
Start address register
End address register
Serial control register 2
Serial control/status register 2
Serial data buffer (32 bytes)
H'FFA4
H'E0
H'FFA5
H'E0
H'FFA6
H'E0
H'FFA7
Not fixed
H'FF80 to H'FF9F
10.3.2 Register Descriptions
1. Start address register (STAR)
Bit
7
—
1
6
—
1
5
—
1
4
STA4
0
3
2
STA2
0
1
STA1
0
0
STA0
0
STA3
0
Initial value
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
STAR is an 8-bit read/write register, for designating a transfer start address in the address space
(H'FF80 to H'FF9F) allocated to the 32-byte data buffer. The lower 5 bits of STAR correspond to
the lower 5 bits of the address. The extent of continuous data transfer is defined in STAR and in
the end address register (EDAR). If the same value is designated by STAR and EDAR, only 1
byte of data is transferred.
Bits 7 to 5 are reserved; they are always read as 1, and cannot be modified.
Upon reset, STAR is initialized to H'E0.
256
2. End address register (EDAR)
Bit
7
—
1
6
—
1
5
—
1
4
EDA4
0
3
EDA3
0
2
EDA2
0
1
EDA1
0
0
EDA0
0
Initial value
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
EDAR is an 8-bit read/write register, for designating a transfer end address in the address space
(H'FF80 to H'FF9F) allocated to the 32-byte data buffer. The lower 5 bits of EDAR correspond to
the lower 5 bits of the address. The extent of continuous data transfer is defined in STAR and in
EDAR. If the same value is designated by STAR and EDAR, only 1 byte of data is transferred.
Bits 7 to 5 are reserved; they are always read as 1, and cannot be modified.
Upon reset, EDAR is initialized to H'E0.
3. Serial control register 2 (SCR2)
Bit
7
—
1
6
—
1
5
—
1
4
GAP1
0
3
GAP0
0
2
CKS2
0
1
CKS1
0
0
CKS0
0
Initial value
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
SCR2 is an 8-bit read/write register for selecting the serial clock, and for setting the gap inserted
between data during continuous transfer when SCI2 uses an internal clock.
Upon reset, SCR2 is initialized to H'E0.
Bits 7 to 5: Reserved bits
Bits 7 to 5 are reserved; they are always read as 1, and cannot be modified.
257
Bits 4 and 3: Gap select (GAP1 to GAP0)
When SCI2 uses an internal clock, gaps can be inserted between successive data bytes. Bits 4 and
3 designate the length of these gaps. During a gap, pin SCK remains at the high level. When no
2
gap is inserted, the STRB signal stays at the low level.
Bit 4
Bit 3
GAP1
GAP0
Description
0
0
1
1
0
1
0
1
No gaps between bytes
(initial value)
A gap of 8 clock cycles is inserted between bytes
A gap of 24 clock cycles is inserted between bytes
A gap of 56 clock cycles is inserted between bytes
Bits 2 to 0: Clock select (CKS2 to CKS0)
Bits 2 to 0 select one of seven internal clock sources or an external clock.
Serial Clock Cycle
Prescaler Division ø = 5 MHz ø= 2.5 MHz
Bit 2 Bit 1 Bit 0
CKS2 CKS1 CKS0
Clock
Source
Pin SCK2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SCK2 output Prescaler S
ø/256 (initial value) 51.2 µs
102.4 µs
25.6 µs
12.8 µs
6.4 µs
3.2 µs
1.6 µs
0.8 µs
—
ø/64
ø/32
ø/16
ø/8
12.8 µs
6.4 µs
3.2 µs
1.6 µs
0.8 µs
—
ø/4
ø/2
SCK2 input External clock
—
—
258
4. Serial control/status register 2 (SCSR2)
Bit
7
—
1
6
—
1
5
—
1
4
3
ORER
0
2
WT
0
1
ABT
0
0
SOL
0
STF
0
Initial value
Read/Write
—
—
—
R/W
R/(W)* R/(W)* R/(W)*
R/W
Note: * Only a write of 0 for flag clearing is possible.
SCSR2 is an 8-bit register indicating SCI2 operation status and error status.
Upon reset, SCSR2 is initialized to H'E0.
Bits 7 to 5: Reserved bits
Bits 7 to 5 are reserved; they are always read as 1, and cannot be modified.
Bit 4: Extended data bit (SOL)
Bit 4 sets the SO output level. When read, SOL returns the transmitted data output at the SO
2
2
pin. After completion of a transmission, SO continues to output the value of the last bit of
2
transmitted data. The SO output can be changed by writing to SOL before or after a
2
transmission. The SOL bit setting remains valid only until the start of the next transmission. To
control the level of the SO pin after transmission ends, it is necessary to write to the SOL bit at
2
the end of each transmission. Note that if the STF bit is cleared to 0 to terminate a transmission in
progress, the transmitted data will be modified when the bit is cleared.
Bit 4
SOL
Description
0
Read
Write
Read
Write
SO2 pin output level is low
(initial value)
SO2 pin output level changes to low
SO2 pin output level is high
1
SO2 pin output level changes to high
259
Bit 3: Overrun error flag (ORER)
When an external clock is used, bit 3 indicates the occurrence of an overrun error. If a clock pulse
is input after transfer completion, this bit is set to 1 indicating an overrun. If noise occurs during a
transfer, causing an extraneous pulse to be superimposed on the normal serial clock, incorrect data
may be transferred. Overrun errors are not detected while pin CS is at the high level.
Bit 3
ORER
Description
0
Clearing conditions:
(initial value)
After reading ORER = 1, cleared by writing 0 to ORER
1
Setting conditions:
Set if a clock pulse is input after transfer is complete, when an external clock is used
Bit 2: Wait flag (WT)
Bit 2 indicates that an attempt was made to read or write the 32-byte serial data buffer while a
transfer was in progress, or while waiting for CS input. The read or write access is not carried out,
and this bit is set to 1.
Bit 2
WT
Description
0
Clearing conditions:
(initial value)
After reading WT = 1, cleared by writing 0 to WT
1
Setting conditions:
An attempt was made to read or write the (32-byte) serial data buffer during a
transfer operation or while waiting for CS input
260
Bit 1: Abort flag (ABT)
Bit 1 indicates that CS went to high during data transfer. When the CS input function is selected,
if a high-level signal is detected at pin CS during a transfer, the transfer is immediately aborted
and this bit is set to 1. At the same time bit IRRS2 in interrupt request register 2 (IRR2) is set
to 1, and pins SCK and SO go to the high-impedance state. Data in the (32-byte) serial data
2
2
buffer and values in the internal registers other than SCSR2 remain unchanged.
Transfer cannot take place while this bit is set to 1. It must be cleared to 0 before resuming the
transfer.
Bit 1
ABT
Description
0
Clearing conditions:
(initial value)
After reading ABT = 1, cleared by writing 0 to ABT
1
Setting conditions:
When pin CS goes high during a transfer
Bit 0: Start/busy flag (STF)
Bit 0 controls the start of a transfer. If bit CS = 0 in PMR2, setting bit STF to 1 causes SCI2 to
start transferring data. If bit CS = 1 in PMR2, then after STF is set to 1, SCI2 starts transferring
data when CS goes low. This bit stays at 1 during the transfer or while waiting for CS input; it is
cleared to 0 after the transfer is completed or when the transfer is aborted by CS. It can therefore
be used as a busy flag.
Clearing this bit to 0 during a transfer aborts the transfer. The contents of the (32-byte) serial data
buffer and of internal registers other than SCSR2 remain unchanged.
Bit 0
STF
Explanation
0
Read: Indicates that transfer is stopped
Write: Stops a transfer operation
Read: Indicates transfer in progress or waiting for CS input
Write: Starts a transfer operation
(initial value)
1
261
10.3.3 Operation
SCI2 has a 32-byte serial data buffer, making possible continuous transfer of up to 32 bytes of data
with one operation. SCI2 transmits and receives data in synchronization with clock pulses.
Depending on register settings, it can transmit, receive, or transmit and receive simultaneously.
When it transmits but does not receive, the serial data buffer values are retained after the
transmission is completed.
Either an internal clock or external clock may be selected as the serial clock. When an internal
clock is selected, gaps may be inserted between the data bytes. It is also possible to output a
strobe signal at pin STRB. When an external clock is selected, the overrun flag allows detection
of erroneous operation due to unwanted clock input.
Transfers can be started or aborted by input at pin CS. Abort is indicated by means of an abort
flag.
1. Clock
The serial clock can be selected from a choice of six internal clock sources or an external clock.
When an internal clock source is selected, pin SCK becomes the clock output pin.
2
2. Data transfer format
Figure 10-3-2 and figure 10-3-3 show the SCI2 data transfer format. Data is sent and received
starting from the least significant bit, in LSB-first format. Transmit data is output from one falling
edge of the serial clock until the next falling edge. Receive data is latched at the rising edge of the
serial clock.
When SCI2 operates on an internal clock, a gap can be inserted between each byte of transferred
data and the next, as shown in figure 10-3-3. During this gap, pin SCK outputs a high-level
2
signal. Also, a strobe pulse can be output at pin STRB.
The length of the gap is designated in bits GAP1 and GAP0 in serial control register 2 (SCR2).
262
Figure 10-3-2 Data Transfer Format (No Gaps between Data)
263
Figure 10-3-3 Data Transfer Format (Gap Inserted between Data)
264
3. Data transfer operations
SCI2 initialization
•
Data transfer on SCI2 first of all requires that SCI2 be initialized by software as follows.
— With bit STF cleared to 0 in SCSR2, select pin functions and the transfer mode in registers
PMR2, PMR3, STAR, EDAR, and SCR2.
— The SCI2 pins double as general input/output ports. Switching between port and SCI2
functions is controlled in PMR3. CMOS output or NMOS open drain output can be selected
in PMR2. The serial clock and gaps between transferred bytes are set in SCR2.
— The start and end addresses of the transfer data area are set in STAR and EDAR. If the end
address is set smaller than the start address, as shown in figure 10-3-4, the transfer wraps
around from H'FF9F to H'FF80 and continues to the end address. If the start address and end
address are the same, only one byte of data will be transferred.
H'FF80
End
End address
Start
Start address
H'FF9F
Figure 10-3-4 Operation When End Address is Smaller than Start Address
265
•
Transmitting
A transmit operation is carried out as follows.
— Set bit SO2 in port mode register 3 (PMR3) to 1, making pin P3 /SO the SO output pin.
5
2
2
Also set bit SCK2 in PMR3 to 1, making pin P3 /SCK the SCK I/O pin. If necessary, set
3
2
2
bit POF2 in port mode register 2 (PMR2) for NMOS open-drain output at pin SO , and set
2
bits CS and STRB in PMR3 to designate use of the CS and STRB pin functions.
— Select the serial clock and, in the case of internal clock operation, the data gap in SCR2.
— Write transmit data in the serial data buffer. This data will remain in the data buffer after
completion of the transfer. It is not necessary to rewrite the buffer when the same data is
retransmitted.
— Set the start address in the lower 5 bits of STAR, and the end address in the lower 5 bits of
EDAR.
— Set the start/busy flag (STF) to 1. If bit CS = 0 in PMR3, transmission starts as soon as STF
is set to 1. If CS = 1 in PMR3, transmission starts when CS goes low.
— After data transmission is complete, bit IRRS2 in interrupt request register 2 (IRR2) is
set to 1, and bit STF is cleared to 0.
When an internal clock is used, a serial clock is output from pin SCK in synchronization with the
2
transmit data. After data transmission is completed, the serial clock is not output until bit STF is
set again. During this time, pin SO continues to output the value of the last bit transmitted.
2
266
When an external clock is used, data is transmitted in synchronization with the serial clock input
at pin SCK . After data transmission is completed, an overrun occurs if the serial clock continues
2
to be input; no data is transmitted and the SCSR2 overrun error flag (bit ORER) is set to 1. Pin
SO continues to output the value of the last preceding bit. Overrun errors are not detected when
2
both pin CS is at the high level and PMR3 bit CS = 1.
While transmission is stopped, the output value of pin SO can be changed by rewriting bit SOL
2
in SCSR2.
During a transmission or while waiting for CS input, the CPU cannot read or write the data buffer.
If a read instruction is executed, H'FF will be read; if a write instruction is executed, the buffer
contents will not change. In either case the wait flag (bit WT) in SCSR2 will be set to 1.
If bit CS = 1 in PMR3 and during transmission a high-level signal is detected at pin CS, the
transmit operation will immediately be aborted, setting the abort flag (bit ABT) to 1. At the same
time bit IRRS2 in interrupt request register 2 (IRR2) will be set to 1, and bit STF will be cleared
to 0. Pins SCK and SO will go to the high-impedance state. Data transfer is not possible while
2
2
bit ABT is set to 1. It must be cleared before resuming the transfer.
Receiving
A receive operation is carried out as follows.
— Set bits SI and SCK in port mode register 3 (PMR3) to 1, designating use of the SI and
•
2
2
2
SCK pin functions. If necessary, set bit CS in PMR3 to select the CS pin function.
2
— Select the serial clock and, in the case of internal clock operation, the data gap in SCR2.
— Allocate an area to hold the received data in the serial data buffer by designating the receive
start address in the lower 5 bits of the start address register (STAR) and the receive end
address in the lower 5 bits of the end address register (EDAR).
— Set the start/busy flag (bit STF) to 1. If bit CS = 0 in PMR3, receiving starts as soon as STF
is set. If CS = 1 in PMR3, receiving starts when CS goes low.
— After receiving is completed, bit IRRS2 in interrupt request register 2 (IRR2) is set to 1, and
bit STF is cleared to 0.
— Read the received data from the serial data buffer.
267
If an internal clock is used, a serial clock is output from pin SCK when the receive operation
2
starts. After receiving is completed, the serial clock is not output until bit STF is set again. When
an external clock source is used, data is received in synchronization with the clock input at pin
SCK . After receiving is completed, an overrun occurs if the serial clock continues to be input; no
2
further data is received and the SCSR2 overrun error flag (bit ORER) is set to 1. Overrun errors
are not detected when both pin CS is high and bit CS = 1 in PMR3.
While receiving or while waiting for CS input, the CPU cannot read or write the data buffer. If a
read instruction is executed, H'FF will be read; if a write instruction is executed the buffer contents
will not change. In either case the wait flag (bit WT) in SCSR2 will be set to 1.
If bit CS = 1 in PMR3 and a high-level signal is detected at pin CS during receiving, the receive
operation will immediately be aborted, setting the abort flag (bit ABT) to 1. At the same time bit
IRRS2 in interrupt request register 2 (IRR2) will be set to 1, and bit STF will be cleared to 0. Pins
SCK and SO will go to the high-impedance state. Data transfer is not possible while bit ABT is
2
2
set to 1. It must be cleared before resuming the transfer.
Simultaneous transmit/receive
A simultaneous transmit/receive operation is carried out as follows.
— Set bits SO , SI , and SCK in PMR3 to 1, designating use of the SO , SI , and SCK pin
•
2
2
2
2
2
2
functions. If necessary, set bit POF2 in port mode register 2 (PMR2) for NMOS open-drain
output at pin SO , and set bits CS and STRB to designate use of the CS and STRB pin
2
functions.
— Select the transfer clock and, in the case of internal clock operation, the data gap in SCR2.
— Write transmit data in the serial data buffer. In simultaneous transmit/receive, received data
replaces transmitted data at the same buffer addresses.
— Set the transfer start address in the lower 5 bits of STAR, and the transfer end address in the
lower 5 bits of EDAR.
— Set the start/busy flag (bit STF) to 1. If bit CS = 0 in PMR3, the transmit/receive transfer
starts as soon as STF is set to 1. If CS = 1 in PMR3, transfer operations start when CS goes
low.
268
— After data transfer is completed, bit IRRS2 in interrupt request register 2 (IRR2) is set to 1,
and bit STF is cleared to 0.
— Read the received data from the serial data buffer.
If an internal clock is used, a serial clock is output from pin SCK when the transfer begins. After
2
the transfer is completed, the serial clock is not output until bit STF is set again. During this time,
pin SO continues to output the value of the last bit transmitted.
2
When an external clock is used, data is transferred in synchronization with the serial clock input at
pin SCK . After the transfer is completed, an overrun occurs if the serial clock continues to be
2
input; no transfer operation takes place and the SCSR2 overrun error flag (bit ORER) is set to 1.
Pin SO continues to output the value of the last transmitted bit. Overrun errors are not detected
2
when both pin CS is high and bit CS = 1 in PMR3.
While data transfer is stopped, the output value of pin SO can be changed by rewriting bit SOL in
2
SCSR2.
During a transfer or while waiting for CS input, the CPU cannot read or write the data buffer. If a
read instruction is executed, H'FF will be read; if a write instruction is executed the buffer contents
will not change. In either case the wait flag (bit WT) in SCSR2 will be set to 1.
If bit CS = 1 in PMR3 and during the transfer a high-level signal is detected at pin CS, the transfer
will immediately be aborted, setting the abort flag (bit ABT) to 1. At the same time bit IRRS2 in
interrupt request register 2 (IRR2) will be set to 1, and bit STF will be cleared to 0. Pins SCK
2
and SO will go to the high-impedance state. Data transfer is not possible while bit ABT is set to
2
1. It must be cleared before resuming the transfer.
10.3.4 Interrupts
SCI2 can generate interrupts when a transfer is completed or when a transfer is aborted by CS.
These interrupts have the same vector address.
When the above conditions occur, bit IRRS2 in interrupt request register 2 (IRR2) is set to 1.
SCI2 interrupt requests can be enabled or disabled in bit IENS2 of interrupt enable register 2
(IENR2). For further details, see 3.3, Interrupts.
When a transfer is aborted by CS, an overrun error occurs, or a read or write of the serial data
buffer is attempted during a transfer or while waiting for CS input, the ABT, ORER, or WT bit in
SCSR2 is set to 1. These bits can be used to determine the cause of the error.
10.3.5 Application Notes
When an external clock is input at pin SCK , bit STF in SCSR2 must first be set to 1 to start data
2
transfer before inputting the external clock.
269
10.4 SCI3
10.4.1 Overview
Serial communication interface 3 (SCI3) has both synchronous and asynchronous serial data
communication capabilities. It also has a multiprocessor communication function for serial data
communication among two or more processors.
1. Features
SCI3 features are listed below.
•
Selection of asynchronous or synchronous mode
a. Asynchronous mode
SCI3 can communicate with a UART (universal asynchronous receiver/transmitter), ACIA
(asynchronous communication interface adapter), or other chip that employs standard
asynchronous serial communication. It can also communicate with two or more other
processors using the multiprocessor communication function. There are twelve selectable
serial data communication formats.
— Data length: seven or eight bits
— Stop bit length: one or two bits
— Parity: even, odd, or none
— Multiprocessor bit: one or none
— Receive error detection: parity, overrun, and framing errors
— Break detection: by reading the RXD level directly when a framing error occurs
b. Synchronous mode
Serial data communication is synchronized with a clock signal. SCI3 can communicate with
other chips having a clocked synchronous communication function.
— Data length: eight bits
— Receive error detection: overrun errors
•
Full duplex communication
The transmitting and receiving sections are independent, so SCI3 can transmit and receive
simultaneously. Both sections use double buffering, so continuous data transfer is possible in
both the transmit and receive directions.
270
•
•
•
Built-in baud rate generator with selectable bit rates.
Internal or external clock may be selected as the transfer clock source.
There are six interrupt sources: transmit end, transmit data empty, receive data full, overrun
error, framing error, and parity error.
2. Block diagram
Figure 10-4-1 shows a block diagram of SCI3.
External
clock
Internal clock
(ø/64, ø/16, ø/4, ø)
SCK3
Baud rate
generator
BRC
BRR
Clock
SMR
SCR3
SSR
Transmit/receive
control
TXD
RXD
TSR
RSR
TDR
RDR
Interrupt
requests
(TEI, TXI,
RXI, ERI)
Notation: RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
SCR3: Serial control register 3
SSR: Serial status register
BRR: Bit rate register
BRC: Bit rate counter
Figure 10-4-1 SCI3 Block Diagram
271
3. Pin configuration
Table 10-4-1 shows the SCI3 pin configuration.
Table 10-4-1 Pin Configuration
Name
Abbrev.
SCK3
RXD
I/O
Function
SCI3 clock
I/O
SCI3 clock input/output
SCI3 receive data input
SCI3 transmit data output
SCI3 receive data input
SCI3 transmit data output
Input
Output
TXD
4. Register configuration
Table 10-4-2 shows the SCI3 internal register configuration.
Table 10-4-2 SCI3 Registers
Name
Abbrev.
SMR
BRR
SCR3
TDR
R/W
R/W
R/W
R/W
R/W
R/W
R
Initial Value
H'00
H'FF
H'00
H'FF
H'84
H'00
—
Address
H'FFA8
H'FFA9
H'FFAA
H'FFAB
H'FFAC
H'FFAD
—
Serial mode register
Bit rate register
Serial control register 3
Transmit data register
Serial status register
Receive data register
Transmit shift register
Receive shift register
Bit rate counter
SSR
RDR
TSR
—
RSR
BRC
—
—
—
—
—
—
272
10.4.2 Register Descriptions
1. Receive shift register (RSR)
Bit
7
6
5
4
3
2
1
0
Read/Write
—
—
—
—
—
—
—
—
The receive shift register (RSR) is for receiving serial data.
Serial data is input in LSB-first order into RSR from pin RXD, converting it to parallel data.
After each byte of data has been received, the byte is automatically transferred to the receive data
register (RDR).
RSR cannot be read or written directly by the CPU.
2. Receive data register (RDR)
Bit
7
RDR7
0
6
RDR6
0
5
RDR5
0
4
RDR4
0
3
RDR3
0
2
RDR2
0
1
RDR1
0
0
RDR0
0
Initial value
Read/Write
R
R
R
R
R
R
R
R
The receive data register (RDR) is an 8-bit register for storing received serial data.
Each time a byte of data is received, the received data is transferred from the receive shift register
(RSR) to RDR, completing a receive operation. Thereafter RSR again becomes ready to receive
new data. RSR and RDR form a double buffer mechanism that allows data to be received
continuously.
RDR is exclusively for receiving data and cannot be written by the CPU.
RDR is initialized to H'00 upon reset or in standby mode, watch mode, subactive mode, or
subsleep mode.
273
3. Transmit shift register (TSR)
Bit
7
6
5
4
3
2
1
0
Read/Write
—
—
—
—
—
—
—
—
The transmit shift register (TSR) is for transmitting serial data.
Transmit data is first transferred from the transmit data register (TDR) to TSR, then is transmitted
from pin TXD, starting from the LSB (bit 0).
After one byte of data has been sent, the next byte is automatically transferred from TDR to TSR,
and the next transmission begins. If no data has been written to TDR (1 is set in TDRE), there is
no data transfer from TDR to TSR.
TSR cannot be read or written directly by the CPU.
4. Transmit data register (TDR)
Bit
7
TDR7
1
6
TDR6
1
5
TDR5
1
4
TDR4
1
3
TDR3
1
2
TDR2
1
1
TDR1
1
0
TDR0
1
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The transmit data register (TDR) is an 8-bit register for holding transmit data.
When SCI3 detects that the transmit shift register (TSR) is empty, it shifts transmit data written in
TDR to TSR and starts serial data transmission. While TSR is transmitting serial data, the next
byte to be transmitted can be written to TDR, realizing continuous transmission.
TDR can be read or written by the CPU at all times.
TDR is initialized to H'FF upon reset or in standby mode, watch mode, subactive mode, or
subsleep mode.
274
5. Serial mode register (SMR)
Bit
7
COM
0
6
5
PE
0
4
PM
0
3
STOP
0
2
MP
0
1
CKS1
0
0
CKS0
0
CHR
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The serial mode register (SMR) is an 8-bit register for setting the serial data communication
format and for selecting the clock source of the baud rate generator. SMR can be read and written
by the CPU at any time.
SMR is initialized to H'00 upon reset or in standby mode, watch mode, subactive mode, or
subsleep mode.
Bit 7: Communication mode (COM)
Bit 7 selects asynchronous mode or synchronous mode as the serial data communication mode.
Bit 7
COM
Description
0
1
Asynchronous mode
Synchronous mode
(initial value)
Bit 6: Character length (CHR)
Bit 6 selects either 7 bits or 8 bits as the data length in asynchronous mode. In synchronous mode
the data length is always 8 bits regardless of the setting here.
Bit 6
CHR
Description
8-bit data
0
1
(initial value)
7-bit data*
Note: * When 7-bit data is selected as the character length in asynchronous mode, the MSB (bit 7)
in the transmit data register is not transmitted.
275
Bit 5: Parity enable (PE)
In asynchronous mode, bit 5 selects whether or not a parity bit is to be added to transmitted data
and checked in received data. In synchronous mode there is no adding or checking of parity
regardless of the setting here.
Bit 5
PE
Description
0
Parity bit adding and checking disabled
Parity bit adding and checking enabled*
(initial value)
1
Note: * When PE is set to 1, then either odd or even parity is added to transmit data, depending on
the setting of the parity mode bit (PM). When data is received, it is checked for odd or
even parity as designated in bit PM.
Bit 4: Parity mode (PM)
In asynchronous mode, bit 4 selects whether odd or even parity is to be added to transmitted data
and checked in received data. The setting here is valid only if parity adding/checking is enabled in
bit PE. In synchronous mode, or if parity adding/checking is disabled in bit PE, bit PM is ignored.
Bit 4
PM
Description
Even parity*1
Odd parity*2
0
(initial value)
1
Notes: 1. When even parity is designated, a parity bit is added to the transmitted data so that the
sum of 1s in the resulting data is an even number. When data is received, the sum of 1s
in the data plus parity bit is checked to see if the result is an even number.
2. When odd parity is designated, a parity bit is added to the transmitted data so that the
sum of 1s in the resulting data is an odd number. When data is received, the sum of 1s
in the data plus parity bit is checked to see if the result is an odd number.
276
Bit 3: Stop bit length (STOP)
Bit 3 selects 1 bit or 2 bits as the stop bit length in asynchronous mode. This setting is valid only
in asynchronous mode. In synchronous mode a stop bit is not added, so this bit is ignored.
Bit 3
STOP
Description
1 stop bit*1
2 stop bits*2
0
1
(initial value)
Notes: 1. When data is transmitted, one 1 bit is added at the end of each transmitted character as
the stop bit.
2. When data is transmitted, two 1 bits are added at the end of each transmitted character
as the stop bits.
When data is received, only the first stop bit is checked regardless of the stop bit length. If the
second stop bit value is 1 it is treated as a stop bit; if it is 0, it is treated as the start bit of the next
character.
Bit 2: Multiprocessor mode (MP)
Bit 2 enables or disables the multiprocessor communication function. When the multiprocessor
communication function is enabled, the parity enable (PE) and parity mode (PM) settings are
ignored. The MP bit is valid only in asynchronous mode; it should be cleared to 0 in synchronous
mode.
See 10.4.6, for details on the multiprocessor communication function.
Bit 2
MP
Description
0
Multiprocessor communication function disabled
Multiprocessor communication function enabled
(initial value)
1
277
Bits 1 and 0: Clock select 1, 0 (CKS1, CKS0)
Bits 1 and 0 select the clock source for the built-in baud rate generator. A choice of ø/64, ø/16,
ø/4, or ø is made in these bits.
See 8, Bit rate register, below for information on the clock source and bit rate register settings, and
their relation to the baud rate.
Bit 1
Bit 0
CKS1
CKS0
Description
ø clock
0
0
1
1
0
1
0
1
(initial value)
ø/4 clock
ø/16 clock
ø/64 clock
6. Serial control register 3 (SCR3)
Bit
7
TIE
0
6
RIE
0
5
TE
0
4
RE
0
3
MPIE
0
2
TEIE
0
1
CKE1
0
0
CKE0
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Serial control register 3 (SCR3) is an 8-bit register that controls SCI3 transmit and receive
operations, enables or disables serial clock output in asynchronous mode, enables or disables
interrupts, and selects the serial clock source. SCR3 can be read and written by the CPU at any
time.
SCR3 is initialized to H'00 upon reset or in standby mode, watch mode, subactive mode, or
subsleep mode.
278
Bit 7: Transmit interrupt enable (TIE)
Bit 7 enables or disables the transmit data empty interrupt (TXI) request when data is transferred
from TDR to TSR and the transmit data register empty bit (TDRE) in the serial status register
(SSR) is set to 1. The TXI interrupt can be cleared by clearing bit TDRE to 0, or by clearing bit
TIE to 0.
Bit 7
TIE
Description
0
Transmit data empty interrupt request (TXI) disabled
Transmit data empty interrupt request (TXI) enabled
(initial value)
1
Bit 6: Receive interrupt enable (RIE)
Bit 6 enables or disables the receive error interrupt (ERI), and the receive data full interrupt (RXI)
requested when data is transferred from RSR to RDR and the receive data register full bit (RDRF)
in the serial status register (SSR) is set to 1. RXI and ERI interrupts can be cleared by clearing
SSR flag RDRF, or flags FER, PER, and OER to 0, or by clearing bit RIE to 0.
Bit 6
RIE
Description
0
Receive data full interrupt request (RXI) and receive error interrupt
request (ERI) disabled
(initial value)
1
Receive data full interrupt request (RXI) and receive error interrupt request (ERI)
enabled
Bit 5: Transmit enable (TE)
Bit 5 enables or disables the start of a transmit operation.
Bit 5
TE
Description
0
Transmit operation disabled*1 (TXD is a general I/O port)
Transmit operation enabled*2 (TXD is the transmit data pin)
(initial value)
1
Notes: 1. The transmit data register empty bit (TDRE) in the serial status register (SSR) is fixed
at 1.
2. In this state, writing transmit data in TDR clears bit TDRE in SSR to 0 and starts serial
data transmission.
Before setting TE to 1 it is necessary to set the transmit format in SMR.
279
Bit 4: Receive enable (RE)
Bit 4 enables or disables the start of a receive operation.
Bit 4
RE
Description
0
Receive operation disabled*1 (RXD is a general I/O port)
Receive operation enabled*2 (RXD is the receive data pin)
(initial value)
1
Notes: 1. When RE is cleared to 0, this has no effect on the SSR flags RDRF, FER, PER, and
OER, which retain their states.
2. Serial data receiving begins when, in this state, a start bit is detected in asynchronous
mode, or serial clock input is detected in synchronous mode.
Before setting RE to 1 it is necessary to set the receive format in SMR.
Bit 3: Multiprocessor interrupt enable (MPIE)
Bit 3 enables or disables multiprocessor interrupt requests. This setting is valid only in
asynchronous mode, and only when the multiprocessor mode bit (MP) in the serial mode register
(SMR) is set to 1. It applies only to data receiving. This bit is ignored when COM is set to 1 or
when bit MP is cleared to 0.
Bit 3
MPIE
Description
0
Multiprocessor interrupt request disabled (ordinary receive operation)
(initial value)
Clearing condition:
Multiprocessor bit receives a data value of 1
1
Multiprocessor interrupt request enabled*
Note: * SCI3 does not transfer receive data from RSR to RDR, does not detect receive errors, and
does not set status flags RDRF, FER, and OER in SSR. Until a multiprocessor bit value of
1 is received, the receive data full interrupt (RXI) and receive error interrupt (ERI) are
disabled and serial status register (SSR) flags RDRF, FER, and OER are not set. When
the multiprocessor bit receives a 1, the MPBR bit of SSR is set to 1, MPIE is automatically
cleared to 0, RXI and ERI interrupts are enabled (provided bits TIE and RIE in SCR3 are
set to 1), and setting of the RDRF, FER, and OER flags is enabled.
280
Bit 2: Transmit end interrupt enable (TEIE)
Bit 2 enables or disables the transmit end interrupt (TEI) requested if there is no valid transmit
data in TDR when the MSB is transmitted.
Bit 2
TEIE
Description
0
1
Transmit end interrupt (TEI) disabled
Transmit end interrupt (TEI) enabled*
(initial value)
Note: * A TEI interrupt can be cleared by clearing the SSR bit TDRE to 0 and clearing the transmit
end bit (TEND) to 0, or by clearing bit TEIE to 0.
Bits 1 and 0: Clock enable 1, 0 (CKE1, CKE0)
Bits 1 and 0 select the clock source and enable or disable clock output at pin SCK . The
3
combination of bits CKE1 and CKE0 determines whether pin SCK is a general I/O port, a clock
3
output pin, or a clock input pin.
Note that the CKE0 setting is valid only when operation is in asynchronous mode using an internal
clock. This bit is invalid in synchronous mode or when using an external clock
(CKE1 = 1). In synchronous mode and in external clock mode, clear CKE0 to 0. After setting
bits CKE1 and CKE0, the operation mode must first be set in the serial mode register (SMR).
See table 10-4-9 in 10.4.3, Operation, for details on clock source selection.
Bit 1
Bit 0
CKE1
CKE0
Communication Mode Clock Source
SCK3 Pin Function
I/O port*1
0
0
1
1
0
1
0
1
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
Internal clock
Internal clock
Internal clock
Reserved
Serial clock output*1
Clock output*2
Reserved
External clock
External clock
Reserved
Clock input*3
Serial clock input
Reserved
Reserved
Reserved
Notes: 1. Initial value
2. A clock is output with the same frequency as the bit rate.
3. Input a clock with a frequency 16 times the bit rate.
281
7. Serial status register (SSR)
Bit
7
TDRE
1
6
RDRF
0
5
OER
0
4
FER
0
3
PER
0
2
TEND
1
1
MPBR
0
0
MPBT
0
Initial value
Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
R
R
R/W
Note: *Only 0 can be written for flag clearing.
The serial status register (SSR) is an 8-bit register containing status flags for indicating SCI3
states, and containing the multiprocessor bits.
SSR can be read and written by the CPU at any time, but the CPU cannot write a 1 to the status
flags TDRE, RDRF, OER, PER, and FER. To clear these flags to 0 it is first necessary to read a 1.
Bit 2 (TEND) and bit 1 (MPBR) are read-only bits and cannot be modified.
SSR is initialized to H'84 upon reset or in standby mode, watch mode, subactive mode, or
subsleep mode.
Bit 7: Transmit data register empty (TDRE)
Bit 7 is a status flag indicating that data has been transferred from TDR to TSR.
Bit 7
TDRE
Description
0
Indicates that transmit data written to TDR has not been transferred to TSR
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE.
When data is written to TDR by an instruction.
1
Indicates that no transmit data has been written to TDR,
(initial value)
or the transmit data written to TDR has been transferred to TSR
Setting conditions:
When bit TE in SCR3 is cleared to 0.
When data is transferred from TDR to TSR.
282
Bit 6: Receive data register full (RDRF)
Bit 6 is a status flag indicating whether there is receive data in RDR.
Bit 6
RDRF
Description
0
Indicates there is no receive data in RDR
(initial value)
Clearing conditions:
After reading RDRF = 1, cleared by writing 0 to RDRF.
When data is read from RDR by an instruction.
1
Indicates that there is receive data in RDR
Setting condition:
When receiving ends normally, with receive data transferred from RSR to RDR
Note: If a receive error is detected at the end of receiving, or if bit RE in serial control register 3
(SCR3) is cleared to 0, RDR and RDRF are unaffected and keep their previous states. An
overrun error (OER) occurs if receiving of data is completed while bit RDRF remains set
to 1. If this happens, receive data will be lost.
Bit 5: Overrun error (OER)
Bit 5 is a status flag indicating that an overrun error has occurred during data receiving.
Bit 5
OER
Description
0
Indicates that data receiving is in progress or has been completed*1
(initial value)
Clearing condition:
After reading OER = 1, cleared by writing 0 to OER
1
Indicates that an overrun error occurred in data receiving*2
Setting condition:
When data receiving is completed while RDRF is set to 1
Notes: 1. When bit RE in serial control register 3 (SCR3) is cleared to 0, OER is unaffected and
keeps its previous state.
2. RDR keeps the data received prior to the overrun; data received after that is lost. While
OER is set to 1, data receiving cannot be continued. In synchronous mode, data
transmitting cannot be continued either.
283
Bit 4: Framing error (FER)
Bit 4 is a status flag indicating that a framing error has occurred during asynchronous receiving.
Bit 4
FER
Description
0
Indicates that data receiving is in progress or has been completed*1
(initial value)
Clearing condition:
After reading FER = 1, cleared by writing 0 to FER
1
Indicates that a framing error occurred in data receiving
Setting condition:
The stop bit at the end of receive data is checked and found to be 0*2
Notes: 1. When bit RE in serial control register 3 (SCR3) is cleared to 0, FER is unaffected and
keeps its previous state.
2. When two stop bits are used only the first stop bit is checked, not the second. When a
framing error occurs, receive data is transferred to RDR but RDRF is not set. While
FER is set to 1, data receiving cannot be continued. In synchronous mode, data
transmitting cannot be continued either.
Bit 3: Parity error (PER)
Bit 3 is a status flag indicating that a parity error has occurred during asynchronous receiving.
Bit 3
PER
Description
0
Indicates that data receiving is in progress or has been completed*1
(initial value)
Clearing condition:
After reading PER = 1, cleared by writing 0 to PER
1
Indicates that a parity error occurred in data receiving*2
Setting condition:
When the sum of 1s in received data plus the parity bit does not match the parity
mode bit (PM) setting in the serial mode register (SMR)
Notes: 1. When bit RE in serial control register 3 (SCR3) is cleared to 0, PER is unaffected and
keeps its previous state.
2. When a parity error occurs, receive data is transferred to RDR but RDRF is not set.
While PER is set to 1, data receiving cannot be continued. In synchronous mode, data
transmitting cannot be continued either.
284
Bit 2: Transmit end (TEND)
Bit 2 is a status flag indicating that TDRE was set to 1 when the last bit of a transmitted character
was sent. TEND is a read-only bit and cannot be modified directly.
Bit 2
TEND
Description
0
Indicates that transmission is in progress
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE.
When data is written to TDR by an instruction.
1
Indicates that a transmission has ended
(initial value)
Setting conditions:
When bit TE in SCR3 is cleared to 0.
If TDRE is set to 1 when the last bit of a transmitted character is sent.
Bit 1: Multiprocessor bit receive (MPBR)
Bit 1 holds the multiprocessor bit in data received in asynchronous mode using a multiprocessor
format. MPBR is a read-only bit and cannot be modified.
Bit 1
MPBR
Description
0
1
Indicates reception of data in which the multiprocessor bit is 0*
Indicates reception of data in which the multiprocessor bit is 1
(initial value)
Note: *If bit RE is cleared to 0 while a multiprocessor format is in use, MPBR retains its previous
state.
285
Bit 0: Multiprocessor bit transmit (MPBT)
Bit 0 holds the multiprocessor bit to be added to transmitted data when a multiprocessor format is
used in asynchronous mode. Bit MPBT is ignored when synchronous mode is chosen, when the
multiprocessor communication function is disabled, or when data transmission is disabled.
Bit 0
MPBT
Description
0
1
The multiprocessor bit in transmit data is 0
The multiprocessor bit in transmit data is 1
(initial value)
8. Bit rate register (BRR)
Bit
7
BRR7
1
6
BRR6
1
5
BRR5
1
4
BRR4
1
3
BRR3
1
2
BRR2
1
1
BRR1
1
0
BRR0
1
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The bit rate register (BRR) is an 8-bit register which, together with the baud rate generator clock
selected by bits CKS1 and CKS0 in the serial mode register (SMR), sets the transmit/receive bit
rate.
BRR can be read or written by the CPU at any time.
BRR is initialized to H'FF upon reset or in standby mode, watch mode, subactive mode, or
subsleep mode.
Table 10-4-3 gives examples of how BRR is set in asynchronous mode. The values in
table 10-4-3 are for active (high-speed) mode.
286
Table 10-4-3 BRR Settings and Bit Rates in Asynchronous Mode (1)
OSC (MHz)
2
2.4576
Error
4
4.194304
Error
(%)
Bit Rate
(bits/s)
Error
(%)
Error
(%)
n
N
n
1
0
0
0
0
0
0
0
0
—
0
N
(%)
n
1
N
n
1
N
110
1
70
+0.03
86
255
127
63
31
15
7
+0.31
141 +0.03
103 +0.16
207 +0.16
103 +0.16
148 –0.04
108 +0.21
217 +0.21
108 +0.21
150
0
207 +0.16
103 +0.16
0
0
0
0
0
0
0
0
—
0
1
1
300
0
0
0
600
0
51
25
12
—
—
—
0
+0.16
+0.16
+0.16
—
0
0
1200
2400
4800
9600
19200
31250
38400
0
0
51
25
12
—
—
1
+0.16
+0.16
+0.16
—
0
54
26
13
6
–0.70
+1.14
–2.48
–2.48
—
0
0
0
—
—
—
0
0
0
—
3
—
—
0
0
—
1
—
—
—
—
—
—
—
0
—
0
0
—
—
—
—
—
—
—
—
Table 10-4-3 BRR Settings and Bit Rates in Asynchronous Mode (2)
OSC (MHz)
4.9152
Error
(%)
174 –0.26
6
7.3728
Error
8
Bit Rate
(bits/s)
Error
(%)
Error
(%)
n
1
1
0
0
0
0
0
0
0
—
0
N
n
1
1
1
0
0
0
0
0
0
0
—
N
n
2
1
1
0
0
0
0
0
0
—
0
N
(%)
n
2
N
110
212 +0.03
155 +0.16
64
191
95
191
95
47
23
11
5
+0.70
70
+0.03
150
127
255
127
63
31
15
7
0
0
0
0
0
0
0
0
—
0
0
0
0
0
0
0
0
0
—
0
1
207 +0.16
103 +0.16
207 +0.16
103 +0.16
300
77
+0.16
1
600
155 +0.16
0
1200
2400
4800
9600
19200
31250
38400
77
38
19
9
+0.16
+0.16
–2.34
–2.34
–2.34
0
0
0
51
25
12
—
3
+0.16
+0.16
+0.16
—
0
0
3
4
—
0
—
2
—
2
0
1
—
—
—
—
—
287
Table 10-4-3 BRR Settings and Bit Rates in Asynchronous Mode (3)
OSC (MHz)
9.8304
Error
10
Bit Rate
(bits/s)
Error
(%)
n
2
1
1
0
0
0
0
0
0
0
0
N
(%)
n
2
2
1
1
0
0
0
0
0
0
0
N
110
86
255
127
255
127
63
31
15
7
+0.31
88
64
–0.25
+0.16
150
0
300
0
129 +0.16
64 +0.16
129 +0.16
600
0
1200
2400
4800
9600
19200
31250
38400
0
0
64
32
15
7
+0.16
–1.36
+1.73
+1.73
0
0
0
0
4
–1.70
0
4
3
3
+1.73
Notes: 1. Settings should be made so that error is
within 1%.
2. BRR setting values are derived by the
following equation.
OSC
6
N =
× 10 – 1
64 × 22n × B
B:
N:
Bit rate (bits/s)
BRR baud rate generator setting (0 ≤ N ≤ 255)
OSC: Value of øOSC (MHz)
n:
Baud rate generator input clock number (n = 0, 1, 2, 3)
3. The error values in table 10-4-3 were
derived by performing the following
calculation and rounding off to two
decimal places.
B – R
Error (%) =
× 100
R
B: Bit rate found from n, N, and OSC
R: Bit rate listed in left column of table 10-4-3
288
The meaning of n is shown in table 10-4-4.
Table 10-4-4 Relation between n and Clock
SMR Setting
n
0
1
2
3
Clock
ø
CKS1
CKS0
0
0
1
1
0
1
0
1
ø/4
ø/16
ø/64
Table 10-4-5 shows the maximum bit rate for selected frequencies in asynchronous mode.
Values in table 10-4-5 are for active (high-speed) mode.
Table 10-4-5 Maximum Bit Rate at Selected Frequencies (Asynchronous Mode)
Setting
OSC (MHz)
Maximum Bit Rate (bits/s)
n
0
0
0
0
0
0
0
0
0
0
N
0
0
0
0
0
0
0
0
0
0
2
31250
38400
62500
65536
76800
93750
115200
125000
153600
156250
2.4576
4
4.194304
4.9152
6
7.3728
8
9.8304
10
289
Table 10-4-6 shows typical BRR settings in synchronous mode. Values in table 10-4-6 are for
active (high-speed) mode.
Table 10-4-6 Typical BRR Settings and Bit Rates (Synchronous Mode)
OSC (MHz)
2
4
8
10
Bit Rate
(bits/s)
n
—
1
N
n
—
2
1
1
0
0
0
0
0
0
0
0
N
n
—
2
2
1
1
0
0
0
0
0
0
0
0
N
n
N
110
250
500
1K
—
—
—
—
—
—
—
1
—
249
124
249
99
49
24
9
124
249
124
199
99
49
19
9
249
124
249
99
199
99
39
19
9
—
1
—
0
—
2.5K
5K
0
124
249
124
49
24
—
0
0
10K
25K
50K
100K
250K
500K
1M
0
0
0
0
0
4
0
—
0
—
4
—
0
0*
1
3
4
0*
1
—
—
—
0*
—
2.5M
Notes: Blank: Cannot be set
—:
*:
Can be set, but error will result
Continuous transfer not possible at this setting
BRR setting values are derived by the following equation.
OSC
8 × 22n × B
N =
× 106 – 1
B:
N:
Bit rate (bits/s)
BRR baud rate generator setting (0 ≤ N ≤ 255)
OSC: Value of øOSC (MHz)
n: Baud rate generator input clock number (n = 0, 1, 2, 3)
290
The meaning of n is shown in table 10-4-7.
Table 10-4-7 Relation between n and Clock
SMR Setting
n
0
1
2
3
Clock
ø
CKS1
CKS0
0
0
1
1
0
1
0
1
ø/4
ø/16
ø/64
10.4.3 Operation
SCI3 supports serial data communication in both asynchronous mode, where each character
transferred is synchronized separately, and synchronous mode, where transfer is synchronized by
clock pulses.
The choice of asynchronous mode or synchronous mode, and the communication format, is made
in the serial mode register (SMR), as shown in table 10-4-8. The SCI3 clock source is determined
by bit COM in SMR and bits CKE1 and CKE0 in serial control register 3 (SCR3), as shown in
table 10-4-9.
1. Asynchronous mode
— Data length: choice of 7 bits or 8 bits
— Transmit/receive format options include addition of parity bit, multiprocessor bit, and one
or two stop bits (character length depends on this combination of options).
— Framing error (FER), parity error (PER), overrun error (OER), and line breaks can be
detected when data is received.
— Clock source: Choice of internal clocks or an external clock
When an internal clock is selected: Operates on baud rate generator clock. A clock can
be output with the same frequency as the bit rate.
When an external clock is selected: A clock input with a frequency 16 times the bit rate
is required (internal baud rate generator is not used).
291
2. Synchronous mode
— Transfer format: 8 bits
— Overrun error can be detected when data is received.
— Clock source: Choice of internal clocks or an external clock
When an internal clock is selected: Operates on baud rate generator clock, and outputs
a serial clock.
When an external clock is selected: The internal baud rate generator is not used.
Operation is synchronous with the input clock.
Table 10-4-8 SMR Settings and SCI3 Communication Format
SMR Setting
Communication Format
Bit7 Bit6 Bit2 Bit5 Bit3
Multipro-
Parity Stop Bit
COM CHR MP PE STOP Mode
Data Length cessor Bit Bit
Length
Asynchronous
mode
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*
8-bit data
7-bit data
No
No
Yes
No
Yes
No
1 bit
2 bits
1 bit
2 bits
1 bit
1
2 bits
1 bit
2 bits
1 bit
Asynchronous
mode
(multiprocessor
format)
0
1
*
1
0
*
*
*
*
*
8-bit data
7-bit data
8-bit data
Yes
No
2 bits
1 bit
2 bits
None
1
Synchronous
mode
Note: * Don’t care
292
Table 10-4-9 SMR and SCR3 Settings and Clock Source Selection
SMR
SCR3
Transmit/Receive Clock
Bit7 Bit1 Bit0
Clock
COM CKE1 CKE0 Mode
Source
Pin SCK3 Function
Asynchronous
mode
0
0
1
0
1
0
Internal
External
I/O port (SCK3 function not used)
Outputs clock with same frequency as bit rate
Clock should be input with frequency 16 times
the desired bit rate
Synchronous
mode
1
0
1
1
0
1
0
0
1
1
1
Internal
External
Outputs a serial clock
Inputs a serial clock
0
1
1
Reserved
(illegal settings)
3. Continuous transmit/receive operation using interrupts
Continuous transmit and receive operations are possible with SCI3, using the RXI or TXI
interrupts. Table 10-4-10 explains this use of these interrupts.
Table 10-4-10 Transmit/Receive Interrupts
Interrupt Flag
Interrupt Conditions
Remarks
RXI
RDRF RIE
When serial data is received
normally and receive data
is transferred from RSR to RDR,
RDRF is set to 1. If RIE is 1 at
this time, RXI is enabled and an
interrupt occurs.
The RXI interrupt handler routine
should read the receive data from
RDR and clear RDRF to 0.
Continuous receiving is possible
if these operations are completed
before the next data has been
completely received in RSR.
(See figure 10-4-2 (a).)
TXI
TDRE TIE
When TSR empty (previous trans- The TXI interrupt handler routine
mission complete) is detected and should write the next transmit data
the transmit data set in TDR is
transferred to TSR, TDRE is
set to 1. If TIE is 1 at this time,
TXI is enabled and an interrupt
occurs. (See figure 10-4-2 (b).)
to TDR and clear TDRE to 0.
Continuous transmission is
possible if these operations are
completed before the data
transferred to TSR has been
completely transmitted.
TEI
TEND TEIE When the last bit of the TSR
TEI indicates that, when the last
transmit character has been sent, bit of the TSR transmit character
if TDRE is 1, then 1 is set in TEND. was sent, the next transmit data
If TEIE is 1 at this time, TEI is
enabled and an interrupt occurs.
(See figure 10-4-2 (c).)
had not been written to TDR.
293
RDR
RDR
RSR (receiving)
RDRF = 0
RSR ↑ (received and transferred)
RXD
pin
RXD
pin
←
RDRF
1
(RXI requested if RIE = 1)
Figure 10-4-2 (a) RDRF Setting and RXI Interrupt
TDR (next transmit data)
TDR
TSR ↓ (transmission complete,
next data transferred)
TSR (transmitting)
TDRE = 0
TXD
pin
TXD
pin
←
TDRE
1
(TXI requested if TIE = 1)
Figure 10-4-2 (b) TDRE Setting and TXI Interrupt
TDR
TDR
TSR (transmitting)
TEND = 0
TSR (transmission end)
TXD
pin
TXD
pin
←
TEND
1
(TEI requested if TEIE = 1)
Figure 10-4-2 (c) TEND Setting and TEI Interrupt
294
10.4.4 Operation in Asynchronous Mode
In asynchronous communication mode, a start bit indicating the start of communication and a stop
bit (1 or 2 bits) indicating the end of communication are added to each character that is sent. In
this way synchronization is achieved for each character as a self-contained unit.
SCI3 consists of independent transmit and receive modules, giving it the capability of full duplex
communication. Both the transmit and receive modules have a double-buffer configuration,
allowing data to be read or written during communication operations so that data can be
transmitted and received continuously.
1. Transmit/receive formats
Figure 10-4-3 shows the general format for asynchronous serial communication.
The communication line in asynchronous communication mode normally stays at the high level,
in the “mark” state. SCI3 monitors the communication line, and begins serial data communication
when it detects a “space” (low-level signal), which is regarded as a start bit.
One character consists of a start bit (low level), transmit/receive data (in LSB-first order), a parity
bit (high or low level), and finally a stop bit (high level), in this order.
In asynchronous data receiving, synchronization is with the falling edge of the start bit. SCI3
samples data on the 8th pulse of a clock that has 16 times the frequency of the bit rate, so each bit
of data is latched at its center.
(LSB)
(MSB)
1
Start
bit
Parity
bit
Stop bit
Mark
state
Serial
data
Transmit or receive data
7 or 8 bits
1 bit
or
none
1 or 2
bits
1 bit
One unit of data (character or frame)
Figure 10-4-3 Data Format in Asynchronous Serial Communication Mode
295
Table 10-4-11 shows the 12 formats that can be selected in asynchronous mode. The format is
selected in the serial mode register (SMR).
Table 10-4-11 Serial Communication Formats in Asynchronous Mode
SMR Setting
Serial Communication Format and Frame Length
CHR PE MP STOP
1
2
3
4
5
6
7
8
9
10
11
12
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
*
*
*
*
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
S
8-bit data
8-bit data
8-bit data
8-bit data
7-bit data
7-bit data
7-bit data
7-bit data
8-bit data
8-bit data
7-bit data
7-bit data
STOP
S
S
S
S
S
S
S
S
S
S
S
STOP STOP
P
P
STOP
STOP STOP
STOP
STOP STOP
P
P
STOP
STOP STOP
MPB STOP
MPB STOP STOP
MPB STOP
1
MPB STOP STOP
Notation: S:
Start bit
STOP: Stop bit
P: Parity bit
MPB: Multiprocessor bit
Note: * Don’t care
296
2. Clock
The clock source is determined by bit COM in SMR and bits CKE1 and CKE0 in serial control
register 3 (SCR3). See table 10-4-9 for the settings. Either an internal clock source can be used to
run the built-in baud rate generator, or an external clock source can be input at pin SCK .
3
When an external clock source is input, it should have a frequency 16 times the desired bit rate.
When an internal clock source is used, SCK is used as the clock output pin. The clock output has
3
the same frequency as the serial bit rate, and is synchronized as in figure 10-4-4 so that the rising
edge of the clock occurs in the center of each bit of transmit/receive data.
Clock
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
Serial
data
1 character (1 frame)
Figure 10-4-4 Phase Relation of Output Clock and Communication Data in Asynchronous
Mode (8-Bit Data, Parity Bit Added, and 2 Stop Bits)
3. Data transmit/receive operations
•
SCI3 initialization
Before data is sent or received, bits TE and RE in serial control register 3 (SCR3) must be cleared
to 0, after which initialization can be performed using the procedure shown in figure 10-4-5.
Note:
When modifying the operation mode, transfer format or other settings, always be sure to clear bits
TE and RE first. When TE is cleared to 0, bit TDRE will be set to 1. Clearing RE does not clear
the status flags RDRF, PER, FER, or OER, or alter the contents of the receive data register (RDR).
When an external clock is used in asynchronous mode, do not stop the clock during operation,
including during initialization. When an external clock is used in synchronous mode, do not
supply the clock during initialization.
297
Figure 10-4-5 shows a typical flow chart for SCI3 initialization.
Start
Clear TE and RE to 0 in SCR3
1. Select the clock in serial control register 3
1
2
3
Set bits CKE1 and CKE0
(SCR3). If clock output is selected in asyn-
chronous mode, a clock signal will be output
as soon as CKE1 and CKE2 have been set.
During reception in synchronous mode, if
clock output is selected by bits CKE1 and
CKE0, a clock signal will be output as soon
as RE is set to 1.
Select communication format in SMR
Set BRR value
2. Set the transmit/receive format in the serial
mode register (SMR).
Wait
3. Set the bit rate register (BRR) to the value
giving the desired bit rate.
This step is not required when an external
clock source is used.
No
Has a 1-bit
interval elapsed?
4. Wait for at least a 1-bit interval, then set
bits RIE, TIE, TEIE, and MPIE, and set bit
TE or RE in SCR3 to 1. Setting TE or RE
enables SCI3 to use the TXD or RXD pin.
The initial states in asynchronous mode
are the mark transmit state and the idle
receive state (waiting for a start bit).
Yes
Set bits RIE, TIE, TEIE, and MPIE
in SCR3, and set TE or RE to 1
4
End
Figure 10-4-5 Typical Flow Chart when SCI3 Is Initialized
298
•
Transmitting
Figure 10-4-6 shows a typical flow chart for data transmission. After SCI3 initialization, follow
the procedure below.
Start
1
Read bit TDRE in SSR
1. Read the serial status register (SRR),
and after confirming that bit TDRE = 1,
write transmit data in the transmit data
register (TDR). When data is written to
TDR, TDRE is automatically cleared to 0.
No
TDRE = 1?
Yes
Write transmit data in TDR
Continue
data transmission?
Yes
2
2. To continue transmitting data, read bit TDRE
to make sure it is set to 1, then write the
next data to TDR. When data is written to
TDR, TDRE is automatically cleared to 0.
No
Read bit TEND in SSR
No
No
TEND = 1?
Yes
3
Break output?
Yes
3. To output a break signal when transmission
ends, first set the port values PCR = 1 and
PDR = 0, then clear bit TE in SCR3 to 0.
Set PDR = 0 and PCR = 1
Clear bit TE in SCR3 to 0
End
Figure 10-4-6 Typical Data Transmission Flow Chart (Asynchronous Mode)
299
SCI3 operates as follows during data transmission in asynchronous mode.
SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data
written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR).
Then TDRE is set to 1 and transmission starts. If bit TIE in SCR3 is set to 1, a TXI interrupt is
requested.
Serial data is transmitted from pin TXD using the communication format outlined in
table 10-4-11. Next, TDRE is checked as the stop bit is being transmitted.
If TDRE is 0, data is transferred from TDR to TSR, and after the stop bit is sent, transmission of
the next frame starts. If TDRE is 1, the TEND bit in SSR is set to 1, and after the stop bit is sent
the output remains at 1 (mark state). A TEI interrupt is requested in this state if bit TEIE in SCR3
is set to 1.
Figure 10-4-7 shows a typical operation in asynchronous transmission mode.
Start
bit
Transmit
data
Parity Stop Start
bit bit bit
Transmit
data
Parity Stop Mark
bit
bit
state
Serial
data
1
0
D0
D1
D7
1 frame
0/1
1
0
D0
D1
D7
1 frame
0/1
1
1
TDRE
TEND
SCI3
operation
TXI request TDRE cleared to 0
Write data in TDR
TXI request
TEI request
User
processing
Figure 10-4-7 Typical Transmit Operation in Asynchronous Mode
(8-Bit Data, Parity Bit Added, and 1 Stop Bit)
300
•
Receiving
Figure 10-4-8 shows a typical flow chart for receiving serial data. After SCI3 initialization,
follow the procedure below.
Start
1. Read bits OER, PER, and
FER in the serial status
register (SSR) to
Read bits OER, PER, and
1
2
FER in SSR
determine if a receive
error has occurred.
If a receive error has
occurred, receive error
processing is executed.
Yes
OER + PER +
FER = 1
No
2. Read the serial status register
(SSR), and after confirming
that bit RDRF = 1, read
Read bit RDRF in SSR
No
received data from the receive
data register (RDR).
When RDR data is read, RDRF
is automatically cleared to 0.
RDRF = 1?
Yes
Read received data in RDR
3. To continue receiving data,
read bit RDRF and finish
reading RDR before the stop
bit of the present frame is
received.
When data is read from RDR,
RDRF is automatically cleared
to 0.
4
Receive error processing
Yes
3
Continue receiving?
No
A
Clear bit RE in SCR3 to 0
End
4. When a receive error occurs,
read bits OER, PER, and FER
in SSR to determine which
error (s) occurred.
After the necessary error
processing, be sure to clear
the above bits all to 0.
Data receiving cannot be resumed
while any of bits OER, PER, or
FER is set to 1.
When a framing error occurs,
a break can be detected by
reading the RXD pin value.
Start receive
error processing
4
Overrun error
processing
Yes
OER = 1?
No
Yes
Yes
FER = 1?
No
Break?
No
Framing error
processing
Yes
PER = 1?
No
Clear bits OER, PER, and
FER in SSR to 0
Parity error
processing
End receive error
processing
A
Figure 10-4-8 Typical Serial Data Receiving Flow Chart in Asynchronous Mode
301
SCI3 operates as follows when receiving serial data in asynchronous mode.
SCI3 monitors the communication line, and when a start bit (0) is detected it performs internal
synchronization and starts receiving. The communication format for data receiving is as outlined
in table 10-4-11. Received data is set in RSR from LSB to MSB, then the parity bit and stop bit(s)
are received. After receiving the data, SCI3 performs the following checks:
•
•
•
Parity check: The number of 1s received is checked to see if it matches the odd or even parity
selected in bit PM of SMR.
Stop bit check: The stop bit is checked for a value of 1. If there are two stop bits, only the
first bit is checked.
Status check: The RDRF bit is checked for a value of 0 to make sure received data can be
transferred from RSR to RDR.
If no receive error is detected by the above checks, bit RDRF is set to 1 and the received data is
stored in RDR. At that time, if bit RIE in SCR3 is set to 1, an RXI interrupt is requested. If the
error check detects a receive error, the appropriate error flag (OER, PER, or FER) is set to 1.
RDRF retains the same value as before the data was received. If at this time bit RIE in SCR3 is
set to 1, an ERI interrupt is requested.
Table 10-4-12 gives the receive error detection conditions and the processing of received data in
each case.
Note: Data receiving cannot be continued while a receive error flag is set. Before continuing the
receive operation it is necessary to clear the OER, FER, PER, and RDRF flags to 0.
Table 10-4-12 Receive Error Conditions and Received Data Processing
Receive Error Abbrev. Detection Conditions
Received Data Processing
Overrun error
Framing error
Parity error
OER
FER
PER
Receiving of the next data ends while Received data is not
bit RDRF in SSR is still set to 1
Stop bit is 0
transferred from RSR to RDR
Received data is transferred
from RSR to RDR
Received data does not match the
parity (odd/even) set in SMR
Received data is not
transferred from RSR to RDR
302
Figure 10-4-9 shows a typical SCI3 data receive operation in asynchronous mode.
Start
bit
Receive
data
Parity Stop Start
bit bit bit
Receive
data
Parity Stop Mark
bit
bit
(idle state)
Serial
data
1
0
D0
D1
D7
0/1
1
0
D0
D1
1 frame
D7
0/1
0
1
1 frame
RDRF
FER
SCI3 operation
User processing
RXI request
RDRF cleared
to 0
Detects stop bit = 0
ERI request due
to framing error
Read RDR data
Framing error
handling
Figure 10-4-9 Typical Receive Operation in Asynchronous Mode
(8-Bit Data, Parity Bit Added, and 1 Stop Bit)
10.4.5 Operation in Synchronous Mode
In synchronous mode, data is sent or received in synchronization with clock pulses. This mode is
suited to high-speed serial communication.
SCI3 consists of independent transmit and receive modules, so full duplex communication is
possible, sharing the same clock between both modules. Both the transmit and receive modules
have a double-buffer configuration. This allows data to be written during a transmit operation so
that data can be transmitted continuously, and enables data to be read during a receive operation
so that data can be received continuously.
1. Transmit/receive format
Figure 10-4-10 shows the general communication data format for synchronous communication.
303
*
*
Serial clock
Serial data
LSB
Bit 0
MSB
Bit 7
Don't
care
Don't
care
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
8 bits
One unit of communication data (character or frame)
Note: *At high level except during continuous transmit/receive.
Figure 10-4-10 Data Format in Synchronous Communication Mode
In synchronous communication, data on the communication line is output from one falling edge of
the serial clock until the next falling edge. Data is guaranteed valid at the rising edge of the serial
clock.
One character of data starts from the LSB and ends with the MSB. The communication line
retains the MSB state after the MSB is output.
In synchronous receive mode, SCI3 latches receive data in synchronization with the rising edge of
the serial clock.
The transmit/receive format is fixed at 8-bit data. No parity bit or multiprocessor bit is added in
this mode.
2. Clock
Either an internal clock from the built-in baud rate generator is used, or an external clock is input
at pin SCK . The choice of clock sources is designated by bit COM in SMR and bits CKE1 and
3
CKE0 in serial control register 3 (SCR3). See table 10-4-9 for details on selecting the clock
source.
When operation is based on an internal clock, a serial clock is output at pin SCK . Eight clock
3
pulses are output per character of transmit/receive data. When no transmit or receive operation is
being performed, the pin is held at the high level.
304
3. Data transmit/receive operations
SCI3 initialization
•
Before transmitting or receiving data, follow the SCI3 initialization procedure explained under
10.4.4, SCI3 Initialization, and illustrated in figure 10-4-5.
•
Transmitting
Figure 10-4-11 shows a typical flow chart for data transmission. After SCI3 initialization, follow
the procedure below.
Start
1. Read the serial status register (SSR),
and after confirming that bit TDRE = 1,
write transmit data in the transmit
data register (TDR).
1
Read bit TDRE in SSR
No
Yes
No
When data is written to TDR, TDRE is
automatically cleared to 0 and data
transmission begins.
If clock output has been selected, after
data is written to TDR, the clock is
output and data transmission begins.
TDRE = 1?
Yes
Write transmit data in TDR
Continue data transmission?
No
2
2. To continue transmitting data, read
bit TDRE to make sure it is set to 1,
then write the next data to TDR.
When data is written to TDR, TDRE
is automatically cleared to 0.
Read bit TEND in SSR
TEND = 1?
Yes
Write 0 to bit TE in SCR3
End
Figure 10-4-11 Typical Data Transmission Flow Chart in Synchronous Mode
305
SCI3 operates as follows during data transmission in synchronous mode.
SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data
written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR).
Then TDRE is set to 1 and transmission starts. If bit TIE in SCR3 is set to 1, a TXI interrupt is
requested.
If clock output is selected, SCI3 outputs eight serial clock pulses. If an external clock is used,
data is output in synchronization with the clock input.
Serial data is transmitted from pin TXD in order from LSB (bit 0) to MSB (bit 7).
Then TDRE is checked as the MSB (bit 7) is being transmitted. If TDRE is 0, data is transferred
from TDR to TSR, and after the MSB (bit 7) is sent, transmission of the next frame starts. If
TDRE is 1, the TEND bit in SSR is set to 1, and after the MSB (bit 7) has been sent, the MSB
state is maintained. A TEI interrupt is requested in this state if bit TEIE in SCR3 is set to 1.
After data transmission ends, pin SCK is held at the high level.
3
Note: Data transmission cannot take place while any of the receive error flags (OER, FER, PER)
is set to 1. Be sure to confirm that these error flags are cleared to 0 before starting transmission.
Figure 10-4-12 shows a typical SCI3 transmit operation in synchronous mode.
Serial
clock
Serial data
Bit 0
Bit 1
1 frame
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
1 frame
TDRE
TEND
SCI3
operation
TXI
request
TDRE cleared to 0 TXI
request
TEI request
User
Write data in TDR
processing
Figure 10-4-12 Typical SCI3 Transmit Operation in Synchronous Mode
306
•
Receiving
Figure 10-4-13 shows a typical flow chart for receiving data. After SCI3 initialization, follow the
procedure below.
Start
1. Read bit OER in the serial status register (SSR)
to determine if an error has occurred. If an
overrun error has occurred, overrun error
processing is executed.
1
2
Read bit OER in SSR
Yes
OER = 1?
No
2. Read the serial status register (SSR), and after
confirming that bit RDRF = 1, read received
data from the receive data register (RDR).
When data is read from RDR, RDRF is
automatically cleared to 0.
Read bit RDRF in SSR
No
RDRF = 1?
Yes
Read received data in RDR
3. To continue receiving data, read bit RDRF and
read the received data in RDR before the MSB
(bit 7) of the present frame is received.
When data is read from RDR, RDRF is
automatically cleared to 0.
4 Overrun error processing
Yes
Continue
3
receiving?
No
4. When an overrun error occurs, read bit OER in
SSR. After the necessary error processing,
be sure to clear OER to 0.
Clear bit RE in SCR3 to 0
Data receiving cannot be resumed while bit
OER is set to 1.
End
Start overrun
processing
4
Overrun error
processing
Clear bit OER in
SSR to 0
End overrun
error processing
Figure 10-4-13 Typical Data Receiving Flow Chart in Synchronous Mode
307
SCI3 operates as follows when receiving serial data in synchronous mode.
SCI3 synchronizes internally with the input or output of the serial clock and starts receiving.
Received data is set in RSR from LSB to MSB.
After data has been received, SCI3 checks to confirm that the value of bit RDRF is 0 indicating
that received data can be transferred from RSR to RDR. If this check passes, RDRF is set to 1 and
the received data is stored in RDR. At this time, if bit RIE in SCR3 is set to 1, an RXI interrupt is
requested. If an overrun error is detected, OER is set to 1 and RDRF remains set to 1. Then if bit
RIE in SCR3 is set to 1, an ERI interrupt is requested.
For the overrun error detection conditions and receive data processing, see table 10-4-12.
Note: Data receiving cannot be continued while a receive error flag is set. Before continuing the
receive operation it is necessary to clear the OER, FER, PER, and RDRF flags to 0.
Figure 10-4-14 shows a typical receive operation in synchronous mode.
Serial
clock
Serial
data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
1 frame
1 frame
RDRF
OER
SCI3
operation
RXI request RDRF cleared
to 0
RXI request
ERI request due
to overrun error
User
processing
Read data
from RDR
RDR data
not read
Overrun error
handling
(RDRF = 1)
Figure 10-4-14 Typical Receive Operation in Synchronous Mode
308
•
Simultaneous transmit/receive
Figure 10-4-15 shows a typical flow chart for transmitting and receiving simultaneously. After
SCI3 synchronization, follow the procedure below.
1. Read the serial status register (SSR),
and after confirming that bit TDRE = 1,
write transmit data in the transmit data
register (TDR). When data is written to
TDR, TDRE is automatically cleared to 0.
Start
1
2
Read bit TDRE in SSR
No
2. Read the serial status register (SSR),
and after confirming that bit RDRF = 1,
read the received data from the receive
data register (RDR). When data is read
from RDR, RDRF is automatically cleared
to 0.
TDRE = 1?
Yes
Write transmit data in TDR
3. To continue transmitting and receiving
serial data, read bit RDRF and finish
reading RDR before the MSB (bit 7) of the
present frame is received. Also read bit
TDRE, check that it is set to 1, and write
the next data in TDR before the MSB of
the current frame has been transmitted.
When data is written to TDR, TDRE is
automatically cleared to 0; and when data
is read from RDR, RDRF is automatically
cleared to 0.
Read bit OER in SSR
Yes
OER = 1?
No
Read RDRF in SSR
4. When an overrun error occurs, read bit
OER in SSR. After the necessary error
processing, be sure to clear OER to 0.
Data transmission and reception cannot
take place while bit OER is set to 1. See
figure 10-4-13 for overrun error processing.
No
RDRF = 1?
Yes
Read received data in RDR
4
Overrun error processing
Yes
Continue
transmitting and
receiving?
3
No
Clear bits TE and
RE in SCR3 to 0
End
Figure 10-4-15 Simultaneous Transmit/Receive Flow Chart in Synchronous Mode
309
Notes: 1. To switch from transmitting to simultaneous transmitting and receiving, use the
following procedure.
•
First confirm that TDRE and TEND are both set to 1 and that SCI3 has finished
transmitting. Next clear TE to 0. Then set both TE and RE to 1.
2. To switch from receiving to simultaneous transmitting and rceiving, use the following
procedure.
•
After confirming that SCI3 has finished receiving, clear RE to 0. Next, after
confirming that RDRF and the error flags (OER FER, PER) are all 0, set both TE
and RE to 1.
10.4.6 Multiprocessor Communication Function
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in asynchronous mode using a format with an
additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by an ID code. A serial
communication cycle consists of two cycles: an ID-sending cycle that identifies the receiving
processor, and a data-sending cycle. The multiprocessor bit is 1 in an ID-sending cycle, and 0 in a
data-sending cycle.
The transmitting processor starts by sending the ID of the receiving processor with which it wants
to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends
transmit data with the multiprocessor bit cleared to 0. When a receiving processor receives data
with the multiprocessor bit set to 1, it compares the data with its own ID. If the data matches its
ID, the receiving processor continues to receive incoming data. If the data does not match its ID,
the receiving processor skips further incoming data until it again receives data with the
multiprocessor bit set to 1. Multiple processors can send and receive data in this way.
Figure 10-4-16 shows an example of communication among different processors using a
multiprocessor format.
310
Transmitting
processor
Communication line
Receiving
processor A
Receiving
processor B
Receiving
processor C
Receiving
processor D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
Serial data
H'01
H'AA
(MPB = 0)
(MPB = 1)
ID-sending cycle
(receiving processor
address)
Data-sending cycle
(data sent to receiving
processor designated
by ID)
MPB: Multiprocessor bit
Figure 10-4-16 Example of Interprocessor Communication Using Multiprocessor Format
(Data H'AA Sent to Receiving Processor A)
Four communication formats are available. Parity-bit settings are ignored when a multiprocessor
format is selected. For details see table 10-4-11.
For a description of the clock used in multiprocessor communication, see 10.4.4, Operation in
Asynchronous Mode.
311
•
Transmitting multiprocessor data
Figure 10-4-17 shows a typical flow chart for multiprocessor serial data transmission. After SCI3
initialization, follow the procedure below.
Start
1
Read bit TDRE in SSR
1. Read the serial status register (SSR), and
after confirming that bit TDRE = 1, set bit
MPBT (multiprocessor bit transmit) in SSR
to 0 or 1, then write transmit data in the
transmit data register (TDR).
No
TDRE = 1?
Yes
When data is written to TDR, TDRE is
automatically cleared to 0.
Set bit MPBT in SSR
Write transmit data to TDR
Yes
Continue
2
2. To continue transmitting data, read bit
TDRE to make sure it is set to 1, then
write the next data to TDR.
transmitting?
No
When data is written to TDR, TDRE
is automatically cleared to 0.
Read bit TEND in SSR
No
No
TEND = 1?
Yes
3. To output a break signal at the end of data
transmission, first set the port values
PCR = 1 and PDR = 0, then clear bit TE
in SCR3 to 0.
Break output?
Yes
3
Set PDR = 0 and PCR = 1
Clear bit TE in SCR3 to 0
End
Figure 10-4-17 Typical Multiprocessor Data Transmission Flow Chart
312
SCI3 operates as follows during data transmission using a multiprocessor format.
SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data
written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR).
Then TDRE is set to 1 and transmission starts. If bit TIE in SCR3 is set to 1, a TXI interrupt is
requested.
Serial data is transmitted from pin TXD using the communication format outlined in
table 10-4-11.
Next, TDRE is checked as the stop bit is being transmitted. If TDRE is 0, data is transferred from
TDR to TSR, and after the stop bit is sent, transmission of the next frame starts. If TDRE is 1, the
TEND bit in SSR is set to 1, and after the stop bit is sent the output remains at 1 (mark state). A
TEI interrupt is requested in this state if bit TEIE (transmit end interrupt enable) in SCR3 is set
to 1.
Figure 10-4-18 shows a typical SCI3 operation in multiprocessor communication mode.
Start
bit
Transmit
data
Stop Start
Transmit
data
Stop Mark
MPB
0/1
MPB
0/1
bit
bit
bit
state
Serial
data
1
0
D0
D1
D7
1
0
D0
D1
D7
1
1
1 frame
1 frame
TDRE
TEND
TEI
request
SCI3
operation
TXI request TDRE cleared
to 0
TXI
request
User
Write data in
processing
TDR
Figure 10-4-18 Typical Multiprocessor Format Transmit Operation
(8-Bit Data, Multiprocessor Bit Added, and 1 Stop Bit)
313
•
Receiving multiprocessor data
Figure 10-4-19 shows a typical flow chart for receiving data using a multiprocessor format. After
SCI3 initialization, follow the procedure below.
Start
1
2
Set bit MPIE in SCR3 to 1
1. Set bit MPIE in serial control register 3 (SCR3) to 1.
Read bits OER and FER in SSR
2. Read bits OER and FER in the serial status register (SSR)
to determine if an error has occurred. If a receive error has
occurred, receive error processing is executed.
Yes
OER + FER = 1?
No
3. Read the serial status register (SSR) and confirm that
RDRF = 1. If RDRF = 1, read the data in the received data
register (RDR) and compare it with the processor’s own ID.
If the received data does not match the ID, set bit MPIE to
1 again. Bit RDRF is automatically cleared to 0 when data
in the received data register (RDR) is read.
3
Read bit RDRF in SSR
No
No
RDRF = 1?
Yes
4. Read SSR, check that bit RDRF = 1, then read received
data from the receive data register (RDR).
Read received data in RDR
Own ID?
Yes
5. If a receive error occurs, read bits OER and FER in SSR
to determine which error occurred. After the necessary
error processing, be sure to clear the error flags to 0.
Serial data transfer cannot take place while
bit OER or FER is set to 1.
Read bits OER and FER in SSR
When a framing error occurs, a break can be detected by
reading the RXD pin value.
Yes
OER + FER = 1?
No
4
Read bit RDRF in SSR
No
RDRF = 1?
Yes
Read received data in RDR
5
Error processing
Yes
Continue receiving?
No
Overrun error
processing
A
Start receive error processing
Clear bit RE in SCR3 to 0
End
Yes
OER = 1?
No
Yes
Break?
No
Yes
FER = 1?
No
Framing error
processing
Clear bits OER and
FER in SSR to 0.
A
End receive error processing
Figure 10-4-19 Typical Flow Chart for Receiving Serial Data Using Multiprocessor Format
314
Figure 10-4-20 gives an example of data reception using a multiprocessor format.
Start
bit
Receive
data (ID1) MPB bit
Stop Start
bit
Receive
data (data 1) MPB bit
Stop
Mark
(idle state)
Serial
data
1
0
D0
D1
D7
1
1
0
D0
D1
D7
0
1
1
1 frame
1 frame
MPIE
RDRF
RDR
value
ID1
SCI3 operation
User processing
RXI request
MPIE cleared to 0
RDRF cleared to 0
No RXI request
RDR state retained
Read data from RDR If not own ID,
set MPIE to 1 again
(a) Data does not match own ID
Start
bit
Receive
data (ID2) MPB bit
Stop Start
bit
Receive
data (data 2) MPB bit
Stop
Mark
(idle state)
Serial
data
1
0
D0
D1
D7
1
1
0
D0
D1
D7
0
1
1
1 frame
1 frame
MPIE
RDRF
RDR
value
Data 2
ID1
ID2
SCI3 operation
RXI request
MPIE cleared to 0
RDRF cleared to 0
RXI
request
RDRF
cleared
to 0
User processing
Read data from RDR
If own ID, continue
receiving
Read data
from RDR
and set
MPIE to 1
again
(b) Data matches own ID
Figure 10-4-20 Example of Multiprocessor Format Receive Operation
(8-Bit Data, Multiprocessor Bit Added, and 1 Stop Bit)
315
10.4.7 Interrupts
SCI3 has six interrupt sources: transmit end, transmit data empty, receive data full, and the three
receive error interrupts (overrun error, framing error, and parity error). All share a common
interrupt vector. Table 10-4-13 describes each interrupt.
Table 10-4-13 SCI3 Interrupts
Interrupt
RXI
Description
Vector Address
Interrupt request due to receive data register full (RDRF)
Interrupt request due to transmit data register empty (TDRE)
Interrupt request due to transmit end (TEND)
Interrupt request due to receive error (OER, FER, or PER)
H'0024
TXI
TEI
ERI
The interrupt requests are enabled and disabled by bits TIE and RIE of SCR3.
When bit TDRE in SSR is set to 1, TXI is requested. When bit TEND in SSR is set to 1, TEI is
requested. These two interrupt requests occur during data transmission.
The initial value of bit TDRE is 1. Accordingly, if the transmit data empty interrupt request (TXI)
is enabled by setting bit TIE to 1 in SCR3 before placing transmit data in TDR, TXI will be
requested even though no transmit data has been readied.
Likewise, the initial value of bit TEND is 1. Accordingly, if the transmit end interrupt request
(TEI) is enabled by setting bit TEIE to 1 in SCR3 before placing transmit data in TDR, TEI will
be requested even though no data has been transmitted.
These interrupt features can be used to advantage by programming the interrupt handler to move
the transmit data into TDR. When this technique is not used, the interrupt enable bits (TIE and
TEIE) should not be set to 1 until after TDR has been loaded with transmit data, to avoid
unwanted TXI and TEI interrupts.
When bit RDRF in SSR is set to 1, RXI is requested. When any of SSR bits OER, FER, or PER is
set to 1, ERI is requested. These two interrupt requests occur during the receiving of data.
Details on interrupts are given in 3.3, Interrupts.
316
10.4.8 Application Notes
When using SCI3, attention should be paid to the following matters.
1. Relation between bit TDRE and writing data to TDR
Bit TDRE in the serial status register (SSR) is a status flag indicating that TDR does not contain
new transmit data. TDRE is automatically cleared to 0 when data is written to TDR. When SCI3
transfers data from TDR to TSR, bit TDRE is set to 1.
Data can be written to TDR regardless of the status of bit TDRE. However, if new data is written
to TDR while TDRE is cleared to 0, assuming the data held in TDR has not yet been shifted to
TSR, it will be lost. For this reason it is advisable to confirm that bit TDRE is set to 1 before each
write to TDR and not write to TDR more than once without checking TDRE in between.
2. Operation when multiple receive errors occur at the same time
When two or more receive errors occur at the same time, the status flags in SSR are set as shown
in table 10-4-14. If an overrun error occurs, data is not transferred from RSR to RDR, and receive
data is lost.
Table 10-4-14 SSR Status Flag States and Transfer of Receive Data
SSR Status Flags
Receive Data Transfer
(RSR → RDR)
RDRF* OER FER PER
Receive Error Status
Overrun error
1
0
0
1
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
1
0
1
1
1
×
o
o
×
×
o
×
Framing error
Parity error
Overrun error + framing error
Overrun error + parity error
Framing error + parity error
Overrun error + framing error + parity error
Notation: o: Receive data transferred from RSR to RDR
×: Receive data not transferred from RSR to RDR
Note: *RDRF keeps the same state as before the data was received. However, if due to a late
read of received data in one frame an overrun error occurs in the next frame, RDRF is
cleared to 0 when RDR is read.
317
3. Break detection and processing
Break signals can be detected by reading the RXD pin directly when a framing error (FER) is
detected. In the break state the input from the RXD pin consists of all 0s, so FER is set and the
parity error flag (PER) may also be set. In the break state SCI3 continues to receive, so if the FER
bit is cleared to 0 it will be set to 1 again.
4. Sending a mark or break signal
When TE is cleared to 0 the TXD pin becomes an I/O port, the level and direction (input or
output) of which are determined by the PDR and PCR bits. This feature can be used to place the
TXD pin in the mark state or send a break signal.
To place the serial communication line in the mark (1) state before TE is set to 1, set the PDR and
PCR bits both to 1. Since TE is cleared to 0, TXD becomes a general output port outputting the
value 1.
To send a break signal during data transmission, set the PCR bit to 1 and clear the PDR bit to 0,
then clear TE to 0. When TE is cleared to 0 the transmitter is initialized, regardless of its current
state, so the TXD pin becomes an output port outputting the value 0.
5. Receive error flags and transmit operation (sysnchronous mode only)
When a receive error flag (ORER, PER, or FER) is set to 1, SCI3 will not start transmitting even if
TDRE is cleared to 0. Be sure to clear the receive error flags to 0 when starting to transmit. Note
that clearing RE to 0 does not clear the receive error flags.
6. Receive data sampling timing and receive margin in asynchronous mode
In asynchronous mode SCI3 operates on a base clock with 16 times the bit rate frequency. In
receiving, SCI3 synchronizes internally with the falling edge of the start bit, which it samples on
the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. See
figure 10-4-21.
318
16 clock cycles
8 clock cycles
0
7
15 0
7
15 0
Internal base
clock
Receive data
(RXD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 10-4-21 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be derived from the following equation.
M = {(0.5 – 1/2N) – (D – 0.5) / N – (L – 0.5) F} × 100% ....................................Equation (1)
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0.5 to 1)
L: Frame length (L = 9 to 12)
F: Absolute value of clock frequency error
In equation (1), if F (absolute value of clock frequency error) = 0 and D (clock duty cycle) = 0.5,
the receive margin is 46.875% as given by equation (2) below.
When D = 0.5 and F = 0,
M = {0.5 – 1/(2 × 16)} × 100% = 46.875% ..........................................................Equation (2)
This value is theoretical. In actual system designs a margin of from 20 to 30 percent should be
allowed.
319
7. Relationship between bit RDRF and reading RDR
While SCI3 is receiving, it checks the RDRF flag. When a frame of data has been received, if the
RDRF flag is cleared to 0, data receiving ends normally. If RDRF is set to 1, an overrun error
occurs.
RDRF is automatically cleared to 0 when the contents of RDR are read. If RDR is read more than
once, the second and later reads will be performed with RDRF cleared to 0. While RDRF is 0, if
RDR is read when reception of the next frame is just ending, data from the next frame may be
read. This is illustrated in figure 10-4-22.
Frame 1
Data 1
Frame 2
Data 2
Frame 3
Data 3
Communica-
tion line
RDRF
RDR
Data 1
Data 2
A
B
RDR read
RDR read
User processing
At A , data 1 is read.
At B , data 2 is read.
Figure 10-4-22 Relationship between Data and RDR Read Timing
To avoid the situation described above, after RDRF is confirmed to be 1, RDR should only be read
once and should not be read twice or more.
When the same data must be read more than once, the data read the first time should be copied to
RAM, for example, and the copied data should be used. An alternative is to read RDR but leave a
safe margin of time before reception of the next frame is completed. In synchronous mode, all
reads of RDR should be completed before bit 7 is received. In asynchronous mode, all reads of
RDR should be completed before the stop bit is received.
320
8. Switching SCK function
3
If pin SCK is used as a clock output pin by SCI3 in synchronous mode and is then switched to a
3
general input/output pin (a pin with a different function), the pin outputs a low level signal for half
a system clock (φ) cycle immediately after it is switched.
This can be prevented by either of the following methods according to the situation.
a. When an SCK function is switched from clock output to non clock-output
3
When stopping data transfer, issue one instruction to clear bits TE and RE to 0 and to set bits
CKE1 and CKE0 in SCR3 to 1 and 0, respectively. In this case, bit COM in SMR should be left 1.
The above prevents SCK from being used as a general input/output pin. To avoid an intermediate
3
level of voltage from being applied to SCK , the line connected to SCK should be pulled up to
3
3
the Vcc level via a resistor, or supplied with output from an external device.
b. When an SCK function is switched from clock output to general input/output
3
When stopping data transfer,
(i) Issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in SCR3 to
1 and 0, respectively.
(ii) Clear bit COM in SCR3 to 0
(iii) Clear bits CKE1 and CKE0 in SCR3 to 0
Note that special care is also needed here to avoid an intermediate level of voltage from being
applied to SCK .
3
9. Switching TXD function
If pin TXD is used as a data output pin by SCI3 in synchronous mode and is then switched to a
general input/output pin (a pin with a different function), the pin outputs a high level signal for
one system clock (φ) cycle immediately after it is switched.
321
Section 11 14-Bit PWM
11.1 Overview
The H8/3834U Series is provided with a 14-bit PWM (pulse width modulator) on-chip, which can
be used as a D/A converter by connecting a low-pass filter.
11.1.1 Features
Features of the 14-bit PWM are as follows.
•
Choice of two conversion periods
A conversion period of 32,768/ø, with a minimum modulation width of 2/ø (PWCR0 = 1), or a
conversion period of 16,384/ø, with a minimum modulation width of 1/ø (PWCR0 = 0), can be
chosen.
•
Pulse division method for less ripple
11.1.2 Block Diagram
Figure 11-1 shows a block diagram of the 14-bit PWM.
PWDRL
PWDRU
PWM
waveform
generator
ø/2
ø/4
PWCR
PWM
Notation:
PWDRL: PWM data register L
PWDRU: PWM data register U
PWCR: PWM control register
Figure 11-1 Block Diagram of the 14 bit PWM
323
11.1.3 Pin Configuration
Table 11-1 shows the output pin assigned to the 14-bit PWM.
Table 11-1 Pin Configuration
Name
Abbrev.
I/O
Function
PWM output pin
PWM
Output
Pulse-division PWM waveform output
11.1.4 Register Configuration
Table 11-2 shows the register configuration of the 14-bit PWM.
Table 11-2 Register Configuration
Name
Abbrev.
PWCR
R/W
W
Initial Value
H'FE
Address
H'FFD0
H'FFD1
H'FFD2
PWM control register
PWM data register U
PWM data register L
PWDRU
PWDRL
W
H'C0
W
H'00
324
11.2 Register Descriptions
11.2.1 PWM Control Register (PWCR)
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
—
1
0
PWCR0
Initial value
Read/Write
0
—
—
—
—
—
—
—
W
PWCR is an 8-bit write-only register for input clock selection.
Upon reset, PWCR is initialized to H'FE.
Bits 7 to 1: Reserved bits
Bits 7 to 1 are reserved; they are always read as 1, and cannot be modified.
Bit 0: Clock select 0 (PWCR0)
Bit 0 selects the clock supplied to the 14-bit PWM. This bit is a write-only bit; it is always read as 1.
Bit 0
PWCR0 Description
0
The input clock is ø/2 (tø = 2/ø). The conversion period is 16,384/ø,
with a minimum modulation width of 1/ø.
(initial value)
1
The input clock is ø/4 (tø = 4/ø). The conversion period is 32,768/ø, with a minimum
modulation width of 2/ø.
Notation:
tø: Period of PWM input clock
325
11.2.2 PWM Data Registers U and L (PWDRU, PWDRL)
PWDRU
Bit
7
—
1
6
—
1
5
4
3
2
1
0
PWDRU5PWDRU4PWDRU3PWDRU2 PWDRU1PWDRU0
Initial value
Read/Write
0
0
0
0
0
0
—
—
W
W
W
W
W
W
PWDRL
Bit
7
6
5
4
3
2
1
0
PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
PWDRU and PWDRL form a 14-bit write-only register, with the upper 6 bits assigned to PWDRU
and the lower 8 bits to PWDRL. The value written to PWDRU and PWDRL gives the total high-
level width of one PWM waveform cycle.
When 14-bit data is written to PWDRU and PWDRL, the register contents are latched in the
PWM waveform generator, updating the PWM waveform generation data. The 14-bit data should
always be written in the following sequence, first to PWDRL and then to PWDRU.
1. Write the lower 8 bits to PWDRL.
2. Write the upper 6 bits to PWDRU.
PWDRU and PWDRL are write-only registers. If they are read, all bits are read as 1.
Upon reset, PWDRU and PWDRL are initialized to H'C000.
326
11.3 Operation
When using the 14-bit PWM, set the registers in the following sequence.
1. Set bit PWM in port mode register 1 (PMR1) to 1 so that pin P1 /PWM is designated for
4
PWM output.
2. Set bit PWCR0 in the PWM control register (PWCR) to select a conversion period of either
32,768/ø (PWCR0 = 1) or 16,384/ø (PWCR0 = 0).
3. Set the output waveform data in PWM data registers U and L (PWDRU/L). Be sure to write
in the correct sequence, first PWDRL then PWDRU. When data is written to PWDRU, the
data in these registers will be latched in the PWM waveform generator, updating the PWM
waveform generation in synchronization with internal signals.
One conversion period consists of 64 pulses, as shown in figure 11-2. The total of the high-
level pulse widths during this period (T ) corresponds to the data in PWDRU and PWDRL.
H
This relation can be represented as follows.
T = (data value in PWDRU and PWDRL + 64) × t /2
H
ø
where t is the PWM input clock period, either 2/ø (bit PWCR0 = 0) or 4/ø (bit PWCR0 = 1).
ø
Example: Settings in order to obtain a conversion period of 8,192 µs:
When bit PWCR0 = 0, the conversion period is 16,384/ø, so ø must be 2 MHz. In
this case t = 128 µs, with 1/ø (resolution) = 0.5 µs.
fn
When bit PWCR0 = 1, the conversion period is 32,768/ø, so ø must be 4 MHz. In
this case t = 128 µs, with 2/ø (resolution) = 0.5 µs.
fn
Accordingly, for a conversion period of 8,192 µs, the system clock frequency (ø)
must be 2 MHz or 4 MHz.
327
1 conversion period
tf1
tf2
tf63
tf64
tH1
tH2
tH3
tH63
tH64
TH = t H1 + t H2+ tH3
+ ..... tH64
t f1 = tf2 = tf3 ..... = tf84
Figure 11-2 PWM Output Waveform
328
Section 12 A/D Converter
12.1 Overview
The H8/3834U Series includes on-chip a resistance-ladder-based successive-approximation
analog-to-digital converter, and can convert up to 12 channels of analog input.
12.1.1 Features
The A/D converter has the following features.
•
•
•
•
•
•
8-bit resolution
12 input channels
Conversion time: approx. 12.4 µs per channel (at 5 MHz operation)
Built-in sample-and-hold function
Interrupt requested on completion of A/D conversion
A/D conversion can be started by external trigger input
12.1.2 Block Diagram
Figure 12-1 shows a block diagram of the A/D converter.
ADTRG
A/D mode
register
AN0
AN1
AN2
AN3
AN4
AN5
A/D start
register
Multiplexer
AN6
AN7
AVCC
AN8
AN9
AN10
AN11
+
Com-
parator
Control logic
–
AVCC
AVSS
AVSS
Reference
voltage
A/D result register
IRRAD
Figure 12-1 Block Diagram of the A/D Converter
329
12.1.3 Pin Configuration
Table 12-1 shows the A/D converter pin configuration.
Table 12-1 Pin Configuration
Name
Abbrev. I/O
Function
Analog power supply pin AVCC
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Power supply and reference voltage of analog part
Ground and reference voltage of analog part
Analog input channel 0
Analog ground pin
Analog input pin 0
Analog input pin 1
Analog input pin 2
Analog input pin 3
Analog input pin 4
Analog input pin 5
Analog input pin 6
Analog input pin 7
Analog input pin 8
Analog input pin 9
Analog input pin 10
Analog input pin 11
AVSS
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
Analog input channel 1
Analog input channel 2
Analog input channel 3
Analog input channel 4
Analog input channel 5
Analog input channel 6
Analog input channel 7
Analog input channel 8
Analog input channel 9
Analog input channel 10
Analog input channel 11
External trigger input pin ADTRG
External trigger input for starting A/D conversion
12.1.4 Register Configuration
Table 12-2 shows the A/D converter register configuration.
Table 12-2 Register Configuration
Name
Abbrev.
AMR
R/W
R/W
R/W
R
Initial Value
H'30
Address
H'FFC4
H'FFC6
H'FFC5
A/D mode register
A/D start register
A/D result register
ADSR
ADRR
H'7F
Not fixed
330
12.2 Register Descriptions
12.2.1 A/D Result Register (ADRR)
Bit
7
ADR7
—
6
ADR6
—
5
ADR5
—
4
ADR4
—
3
ADR3
—
2
ADR2
—
1
ADR1
—
0
ADR0
—
Initial value
Read/Write
R
R
R
R
R
R
R
R
The A/D result register (ADRR) is an 8-bit read-only register for holding the results of analog-to-
digital conversion.
ADRR can be read by the CPU at any time, but the ADRR values during A/D conversion are not
fixed.
After A/D conversion is complete, the conversion result is stored in ADRR as 8-bit data; this data
is held in ADRR until the next conversion operation starts.
ADRR is not cleared on reset.
12.2.2 A/D Mode Register (AMR)
Bit
7
6
TRGE
0
5
—
1
4
—
1
3
2
1
0
CKS
0
CH3
0
CH2
0
CH1
0
CH0
0
Initial value
Read/Write
R/W
R/W
—
—
R/W
R/W
R/W
R/W
AMR is an 8-bit read/write register for specifying the A/D conversion speed, external trigger
option, and the analog input pins.
Upon reset, AMR is initialized to H'30.
Bit 7: Clock select (CKS)
Bit 7 sets the A/D conversion speed.
Conversion Time
Bit 7
CKS
Conversion Period
62/ø (initial value)
31/ø
ø = 2 MHz
31 µs
ø = 5 MHz
12.4 µs
*
0
1
15.5 µs
Note: * Operation is not guaranteed if the conversion time is less than 12.4 µs. Set bit 7 for a
value of at least 12.4 µs.
331
Bit 6: External trigger select (TRGE)
Bit 6 enables or disables the start of A/D conversion by external trigger input.
Bit 6
TRGE
Description
0
1
Disables start of A/D conversion by external trigger
(initial value)
Enables start of A/D conversion by rising or falling edge of external trigger at pin
ADTRG*
Note: * The external trigger (ADTRG) edge is selected by bit IEG4 of the IRQ edge select register
(IEGR). See 3.3.2 for details.
Bits 5 and 4: Reserved bits
Bits 5 and 4 are reserved; they are always read as 1, and cannot be modified.
Bits 3 to 0: Channel select (CH3 to CH0)
Bits 3 to 0 select the analog input channel.
The channel selection should be made while bit ADSF is cleared to 0.
Bit 3
CH3
Bit 2
CH2
Bit 1
CH1
Bit 0
CH0
Analog Input Channel
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
*
*
No channel selected
(initial value)
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
Note: * Don’t care
332
12.2.3 A/D Start Register (ADSR)
Bit
7
ADSF
0
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
—
1
0
—
1
Initial value
Read/Write
R/W
—
—
—
—
—
—
—
The A/D start register (ADSR) is an 8-bit read/write register for starting and stopping A/D
conversion.
A/D conversion is started by writing 1 to the A/D start flag (ADSF) or by input of the designated
edge of the external trigger signal, which also sets ADSF to 1. When conversion is complete, the
converted data is set in the A/D result register (ADRR), and at the same time ADSF is cleared
to 0.
Bit 7: A/D start flag (ADSF)
Bit 7 controls and indicates the start and end of A/D conversion.
Bit 7
ADSF
Description
0
Read
Write
Read
Write
Indicates the completion of A/D conversion
(initial value)
Stops A/D conversion
1
Indicates A/D conversion in progress
Starts A/D conversion
Bits 6 to 0: Reserved bits
Bits 6 to 0 are reserved; they are always read as 1, and cannot be modified.
333
12.3 Operation
12.3.1 A/D Conversion Operation
The A/D converter operates by successive approximations, and yields its conversion result as 8-bit
data.
A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a
value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete.
The completion of conversion also sets bit IRRAD in interrupt request register 2 (IRR2) to 1. An
A/D conversion end interrupt is requested if bit IENAD in interrupt enable register 2 (IENR2) is
set to 1.
If the conversion time or input channel needs to be changed in the A/D mode register (AMR)
during A/D conversion, bit ADSF should first be cleared to 0, stopping the conversion operation,
in order to avoid malfunction.
12.3.2 Start of A/D Conversion by External Trigger Input
The A/D converter can be made to start A/D conversion by input of an external trigger signal.
External trigger input is enabled at pin ADTRG when bit IRQ4 in port mode register 2 (PMR2) is
set to 1, and bit TRGE in AMR is set to 1. Then when the input signal edge designated in bit
IEG4 of the IRQ edge select register (IEGR) is detected at pin ADTRG, bit ADSF in ADSR will
be set to 1, starting A/D conversion.
Figure 12-2 shows the timing.
ø
Pin ADTRG
(when bit
IEG4 = 0)
ADSF
A/D conversion
Figure 12-2 External Trigger Input Timing
334
12.4 Interrupts
When A/D conversion ends (ADSF changes from 1 to 0), bit IRRAD in interrupt request
register 2 (IRR2) is set to 1.
A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt
enable register 2 (IENR2).
For further details see 3.3, Interrupts.
12.5 Typical Use
An example of how the A/D converter can be used is given below, using channel 1 (pin AN ) as
1
the analog input channel. Figure 12-3 shows the operation timing.
•
Bits CH3 to CH0 of the A/D mode register (AMR) are set to 0101, making pin AN the
1
analog input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D
conversion is started by setting bit ADSF to 1.
•
When A/D conversion is complete, bit IRRAD is set to 1, and the A/D conversion result is
stored in the A/D result register (ADRR). At the same time ADSF is cleared to 0, and the
A/D converter goes to the idle state.
•
•
•
•
Bit IENAD = 1, so an A/D conversion end interrupt is requested.
The A/D interrupt handling routine starts.
The A/D conversion result is read and processed.
The A/D interrupt handling routine ends.
If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place.
Figures 12-4 and 12-5 show flow charts of procedures for using the A/D converter.
335
Figure 12-3 Typical A/D Converter Operation Timing
336
Start
Set A/D conversion speed
and input channel
Disable A/D conversion
end interrupt
Start A/D conversion
Read ADSR
No
ADSF = 0?
Yes
Read ADRR data
Yes
Perform A/D
conversion?
No
End
Figure 12-4 Flow Chart of Procedure for Using A/D Converter (1) (Polling by Software)
337
Start
Set A/D conversion speed
and input channels
Enable A/D conversion
end interrupt
Start A/D conversion
Yes
A/D conversion
end interrupt?
No
Clear bit IRRAD to
0 in IRR2
Read ADRR data
Yes
Perform A/D
conversion?
No
End
Figure 12-5 Flow Chart of Procedure for Using A/D Converter (2) (Interrupts Used)
12.6 Application Notes
•
Data in the A/D result register (ADRR) should be read only when the A/D start flag (ADSF)
in the A/D start register (ADSR) is cleared to 0.
•
Changing the digital input signal at an adjacent pin during A/D conversion may adversely
affect conversion accuracy.
338
Section 13 LCD Controller/Driver
13.1 Overview
The H8/3834U Series has an on-chip segment-type LCD controller circuit, LCD driver, and power
supply circuit, for direct driving of an LCD panel.
13.1.1 Features
Features of the LCD controller/driver are as follows.
•
Display capacity
External Segment
Expansion Driver
Duty
—
Internal Driver
40 segments
36 segments
36 segments
36 segments
36 segments
On-chip driver only
0
Use with external segment
expansion driver
Static
1/2
476 segments
220 segments
92 segments
92 segments
1/3
1/4
The HD66100 can be used for external expansion of the number of segments.
•
LCD RAM capacity
8 bits × 64 bytes (512 bits)
•
•
•
Word access to LCD RAM
Segment output pins can be switched to general-purpose ports in groups of 4
Unused common output pins can be used either for boosting common output (by parallel
connection) or as ports.
•
•
•
Displays in all operation modes except standby mode.
Choice of 11 frame frequencies
Internal voltage divider for liquid crystal driver power supply
339
13.1.2 Block Diagram
Figure 13-1 shows a block diagram of the LCD controller/driver.
VCC
V1
V2
LCD driver
power supply
V3
M
VSS
CL2
ø/2 to ø/256
øW
COM1
Common
data latch
Common
driver
COM4
SEG40 /CL1
SEG39 /CL2
SEG38 /DO
SEG37 /M
SEG36
LPCR
LCR
40-bit
shift
register
Segment
driver
Display timing generator
CL1
LCD RAM
64 bytes
SEG1
SEGn, DO
Notation:
LPCR: LCD port control register
LCR: LCD control register
Figure 13-1 LCD Controller/Driver Block Diagram
340
13.1.3 Pin Configuration
Table 13-1 shows the output pins assigned to the LCD controller/driver.
Table 13-1 Pin Configuration
Name
Abbrev.
I/O
Function
LCD segment output
SEG40 to Output Liquid crystal segment driver pins. All pins can be
SEG1
programmed also as ports.
LCD common output
COM4 to
COM1
Output Liquid crystal common driver pins. Parallel
connection is possible at static and 1/2 duty.
External segment
expansion signal
CL1
CL2
M
Output Display data latch clock; doubles as SEG40
Output Display data shift clock; doubles as SEG39
Output LCD alternating signal; doubles as SEG37
Output Serial display data; doubles as SEG38
DO
LCD power supply
V1, V2, V3 Input
For external connection to bypass capacitor or for
use of external power supply circuit
13.1.4 Register Configuration
Table 13-2 shows the register configuration of the LCD controller/driver.
Table 13-2 Register Configuration
Name
Abbrev.
LPCR
LCR
R/W
R/W
R/W
R/W
Initial Value
H'00
Address
LCD port control register
LCD control register
LCD RAM
H'FFC0
H'80
H'FFC1
—
Not fixed
H'F740 to H'F77F*
Note: * Value after reset.
341
13.2 Register Descriptions
13.2.1 LCD Port Control Register (LPCR)
Bit
7
DTS1
0
6
DTS0
0
5
CMX
0
4
3
SGS3
0
2
SGS2
0
1
SGS1
0
0
SGS0
0
SGX
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The LCD port control register is an 8-bit read/write register, used for selecting the duty cycle and
the LCD driver and pin functions, etc. Upon reset, LPCR is initialized to H'00.
Bits 7 to 5: Duty and common function select (DTS1, DTS0, CMX)
Bits 7 to 6 select a driver duty of static, 1/2, 1/3, or 1/4. Bit 5 determines whether the common
pins not used at a given duty are to be used as ports or, in order to increase the common driving
capacity, as multiple pins outputting the same waveform.
Bit 7 Bit 6 Bit 5
DTS1 DTS0 CMX Duty
Common Driver*1 Other Uses
0
0
0
1
Static
COM1 (initial value) COM4, COM3 and COM2 usable as ports
COM4 to COM1
COM4, COM3 and COM2 output the same
waveform as COM1
0
1
0
1
1/2 duty COM2 to COM1
COM4 to COM1
COM4 and COM3 usable as ports
COM4 outputs the same waveform as
COM3, and COM2 the same waveform as
COM1
1
1
0
1
0
1
0
1
1/3 duty COM3 to COM1
COM4 to COM1
COM4 usable as port
COM4 outputs a non-select waveform*2
—
1/4 duty COM4 to COM1
Notes: 1. Pins COM4 to COM1 become ports when bit SGX = 0 and bits SGS3 to SGS0 = 0000.
Otherwise the common drivers are as indicated in the table above.
2. A non-select waveform is always output at pin COM4, which therefore should not be
used.
342
Bit 4: Expansion signal select (SGX)
Bit 4 selects whether pins SEG /CL , SEG /CL , SEG /DO, and SEG /M are used as segment
40
1
39
2
38
37
pins (SEG to SEG ) or as external segment expansion pins (CL , CL , DO, M).
40
37
1
2
Bit 4
SGX
Description
0
1
Pins SEG40 to SEG37
*
(initial value)
Pins CL1, CL2, DO, M
Note: * Selected as ports when bits SGS3 to SGS0 = 0000.
Bits 3 to 0: Segment driver select (SGS3 to SGS0)
Bits 3 to 0 select the pins to be used as segment drivers.
Functions of Pins SEG to SEG
40
1
Bit4 Bit 3 Bit 2 Bit 1 Bit 0 SEG to SEG to SEG to SEG to SEG to SEG to SEG to SEG to SEG to SEG to
40
37
36
33
32
29
28
25
24
21
20
17
16
13
12
9
8
5
4
1
SGX SGS3 SGS2 SGS1 SGS0 SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
Remarks
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
*
*
0
0
0
1
1
0
0
1
1
*
*
0
0
1
0
1
0
1
0
1
0
1
0
Port
Port
Port
Port
Port
Port
Port
Port
SEG
SEG
SEG
SEG
SEG
SEG
Port
Port
Port
Port
Port
Port
SEG
SEG
SEG
SEG
SEG
Port
Port
Port
Port
Port
Port
Port
SEG
SEG
SEG
SEG
Port
Port
Port
Port
Port
Port
Port
Port
SEG
SEG
SEG
Port
Port
Port
Port
Port
Port
Port
Port
Port
SEG
SEG
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
SEG
Port
(initial value)
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
Port
Port
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
Port
Port
SEG
SEG
SEG
SEG
SEG
SEG
SEG
Port
1
External Port
segment
expansion
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
*
0
1
1
0
0
1
1
*
1
0
1
0
1
0
1
0
External SEG
segment
Port
Port
Port
Port
Port
Port
Port
SEG
SEG
SEG
SEG
Port
Port
Port
Port
Port
SEG
SEG
SEG
Port
Port
Port
Port
Port
Port
SEG
SEG
Port
Port
Port
Port
Port
Port
Port
SEG
Port
Port
Port
Port
Port
Port
Port
Port
expansion
External SEG
segment
expansion
SEG
SEG
SEG
SEG
SEG
SEG
SEG
Port
Port
External SEG
segment
expansion
SEG
SEG
SEG
SEG
SEG
SEG
Port
External SEG
segment
expansion
SEG
SEG
SEG
SEG
SEG
External SEG
segment
expansion
External SEG
segment
expansion
External SEG
segment
expansion
External SEG
segment
expansion
1
*
*
1
External SEG
segment
expansion
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
Note: * Don’t care
343
13.2.2 LCD Control Register (LCR)
Bit
7
—
1
6
PSW
0
5
4
DISP
0
3
CKS3
0
2
CKS2
0
1
CKS1
0
0
CKS0
0
ACT
0
Initial value
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The LCD control register is an 8-bit read/write register for on/off control of the resistive voltage
divider used as the LCD driver power supply, for display data control, and for frame frequency
selection. Upon reset, LCR is initialized to H'80.
Bit 7: Reserved bit
Bit 7 is reserved; it is always read as 1, and cannot be modified.
Bit 6: Power switch (PSW)
Bit 6 switches the resistive voltage divider provided to power the LCD driver on/off. In low-
power modes when the LCD display is not used, or when an external power supply is used for the
LCD, the resistive voltage divider can be switched off. When bit ACT = 0, or in standby mode,
the resistive voltage divider is in the off state regardless of the bit 6 setting.
Bit 6
PSW
Description
0
1
LCD power supply resistive voltage divider off
LCD power supply resistive voltage divider on
(initial value)
Bit 5: Display active (ACT)
Bit 5 selects whether the LCD controller/driver is used or not. When this bit is cleared to 0, the
LCD controller/driver module halts operation, and the resistive voltage divider provided for the
LCD driver power supply goes to the off state regardless of the PSW setting. However, register
contents are retained.
Bit 5
ACT
Description
0
1
LCD controller/driver operation stopped
LCD controller/driver operational
(initial value)
344
Bit 4: Display data control (DISP)
Bit 4 selects whether the LCD RAM contents are displayed or blank data is displayed regardless
of the LCD RAM contents. This bit is valid also when the HD66100 is used for external segment
expansion.
Bit 4
DISP
Description
0
1
Blank data displayed
LCD RAM data displayed
(initial value)
Bits 3 to 0: Frame frequency select (CKS3 to CKS0)
Bits 3 to 0 select the clock used by the LCD controller/driver, and the frame frequency. In
subactive, watch, and subsleep modes the system clock (ø) is stopped, so there will be no display
in these modes if ø/2 to ø/256 is chosen as the clock source. For display in these modes, clock ø
W
or ø /2 must be selected.
W
Frame Frequency*3
ø = 625 kHz*1
Bit 3
Bit 2
Bit 1
Bit 0
CKS3 CKS2 CKS1 CKS0
Clock
øW
ø = 5 MHz
128 Hz*2
64 Hz
32 Hz
—
0
0
0
1
1
1
1
1
1
1
1
*
*
*
0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
1
0
1
*
(initial value)
øW
øW/2
ø/2
0
1
0
1
0
1
0
1
610 Hz
305 Hz
153 Hz
76.3 Hz
38.1 Hz
—
ø/4
—
ø/8
—
ø/16
ø/32
ø/64
ø/128
ø/256
610 Hz
305 Hz
153 Hz
76.3 Hz
38.1 Hz
—
—
Notes: * Don’t care
1. Frame frequency in active (medium-speed) mode
2. Only the upper 32 bytes of the display RAM are used.
3. When a duty cycle of 1/3 is chosen, the frame frequency will be 4/3 times the
frequencies shown in the above table.
345
13.3 Operation
13.3.1 Settings Prior to LCD Display
Various decisions related to hardware and software must be made before using the LCD
controller/driver with an LCD display. The settings are described below.
1. Hardware settings
•
Use at 1/2 duty
To use at 1/2 duty, connect pins V and V as shown in figure 13-2.
2
3
VCC
V1
V2
V3
VSS
Figure 13-2 LCD Driver Power Supply Processing at 1/2 Duty
Large-panel display
•
Because of the large impedance of the built-in resistive voltage divider, the H8/3834U Series LCD
controller/driver is not well suited to driving large-panel displays. If use of a large panel leads to
an unclear display, refer to 13.3.5 on boosting the LCD driver power supply. At static and 1/2
duty it is possible to boost the common output driving capacity. Set bit CMX to 1 when selecting
the duty cycle. In this mode, at static duty pins COM to COM output the same waveform, while
4
1
at 1/2 duty pins COM and COM output the COM waveform and pins COM and COM output
2
1
1
4
3
the COM waveform.
2
346
•
Segment expansion
The HD66100 can be connected externally to expand the number of segments. See 13.3.3,
Connection to HD66100.
2. Software settings
•
Duty cycle selection
The duty cycle is selected in bits DTS1 and DTS0, with a choice of static, 1/2, 1/3, or 1/4 duty.
Segment driver selection
The segment drivers to be used are selected in bits SGS3 to SGS0.
Frame frequency selection
•
•
The frame frequency is selected in bits CKS3 to CKS0. The frame frequency should be selected
depending on the specification of the LCD panel to be used. Refer to 13.3.4, Operation in Power-
Down Modes, for information on clock selection in watch mode, subactive mode, and subsleep
mode.
13.3.2 Relation of LCD RAM to Display
The relation of the LCD RAM to segments depends on the duty cycle. LCD RAM memory maps
for each duty cycle when segments are not expanded externally are shown in figures 13-3 to 13-6.
When segments are expanded externally, the LCD RAM memory maps for each duty cycle are as
shown in figures 13-7 to 13-10. It is also possible to use only external segments and not use the
segment pins on this chip, in which case the LCD RAM memory map is as shown in figure 13-11.
After setting the registers that control the LCD display, write data to the area corresponding to the
duty cycle selected, using the same instructions as for the ordinary RAM. If the display is
switched on, the data will be displayed automatically. Both word and byte access instructions can
be used for writing to the LCD RAM.
347
13.3.3 Connection to HD66100
To expand the number of segments externally, connect the H8/3834U Series to the HD66100
segment chip. The HD66100 chip provides an additional 80 segments. When external segments
are used, set bit SGX in LPCR for use of pins SEG to SEG as external segment expansion
40
37
signal pins. Data will be output starting from LCD RAM pin SEG . When bits SGS3 to SGS0
37
in LPCR are set to 0000, data will be output starting from LCD RAM pin SEG .
1
Figure 13-12 shows typical connections to the HD66100. The output level is determined by the
combination of data pins and pin M; but that combination differs between the H8/3834U Series
and the HD66100. Table 13-3 shows the output level of the LCD driver power supply.
Figure 13-13 shows the common and segment waveforms at each duty.
If bit ACT = 0, then if CL = 0, CL = 0 and M = 0, DO stops with the data output at that moment
2
1
(1 or 0). In standby mode the expansion pins are in the high-impedance (floating) state.
External expansion increases the load on the LCD panel, as a result of which the internal power
supply may not have sufficient capacity. In that case refer to 13.3.5 on boosting the LCD driver
power supply.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H'F740*
H'F753*
SEG2 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1 SEG1
Internal driver
display area
SEG40 SEG40 SEG40 SEG40 SEG39 SEG39 SEG39 SEG39
Area not used
for display
H'F77F*
COM4 COM3 COM2 COM1 COM4 COM3 COM2 COM1
Note: * Values immediately after reset.
Figure 13-3 LCD RAM Map 1: No External Segment Expansion (1/4 Duty)
348
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H'F740*
H'F753*
SEG2 SEG2 SEG2
SEG1 SEG1 SEG1
Internal driver
display area
SEG40 SEG40 SEG40
SEG39 SEG39 SEG39
Area not used
for display
H'F77F*
COM3 COM2 COM1
COM3 COM2 COM1
Note: * Values immediately after reset.
Figure 13-4 LCD RAM Map 2: No External Segment Expansion (1/3 Duty)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H'F740*
H'F749*
SEG4 SEG4 SEG3 SEG3 SEG2 SEG2 SEG1 SEG1
Internal driver
display area
SEG40 SEG40 SEG39 SEG39 SEG38 SEG38 SEG37 SEG37
Area not used
for display
H'F77F*
COM2 COM1 COM2 COM1 COM2 COM1 COM2 COM1
Note: * Values immediately after reset.
Figure 13-5 LCD RAM Map 3: No External Segment Expansion (1/2 Duty)
349
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H'F740*
H'F744*
SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33
Internal driver
display area
Area not used
for display
H'F77F*
COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1
Note: * Values immediately after reset.
Figure 13-6 LCD RAM Map 4: No External Segment Expansion (Static Duty)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H'F740*
SEG2
SEG2 SEG2 SEG2 SEG1 SEG1 SEG1 SEG1
Internal driver
display area
H'F751*
H'F75F*
SEG36 SEG36 SEG36 SEG36 SEG35 SEG35 SEG35 SEG35
SEG38 SEG38 SEG38 SEG38 SEG37 SEG37 SEG37 SEG37
SEG64 SEG64 SEG64 SEG64 SEG63 SEG63 SEG63 SEG63
External driver
display area
(when CKS3 = CKS1 = CKS0 = 0)
External driver
display area
H'F77F* SEG128 SEG128 SEG128 SEG128 SEG127 SEG127 SEG127 SEG127
COM4 COM3 COM2 COM1 COM4 COM3 COM2 COM1
Note: * Values immediately after reset.
Figure 13-7 LCD RAM Map 1: External Segment Expansion (1/4 Duty)
350
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H'F740*
SEG2 SEG2 SEG2
SEG1 SEG1 SEG1
Internal driver
display area
H'F751*
H'F75F*
SEG36 SEG36 SEG36
SEG38 SEG38 SEG38
SEG64 SEG64 SEG64
SEG35 SEG35 SEG35
SEG37 SEG37 SEG37
SEG63 SEG63 SEG63
External driver
display area
(when CKS3 = CKS1 = CKS0 = 0)
External driver
display area
H'F77F*
SEG128 SEG128 SEG128
COM3 COM 2 COM 1
SEG127 SEG127 SEG127
COM 3 COM 2 COM 1
Note: * Values immediately after reset.
Figure 13-8 LCD RAM Map 2: External Segment Expansion (1/3 Duty)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H'F740*
H'F748*
SEG4
SEG4
SEG3
SEG3
SEG2
SEG2 SEG1 SEG1
Internal driver
display area
SEG36 SEG36 SEG35 SEG35 SEG34 SEG34 SEG33 SEG33
SEG40 SEG40 SEG39 SEG39 SEG38 SEG38 SEG37 SEG37
External driver
display area
(when CKS3 = CKS1 = CKS0 = 0)
H'F75F* SEG128 SEG128 SEG127 SEG127 SEG126 SEG126 SEG125 SEG125
External driver
display area
H'F77F* SEG256 SEG256 SEG255 SEG255 SEG254 SEG254 SEG253 SEG253
COM 2 COM1 COM2 COM1 COM2 COM 1 COM 2 COM 1
Note: * Values immediately after reset.
Figure 13-9 LCD RAM Map 3: External Segment Expansion (1/2 Duty)
351
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33
Internal driver
display area
H'F740*
H'F744*
External driver
display area
(when CKS3 = CKS1 = CKS0 = 0)
H'F75F* SEG256 SEG255 SEG254 SEG253 SEG252 SEG251 SEG250 SEG249
External driver
display area
H'F77F* SEG512 SEG511 SEG510 SEG509 SEG508 SEG507 SEG506 SEG505
COM 1 COM 1 COM 1 COM 1 COM 1 COM 1 COM 1 COM 1
Note: * Values immediately after reset.
Figure 13-10 LCD RAM Map 4: External Segment Expansion (Static Duty)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H'F740*
SEG2 SEG2
SEG2 SEG2
SEG1
SEG1 SEG1 SEG1
External driver
display area
(when CKS3 = CKS1 = CKS0 = 0)
H'F75F*
SEG64 SEG64 SEG64 SEG64 SEG63 SEG63 SEG63 SEG63
External driver
display area
H'F77F* SEG128 SEG128 SEG128 SEG128 SEG127 SEG127 SEG127 SEG127
COM 4 COM3 COM 2 COM 1 COM4 COM 3 COM 2 COM 1
Note: * Values immediately after reset.
Figure 13-11 LCD RAM Map When All External Segments are Used
(Example: SGX = 1, SGS3 to SGS0 = 0000, 1/4 Duty)
352
1/3 bias; 1/4 duty or 1/3 duty
VCC
VCC
V1
V4
V1
V2
V3
V3
V2
VSS
GND
VEE
SHL
CL1
CL2
DI
This LSI
This LSI
This LSI
HD66100
HD66100
HD66100
SEG40 /CL1
SEG39 /CL2
SEG38 /DO
SEG37 /M
M
1/2 duty
VCC
V1
V2
VCC
V1
V4
V3
V2
GND
VEE
SHL
CL1
CL2
DI
V3
VSS
SEG40 /CL1
SEG39 /CL2
SEG38 /DO
SEG37 /M
M
Static
VCC
V1
V2
VCC
V1
V4
V3
V2
GND
VEE
SHL
CL1
CL2
DI
V3
VSS
SEG40 /CL1
SEG39 /CL2
SEG38 /DO
SEG37 /M
M
Figure 13-12 Connection to HD66100
353
1 frame
M
Data
V1
V2
V3
COM1
VSS
V1
V2
V3
VSS
COM2
COM3
COM4
SEGn
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
Figure 13-13 (a) Waveforms at 1/4 Duty
1 frame
M
Data
V1
V2
V3
COM1
VSS
V1
V2
V3
VSS
COM2
COM3
V1
V2
V3
VSS
V1
V2
V3
SEGn
VSS
Figure 13-13 (b) Waveforms at 1/3 Duty
354
1 frame
M
Data
V1
V2 , V3
VSS
COM1
V1
V2 , V3
VSS
COM2
SEGn
Figure 13-13 (c) Waveforms at 1/2 Duty
1 frame
M
Data
V1
COM1
VSS
V1
SEGn
VSS
Figure 13-13 (d) Waveforms at Static Duty
355
Table 13-3 Output Levels
Data
M
0
0
1
1
0
1
0
1
Static
Common output
Segment output
Common output
Segment output
Common output
Segment output
Common output
Segment output
V1
V1
V2, V3
V1
V3
V2
V3
V2
VSS
VSS
V2, V3
VSS
V2
V1
VSS
V1
VSS
V1
1/2 duty
1/3 duty
1/4 duty
VSS
V1
VSS
V1
VSS
V1
V3
VSS
V1
V2
VSS
V1
V3
VSS
13.3.4 Operation in Power-Down Modes
The LCD controller/driver can be operated in the low-power modes, as shown in table 13-4.
In the subactive, watch, and subsleep modes, the system clock pulse generator stops running, so
no clock signal will be supplied and the display will be stopped, unless ø or ø /2 was selected
W
W
when setting bits CKS3 to CKS0 in LCR. Since this may result in a direct current being applied
to the LCD panel, be sure to select ø or ø /2 as the clock if these modes are used. In active
W
W
(medium-speed) mode the system clock is changed, making it necessary to adjust the frame
frequency setting (in bits CKS3 to CKS0) to avoid a change in frame frequency.
Table 13-4 LCD Controller/Driver Operation in Power-Down Modes
Mode
Reset
Active Sleep
Watch
Subactive Subsleep Standby
Clock
ø
Running Running Running Stopped Stopped
Running Running Running Running Running
Stopped
Running
Stopped
On*3
Stopped
øW
Stopped*1
Stopped*2
Stopped*2
Display ACT = 0 Stopped Stopped Stopped Stopped Stopped
ACT = 1 Stopped On On
On*3 On*3
Notes: 1. The subclock pulse generator does not stop, but clock supply is stopped.
2. The LCD driver power supply resistive voltage divider is off regardless of bit PSW.
3. The display will not function unless øW or øW/2 is selected as the clock.
356
13.3.5 Boosting the LCD Driver Power Supply
When a large LCD panel is driven, or if segments are expanded externally, the built-in power
supply capacity may be insufficient, making it necessary to lower the power supply impedance.
One method, shown in figure 13-12, is to connect a bypass capacitor of around 0.1 µF to 0.3 µF to
pins V , V , and V . Another approach, shown in figure 13-14 below, is to connect a resistive
1
2
3
voltage divider externally.
VCC
R
R
R
R
V1
V2
V3
R = several kΩ
This LSI
VSS
C = 0.1 µF to 0.3 µF
Figure 13-14 Connecting an External Resistive Voltage Divider
357
Section 14 Electrical Characteristics
14.1 H8/3834U Series Absolute Maximum Ratings
Table 14-1 lists the absolute maximum ratings.
Table 14-1 Absolute Maximum Ratings
Item
Symbol
VCC
Value
Unit
V
Power supply voltage
Analog power supply voltage
Programming voltage
–0.3 to +7.0
–0.3 to +7.0
–0.3 to +13.0
–0.3 to VCC + 0.3
–0.3 to AVCC + 0.3
–20 to +75
AVCC
VPP
V
V
Input voltage
Ports other than ports B and C
Ports B and C
Vin
V
AVin
Topr
V
Operating temperature
Storage temperature
°C
°C
Tstg
–55 to +125
Note: Permanent damage may occur to the chip if maximum ratings are exceeded. Normal
operation should be under the conditions specified in Electrical Characteristics. Exceeding
these values can result in incorrect operation and reduced reliability.
359
14.2 H8/3833U and H8/3834U Electrical Characteristics
14.2.1 Power Supply Voltage and Operating Range
The power supply voltage and operating range of the H8/3833U and H8/3834U are indicated by
the shaded region in the figures below.
1. Power supply voltage vs. oscillator frequency range of H8/3833U and H8/3834U
10.0
32.768
5.0
2.0
2.7
4.0
5.5
2.7
4.0
5.5
VCC (V)
VCC (V)
• Active mode (high speed)
• Sleep mode
• All operating modes
360
2. Power supply voltage vs. clock frequency range of H8/3833U and H8/3834U
5.0
16.384
2.5
8.192
4.096
0.5
2.7
4.0
5.5
2.7
4.0
5.5
VCC (V)
VCC (V)
• Active mode (high speed)
• Sleep mode (except CPU)
• Subactive mode
• Subsleep mode (except CPU)
• Watch mode (except CPU)
625.0
500.0
312.5
62.5
2.7
4.0
5.5
VCC (V)
• Active mode (medium speed)
3. Analog power supply voltage vs. A/D converter operating range of H8/3833U and H8/3834U
5.0
625.0
500.0
2.5
0.5
312.5
62.5
2.7
4.0
5.5
2.7
4.0
5.5
AVCC (V)
AVCC (V)
• Active (high speed) mode
• Sleep mode
• Active (medium speed) mode
361
14.2.2 DC Characteristics
Table 14-2 lists the DC characteristics of the H8/3833U and H8/3834U.
Table 14-2 DC Characteristics of H8/3833U and H8/3834U
V
= 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C,
CC
CC
SS
SS
a
including subactive mode, unless otherwise indicated.
Item
Symbol Applicable Pins
Min
Typ Max
Unit Test Condition
Note
Input high VIH
voltage
RES, MD0,
0.8 VCC
—
VCC + 0.3
V
VCC = 4.0 V to 5.5 V
WKP0 to WKP7,
IRQ0 to IRQ4,
TMIB, TMIC, TMIF
CS, TMIG,
0.9 VCC
—
VCC + 0.3
SCK1, SCK2,
SCK3, ADTRG
UD, SI1, SI2, RXD 0.7 VCC
0.8 VCC
—
—
—
—
—
VCC + 0.3
VCC + 0.3
VCC + 0.3
VCC + 0.3
VCC + 0.3
V
V
V
VCC = 4.0 V to 5.5 V
VCC = 4.0 V to 5.5 V
VCC = 4.0 V to 5.5 V
OSC1
VCC – 0.5
VCC – 0.3
0.7 VCC
P10 to P17
P20 to P27
P30 to P37
P40 to P43
P50 to P57
P60 to P67
P70 to P77
P80 to P87
P90 to P97
PA0 to PA3
0.8 VCC
—
VCC + 0.3
PB0 to PB7
PC0 to PC3
0.7 VCC
0.8 VCC
–0.3
—
—
—
AVCC + 0.3
AVCC + 0.3
0.2 VCC
V
V
VCC = 4.0 V to 5.5 V
VCC = 4.0 V to 5.5 V
Input low
voltage
VIL
RES, MD0,
WKP0 to WKP7,
IRQ0 to IRQ4,
TMIB, TMIC, TMIF,
CS, TMIG,
–0.3
—
0.1 VCC
SCK1, SCK2,
SCK3, ADTRG
UD, SI1, SI2, RXD –0.3
–0.3
—
—
—
—
0.3 VCC
0.2 VCC
0.5
V
V
VCC = 4.0 V to 5.5 V
VCC = 4.0 V to 5.5 V
OSC1
–0.3
–0.3
0.3
Note: Connect pin TEST to VSS
.
362
Table 14-2 DC Characteristics of H8/3833U and H8/3834U (cont)
V
= 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C,
CC
CC
SS
SS
a
including subactive mode, unless otherwise indicated.
Item
Symbol Applicable Pins
Min
Typ Max
Unit Test Condition
Note
Input low
voltage
VIL
P10 to P17
P20 to P27
P30 to P37
P40 to P43
P50 to P57
P60 to P67
P70 to P77
P80 to P87
P90 to P97
PA0 to PA3
PB0 to PB7
PC0 to PC3
–0.3
—
0.3 VCC
V
VCC = 4.0 V to 5.5 V
–0.3
—
0.2 VCC
Output
high voltage
VOH
P10 to P17
P20 to P27
P30 to P37
P40 to P42
P50 to P57
P60 to P67
P70 to P77
P80 to P87
P90 to P97
PA0 to PA3
VCC – 1.0
VCC – 0.5
VCC – 0.5
—
—
—
—
—
—
V
VCC = 4.0 V to 5.5 V
–IOH = 1.0 mA
VCC = 4.0 V to 5.5 V
–IOH = 0.5 mA
–IOH = 0.1 mA
Output
low voltage
VOL
P10 to P17
P40 to P42
—
—
0.6
V
VCC = 4.0 V to 5.5 V
IOL = 1.6 mA
—
—
—
—
0.5
0.5
IOL = 0.4 mA
IOL = 0.4 mA
P50 to P57
P60 to P67
P70 to P77
P80 to P87
P90 to P97
PA0 to PA3
P20 to P27
P30 to P37
—
—
—
—
—
—
1.5
0.6
0.5
VCC = 4.0 V to 5.5 V
IOL = 10 mA
VCC = 4.0 V to 5.5 V
IOL = 1.6 mA
IOL = 0.4 mA
Note: Connect pin TEST to VSS
.
363
Table 14-2 DC Characteristics of H8/3833U and H8/3834U (cont)
= 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C,
V
CC
CC
SS
SS
a
including subactive mode, unless otherwise indicated.
Item
Symbol Applicable Pins
Min Typ Max Unit
Test Condition
Note
Input
leakage
current
|IIL|
RES, P43
—
—
—
—
—
—
20
1
µA
VIN = 0.5 V to
VCC – 0.5 V
2
1
OSC1, MD0
P10 to P17
P20 to P27
P30 to P37
P40 to P42
P50 to P57
P60 to P67
P70 to P77
P80 to P87
P90 to P97
PA0 to PA3
1
µA
VIN = 0.5 V to
VCC – 0.5 V
PB0 to PB7
PC0 to PC3
—
50
—
—
—
—
35
—
1
VIN = 0.5 V to
AVCC – 0.5 V
Pull-up
MOS
–IP
P10 to P17
P30 to P37
P50 to P57
P60 to P67
300 µA
VCC = 5 V,
VIN = 0 V
current
—
µA
pF
VCC = 2.7 V,
VIN = 0 V
Reference
value
Input
CIN
All input pins except
power supply, RES,
P43 pin
15
f = 1 MHz,
VIN = 0 V
Ta = 25°C
capacitance
RES
—
—
—
—
—
—
—
—
60
15
30
15
2
1
2
1
P43
Notes: 1. Applies to HD6433833U and HD6433834U.
2. Applies to HD6473834U.
364
Table 14-2 DC Characteristics of H8/3833U and H8/3834U (cont)
V
= 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C,
CC SS SS a
CC
including subactive mode, unless otherwise indicated.
Applicable
Item
Symbol Pins
Min Typ Max Unit Test Condition
Note
Active mode
current
dissipation
IOPE1
IOPE2
ISLEEP
VCC
VCC
VCC
—
—
—
12
2.5
5
24
mA Active mode (high speed),
VCC = 5 V, fosc = 10 MHz
1, 2
5
mA Active mode (medium speed), 1, 2
VCC = 5 V, fosc = 10 MHz
Sleep mode
current
10
mA VCC = 5 V, fosc = 10 MHz
1, 2
dissipation
Subactive mode ISUB
current
dissipation
VCC
—
—
—
—
—
2
50
40
40
—
—
—
130 µA
VCC = 2.7 V, LCD on,
32-kHz crystal oscillator
(øSUB = øw/2)
1, 2
—
90
6
µA
µA
µA
µA
V
VCC = 2.7 V, LCD on,
32-kHz crystal oscillator
(øSUB = øw/8)
Reference
value
1, 2
Subsleep mode ISUBSP
current
dissipation
VCC
VCC
VCC
VCC
VCC = 2.7 V, LCD on,
32-kHz crystal oscillator
(øSUB = øw/2)
1, 2
1, 2
1, 2
1, 2
Watch mode
current
IWATCH
VCC = 2.7 V, LCD not used,
32-kHz crystal oscillator
(øSUB = øw/8)
dissipation
Standby mode
current
ISTBY
5
32-kHz crystal oscillator
not used
dissipation
RAM data
VRAM
—
retaining voltage
Notes: 1. Pin states during current measurement
LCD
RES
Other Power
Mode
Pin
Internal State
Pins
Supply Oscillator Pins
Active mode
(high and medium
speed)
VCC Operates
VCC
Open
System clock oscillator: Crystal
Subclock oscillator: Pin X1 = VCC
Sleep mode
VCC Only timer operates
VCC
VCC
VCC
Open
Open
Open
Subactive mode VCC Operates
System clock oscillator: Crystal
Subclock oscillator: Crystal
Subsleep mode VCC Only timer operates,
CPU stops
Watch mode
VCC Only time-base clock VCC
operates, CPU stops
Open
Open
Standby mode
VCC CPU and timers all
stop
VCC
System clock oscillator: Crystal
Subclock oscillator: Pin X1 = VCC
2. Excludes current in pull-up MOS transistors and output buffers.
365
Table 14-2 DC Characteristics of H8/3833U and H8/3834U (cont)
= 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C,
V
CC
CC
SS
SS
a
including subactive mode, unless otherwise indicated.
Applicable
Item
Symbol Pins
Min Typ Max Unit Test Condition
Allowable output
low current (per pin)
IOL
Output pins except in
—
—
2
mA
mA
VCC = 4.0 V to 5.5 V
ports 2 and 3
Ports 2 and 3
All output pins
—
—
—
—
—
—
10
0.5
40
VCC = 4.0 V to 5.5 V
Allowable output
low current (total)
ΣIOL
Output pins except in
ports 2 and 3
VCC = 4.0 V to 5.5 V
VCC = 4.0 V to 5.5 V
Ports 2 and 3
All output pins
All output pins
—
—
—
—
—
—
—
—
—
—
—
—
80
20
2
Allowable output
high current (per pin)
–IOH
mA
mA
VCC = 4.0 V to 5.5 V
VCC = 4.0 V to 5.5 V
0.2
15
10
Allowable output
high current (total)
Σ–IOH
All output pins
366
14.2.3 AC Characteristics
Table 14-3 lists the control signal timing, and tables 14-4 and 14-5 list the serial interface timing
of the H8/3833U and H8/3834U.
Table 14-3 Control Signal Timing of H8/3833U and H8/3834U
V
= 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C,
CC SS SS a
CC
including subactive mode, unless otherwise specified.
Applicable
Symbol Pins
Reference
Figure
Item
Min Typ
Max Unit Test Condition
System clock
oscillation frequency
fOSC
tOSC
tcyc
OSC1, OSC2
2
—
—
—
—
—
—
10
5
MHz VCC = 4.0 V to 5.5 V
2
OSC clock (øOSC
cycle time
)
OSC1, OSC2 100
1000 ns
1000
VCC = 4.0 V to 5.5 V 1
200
2
Figure 14-1
1
System clock (ø)
cycle time
16
tOSC
—
2000 ns
Subclock oscillation
frequency
fW
X1, X2
X1, X2
—
32.768 —
kHz
Watch clock cycle time tW
—
2
30.5
—
—
8
µs
tW
Subclock (øSUB
)
tsubcyc
2
cycle time
Instruction cycle time
2
—
—
tcyc
tsubcyc
Oscillation stabilization trc
time (crystal oscillator)
OSC1, OSC2
—
—
—
—
—
—
40
60
2
ms
VCC = 4.0 V to 5.5 V
Oscillation stabilization trc
time
X1, X2
OSC1
s
External clock high
width
tCPH
40
80
40
80
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
—
—
15
20
15
20
—
ns
VCC = 4.0 V to 5.5 V Figure 14-1
VCC = 4.0 V to 5.5 V Figure 14-1
VCC = 4.0 V to 5.5 V Figure 14-1
VCC = 4.0 V to 5.5 V Figure 14-1
Figure 14-2
External clock low
width
tCPL
OSC1
ns
External clock rise time tCPr
ns
External clock fall time tCPf
ns
Pin RES low width
tREL
RES
tcyc
Notes: 1. A frequency between 1 MHz to 10 MHz is required when an external clock is input.
2. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2).
367
Table 14-3 Control Signal Timing of H8/3833U and H8/3834U (cont)
V
= 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C,
CC SS SS a
CC
including subactive mode, unless otherwise specified.
Applicable
Symbol Pins
Reference
Figure
Item
Min Typ
Max Unit Test Condition
Input pin high width
tIH IRQ0 to IRQ4
2
2
4
—
—
—
—
—
—
tcyc
tsubcyc
Figure 14-3
Figure 14-3
Figure 14-4
WKP0 to WKP7
ADTRG
TMIB, TMIC
TMIF, TMIG
Input pin low width
tIL
IRQ0 to IRQ4
WKP0 to WKP7
ADTRG
tcyc
tsubcyc
TMIB, TMIC
TMIF, TMIG
Pin UD minimum
modulation width
tUDH
tUDL
UD
tcyc
tsubcyc
Table 14-4 Serial Interface (SCI1, SCI2) Timing of H8/3833U and H8/3834U
V
= 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C, unless
CC SS SS a
CC
otherwise specified.
Applicable
Symbol Pins
Reference
Figure
Item
Min Typ
Max Unit Test Condition
Input serial clock
cycle time
tscyc
SCK1, SCK2
2
SCK1, SCK2 0.4
SCK1, SCK2 0.4
—
—
—
—
—
—
tcyc
tscyc
tscyc
ns
Figure 14-5
Input serial clock
high width
tSCKH
tSCKL
Figure 14-5
Input serial clock
low width
Figure 14-5
Input serial clock rise tSCKr
time
SCK1, SCK2
SCK1, SCK2
SO1, SO2
SI1, SI2
—
—
—
—
—
—
—
—
—
—
—
—
—
60
80
60
80
VCC = 4.0 V to 5.5 V Figure 14-5
—
Input serial clock fall tSCKf
time
—
ns
VCC = 4.0 V to 5.5 V Figure 14-5
VCC = 4.0 V to 5.5 V Figure 14-5
VCC = 4.0 V to 5.5 V Figure 14-5
VCC = 4.0 V to 5.5 V Figure 14-5
—
Serial output data
delay time
tSOD
—
200 ns
350
—
Serial input data
setup time
tSIS
200
400
200
400
2
—
—
—
—
—
—
ns
Serial input data
hold time
tSIH
SI1, SI2
ns
CS setup time
CS hold time
tCSS
tCSH
CS
CS
tcyc
tcyc
Figure 14-6
Figure 14-6
2
368
Table 14-5 Serial Interface (SCI3) Timing of H8/3833U and H8/3834U
= 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C, unless
V
CC
CC
SS
SS
a
otherwise specified.
Reference
Figure
Item
Symbol Min Typ Max Unit Test Condition
Input clock cycle Asynchronous
Synchronous
tscyc
4
—
—
—
—
—
—
—
—
—
—
—
0.6
1
tcyc
Figure 14-7
6
Input clock pulse width
tSCKW
tTXD
0.4
—
tscyc
tcyc
Figure 14-7
Transmit data delay time
(synchronous mode)
VCC = 4.0 V to 5.5 V Figure 14-8
—
1
Receive data setup time
(synchronous mode)
tRXS
200
400
200
400
—
—
—
—
ns
ns
VCC = 4.0 V to 5.5 V Figure 14-8
VCC = 4.0 V to 5.5 V Figure 14-8
Receive data hold time
(synchronous mode)
tRXH
369
14.2.4 A/D Converter Characteristics
Table 14-6 shows the A/D converter characteristics of the H8/3833U and H8/3834U.
Table 14-6 A/D Converter Characteristics of H8/3833U and H8/3834U
V
= 2.7 V to 5.5 V, AV = V = 0.0 V, T = –20°C to +75°C, unless otherwise specified.
SS SS a
CC
Applicable
Symbol Pins
Item
Min
Typ Max
Unit Test Condition
Note
Analog power
supply voltage
AVCC
AVCC
2.7
—
5.5
V
1
Analog input
voltage
AVIN
AN0 to AN11 –0.3
—
AVCC + 0.3
V
AIOPE
AVCC
—
—
—
1.5
—
mA AVCC = 5.0 V
µA
Analog power
supply current
AISTOP1 AVCC
150
2
Refere-
nce value
AISTOP2 AVCC
CAIN AN0 to AN11
—
—
—
—
5
µA
pF
3
Analog input
capacitance
30
Allowable signal RAIN
source
—
—
10
kΩ
impedance
Resolution
(data length)
—
—
—
—
—
—
—
—
8
bit
Non-linearity
error
±2.0
±0.5
±2.5
LSB
LSB
LSB
Quantization
error
Absolute
accuracy
Conversion time
12.4
24.8
—
—
124
124
µs
AVCC = 4.5 V to 5.5 V
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes while the A/D
converter is idle.
370
14.2.5 LCD Characteristics
Table 14-7 lists the LCD characteristics, and table 14-8 lists the AC characteristics for external
segment expansion of the H8/3833U and H8/3834U.
Table 14-7 LCD Characteristics of H8/3833U and H8/3834U
V
= 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C,
CC SS SS a
CC
including subactive mode, unless otherwise specified.
Applicable
Item
Symbol Pins
Min Typ Max Unit Test Condition
Note
Segment driver
voltage drop
VDS
SEG1 to
SEG40
—
—
50
—
0.6
V
ID = 2 µA
1
Common driver
voltage drop
VDC
RLCD
COM1 to
COM4
—
0.3
V
ID = 2 µA
1
LCD power supply
voltage divider
resistance
300 900 kΩ
Between V1 and
VSS
LCD power supply
voltage
VLCD
V1
2.7
—
VCC
V
2
Notes: 1. These are the voltage drops between the voltage supply pins V1, V2, V3 , and Vss, and the segment
pins or common pins.
2. When VLCD is supplied from an external source, the following relation must hold: VCC ≥ V1 ≥ V2 ≥
V3 ≥ VSS
Table 14-8 AC Characteristics for External Segment Expansion of H8/3833U and H8/3834U
V
= 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C,
CC SS SS a
CC
including subactive mode, unless otherwise specified.
Applicable
Symbol Pins
Reference
Figure
Item
Min Typ Max Unit Test Condition
Clock high width
Clock low width
Clock setup time
Data setup time
Data hold time
M delay time
tCWH
tCWL
tCSU
tSU
CL1, CL2
800
800
500
300
300
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
*
*
*
*
*
Figure 14-9
Figure 14-9
Figure 14-9
Figure 14-9
Figure 14-9
Figure 14-9
Figure 14-9
CL2
CL1, CL2
DO
tDH
DO
tDM
M
–1000 —
1000 ns
100 ns
Clock rise and fall
times
tCT
CL1, CL2
—
—
Note: * Value when the frame frequency is set to between 30.5 Hz and 488 Hz.
371
14.3 H8/3835U, H8/3836U, and H8/3837U Electrical Characteristics
14.3.1 Power Supply Voltage and Operating Range
The power supply voltage and operating range of the H8/3835U, H8/3836U, and H8/3837U are
indicated by the shaded region in the figures below.
1. Power supply voltage vs. oscillator frequency range of H8/3835U, H8/3836U, and H8/3837U
10.0
32.768
5.0
2.0
2.7
4.0
5.5
2.7
4.0
5.5
VCC (V)
VCC (V)
• Active mode (high speeds)
• Sleep mode
• All operating modes
372
2. Power supply voltage vs. clock frequency range of H8/3835U, H8/3836U, and H8/3837U
5.0
16.384
2.5
8.192
4.096
0.5
2.7
4.0
5.5
2.7
4.0
5.5
VCC (V)
VCC (V)
• Active mode (high speed)
• Sleep mode (except CPU)
• Subactive mode
• Subsleep mode (except CPU)
• Watch mode (except CPU)
625.0
500.0
312.5
62.5
2.7
4.0
5.5
VCC (V)
• Active mode (medium speed)
3. Analog power supply voltage vs. A/D converter operating range of H8/3835U, H8/3836U,
and H8/3837U
5.0
625.0
500.0
2.5
0.5
312.5
62.5
2.7
4.0
5.5
2.7
4.0
5.5
AVCC (V)
AVCC (V)
• Active (high speed) mode
• Sleep mode
• Active (medium speed) mode
373
14.3.2 DC Characteristics
Table 14-9 lists the DC characteristics of the H8/3835U, H8/3836U, and H8/3837U.
Table 14-9 DC Characteristics of H8/3835U, H8/3836U, and H8/3837U
V
= 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C,
CC
CC
SS
SS
a
including subactive mode, unless otherwise indicated.
Item
Symbol Applicable Pins
Min
Typ Max
Unit Test Condition
Note
Input high VIH
voltage
RES, MD0,
0.8 VCC
—
VCC + 0.3
V
VCC = 4.0 V to 5.5 V
WKP0 to WKP7,
IRQ0 to IRQ4,
TMIB, TMIC, TMIF
CS, TMIG,
0.9 VCC
—
VCC + 0.3
SCK1, SCK2,
SCK3, ADTRG
UD, SI1, SI2, RXD 0.7 VCC
0.8 VCC
—
—
VCC + 0.3
VCC + 0.3
VCC + 0.3
VCC + 0.3
VCC + 0.3
V
V
V
VCC = 4.0 V to 5.5 V
VCC = 4.0 V to 5.5 V
VCC = 4.0 V to 5.5 V
OSC1
VCC – 0.5 —
VCC – 0.3 —
P10 to P17
P20 to P27
P30 to P37
P40 to P43
P50 to P57
P60 to P67
P70 to P77
P80 to P87
P90 to P97
PA0 to PA3
0.7 VCC
—
0.8 VCC
—
VCC + 0.3
PB0 to PB7
PC0 to PC3
0.7 VCC
0.8 VCC
–0.3
—
—
—
AVCC + 0.3 V
AVCC + 0.3
VCC = 4.0 V to 5.5 V
VCC = 4.0 V to 5.5 V
Input low
voltage
VIL
RES, MD0,
0.2 VCC
V
WKP0 to WKP7,
IRQ0 to IRQ4,
TMIB, TMIC, TMIF,
CS, TMIG,
–0.3
—
0.1 VCC
SCK1, SCK2,
SCK3, ADTRG
UD, SI1, SI2, RXD –0.3
–0.3
—
—
—
—
0.3 VCC
0.2 VCC
0.5
V
V
VCC = 4.0 V to 5.5 V
VCC = 4.0 V to 5.5 V
OSC1
–0.3
–0.3
0.3
Note: Connect pin TEST to VSS
.
374
Table 14-9 DC Characteristics of H8/3835U, H8/3836U, and H8/3837U (cont)
V
= 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C,
CC
CC
SS
SS
a
including subactive mode, unless otherwise indicated.
Item
Symbol Applicable Pins
Min
Typ Max
Unit Test Condition
Note
Input low
voltage
VIL
P10 to P17
P20 to P27
P30 to P37
P40 to P43
P50 to P57
P60 to P67
P70 to P77
P80 to P87
P90 to P97
PA0 to PA3
PB0 to PB7
PC0 to PC3
–0.3
—
0.3 VCC
V
VCC = 4.0 V to 5.5 V
–0.3
—
0.2 VCC
Output
high voltage
VOH
P10 to P17
P20 to P27
P30 to P37
P40 to P42
P50 to P57
P60 to P67
P70 to P77
P80 to P87
P90 to P97
PA0 to PA3
VCC – 1.0 —
VCC – 0.5 —
VCC – 0.5 —
—
—
—
V
VCC = 4.0 V to 5.5 V
–IOH = 1.0 mA
VCC = 4.0 V to 5.5 V
–IOH = 0.5 mA
–IOH = 0.1 mA
Output
low voltage
VOL
P10 to P17
P40 to P42
—
—
0.6
V
VCC = 4.0 V to 5.5 V
IOL = 1.6 mA
—
—
—
—
0.5
0.5
IOL = 0.4 mA
IOL = 0.4 mA
P50 to P57
P60 to P67
P70 to P77
P80 to P87
P90 to P97
PA0 to PA3
P20 to P27
P30 to P37
—
—
—
—
—
—
1.5
0.6
0.5
VCC = 4.0 V to 5.5 V
IOL = 10 mA
VCC = 4.0 V to 5.5 V
IOL = 1.6 mA
IOL = 0.4 mA
Note: Connect pin TEST to VSS
.
375
Table 14-9 DC Characteristics of H8/3835U, H8/3836U, and H8/3837U (cont)
= 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C,
V
CC
CC
SS
SS
a
including subactive mode, unless otherwise indicated.
Item
Symbol Applicable Pins
Min Typ Max Unit
Test Condition
Note
Input
leakage
current
|IIL|
RES, P43
—
—
—
—
—
—
20
1
µA
VIN = 0.5 V to
VCC – 0.5 V
2
1
OSC1, MD0
P10 to P17
P20 to P27
P30 to P37
P40 to P42
P50 to P57
P60 to P67
P70 to P77
P80 to P87
P90 to P97
PA0 to PA3
1
µA
VIN = 0.5 V to
VCC – 0.5 V
PB0 to PB7
PC0 to PC3
—
50
—
—
—
—
35
—
1
VIN = 0.5 V to
AVCC – 0.5 V
Pull-up
MOS
–IP
P10 to P17
P30 to P37
P50 to P57
P60 to P67
300 µA
VCC = 5 V,
VIN = 0 V
current
—
µA
pF
VCC = 2.7 V,
VIN = 0 V
Reference
value
Input
CIN
All input pins except
power supply, RES
P43 pin
15
f = 1 MHz,
VIN = 0 V
Ta = 25°C
capacitance
RES
—
—
—
—
—
—
—
—
60
15
30
15
2
1
2
1
P43
Notes: 1. Applies to HD6433835U, HD6433836U, and HD6433837U.
2. Applies to HD6473837U.
376
Table 14-9 DC Characteristics of H8/3835U, H8/3836U, and H8/3837U (cont)
V
= 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C,
CC SS SS a
CC
including subactive mode, unless otherwise indicated.
Applicable
Item
Symbol Pins
Min Typ Max Unit Test Condition
Note
Active mode
current
dissipation
IOPE1
IOPE2
ISLEEP
VCC
VCC
VCC
—
—
—
13.5 24.0 mA Active mode (high speed),
VCC = 5 V, fosc = 10 MHz
1, 2
2.5 5.0
mA Active mode (medium speed), 1, 2
VCC = 5 V, fosc = 10 MHz
Sleep mode
current
5.0 10.0 mA VCC = 5 V, fosc = 10 MHz
1, 2
dissipation
Subactive mode ISUB
current
dissipation
VCC
—
—
—
—
—
2
50.0 130.0 µA VCC = 2.7 V, LCD on,
32-kHz crystal oscillator
(øSUB = øw/2)
1, 2
40.0 —
µA VCC = 2.7 V, LCD on,
32-kHz crystal oscillator
(øSUB = øw/8)
Reference
value
1, 2
Subsleep mode ISUBSP
current
dissipation
VCC
VCC
VCC
VCC
40.0 90.0 µA VCC = 2.7 V, LCD on,
32-kHz crystal oscillator
(øSUB = øw/2)
1, 2
1, 2
1, 2
1, 2
Watch mode
current
IWATCH
—
—
—
6
µA VCC = 2.7 V, LCD not used,
32-kHz crystal oscillator
(øSUB = øw/8)
dissipation
Standby mode
current
ISTBY
5
µA 32-kHz crystal oscillator
not used
dissipation
RAM data
VRAM
—
V
retaining voltage
Notes: 1. Pin states during current measurement
LCD
RES
Other Power
Mode
Pin
Internal State
Pins
Supply Oscillator Pins
Active mode
(high and medium
speed)
VCC Operates
VCC
Open
System clock oscillator: Crystal
Subclock oscillator: Pin X1 = VCC
Sleep mode
VCC Only timer operates
VCC
VCC
VCC
Open
Open
Open
Subactive mode VCC Operates
System clock oscillator: Crystal
Subclock oscillator: Crystal
Subsleep mode VCC Only timer operates,
CPU stops
Watch mode
VCC Only time-base clock VCC
operates, CPU stops
Open
Open
Standby mode
VCC CPU and timers all
stop
VCC
System clock oscillator: Crystal
Subclock oscillator: Pin X1 = VCC
2. Excludes current in pull-up MOS transistors and output buffers.
377
Table 14-9 DC Characteristics of H8/3835U, H8/3836U, and H8/3837U (cont)
= 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C,
V
CC
CC
SS
SS
a
including subactive mode, unless otherwise indicated.
Applicable
Item
Symbol Pins
Min Typ Max Unit Test Condition
Allowable output
low current (per pin)
IOL
Output pins except in
—
—
2
mA
mA
VCC = 4.0 V to 5.5 V
ports 2 and 3
Ports 2 and 3
All output pins
—
—
—
—
—
—
10
0.5
40
VCC = 4.0 V to 5.5 V
Allowable output
low current (total)
ΣIOL
Output pins except in
ports 2 and 3
VCC = 4.0 V to 5.5 V
VCC = 4.0 V to 5.5 V
Ports 2 and 3
All output pins
All output pins
—
—
—
—
—
—
—
—
—
—
—
—
80
20
2
Allowable output
high current (per pin)
–IOH
mA
mA
VCC = 4.0 V to 5.5 V
VCC = 4.0 V to 5.5 V
0.2
15
10
Allowable output
high current (total)
Σ–IOH
All output pins
378
14.3.3 AC Characteristics
Table 14-10 lists the control signal timing, and tables 14-11 and 14-12 list the serial interface
timing of the H8/3835U, H8/3836U, and H8/3837U.
Table 14-10 Control Signal Timing of H8/3835U, H8/3836U, and H8/3837U
V
= 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C,
CC SS SS a
CC
including subactive mode, unless otherwise specified.
Applicable
Symbol Pins
Reference
Figure
Item
Min Typ
Max Unit Test Condition
System clock
oscillation frequency
fOSC
tOSC
tcyc
OSC1, OSC2
2
—
—
—
—
—
—
10
5
MHz VCC = 4.0 V to 5.5 V
2
OSC clock (øOSC
cycle time
)
OSC1, OSC2 100
1000 ns
1000
VCC = 4.0 V to 5.5 V 1
200
2
Figure 14-1
1
System clock (ø)
cycle time
16
tOSC
—
2000 ns
Subclock oscillation
frequency
fW
X1, X2
X1, X2
—
—
2
32.768 —
kHz
Watch clock (øW)
cycle time
tW
30.5
—
—
8
µs
Subclock (øSUB
)
tsubcyc
tW
2
cycle time
Instruction cycle time
2
—
—
tcyc
tsubcyc
Oscillation stabilization
time (crystal oscillator)
trc
OSC1, OSC2
—
—
—
—
—
—
40
60
2
ms
VCC = 4.0 V to 5.5 V
Oscillation stabilization trc
time
X1, X2
OSC1
s
External clock high
width
tCPH
40
80
40
80
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
—
—
15
20
15
20
—
ns
VCC = 4.0 V to 5.5 V Figure 14-1
VCC = 4.0 V to 5.5 V Figure 14-1
VCC = 4.0 V to 5.5 V Figure 14-1
VCC = 4.0 V to 5.5 V Figure 14-1
Figure 14-2
External clock low
width
tCPL
OSC1
ns
External clock rise time tCPr
External clock fall time tCPf
ns
ns
Pin RES low width
tREL
RES
tcyc
Notes: 1. A frequency between 1 MHz to 10 MHz is required when an external clock is input.
2. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2).
379
Table 14-10 Control Signal Timing of H8/3835U, H8/3836U, and H8/3837U (cont)
V
= 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C,
CC SS SS a
CC
including subactive mode, unless otherwise specified.
Applicable
Symbol Pins
Reference
Figure
Item
Min Typ
Max Unit Test Condition
Input pin high width
tIH IRQ0 to IRQ4
2
2
4
—
—
—
—
—
—
tcyc
tsubcyc
Figure 14-3
Figure 14-3
Figure 14-4
WKP0 to WKP7
ADTRG
TMIB, TMIC
TMIF, TMIG
Input pin low width
tIL
IRQ0 to IRQ4
WKP0 to WKP7
ADTRG
tcyc
tsubcyc
TMIB, TMIC
TMIF, TMIG
Pin UD minimum
modulation width
tUDH
tUDL
UD
tcyc
tsubcyc
Table 14-11 Serial Interface (SCI1, SCI2) Timing of H8/3835U, H8/3836U, and H8/3837U
V
= 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C, unless
CC SS SS a
CC
otherwise specified.
Applicable
Symbol Pins
Reference
Figure
Item
Min Typ
Max Unit Test Condition
Input serial clock
cycle time
tscyc
SCK1, SCK2
2
SCK1, SCK2 0.4
SCK1, SCK2 0.4
—
—
—
—
—
—
tcyc
tscyc
tscyc
ns
Figure 14-5
Input serial clock
high width
tSCKH
tSCKL
Figure 14-5
Input serial clock
low width
Figure 14-5
Input serial clock rise tSCKr
time
SCK1, SCK2
SCK1, SCK2
SO1, SO2
SI1, SI2
—
—
—
—
—
—
—
—
—
—
—
—
—
60
80
60
80
VCC = 4.0 V to 5.5 V Figure 14-5
—
Input serial clock fall tSCKf
time
—
ns
VCC = 4.0 V to 5.5 V Figure 14-5
VCC = 4.0 V to 5.5 V Figure 14-5
VCC = 4.0 V to 5.5 V Figure 14-5
VCC = 4.0 V to 5.5 V Figure 14-5
—
Serial output data
delay time
tSOD
—
200 ns
350
—
Serial input data
setup time
tSIS
200
400
200
400
2
—
—
—
—
—
—
ns
Serial input data
hold time
tSIH
SI1, SI2
ns
CS setup time
CS hold time
tCSS
tCSH
CS
CS
tcyc
tcyc
Figure 14-6
Figure 14-6
2
380
Table 14-12 Serial Interface (SCI3) Timing of H8/3835U, H8/3836U, and H8/3837U
= 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C, unless
V
CC
CC
SS
SS
a
otherwise specified.
Reference
Figure
Item
Symbol Min Typ Max Unit Test Condition
Input clock cycle Asynchronous
Synchronous
tscyc
4
—
—
—
—
—
—
—
—
—
—
—
0.6
1
tcyc
Figure 14-7
6
Input clock pulse width
tSCKW
tTXD
0.4
—
tscyc
tcyc
Figure 14-7
Transmit data delay time
(synchronous mode)
VCC = 4.0 V to 5.5 V Figure 14-8
—
1
Receive data setup time
(synchronous mode)
tRXS
200
400
200
400
—
—
—
—
ns
ns
VCC = 4.0 V to 5.5 V Figure 14-8
VCC = 4.0 V to 5.5 V Figure 14-8
Receive data hold time
(synchronous mode)
tRXH
381
14.3.4 A/D Converter Characteristics
Table 14-13 shows the A/D converter characteristics of the H8/3835U, H8/3836U, and H8/3837U.
Table 14-13 A/D Converter Characteristics of H8/3835U, H8/3836U, and H8/3837U
V
= 2.7 V to 5.5 V, AV = V = 0.0 V, T = –20°C to +75°C, unless otherwise specified.
SS SS a
CC
Applicable
Symbol Pins
Item
Min
Typ Max
Unit Test Condition
Note
Analog power
supply voltage
AVCC
AVCC
2.7
—
5.5
V
1
Analog input
voltage
AVIN
AN0 to AN11 AVSS – 0.3 —
AVCC + 0.3
V
Analog power
supply current
AIOPE
AVCC
—
—
—
1.5
—
mA AVCC = 5.0 V
µA
AISTOP1 AVCC
150
2
Refere-
nce value
AISTOP2 AVCC
CAIN AN0 to AN11
—
—
—
—
5
µA
pF
3
Analog input
capacitance
30
Allowable signal RAIN
source
—
—
10
kΩ
impedance
Resolution
(data length)
—
—
—
—
—
—
—
—
8
bit
Non-linearity
error
±2.0
±0.5
±2.5
LSB
LSB
LSB
Quantization
error
Absolute
accuracy
Conversion time
12.4
24.8
—
—
124
124
µs
AVCC = 4.5 V to 5.5 V
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes while the A/D
converter is idle.
382
14.3.5 LCD Characteristics
Table 14-14 lists the LCD characteristics, and table 14-15 lists the AC characteristics for external
segment expansion of the H8/3835U, H8/3836U, and H8/3837U.
Table 14-14 LCD Characteristics of H8/3835U, H8/3836U, and H8/3837U
V
= 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C,
CC SS SS a
CC
including subactive mode, unless otherwise specified.
Applicable
Item
Symbol Pins
Min Typ Max Unit Test Condition
Note
Segment driver
voltage drop
VDS
SEG1 to
SEG40
—
—
50
—
0.6
V
ID = 2 µA
1
Common driver
voltage drop
VDC
RLCD
COM1 to
COM4
—
0.3
V
ID = 2 µA
1
LCD power supply
voltage divider
resistance
300 900 kΩ
Between V1 and
VSS
LCD power supply
voltage
VLCD
V1
2.7
—
VCC
V
2
Notes: 1. These are the voltage drops between the voltage supply pins V1, V2, V3 , and Vss, and the segment
pins or common pins.
2. When VLCD is supplied from an external source, the following relation must hold: VCC ≥ V1 ≥ V2 ≥
V3 ≥ VSS
Table 14-15 AC Characteristics for External Segment Expansion of H8/3835U, H8/3836U,
and H8/3837U
V
= 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = AV = 0.0 V, T = –20°C to +75°C,
CC SS SS a
CC
including subactive mode, unless otherwise specified.
Applicable
Symbol Pins
Reference
Figure
Item
Min Typ Max Unit Test Condition
Clock high width
Clock low width
Clock setup time
Data setup time
Data hold time
M delay time
tCWH
tCWL
tCSU
tSU
CL1, CL2
800
800
500
300
300
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
*
*
*
*
*
Figure 14-9
Figure 14-9
Figure 14-9
Figure 14-9
Figure 14-9
Figure 14-9
Figure 14-9
CL2
CL1, CL2
DO
tDH
DO
tDM
M
–1000 —
1000 ns
100 ns
Clock rise and fall
times
tCT
CL1, CL2
—
—
Note: * Value when the frame frequency is set to between 30.5 Hz and 488 Hz.
383
14.4 Operation Timing
Figures 14-1 to 14-10 show timing diagrams.
tOSC
V
IH
OSC1
V
IL
tCPH
tCPr
tCPL
tCPf
Figure 14-1 System Clock Input Timing
RES
V
IL
tREL
Figure 14-2 RES Low Width
IRQ0 to IRQ4
WKP0 to WKP7
ADTRG
V
IH
TMIB, TMIC
TMIF, TMIG
V
IL
tIL
tIH
Figure 14-3 Input Timing
384
V
IH
UD
V
IL
tUDL
tUDH
Figure 14-4 Minimum UD High and Low Width
385
tscyc
VIH or VOH
*
SCK1
SCK2
VIL or VOL
*
tSCKL
tSCKH
tSCKr
tSCKf
tSOD
VOH
*
SO1
SO2
VOL
*
tSIS
tSIH
SI1
SI2
Notes: * Output timing reference levels
Output high: VOH = 2.0 V
Output low: VOL = 0.8 V
Load conditions are shown in figure 14-10.
Figure 14-5 Serial Interface 1 and 2 Input/Output Timing
386
VIH
CS
VIL
tCSS
tCSH
VIH
SCK2
VIL
Figure 14-6 Serial Interface 2 Chip Select Timing
tSCKW
SCK3
tscyc
Figure 14-7 SCK Input Clock Timing
3
387
tscyc
VIH or VOH
*
SCK3
TXD
VIL or VOL
*
tTXD
VOH
VOL
*
*
(transmit data)
tRXS tRXH
TXD
(receive data)
Notes: * Output timing reference levels
Output high: VOH= 2.0 V
Output low: VOL = 0.8 V
Load conditions are shown in figure 14-10.
Figure 14-8 Input/Output Timing of Serial Interface 3 in Synchronous Mode
tCT
VCC – 0.5 V
CL
1
2
0.4 V
tCWH
tCWH
tCSU
VCC– 0.5 V
CL
DO
M
0.4 V
tCSU
tCWL
tCT
VCC – 0.5 V
0.4 V
tSU
tDH
0.4 V
tDM
Figure 14-9 Segment Expansion Signal Timing
388
14.5 Output Load Circuit
VCC
2.4 kΩ
Output pin
30 pF
12 kΩ
Figure 14-10 Output Load Condition
389
Appendix A CPU Instruction Set
A.1 Instructions
Operation Notation
Rd8/16
General register (destination) (8 or 16 bits)
General register (source) (8 or 16 bits)
General register (8 or 16 bits)
Condition code register
N (negative) flag in CCR
Z (zero) flag in CCR
V (overflow) flag in CCR
C (carry) flag in CCR
Program counter
Rs8/16
Rn8/16
CCR
N
Z
V
C
PC
SP
Stack pointer
#xx: 3/8/16
Immediate data (3, 8, or 16 bits)
Displacement (8 or 16 bits)
Absolute address (8 or 16 bits)
Addition
d: 8/16
@aa: 8/16
+
–
×
÷
Subtraction
Multiplication
Division
Logical AND
Logical OR
Exclusive logical OR
Move
→
—
Logical complement
Condition Code Notation
Symbol
↕
*
Modified according to the instruction result
Not fixed (value not guaranteed)
Always cleared to 0
0
—
Not affected by the instruction execution result
391
Table A-1 lists the H8/300L CPU instruction set.
Table A-1 Instruction Set
Addressing Mode/
Instruction Length (bytes)
Condition Code
H N Z V C
Mnemonic
Operation
I
MOV.B #xx:8, Rd
MOV.B Rs, Rd
B
B
B
B
B
#xx:8 → Rd8
2
2
2
4
2
— — ↕ ↕ 0 — 2
— — ↕ ↕ 0 — 2
— — ↕ ↕ 0 — 4
— — ↕ ↕ 0 — 6
— — ↕ ↕ 0 — 6
Rs8 → Rd8
MOV.B @Rs, Rd
MOV.B @(d:16, Rs), Rd
MOV.B @Rs+, Rd
@Rs16 → Rd8
@(d:16, Rs16)→ Rd8
@Rs16 → Rd8
Rs16+1 → Rs16
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B Rs, @Rd
B
B
B
B
B
@aa:8 → Rd8
2
— — ↕ ↕ 0 — 4
— — ↕ ↕ 0 — 6
— — ↕ ↕ 0 — 4
— — ↕ ↕ 0 — 6
— — ↕ ↕ 0 — 6
@aa:16 → Rd8
Rs8 → @Rd16
4
2
4
2
MOV.B Rs, @(d:16, Rd)
MOV.B Rs, @–Rd
Rs8 → @(d:16, Rd16)
Rd16–1 → Rd16
Rs8 → @Rd16
MOV.B Rs, @aa:8
MOV.B Rs, @aa:16
MOV.W #xx:16, Rd
MOV.W Rs, Rd
B
B
Rs8 → @aa:8
2
— — ↕ ↕ 0 — 4
— — ↕ ↕ 0 — 6
— — ↕ ↕ 0 — 4
— — ↕ ↕ 0 — 2
— — ↕ ↕ 0 — 4
— — ↕ ↕ 0 — 6
— — ↕ ↕ 0 — 6
Rs8 → @aa:16
#xx:16 → Rd
4
W
W
W
W
W
4
2
2
4
2
Rs16 → Rd16
MOV.W @Rs, Rd
MOV.W @(d:16, Rs), Rd
MOV.W @Rs+, Rd
@Rs16 → Rd16
@(d:16, Rs16) → Rd16
@Rs16 → Rd16
Rs16+2 → Rs16
MOV.W @aa:16, Rd
MOV.W Rs, @Rd
W
W
W
W
@aa:16 → Rd16
4
— — ↕ ↕ 0 — 6
— — ↕ ↕ 0 — 4
— — ↕ ↕ 0 — 6
— — ↕ ↕ 0 — 6
Rs16 → @Rd16
2
4
2
MOV.W Rs, @(d:16, Rd)
MOV.W Rs, @–Rd
Rs16 → @(d:16, Rd16)
Rd16–2 → Rd16
Rs16 → @Rd16
MOV.W Rs, @aa:16
POP Rd
W
W
Rs16 → @aa:16
4
2
— — ↕ ↕ 0 — 6
— — ↕ ↕ 0 — 6
@SP → Rd16
SP+2 → SP
PUSH Rs
W
SP–2 → SP
2
— — ↕ ↕ 0 — 6
Rs16 → @SP
392
Table A-1 Instruction Set (cont)
Addressing Mode/
Instruction Length (bytes)
Condition Code
H N
4 — — — — — — ➃
Mnemonic
Operation
I
Z V C
EEPMOV
— if R4L≠0 then
Repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4L–1 → R4L
Until R4L=0
else next;
ADD.B #xx:8, Rd
ADD.B Rs, Rd
ADD.W Rs, Rd
ADDX.B #xx:8, Rd
ADDX.B Rs, Rd
ADDS.W #1, Rd
ADDS.W #2, Rd
INC.B Rd
B
B
Rd8+#xx:8 → Rd8
Rd8+Rs8 → Rd8
Rd16+Rs16 → Rd16
Rd8+#xx:8 +C → Rd8
Rd8+Rs8 +C → Rd8
Rd16+1 → Rd16
Rd16+2 → Rd16
Rd8+1 → Rd8
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
—
—
↕ ↕ ↕ ↕ ↕ 2
↕ ↕ ↕ ↕ ↕ 2
W
B
— ➀ ↕ ↕ ↕ ↕ 2
—
—
↕ ↕ ➁ ↕ ↕ 2
↕ ↕ ➁ ↕ ↕ 2
B
W
W
B
— — — — — — 2
— — — — — — 2
— — ↕ ↕ ↕ — 2
DAA.B Rd
B
Rd8 decimal adjust → Rd8
Rd8–Rs8 → Rd8
Rd16–Rs16 → Rd16
Rd8–#xx:8 –C → Rd8
Rd8–Rs8 –C → Rd8
Rd16–1 → Rd16
Rd16–2 → Rd16
Rd8–1 → Rd8
—
—
*
↕ ↕ * ➂ 2
SUB.B Rs, Rd
SUB.W Rs, Rd
SUBX.B #xx:8, Rd
SUBX.B Rs, Rd
SUBS.W #1, Rd
SUBS.W #2, Rd
DEC.B Rd
B
↕ ↕ ↕ ↕ ↕ 2
W
B
— ➀ ↕ ↕ ↕ ↕ 2
—
—
↕ ↕ ➁ ↕ ↕ 2
↕ ↕ ➁ ↕ ↕ 2
B
W
W
B
— — — — — — 2
— — — — — — 2
— — ↕ ↕ ↕ — 2
DAS.B Rd
B
Rd8 decimal adjust → Rd8
0–Rd → Rd
—
—
—
—
*
↕ ↕ * — 2
NEG.B Rd
B
↕ ↕ ↕ ↕ ↕ 2
↕ ↕ ↕ ↕ ↕ 2
↕ ↕ ↕ ↕ ↕ 2
CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W Rs, Rd
B
Rd8–#xx:8
B
Rd8–Rs8
W
Rd16–Rs16
— ➀ ↕ ↕ ↕ ↕ 2
393
Table A-1 Instruction Set (cont)
Addressing Mode/
Instruction Length (bytes)
Condition Code
H N Z V C
Mnemonic
Operation
I
MULXU.B Rs, Rd
DIVXU.B Rs, Rd
B
B
Rd8 × Rs8 → Rd16
2
2
— — — — — — 14
Rd16÷Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
— — ➄ ➅ — — 14
AND.B #xx:8, Rd
AND.B Rs, Rd
OR.B #xx:8, Rd
OR.B Rs, Rd
XOR.B #xx:8, Rd
XOR.B Rs, Rd
NOT.B Rd
B
B
B
B
B
B
B
B
Rd8 #xx:8 → Rd8
Rd8 Rs8 → Rd8
Rd8 #xx:8 → Rd8
Rd8 Rs8 → Rd8
Rd8 #xx:8 → Rd8
Rd8 Rs8 → Rd8
Rd → Rd
2
2
2
2
2
2
2
2
— — ↕ ↕ 0 — 2
— — ↕ ↕ 0 — 2
— — ↕ ↕ 0 — 2
— — ↕ ↕ 0 — 2
— — ↕ ↕ 0 — 2
— — ↕ ↕ 0 — 2
— — ↕ ↕ 0 — 2
— — ↕ ↕ ↕ ↕ 2
SHAL.B Rd
C
0
b7
b0
SHAR.B Rd
SHLL.B Rd
SHLR.B Rd
ROTXL.B Rd
ROTXR.B Rd
B
B
B
B
B
2
2
2
2
2
— — ↕ ↕ 0 ↕ 2
— — ↕ ↕ 0 ↕ 2
— — 0 ↕ 0 ↕ 2
— — ↕ ↕ 0 ↕ 2
— — ↕ ↕ 0 ↕ 2
C
b7
b0
C
0
b7
b0
0
C
b7
b0
C
b7
b0
b7
b0
C
394
Table A-1 Instruction Set (cont)
Addressing Mode/
Instruction Length (bytes)
Condition Code
H N Z V C
Mnemonic
Operation
I
ROTL.B Rd
B
B
2
2
— — ↕ ↕ 0 ↕ 2
C
b7
b0
ROTR.B Rd
— — ↕ ↕ 0 ↕ 2
C
b7
b0
BSET #xx:3, Rd
BSET #xx:3, @Rd
BSET #xx:3, @aa:8
BSET Rn, Rd
B
B
B
B
B
B
B
B
B
B
B
B
B
(#xx:3 of Rd8) ← 1
2
4
4
2
4
4
2
4
4
2
4
4
2
— — — — — — 2
— — — — — — 8
— — — — — — 8
— — — — — — 2
— — — — — — 8
— — — — — — 8
— — — — — — 2
— — — — — — 8
— — — — — — 8
— — — — — — 2
— — — — — — 8
— — — — — — 8
— — — — — — 2
(#xx:3 of @Rd16) ← 1
(#xx:3 of @aa:8) ← 1
(Rn8 of Rd8) ← 1
BSET Rn, @Rd
BSET Rn, @aa:8
BCLR #xx:3, Rd
BCLR #xx:3, @Rd
BCLR #xx:3, @aa:8
BCLR Rn, Rd
(Rn8 of @Rd16) ← 1
(Rn8 of @aa:8) ← 1
(#xx:3 of Rd8) ← 0
(#xx:3 of @Rd16) ← 0
(#xx:3 of @aa:8) ← 0
(Rn8 of Rd8) ← 0
BCLR Rn, @Rd
BCLR Rn, @aa:8
BNOT #xx:3, Rd
(Rn8 of @Rd16) ← 0
(Rn8 of @aa:8) ← 0
(#xx:3 of Rd8) ←
(#xx:3 of Rd8)
BNOT #xx:3, @Rd
BNOT #xx:3, @aa:8
BNOT Rn, Rd
B
B
B
B
B
(#xx:3 of @Rd16) ←
(#xx:3 of @Rd16)
4
— — — — — — 8
— — — — — — 8
— — — — — — 2
— — — — — — 8
— — — — — — 8
(#xx:3 of @aa:8) ←
(#xx:3 of @aa:8)
4
(Rn8 of Rd8) ←
(Rn8 of Rd8)
2
4
4
BNOT Rn, @Rd
BNOT Rn, @aa:8
(Rn8 of @Rd16) ←
(Rn8 of @Rd16)
(Rn8 of @aa:8) ←
(Rn8 of @aa:8)
395
Table A-1 Instruction Set (cont)
Addressing Mode/
Instruction Length (bytes)
Condition Code
H N Z V C
Mnemonic
Operation
I
BTST #xx:3, Rd
BTST #xx:3, @Rd
BTST #xx:3, @aa:8
BTST Rn, Rd
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
(#xx:3 of Rd8) → Z
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
4
2
4
— — — ↕ — — 2
— — — ↕ — — 6
— — — ↕ — — 6
— — — ↕ — — 2
— — — ↕ — — 6
— — — ↕ — — 6
— — — — — ↕ 2
— — — — — ↕ 6
— — — — — ↕ 6
— — — — — ↕ 2
— — — — — ↕ 6
— — — — — ↕ 6
— — — — — — 2
— — — — — — 8
— — — — — — 8
— — — — — — 2
— — — — — — 8
— — — — — — 8
— — — — — ↕ 2
— — — — — ↕ 6
— — — — — ↕ 6
— — — — — ↕ 2
— — — — — ↕ 6
— — — — — ↕ 6
— — — — — ↕ 2
— — — — — ↕ 6
— — — — — ↕ 6
— — — — — ↕ 2
— — — — — ↕ 6
(#xx:3 of @Rd16) → Z
(#xx:3 of @aa:8) → Z
(Rn8 of Rd8) → Z
BTST Rn, @Rd
BTST Rn, @aa:8
BLD #xx:3, Rd
(Rn8 of @Rd16) → Z
(Rn8 of @aa:8) → Z
(#xx:3 of Rd8) → C
BLD #xx:3, @Rd
BLD #xx:3, @aa:8
BILD #xx:3, Rd
(#xx:3 of @Rd16) → C
(#xx:3 of @aa:8) → C
(#xx:3 of Rd8) → C
BILD #xx:3, @Rd
BILD #xx:3, @aa:8
BST #xx:3, Rd
(#xx:3 of @Rd16) → C
(#xx:3 of @aa:8) → C
C → (#xx:3 of Rd8)
BST #xx:3, @Rd
BST #xx:3, @aa:8
BIST #xx:3, Rd
C → (#xx:3 of @Rd16)
C → (#xx:3 of @aa:8)
C → (#xx:3 of Rd8)
BIST #xx:3, @Rd
BIST #xx:3, @aa:8
BAND #xx:3, Rd
BAND #xx:3, @Rd
BAND #xx:3, @aa:8
BIAND #xx:3, Rd
BIAND #xx:3, @Rd
BIAND #xx:3, @aa:8
BOR #xx:3, Rd
C → (#xx:3 of @Rd16)
C → (#xx:3 of @aa:8)
C (#xx:3 of Rd8) → C
C (#xx:3 of @Rd16) → C
C (#xx:3 of @aa:8) → C
C (#xx:3 of Rd8) → C
C (#xx:3 of @Rd16) → C
C (#xx:3 of @aa:8) → C
C (#xx:3 of Rd8) → C
C (#xx:3 of @Rd16) → C
C (#xx:3 of @aa:8) → C
C (#xx:3 of Rd8) → C
C (#xx:3 of @Rd16) → C
BOR #xx:3, @Rd
BOR #xx:3, @aa:8
BIOR #xx:3, Rd
BIOR #xx:3, @Rd
396
Table A-1 Instruction Set (cont)
Addressing Mode/
Instruction Length (bytes)
Condition Code
H N Z V C
Branching
Condition
Mnemonic
Operation
I
BIOR #xx:3, @aa:8
BXOR #xx:3, Rd
BXOR #xx:3, @Rd
BXOR #xx:3, @aa:8
BIXOR #xx:3, Rd
BIXOR #xx:3, @Rd
BIXOR #xx:3, @aa:8
BRA d:8 (BT d:8)
BRN d:8 (BF d:8)
BHI d:8
B
B
B
B
B
B
B
C (#xx:3 of @aa:8) → C
C (#xx:3 of Rd8) → C
C (#xx:3 of @Rd16) → C
C (#xx:3 of @aa:8) → C
C (#xx:3 of Rd8) → C
C (#xx:3 of @Rd16) → C
C (#xx:3 of @aa:8) → C
4
— — — — — ↕ 6
— — — — — ↕ 2
— — — — — ↕ 6
— — — — — ↕ 6
— — — — — ↕ 2
— — — — — ↕ 6
— — — — — ↕ 6
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 4
— — — — — — 6
— — — — — — 8
— — — — — — 6
2
4
4
2
4
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
2
2
— PC ← PC+d:8
— PC ← PC+2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
If
C
C
Z = 0
Z = 1
condition
is true
then
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
C = 0
PC ←
PC+d:8
else next;
C = 1
Z = 0
BEQ d:8
Z = 1
BVC d:8
V = 0
BVS d:8
V = 1
BPL d:8
N = 0
BMI d:8
N = 1
BGE d:8
N V = 0
N V = 1
BLT d:8
BGT d:8
Z
Z
(N V) = 0
(N V) = 1
BLE d:8
JMP @Rn
— PC ← Rn16
— PC ← aa:16
JMP @aa:16
JMP @@aa:8
BSR d:8
— PC ← @aa:8
— SP–2 → SP
PC → @SP
PC ← PC+d:8
397
Table A-1 Instruction Set (cont)
Addressing Mode/
Instruction Length (bytes)
Condition Code
H N Z V C
Mnemonic
Operation
I
JSR @Rn
— SP–2 → SP
PC → @SP
2
4
2
— — — — — — 6
— — — — — — 8
— — — — — — 8
2 — — — — — — 8
PC ← Rn16
JSR @aa:16
JSR @@aa:8
— SP–2 → SP
PC → @SP
PC ← aa:16
SP–2 → SP
PC → @SP
PC ← @aa:8
RTS
RTE
— PC ← @SP
SP+2 → SP
— CCR ← @SP
SP+2 → SP
2 ↕ ↕ ↕ ↕ ↕ ↕ 10
PC ← @SP
SP+2 → SP
SLEEP
— Transit to sleep mode.
2 — — — — — — 2
↕ ↕ ↕ ↕ ↕ ↕ 2
↕ ↕ ↕ ↕ ↕ ↕ 2
— — — — — — 2
↕ ↕ ↕ ↕ ↕ ↕ 2
↕ ↕ ↕ ↕ ↕ ↕ 2
↕ ↕ ↕ ↕ ↕ ↕ 2
2 — — — — — — 2
LDC #xx:8, CCR
LDC Rs, CCR
STC CCR, Rd
ANDC #xx:8, CCR
ORC #xx:8, CCR
XORC #xx:8, CCR
NOP
B
B
B
B
B
B
#xx:8 → CCR
2
2
2
2
2
2
Rs8 → CCR
CCR → Rd8
CCR #xx:8 → CCR
CCR #xx:8 → CCR
CCR #xx:8 → CCR
— PC ← PC+2
Notes: * The number of execution states given here assumes the opcode and operand data are in on-chip
memory. For other cases see Appendix A.3 below.
➀ Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0.
➁ If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0.
➂ Set to 1 if decimal adjustment produces a carry; otherwise retains value prior to arithmetic operation.
➃ The number of states required for execution is 4n + 9 (n = value of R4L).
➄ Set to 1 if the divisor is negative; otherwise cleared to 0.
➅ Set to 1 if the divisor is zero; otherwise cleared to 0.
398
A.2 Operation Code Map
Table A-2 is an operation code map. It shows the operation codes contained in the first byte of the
instruction code (bits 15 to 8 of the first instruction word).
Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0.
Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
399
400
A.3 Number of Execution States
The tables here can be used to calculate the number of states required for instruction execution.
Table A-3 indicates the number of states required for each cycle (instruction fetch, branch address
read, stack operation, byte data access, word data access, internal operation).
Table A-4 indicates the number of cycles of each type occurring in each instruction. The total
number of states required for execution of an instruction can be calculated from these two tables
as follows:
Execution states = I × S + J × S + K × S + L × S + M × S + N × S
N
I
J
K
L
M
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
BSET #0, @FF00
From table A-4:
I = L = 2, J = K = M = N= 0
From table A-3:
S = 2, S = 2
I
L
Number of states required for execution = 2 × 2 + 2 × 2 = 8
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and
on-chip RAM is used for stack area.
JSR @@ 30
From table A-4:
I = 2, J = K = 1, L = M = N = 0
From table A-3:
S = S = S = 2
I
J
K
Number of states required for execution = 2 × 2 + 1 × 2+ 1 × 2 = 8
401
Table A-3 Number of Cycles in Each Instruction
Access Location
On-Chip Peripheral Module
Execution Status
(instruction cycle)
On-Chip Memory
Instruction fetch
SI
2
—
Branch address read
Stack operation
SJ
SK
SL
SM
SN
Byte data access
Word data access
Internal operation
2 or 3*
—
1
Note: * Depends on which on-chip module is accessed. See 2.9.1, Notes on Data Access for
details.
402
Table A-4 Number of Cycles in Each Instruction
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
I
Addr. Read Operation Access
Access
M
Operation
N
Instruction Mnemonic
J
K
L
ADD
ADD.B #xx:8, Rd
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
2
1
ADD.B Rs, Rd
ADD.W Rs, Rd
ADDS.W #1, Rd
ADDS.W #2, Rd
ADDX.B #xx:8, Rd
ADDX.B Rs, Rd
AND.B #xx:8, Rd
AND.B Rs, Rd
ANDC #xx:8, CCR
BAND #xx:3, Rd
BAND #xx:3, @Rd
BAND #xx:3, @aa:8
BRA d:8 (BT d:8)
BRN d:8 (BF d:8)
BHI d:8
ADDS
ADDX
AND
ANDC
BAND
1
1
Bcc
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
BEQ d:8
BVC d:8
BVS d:8
BPL d:8
BMI d:8
BGE d:8
BLT d:8
BGT d:8
BLE d:8
BCLR
BCLR #xx:3, Rd
BCLR #xx:3, @Rd
BCLR #xx:3, @aa:8
BCLR Rn, Rd
2
2
403
Table A-4 Number of Cycles in Each Instruction (cont)
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
I
Addr. Read Operation Access
Access
M
Operation
N
Instruction Mnemonic
J
K
L
2
2
BCLR
BCLR Rn, @Rd
2
2
1
2
BCLR Rn, @aa:8
BIAND #xx:3, Rd
BIAND #xx:3, @Rd
BIAND
1
1
BIAND #xx:3, @aa:8 2
BILD
BILD #xx:3, Rd
1
2
2
1
2
2
1
2
2
1
2
BILD #xx:3, @Rd
BILD #xx:3, @aa:8
BIOR #xx:3, Rd
1
1
BIOR
BIST
BIOR #xx:3, @Rd
BIOR #xx:3, @aa:8
BIST #xx:3, Rd
1
1
BIST #xx:3, @Rd
BIST #xx:3, @aa:8
BIXOR #xx:3, Rd
BIXOR #xx:3, @Rd
2
2
BIXOR
BLD
1
1
BIXOR #xx:3, @aa:8 2
BLD #xx:3, Rd
1
2
2
1
2
2
1
2
2
1
2
2
1
2
2
1
2
BLD #xx:3, @Rd
BLD #xx:3, @aa:8
BNOT #xx:3, Rd
BNOT #xx:3, @Rd
BNOT #xx:3, @aa:8
BNOT Rn, Rd
1
1
BNOT
2
2
BNOT Rn, @Rd
BNOT Rn, @aa:8
BOR #xx:3, Rd
2
2
BOR
BOR #xx:3, @Rd
BOR #xx:3, @aa:8
BSET #xx:3, Rd
BSET #xx:3, @Rd
BSET #xx:3, @aa:8
BSET Rn, Rd
1
1
BSET
2
2
BSET Rn, @Rd
2
404
Table A-4 Number of Cycles in Each Instruction (cont)
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
I
Addr. Read Operation Access
Access
M
Operation
N
Instruction Mnemonic
J
K
L
BSET
BSR
BST
BSET Rn, @aa:8
2
2
1
2
2
1
2
2
1
2
2
1
2
2
BSR d:8
1
BST #xx:3, Rd
BST #xx:3, @Rd
BST #xx:3, @aa:8
BTST #xx:3, Rd
BTST #xx:3, @Rd
BTST #xx:3, @aa:8
BTST Rn, Rd
2
2
BTST
1
1
BTST Rn, @Rd
BTST Rn, @aa:8
BXOR #xx:3, Rd
BXOR #xx:3, @Rd
1
1
BXOR
CMP
1
1
BXOR #xx:3, @aa:8 2
CMP. B #xx:8, Rd
CMP. B Rs, Rd
CMP.W Rs, Rd
DAA.B Rd
1
1
1
1
1
1
1
2
1
2
2
2
2
2
2
1
1
1
1
1
DAA
DAS
DAS.B Rd
DEC
DEC.B Rd
DIVXU
EEPMOV
INC
DIVXU.B Rs, Rd
EEPMOV
12
1
2n+2*
INC.B Rd
JMP
JMP @Rn
JMP @aa:16
JMP @@aa:8
JSR @Rn
2
2
1
1
JSR
1
1
1
JSR @aa:16
JSR @@aa:8
LDC #xx:8, CCR
LDC Rs, CCR
MOV.B #xx:8, Rd
MOV.B Rs, Rd
MOV.B @Rs, Rd
2
LDC
MOV
1
Note: n: Initial value in R4L. The source and destination operands are accessed n + 1 times each.
405
Table A-4 Number of Cycles in Each Instruction (cont)
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
I
Addr. Read Operation Access
Access
M
Operation
N
Instruction Mnemonic
J
K
L
1
1
1
1
1
1
1
1
1
MOV
MOV.B @(d:16, Rs), Rd
2
1
1
2
1
2
1
1
2
2
1
1
2
1
2
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
MOV.B @Rs+, Rd
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B Rs, @Rd
MOV.B Rs, @(d:16, Rd)
MOV.B Rs, @–Rd
MOV.B Rs, @aa:8
MOV.B Rs, @aa:16
MOV.W #xx:16, Rd
MOV.W Rs, Rd
MOV.W @Rs, Rd
MOV.W @(d:16, Rs), Rd
MOV.W @Rs+, Rd
MOV.W @aa:16, Rd
MOV.W Rs, @Rd
MOV.W Rs, @(d:16, Rd)
MOV.W Rs, @–Rd
MOV.W Rs, @aa:16
MULXU.B Rs, Rd
NEG.B Rd
2
2
1
1
1
1
1
1
1
1
2
2
MULXU
NEG
NOP
NOT
12
NOP
NOT.B Rd
OR
OR.B #xx:8, Rd
OR.B Rs, Rd
ORC
ORC #xx:8, CCR
POP Rd
POP
1
1
2
2
PUSH
ROTL
ROTR
ROTXL
ROTXR
RTE
PUSH Rs
ROTL.B Rd
ROTR.B Rd
ROTXL.B Rd
ROTXR.B Rd
RTE
2
1
2
2
RTS
RTS
406
Table A-4 Number of Cycles in Each Instruction (cont)
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
I
Addr. Read Operation Access
Access
M
Operation
N
Instruction Mnemonic
J
K
L
SHLL
SHAL
SHAR
SHLR
SLEEP
STC
SHLL.B Rd
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SHAL.B Rd
SHAR.B Rd
SHLR.B Rd
SLEEP
STC CCR, Rd
SUB.B Rs, Rd
SUB.W Rs, Rd
SUBS.W #1, Rd
SUBS.W #2, Rd
SUBX.B #xx:8, Rd
SUBX.B Rs, Rd
XOR.B #xx:8, Rd
XOR.B Rs, Rd
XORC #xx:8, CCR
SUB
SUBS
SUBX
XOR
XORC
407
Appendix B On-Chip Registers
B.1 I/O Registers (1)
Bit Names
Address Register
Module
Name
(low)
H'A0
H'A1
H'A2
H'A3
H'A4
H'A5
H'A6
H'A7
H'A8
H'A9
H'AA
H'AB
H'AC
H'AD
H'AE
H'AF
Name
SCR1
SCSR1
SDRU
SDRL
STAR
EDAR
SCR2
SCSR2
SMR
Bit 7
SNC1
—
Bit 6
SNC0
SOL
Bit 5
—
Bit 4
Bit 3
CKS3
—
Bit 2
CKS2
—
Bit 1
CKS1
—
Bit 0
CKS0
STF
—
—
SCI1
SCI2
SCI3
ORER
SDRU7 SDRU6 SDRU5 SDRU4 SDRU3 SDRU2 SDRU1 SDRU0
SDRL7 SDRL6 SDRL5 SDRL4 SDRL3 SDRL2 SDRL1 SDRL0
—
—
—
STA4
EDA4
GAP1
SOL
STA3
EDA3
GAP0
ORER
STOP
BRR3
MPIE
TDR3
PER
STA2
EDA2
CKS2
WT
STA1
EDA1
CKS1
ABT
STA0
EDA0
CKS0
STF
—
—
—
—
—
—
—
—
—
COM
BRR7
TIE
CHR
BRR6
RIE
PE
PM
MP
CKS1
BRR1
CKE1
TDR1
MPBR
RDR1
CKS0
BRR0
CKE0
TDR0
MPBT
RDR0
BRR
BRR5
TE
BRR4
RE
BRR2
TEIE
TDR2
TEND
RDR2
SCR3
TDR
TDR7
TDRE
RDR7
TDR6
RDRF
RDR6
TDR5
OER
RDR5
TDR4
FER
SSR
RDR
RDR4
RDR3
H'B0
H'B1
H'B2
H'B3
TMA
TCA
TMB
TMA7
TCA7
TMB7
TMA6
TCA6
—
TMA5
TCA5
—
—
TMA3
TCA3
—
TMA2
TCA2
TMB2
TMA1
TCA1
TMB1
TMA0
TCA0
TMB0
Timer A
Timer B
TCA4
—
TCB/TLB TCB7/
TLB7
TCB6/
TLB6
TCB5/
TLB5
TCB4/
TLB4
TCB3/
TLB3
TCB2/
TLB2
TCB1/
TLB1
TCB0/
TLB0
H'B4
H'B5
TMC
TMC7
TMC6
TMC5
—
—
TMC2
TMC1
TMC0
Timer C
TCC/TLC TCC7/
TLC7
TCC6/
TLC6
TCC5/
TLC5
TCC4/
TLC4
TCC3/
TLC3
TCC2/
TLC2
TCC1/
TLC1
TCC0/
TLC0
H'B6
TCRF
TOLH
CKSH2 CKSH1 CKSH0 TOLL
CMFH OVIEH CCLRH OVFL
TCFH7 TCFH6 TCFH5 TCFH4 TCFH3 TCFH2 TCFH1 TCFH0
TCFL7 TCFL6 TCFL5 TCFL4 TCFL3 TCFL2 TCFL1 TCFL0
CKSL2 CKSL1 CKSL0 Timer F
H'B7
TCSRF OVFH
CMFL OVIEL CCLRL
H'B8
TCFH
TCFL
H'B9
H'BA
Notation:
OCRFH OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 OCRFH2 OCRFH1 OCRFH0
SCI1: Serial communication interface 1
SCI2: Serial communication interface 2
SCI3: Serial communication interface 3
408
Bit Names
Bit 4 Bit 3
Address Register
Module
Name
(low)
H'BB
H'BC
H'BD
H'BE
H'BF
Name
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
OCRFL OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0 Timer F
TMG
OVFH
OVFL
OVIE
IIEGS
CCLR1 CCLR0 CKS1
CKS0
Timer G
ICRGF
ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0
ICRGR ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0
H'C0
LPCR
LCR
DTS1
—
DTS0
PSW
CMX
ACT
SGX
SGS3
CKS3
SGS2
CKS2
SGS1
CKS1
SGS0
CKS0
LCD
con-
troller/
driver
H'C1
DISP
H'C2
H'C3
H'C4
H'C5
H'C6
H'C7
H'C8
H'C9
H'CA
H'CB
H'CC
H'CD
H'CE
H'CF
AMR
CKS
TRGE
ADR6
—
—
—
CH3
ADR3
—
CH2
ADR2
—
CH1
ADR1
—
CH0
ADR0
—
A/D
convert-
er
ADRR
ADSR
ADR7
ADSF
ADR5
—
ADR4
—
PMR1
PMR2
PMR3
PMR4
PMR5
IRQ3
—
IRQ2
—
IRQ1
POF2
SO2
PWM
NCS
SI2
TMIG
IRQ0
SCK2
TMOFH TMOFL TMOW
I/O
ports
POF1
SO1
UD
SI1
IRQ4
CS
STRB
SCK1
NMOD7 NMOD6 NMOD5 NMOD4 NMOD3 NMOD2 NMOD1 NMOD0
WKP7
WKP6
WKP5
WKP4
WKP3
WKP2
WKP1
WKP0
RLCTR
—
—
—
—
—
—
—
—
—
—
RLCT1 RLCT0
— PWCR0 14-bit
H'D0
H'D1
H'D2
H'D3
H'D4
H'D5
H'D6
H'D7
H'D8
H'D9
H'DA
H'DB
H'DC
H'DD
PWCR
—
—
—
—
PWM
PWDRU
PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0
PWDRL PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0
PDR1
PDR2
PDR3
PDR4
PDR5
PDR6
PDR7
PDR8
PDR9
PDRA
P17
P27
P37
—
P16
P26
P36
—
P15
P25
P35
—
P14
P24
P34
—
P13
P23
P33
P43
P53
P63
P73
P83
P93
PA3
P12
P22
P32
P42
P52
P62
P72
P82
P92
PA2
P11
P21
P31
P41
P51
P61
P71
P81
P91
PA1
P10
P20
P30
P40
P50
P60
P70
P80
P90
PA0
I/O
ports
P57
P67
P77
P87
P97
—
P56
P66
P76
P86
P96
—
P55
P65
P75
P85
P95
—
P54
P64
P74
P84
P94
—
409
Bit Names
Bit 4 Bit 3
Address Register
Module
Name
(low)
H'DE
H'DF
H'E0
H'E1
H'E2
H'E3
H'E4
H'E5
H'E6
H'E7
H'E8
H'E9
H'EA
H'EB
H'EC
H'ED
H'EE
H'EF
Name
PDRB
PDRC
Bit 7
PB7
—
Bit 6
PB6
—
Bit 5
PB5
—
Bit 2
PB2
PC2
Bit 1
PB1
PC1
Bit 0
PB0
PC0
PB4
—
PB3
PC3
I/O
ports
PUCR1 PUCR17 PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10
PUCR3 PUCR37 PUCR36 PUCR35 PUCR34 PUCR33 PUCR32 PUCR31 PUCR30
PUCR5 PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50
PUCR6 PUCR67 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60
PCR1
PCR2
PCR3
PCR4
PCR5
PCR6
PCR7
PCR8
PCR9
PCRA
PCR17
PCR27
PCR37
—
PCR16
PCR26
PCR36
—
PCR15
PCR25
PCR35
—
PCR14
PCR24
PCR34
—
PCR13
PCR23
PCR33
—
PCR12
PCR22
PCR32
PCR42
PCR52
PCR62
PCR72
PCR82
PCR92
PCR11
PCR21
PCR31
PCR41
PCR51
PCR61
PCR71
PCR81
PCR91
PCR10
PCR20
PCR30
PCR40
PCR50
PCR60
PCR70
PCR80
PCR90
PCR57
PCR67
PCR77
PCR87
PCR97
—
PCR56
PCR66
PCR76
PCR86
PCR96
—
PCR55
PCR65
PCR75
PCR85
PCR95
—
PCR54
PCR64
PCR74
PCR84
PCR94
—
PCR53
PCR63
PCR73
PCR83
PCR93
PCRA3 PCRA2 PCRA1 PCRA0
H'F0
H'F1
H'F2
H'F3
H'F4
H'F5
H'F6
H'F7
H'F8
H'F9
SYSCR1 SSBY
SYSCR2 —
STS2
—
STS1
—
STS0
LSON
—
—
—
System
control
NESEL DTON
MSON
IEG2
IEN2
SA1
IEG1
IEN1
SA0
IEG0
IEN0
IENTB
IEGR
—
—
—
IEG4
IEG3
IEN3
IENR1
IENR2
IENTA
IENDT
IENS1
IENAD
IENWP IEN4
IENS2
IENTG
IENTFH IENTFL IENTC
IRR1
IRR2
IRRTA
IRRDT
IRRS1
IRRAD
—
IRRI4
IRRI3
IRRI2
IRRI1
IRRI0
System
control
IRRS2
IRRTG
IRRTFH IRRTFL IRRTC
IRRTB
IWPR
IWPF7
IWPF6
IWPF5
IWPF4
IWPF3
IWPF2
IWPF1
IWPF0
System
control
H'FA
H'FB
H'FC
H'FD
H'FE
H'FF
H'FF
410
B.2 I/O Registers (2)
Register
acronym
Register
name
Address to which the
register is mapped
Name of
on-chip
supporting
module
TMC—Timer mode register C
H'B4
Timer C
Bit
numbers
Bit
7
TMC7
0
6
5
4
—
1
3
—
1
2
TMC2
0
1
TMC1
0
0
TMC0
0
Initial bit
values
TMC6
0
TMC5
0
Initial value
Read/Write
Names of the
bits. Dashes
(—) indicate
reserved bits.
R/W
R/W
R/W
—
—
R/W
R/W
R/W
Clock select
0
0
1
0
1
0
1
0
1
0
1
0
1
Internal clock: ø/8192
Internal clock: ø/2048
Internal clock: ø/512
Internal clock: ø/64
Internal clock: ø/16
Internal clock: ø/4
Possible types of access
Full name
of bit
R
Read only
Write only
W
1
R/W Read and write
Descriptions
of bit settings
Internal clock: øW/4
External event (TMIC): Rising or falling edge
Counter up/down control
0
0
1
*
TCC is an up-counter
TCC is a down-counter
1
TCC up/down control is determined by input at pin
UD. TCC is a down-counter if the UD input is high,
and an up-counter if the UD input is low.
411
SCR1—Serial control register 1
H'A0
SCI1
Bit
7
SNC1
0
6
SNC0
0
5
—
4
—
3
CKS3
0
2
1
CKS1
0
0
CKS2
0
CKS0
0
Initial value
Read/Write
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock Select (CKS2 to CKS0)
Serial Clock Cycle
Synchronous
Bit 2 Bit 1 Bit 0
Prescaler
CKS2 CKS1 CKS0 Division
ø = 5 MHz
ø = 2.5 MHz
0
0
1
0
1
0
1
0
1
0
1
0
1
ø/1024
ø/256
ø/64
ø/32
ø/16
ø/8
204.8 µs
51.2 µs
12.8 µs
6.4 µs
3.2 µs
1.6 µs
0.8 µs
—
409.6 µs
102.4 µs
25.6 µs
12.8 µs
6.4 µs
1
3.2 µs
ø/4
1.6 µs
ø/2
0.8 µs
Clock source select
0
1
Clock source is prescaler S, and pin SCK1 is output pin
Clock source is external clock, and pin SCK1 is input pin
Operation mode select
0
0
1
0
1
8-bit synchronous transfer mode
16-bit synchronous transfer mode
Continuous clock output mode
Reserved
1
412
SCSR1—Serial control/status register 1
H'A1
SCI1
Bit
7
—
1
6
5
4
—
0
3
—
0
2
1
—
0
0
SOL
0
ORER
0
—
0
STF
0
Initial value
Read/Write
—
R/W
R/(W)*
—
—
—
—
R/W
Start flag
0
Read Indicates that transfer is stopped
Write Invalid
1
Read Indicates transfer in progress
Write Starts a transfer operation
Overrun error flag
0
[Clearing condition]
After reading 1, cleared by writing 0
1
[Setting condition]
Set if a clock pulse is input after transfer
is complete, when an external clock is used
Extended data bit
0
Read SO1 pin output level is low
Write SO1 pin output level changes to low
Read SO1 pin output level is high
1
Write SO1 pin output level changes to high
Note: * Only a write of 0 for flag clearing is possible.
413
SDRU—Serial data register U
H'A2
SCI1
Bit
7
6
5
4
3
2
1
0
SDRU7 SDRU6 SDRU5 SDRU4 SDRU3 SDRU2 SDRU1 SDRU0
Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Stores transmit and receive data
8-bit transfer mode: Not used
16-bit transfer mode: Upper 8 bits of data
SDRL—Serial data register L
H'A3
SCI1
Bit
7
6
5
4
3
2
1
0
SDRL7 SDRL6 SDRL5 SDRL4 SDRL3 SDRL2 SDRL1 SDRL0
Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Stores transmit and receive data
8-bit transfer mode: 8-bit data
16-bit transfer mode: Lower 8 bits of data
STAR—Start address register
H'A4
SCI2
Bit
7
—
1
6
—
1
5
—
1
4
STA4
0
3
STA3
0
2
STA2
0
1
STA1
0
0
STA0
0
Initial value
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Transfer start address in range from
H'FF80 to H'FF9F
414
EDAR—End address register
H'A5
SCI2
Bit
7
—
1
6
—
1
5
—
1
4
EDA4
0
3
EDA3
0
2
1
EDA1
0
0
EDA2
0
EDA0
0
Initial value
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Transfer end address in range from
H'FF80 to H'FF9F
SCR2—Serial control register 2
H'A6
SCI2
Bit
7
—
1
6
—
1
5
—
1
4
GAP1
0
3
GAP0
0
2
CKS2
0
1
CKS1
0
0
CKS0
0
Initial value
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
Clock Select (CKS2 to CKS0)
Bit 2 Bit 1 Bit 0
Serial Clock Cycle
ø = 5 MHz ø = 2.5 MHz
51.2 µs
Prescaler
Clock Source Division
CKS2 CKS1 CKS0
Pin SCK2
0
0
1
0
1
0
1
0
1
0
1
0
1
SCK2 output Prescaler S
ø/256
ø/64
ø/32
ø/16
ø/8
102.4 µs
25.6 µs
12.8 µs
6.4 µs
3.2 µs
1.6 µs
0.8 µs
—
12.8 µs
6.4 µs
3.2 µs
1.6 µs
0.8 µs
—
1
ø/4
ø/2
SCK2 input
External clock —
—
Gap select
0
0
1
0
1
No gaps between bytes
A gap of 8 clock cycles is inserted between bytes
A gap of 24 clock cycles is inserted between bytes
A gap of 56 clock cycles is inserted between bytes
1
415
SCSR2—Serial control/status register 2
H'A7
SCI2
Bit
7
—
1
6
—
1
5
—
1
4
3
ORER
0
2
1
ABT
0
0
SOL
0
WT
0
STF
0
Initial value
Read/Write
—
—
—
R/W
R/(W)* R/(W)* R/(W)*
R/W
Start flag
0
Read Indicates that transfer is stopped
Write Stops a transfer operation
1
Read Indicates transfer in progress or waiting for CS input
Write Starts a transfer operation
Abort flag
0
[Clearing condition]
After reading 1, cleared by writing 0
1
[Setting condition]
When CS goes high during a transfer
Wait flag
0
[Clearing condition]
After reading 1, cleared by writing 0
[Setting condition]
1
An attempt was made to read or write the (32-byte) serial data buffer
during a transfer or while waiting for CS input
Overrun error flag
0
[Clearing condition]
After reading 1, cleared by writing 0
1
[Setting condition]
Set if a clock pulse is input after transfer is complete, when an
external clock is used
Extended data bit
0
Read SO2 pin output level is low
Write SO2 pin output level changes to low
Read SO2 pin output level is high
1
Write SO2 pin output level changes to high
*
Note: Only a write of 0 for flag clearing is possible.
416
SMR—Serial mode register
H'A8
SCI3
Bit
7
COM
0
6
5
PE
0
4
PM
0
3
2
MP
0
1
CKS1
0
0
CHR
0
STOP
0
CKS0
Initial value
Read/Write
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock select 0, 1
0
0
1
0
1
ø clock
Multiprocessor mode
ø/4 clock
ø/16 clock
ø/64 clock
0
1
Multiprocessor communication function disabled
Multiprocessor communication function enabled
1
Stop bit length
0
1
1 stop bit
2 stop bits
Parity mode
0
1
Even parity
Odd parity
Parity enable
0
1
Parity bit adding and checking disabled
Parity bit adding and checking enabled
Character length
0
1
8-bit data
7-bit data
Communication mode
0
1
Asynchronous mode
Synchronous mode
BRR—Bit rate register
H'A9
SCI3
Bit
7
BRR7
1
6
BRR6
1
5
BRR5
1
4
BRR4
1
3
BRR3
1
2
1
0
BRR0
1
BRR2
1
BRR1
1
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
417
SCR3—Serial control register 3
H'AA
SCI3
Bit
7
TIE
0
6
RIE
0
5
TE
0
4
RE
0
3
MPIE
0
2
1
CKE1
0
0
TEIE
0
CKE0
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock enable
Description
Bit 1
CKE1
0
Bit 0
CKE0
0
Communication Mode
Asynchronous
Synchronous
Clock Source
Internal clock
Internal clock
Internal clock
Reserved
SCK3 Pin Function
I/O port
Serial clock output
Clock output
Reserved
1
0
1
Asynchronous
Synchronous
1
Asynchronous
Synchronous
External clock
External clock
Reserved
Clock input
Serial clock input
Reserved
Asynchronous
Synchronous
Reserved
Reserved
Transmit end interrupt enable
0
1
Transmit end interrupt (TEI) disabled
Transmit end interrupt (TEI) enabled
Multiprocessor interrupt enable
0
Multiprocessor interrupt request disabled (ordinary receive operation)
[Clearing condition]
Multiprocessor bit receives a data value of 1
1
Multiprocessor interrupt request enabled
Until a multiprocessor bit value of 1 is received, the receive data full interrupt (RXI) and receive
error interrupt (ERI) are disabled, and serial status register (SSR) flags RDRF, FER, and
OER are not set.
Receive enable
0
1
Receive operation disabled (RXD is a general I/O port)
Receive operation enabled (RXD is the receive data pin)
Transmit enable
0
1
Transmit operation disabled (TXD is a general I/O port)
Transmit operation enabled (TXD is the transmit data pin)
Receive interrupt enable
0
1
Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled
Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled
Transmit interrupt enable (TIE)
0
1
Transmit data empty interrupt request (TXI) disabled
Transmit data empty interrupt request (TXI) enabled
418
TDR—Transmit data register
H'AB
SCI3
Bit
7
TDR7
1
6
TDR6
1
5
TDR5
1
4
TDR4
1
3
TDR3
1
2
1
TDR1
1
0
TDR2
1
TDR0
1
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data to be transferred to TSR
419
SSR—Serial status register
H'AC
SCI3
Bit
7
TDRE
1
6
RDRF
0
5
OER
0
4
FER
0
3
PER
0
2
1
MPBR
0
0
TEND
MPBT
0
Initial value
Read/Write
1
R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
R
R
R/W
Multiprocessor bit receive
Multiprocessor bit transmit
0 Indicates reception of data in which the multiprocessor bit is 0
1 Indicates reception of data in which the multiprocessor bit is 1
0 The multiprocessor bit in transmit data is 0
1 The multiprocessor bit in transmit data is 1
Transmit end
0 Indicates that transmission is in progress
[Clearing conditions] After reading TDRE = 1, cleared by writing 0 to TDRE.
When data is written to TDR by an instruction.
1 Indicates that a transmission has ended
[Setting conditions]
When bit TE in serial control register 3 (SCR3) is 0.
If TDRE is set to 1 when the last bit of a transmitted character is sent.
Parity error
0 Indicates that data receiving is in progress or has been completed
[Clearing conditions] After reading PER = 1, cleared by writing 0
1 Indicates that a parity error occurred in data receiving
[Setting conditions]
When the sum of 1s in received data plus the parity bit does not match
the parity mode bit (PM) setting in the serial mode register (SMR)
Framing error
0 Indicates that data receiving is in progress or has been completed
[Clearing conditions] After reading FER = 1, cleared by writing 0
1 Indicates that a framing error occurred in data receiving
[Setting conditions]
The stop bit at the end of receive data is checked and found to be 0
Overrun error
0 Indicates that data receiving is in progress or has been completed
[Clearing conditions] After reading OER = 1, cleared by writing 0
1 Indicates that an overrun error occurred in data receiving
[Setting conditions]
When data receiving is completed while RDRF is set to 1
Receive data register full
0 Indicates there is no receive data in RDR
[Clearing conditions] After reading RDRF = 1, cleared by writing 0.
When data is read from RDR by an instruction.
1 Indicates that there is receive data in RDR
[Setting conditions]
When receiving ends normally, with receive data transferred from RSR to RDR
Transmit data register empty
0 Indicates that transmit data written to TDR has not been transferred to TSR
[Clearing conditions] After reading TDRE = 1, cleared by writing 0.
When data is written to TDR by an instruction.
1 Indicates that no transmit data has been written to TDR, or the transmit data written to TDR has been transferred to TSR
[Setting conditions]
When bit TE in serial control register 3 (SCR3) is 0.
When data is transferred from TDR to TSR.
Note: *Only a write of 0 for flag clearing is possible.
420
RDR—Receive data register
H'AD
SCI3
Bit
7
RDR7
0
6
RDR6
0
5
RDR5
0
4
RDR4
0
3
RDR3
0
2
1
RDR1
0
0
RDR2
RDR0
Initial value
Read/Write
0
0
R
R
R
R
R
R
R
R
TMA—Timer mode register A
H'B0
Timer A
Bit
7
TMA7
0
6
TMA6
0
5
TMA5
0
4
—
1
3
TMA3
0
2
TMA2
0
1
TMA1
0
0
TMA0
0
Initial value
Read/Write
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
Clock output select Internal clock select
0
0
1
0
1
0
1
0
1
0
1
0
1
ø/32
ø/16
ø/8
Prescaler and Divider Ratio
TMA3 TMA2 TMA1 TMA0 or Overflow Period
Function
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PSS
PSS
PSS
PSS
PSS
PSS
PSS
PSS
PSW
PSW
PSW
PSW
ø/8192
ø/4096
ø/2048
ø/512
ø/256
ø/128
ø/32
Interval
timer
ø/4
1
øW/32
øW/16
øW/8
øW/4
ø/8
1
1 s
Time
base
0.5 s
0.25 s
0.03125 s
PSW and TCA are reset
421
TCA—Timer counter A
H'B1
Timer A
Bit
7
TCA7
0
6
TCA6
0
5
TCA5
0
4
TCA4
0
3
TCA3
0
2
1
TCA1
0
0
TCA0
0
TCA2
Initial value
Read/Write
0
R
R
R
R
R
R
R
R
Count value
TMB—Timer mode register B
H'B2
Timer B
Bit
7
TMB7
0
6
—
1
5
—
1
4
—
1
3
—
1
2
TMB2
0
1
TMB1
0
0
TMB0
0
Initial value
Read/Write
R/W
—
—
—
—
R/W
R/W
R/W
Auto-reload function select
Clock select
0
1
Interval timer function selected
Auto-reload function selected
0
0
1
0
1
0
1
0
1
0
1
0
1
Internal clock: ø/8192
Internal clock: ø/2048
Internal clock: ø/512
Internal clock: ø/256
Internal clock: ø/64
Internal clock: ø/16
Internal clock: ø/4
1
External event (TMIB): Rising or falling edge
422
TCB—Timer counter B
H'B3
Timer B
Bit
7
TCB7
0
6
TCB6
0
5
TCB5
0
4
TCB4
0
3
TCB3
0
2
1
TCB1
0
0
TCB0
0
TCB2
Initial value
Read/Write
0
R
R
R
R
R
R
R
R
Count value
TLB—Timer load register B
H'B3
Timer B
Bit
7
TLB7
0
6
TLB6
0
5
TLB5
0
4
TLB4
0
3
TLB3
0
2
TLB2
0
1
TLB1
0
0
TLB0
0
Initial value
Read/Write
W
W
W
W
W
W
W
W
Reload value
423
TMC—Timer mode register C
H'B4
Timer C
Bit
7
TMC7
0
6
TMC6
0
5
TMC5
0
4
—
1
3
—
1
2
1
TMC1
0
0
TMC0
0
TMC2
0
Initial value
Read/Write
R/W
R/W
R/W
—
—
R/W
R/W
R/W
Clock select
0
0
1
0
1
0
1
0
1
0
1
0
1
Internal clock: ø/8192
Internal clock: ø/2048
Internal clock: ø/512
Internal clock: ø/64
Internal clock: ø/16
Internal clock: ø/4
Auto-reload function select
0
1
Interval timer function selected
Auto-reload function selected
1
Internal clock: øW/4
External event (TMIC): Rising or falling edge
Counter up/down control
0
0
1
*
TCC is an up-counter
TCC is a down-counter
1
TCC up/down control is determined by input at pin
UD. TCC is a down-counter if the UD input is high,
and an up-counter if the UD input is low.
Note: *Don’t care
TCC—Timer counter C
H'B5
Timer C
Bit
7
TCC7
0
6
TCC6
0
5
4
TCC4
0
3
TCC3
0
2
1
TCC1
0
0
TCC0
0
TCC5
TCC2
Initial value
Read/Write
0
0
R
R
R
R
R
R
R
R
Count value
424
TLC—Timer load register C
H'B5
Timer C
Bit
7
TLC7
0
6
TLC6
0
5
TLC5
0
4
TLC4
0
3
TLC3
0
2
1
TLC1
0
0
TLC0
0
TLC2
0
Initial value
Read/Write
W
W
W
W
W
W
W
W
Reload value
TCRF—Timer control register F
H'B6
Timer F
Bit
7
6
5
4
3
2
1
0
TOLH CKSH2 CKSH1 CKSH0 TOLL
CKSL2 CKSL1 CKSL0
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Toggle output level H
Clock select L
0
1
Low level
High level
0
1
External event (TMIF): Rising or falling edge
Internal clock: ø/32
*
0
*
0
1
0
1
Internal clock: ø/16
1
Internal clock: ø/4
Internal clock: ø/2
Toggle output level L
0
1
Low level
High level
Clock select H
0
1
16-bit mode selected. TCFL overflow signals are counted.
Internal clock: ø/32
*
0
*
0
1
0
1
Internal clock: ø/16
1
Internal clock: ø/4
Internal clock: ø/2
Note: *Don’t care
425
TCSRF—Timer control/status register F
H'B7
Timer F
Bit
7
OVFH
0
6
CMFH
0
5
4
3
2
1
0
OVIEH CCLRH OVFL
CMFL
OVIEL CCLRL
Initial value
Read/Write
0
0
0
0
0
0
R/(W)* R/(W)*
R/W
R/W
R/(W)* R/(W)*
R/W
R/W
Timer overflow interrupt enable L
0
1
TCFL overflow interrupt disabled
TCFL overflow interrupt enabled
Compare match flag L
0
[Clearing condition]
After reading CMFL = 1, cleared by writing 0 to CMFL
1
[Setting condition]
When the TCFL value matches the OCRFL value
Timer overflow flag L
0
[Clearing condition]
After reading OVFL = 1, cleared by writing 0 to OVFL
1
[Setting condition]
When the value of TCFL goes from H'FF to H'00
Counter clear H
0
16-bit mode: TCF clearing by compare match disabled
8-bit mode: TCFH clearing by compare match disabled
1
16-bit mode: TCF clearing by compare match enabled
8-bit mode: TCFH clearing by compare match enabled
Timer overflow interrupt enable H
Counter clear L
0
1
TCFH overflow interrupt disabled
TCFH overflow interrupt enabled
0
1
TCFL clearing by compare match disabled
TCFL clearing by compare match enabled
Compare match flag H
0
[Clearing condition]
After reading CMFH = 1, cleared by writing 0 to CMFH
1
[Setting condition]
When the TCFH value matches the OCRFH value
Timer overflow flag H
0
[Clearing condition]
After reading OVFH = 1, cleared by writing 0 to OVFH
1
[Setting condition]
When the value of TCFH goes from H'FF to H'00
Note: * Only a write of 0 for flag clearing is possible.
426
TCFH—8-bit timer counter FH
H'B8
Timer F
Bit
7
6
5
4
3
2
1
0
TCFH7 TCFH6 TCFH5 TCFH4 TCFH3 TCFH2 TCFH1 TCFH0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Count value
TCFL—8-bit timer counter FL
H'B9
Timer F
Bit
7
6
5
4
3
2
1
0
TCFL7 TCFL6 TCFL5 TCFL4 TCFL3 TCFL2 TCFL1 TCFL0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Count value
OCRFH—Output compare register FH
H'BA
Timer F
Bit
7
6
5
4
3
2
1
0
OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 OCRFH2 OCRFH1 OCRFH0
Initial value
Read/Write
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OCRFL—Output compare register FL
H'BB
Timer F
Bit
7
6
5
4
3
2
1
0
OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0
Initial value
Read/Write
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
427
TMG—Timer mode register G
H'BC
Timer G
Bit
7
OVFH
0
6
OVFL
0
5
OVIE
0
4
3
2
1
CKS1
0
0
CKS0
0
IIEGS CCLR1 CCLR0
Initial value
Read/Write
0
0
0
R/(W)* R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
Clock select
0
0
1
0
1
Internal clock: ø/64
Internal clock: ø/32
Internal clock: ø/2
Internal clock: øW/2
1
Counter clear
0
0
1
0
1
TCG is not cleared
TCG is cleared at the falling edge of the input capture signal
TCG is cleared at the rising edge of the input capture signal
TCG is cleared at both edges of the input capture signal
1
Input capture interrupt edge select
0
1
Interrupts are requested at the rising edge of the input capture signal
Interrupts are requested at the falling edge of the input capture signal
Timer overflow interrupt enable
0
1
TCG overflow interrupt disabled
TCG overflow interrupt enabled
Timer overflow flag L
0
[Clearing condition]
After reading OVFL = 1, cleared by writing 0 to OVFL
1
[Setting condition]
When the value of TCG goes from H'FF to H'00
Timer overflow flag H
0
[Clearing condition]
After reading OVFH = 1, cleared by writing 0 to OVFH
1
[Setting condition]
When the value of TCG goes from H'FF to H'00
Note: * Only a write of 0 for flag clearing is possible.
428
ICRGF—Input capture register GF
H'BD
Timer G
Bit
7
6
5
4
3
2
1
0
ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
ICRGR—Input capture register GR
H'BE
Timer G
Bit
7
6
5
4
3
2
1
0
ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
429
LPCR—LCD port control register
H'C0 LCD controller/driver
Bit
7
DTS1
0
6
DTS0
0
5
CMX
0
4
3
SGS3
0
2
SGS2
0
1
SGS1
0
0
SGS0
0
SGX
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Segment driver select
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Functions of Pins SEG to SEG
40 1
SEG to
SEG to SEG to SEG to SEG to SEG to SEG to SEG to SEG to SEG to
40
36
32
28
24
20
16
12
8
4
SGX SGS3 SGS2 SGS1 SGS0 SEG
SEG
SEG
SEG
SEG
Port
Port
Port
Port
SEG
SEG
SEG
SEG
SEG
SEG
Port
SEG
Port
Port
Port
Port
Port
SEG
SEG
SEG
SEG
SEG
Port
SEG
Port
Port
Port
Port
Port
Port
SEG
SEG
SEG
SEG
Port
SEG
Port
Port
Port
Port
Port
Port
Port
SEG
SEG
SEG
Port
SEG
Port
Port
Port
Port
Port
Port
Port
Port
SEG
SEG
Port
SEG
Port
Port
Port
Port
Port
Port
Port
Port
Port
SEG
Port
Remarks
37
33
29
25
21
17
13
9
5
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Port
Port
Port
Port
(initial value)
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
Port
Port
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
Port
Port
SEG
SEG
SEG
SEG
SEG
SEG
SEG
Port
1
1
0
*
*
1
0
0
External segment Port
expansion
1
0
1
0
1
0
1
0
1
External segment SEG
expansion
Port
Port
Port
Port
Port
Port
Port
SEG
SEG
SEG
SEG
SEG
Port
Port
Port
Port
Port
SEG
SEG
SEG
SEG
Port
Port
Port
Port
Port
Port
SEG
SEG
SEG
Port
Port
Port
Port
Port
Port
Port
SEG
SEG
Port
Port
Port
Port
Port
Port
Port
Port
SEG
External segment
expansion
1
0
1
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
Port
Port
External segment SEG
expansion
SEG
SEG
SEG
SEG
SEG
SEG
SEG
Port
External segment
expansion
1
SEG
SEG
SEG
SEG
SEG
SEG
SEG
External segment SEG
expansion
External segment SEG
expansion
External segment SEG
expansion
1
External segment SEG
expansion
*
*
External segment SEG
expansion
Expansion signal select
0
Pins SEG to SEG
40 37
1
Pins CL , CL , DO, and M
1
2
Duty and common function select
Bit 7 Bit 6 Bit 5
DTS1 DTS0 CMX Duty
Common Driver Other Uses
COM COM , COM , and COM usable as ports
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
Static
1
3
2
1
COM to COM
COM , COM , and COM output the same waveform as COM
4 3 2 1
4
1
1/2 duty COM , COM
COM and COM usable as ports
4 3
2
1
COM to COM
COM outputs the same waveform as COM , and COM the same waveform as COM
4 3 2 1
4
1
1
1
1
1/3 duty COM to COM
COM usable as port
4
3
COM to COM
COM outputs a non-select waveform
4
4
1/4 duty COM to COM
—
4
430
LCR—LCD control register
H'C1 LCD controller/driver
Bit
7
—
1
6
PSW
0
5
4
DISP
0
3
CKS3
0
2
CKS2
0
1
CKS1
0
0
CKS0
0
ACT
0
Initial value
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Frame frequency select
Bit 3 Bit 2 Bit 1 Bit 0
CKS3 CKS2 CKS1 CKS0 Clock ø = 5 MHz ø = 625 Hz
Frame Frequency
0
0
0
1
øW
128 Hz (initial value)
64 Hz
*
øW
1
0
øW/2
ø/2
32 Hz
*
0
1
0
1
0
1
0
1
1
0
—
610 Hz
305 Hz
153 Hz
76.3 Hz
38.1 Hz
—
ø/4
—
1
0
1
ø/8
—
ø/16
ø/32
ø/64
610 Hz
305 Hz
153 Hz
1
ø/128 76.3 Hz
ø/256 38.1 Hz
—
—
Display data control
0
1
Blank data displayed
LCD RAM data displayed
Display active
0
1
LCD controller/driver operation stopped
LCD controller/driver operational
Power switch
0
1
LCD power supply resistive voltage divider off
LCD power supply resistive voltage divider on
Note: *Don’t care
431
AMR—A/D mode register
H'C4
A/D converter
Bit
7
6
TRGE
0
5
—
1
4
—
1
3
2
1
0
CKS
0
CH3
0
CH2
0
CH1
0
CH0
0
Initial value
Read/Write
R/W
R/W
—
—
R/W
R/W
R/W
R/W
Channel select
Bit 3 Bit 2 Bit 1 Bit 0
CH3 CH2 CH1 CH0 Analog input channel
0
0
1
No channel selected
*
0
*
0
1
0
1
0
1
0
1
0
1
0
1
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
1
0
1
0
1
1
0
1
External trigger select
0
1
Disables start of A/D conversion by external trigger
Enables start of A/D conversion by rising or falling edge
of external trigger at pin ADTRG
Clock select
Bit 7
Conversion Time
CKS Conversion Period ø = 2 MHz ø = 5 MHz
0
1
62/ø
31/ø
31 µs
15.5 µs
12.4 µs
*1
—
Notes: * Don’t care
1. Operation is not guaranteed if the conversion time is less than 12.4 µs.
Set bit 7 for a value of at least 12.4 µs.
432
ADRR—A/D result register
H'C5
A/D converter
Bit
7
6
5
4
3
2
1
0
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
Initial value
Read/Write
Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed
R
R
R
R
R
R
R
R
A/D conversion result
ADSR—A/D start register
H'C6
A/D converter
Bit
7
ADSF
0
6
5
4
—
1
3
—
1
2
1
0
—
1
—
1
—
1
—
1
—
1
Initial value
Read/Write
R/W
—
—
—
—
—
—
—
A/D status flag
0
Read Indicates the completion of A/D conversion
Write Stops A/D conversion
1
Read Indicates A/D conversion in progress
Write Starts A/D conversion
433
PMR1—Port mode register 1
H'C8
I/O ports
Bit
7
IRQ3
0
6
IRQ2
0
5
IRQ1
0
4
PWM
0
3
2
1
0
TMIG TMOFH TMOFL TMOW
Initial value
Read/Write
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P10/TMOW pin function switch
0
1
Functions as P10 I/O pin
Functions as TMOW output pin
P11/TMOFL pin function switch
0
1
Functions as P11 I/O pin
Functions as TMOFL output pin
P12/TMOFH pin function switch
0
1
Functions as P12 I/O pin
Functions as TMOFH output pin
P13/TMIG pin function switch
0
1
Functions as P13 I/O pin
Functions as TMIG input pin
P14/PWM pin function switch
0
1
Functions as P14 I/O pin
Functions as PWM output pin
P15/IRQ1/TMIB pin function switch
0
1
Functions as P15 I/O pin
Functions as IRQ1/TMIB input pin
P16/IRQ2/TMIC pin function switch
0
1
Functions as P16 I/O pin
Functions as IRQ2/TMIC input pin
P17/IRQ3/TMIF pin function switch
0
1
Functions as P17 I/O pin
Functions as IRQ3/TMIF input pin
434
PMR2—Port mode register 2
H'C9
I/O ports
Bit
7
—
1
6
—
1
5
POF2
0
4
3
IRQ0
0
2
1
UD
0
0
IRQ4
0
NCS
0
POF1
0
Initial value
Read/Write
—
—
R/W
R/W
R/W
R/W
R/W
R/W
P20/IRQ4/ADTRG pin function switch
0
1
Functions as P20 I/O pin
Functions as IRQ4/ADTRG input pin
P21/UD pin function switch
0
1
Functions as P21 I/O pin
Functions as UD input pin
P32/SO1 pin PMOS control
0
1
CMOS output
NMOS open-drain output
P43/IRQ0 pin function switch
0
1
Functions as P43 I/O pin
Functions as IRQ0 input pin
TMIG noise canceller select
0
1
Noise canceller function not selected
Noise canceller function selected
P35/SO2 pin PMOS control
0
1
CMOS output
NMOS open-drain output
435
PMR3—Port mode register 3
H'CA
I/O ports
Bit
7
CS
0
6
STRB
0
5
4
SI2
0
3
2
1
SI1
0
0
SO2
0
SCK2
0
SO12
0
SCK1
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P30/SCK1 pin function switch
0
1
Functions as P30 I/O pin
Functions as SCK1 I/O pin
P31/SI1 pin function switch
0
1
Functions as P31 I/O pin
Functions as SI1 input pin
P32/SO1 pin function switch
0
1
Functions as P32 I/O pin
Functions as SO1 output pin
P33/SCK2 pin function switch
0
1
Functions as P33 I/O pin
Functions as SCK2 I/O pin
P34/SI2 pin function switch
0
1
Functions as P34 I/O pin
Functions as SI2 input pin
P35/SO2 pin function switch
0
1
Functions as P35 I/O pin
Functions as SO2 output pin
P36/STRB pin function switch
0
1
Functions as P36 I/O pin
Functions as STRB output pin
P37/CS pin function switch
0
1
Functions as P37 I/O pin
Functions as CS input pin
436
PMR4—Port mode register 4
H'CB
I/O ports
Bit
7
6
5
4
3
2
1
0
NMOD7 NMOD6 NMOD5 NMOD4 NMOD3 NMOD2 NMOD1 NMOD0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
P2n has CMOS output
P2n has NMOS open-drain output
PMR5—Port mode register 5
H'CC
I/O ports
6
WKP6
0
5
Bit
7
WKP7
0
4
WKP4
0
3
WKP3
0
2
WKP2
0
1
WKP1
0
0
WKP0
0
WKP5
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P5n/WKPn /SEGn + 1 pin function switch
0
1
Functions as P5n I/O pin
Functions as WKPn input pin
RLCTR—LCD RAM relocation register
H'CF
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
—
1
1
0
RLCT1 RLCT0
Initial value
Read/Write
0
0
—
—
—
—
—
—
R/W
R/W
437
PWCR—PWM control register
H'D0
14-bit PWM
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
1
—
1
0
—
1
PWCR0
Initial value
Read/Write
0
—
—
—
—
—
—
—
W
Clock select
0
The input clock is ø/2 (tø* = 2/ø). The conversion period is 16,384/ø,
with a minimum modulation width of 1/ø
1
The input clock is ø/4 (tø* = 4/ø). The conversion period is 32,768/ø,
with a minimum modulation width of 2/ø
Note: *tø: Period of PWM input clock
PWDRU—PWM data register U
H'D1
14-bit PWM
Bit
7
—
1
6
—
1
5
4
3
2
1
0
PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDUR1 PWDRU0
Initial value
Read/Write
0
0
0
0
0
0
—
—
W
W
W
W
W
W
Upper 6 bits of data for generating PWM waveform
PWDRL—PWM data register L
H'D2
14-bit PWM
Bit
7
6
5
4
3
2
1
0
PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Lower 8 bits of data for generating PWM waveform
438
PDR1—Port data register 1
H'D4
I/O ports
Bit
7
P17
0
6
P16
0
5
P15
0
4
P14
0
3
P13
0
2
1
P11
0
0
P10
0
P12
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR2—Port data register 2
H'D5
I/O ports
Bit
7
P27
0
6
P26
0
5
P25
0
4
P24
0
3
P23
0
2
P22
0
1
P21
0
0
P20
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR3—Port data register 3
H'D6
I/O ports
Bit
7
P37
0
6
P36
0
5
P35
0
4
P34
0
3
P33
0
2
P32
0
1
P31
0
0
P30
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR4—Port data register 4
H'D7
I/O ports
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
P43
1
2
P42
0
1
P41
0
0
P40
0
Initial value
Read/Write
—
—
—
—
R
R/W
R/W
R/W
PDR5—Port data register 5
H'D8
I/O ports
Bit
7
P57
0
6
P56
0
5
P55
0
4
P54
0
3
P53
0
2
P52
0
1
P51
0
0
P50
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
439
PDR6—Port data register 6
H'D9
I/O ports
Bit
7
P67
0
6
P66
0
5
P65
0
4
P64
0
3
P63
0
2
1
P61
0
0
P60
0
P62
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR7—Port data register 7
H'DA
I/O ports
Bit
7
P77
0
6
P76
0
5
P75
0
4
P74
0
3
P73
0
2
P72
0
1
P71
0
0
P70
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR8—Port data register 8
H'DB
I/O ports
Bit
7
P87
0
6
P86
0
5
P85
0
4
P84
0
3
P83
0
2
P82
0
1
P81
0
0
P80
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR9—Port data register 9
H'DC
I/O ports
Bit
7
P97
0
6
P96
0
5
P95
0
4
P94
0
3
P93
0
2
P92
0
1
P91
0
0
P90
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDRA—Port data register A
H'DD
I/O ports
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
2
1
0
PA3
0
PA2
0
PA1
0
PA0
0
Initial value
Read/Write
_
—
—
—
R/W
R/W
R/W
R/W
440
PDRB—Port data register B
H'DE
I/O ports
Bit
7
6
5
4
3
2
1
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Initial value
Read/Write
R
R
R
R
R
R
R
R
PDRC—Port data register C
H'DF
I/O ports
Bit
7
6
5
4
3
2
1
0
—
—
—
—
PC3
PC2
PC1
PC0
Initial value
Read/Write
—
—
—
—
R
R
R
R
PUCR1—Port pull-up control register 1
H'E0
I/O ports
Bit
7
6
5
4
3
2
1
0
PUCR17 PUCR1 PUCR15 PUCR1 PUCR13 PUCR12 PUCR11 PUCR10
6
4
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR3—Port pull-up control register 3
H'E1
I/O ports
Bit
7
6
5
4
3
2
1
0
PUCR37 PUCR36 PUCR35 PUCR34 PUCR33 PUCR32 PUCR31 PUCR30
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR5—Port pull-up control register 5
H'E2
I/O ports
Bit
7
6
5
4
3
2
1
0
PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
441
PUCR6—Port pull-up control register 6
H'E3
I/O ports
Bit
7
6
5
4
3
2
1
0
PUCR67 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PCR1—Port control register 1
H'E4
I/O ports
Bit
7
PCR17
0
6
5
4
3
2
1
0
PCR16 PCR15 PCR14 PCR13 PCR12 PCR11 PCR10
Initial value
Read/Write
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 1 input/output select
0
1
Input pin
Output pin
PCR2—Port control register 2
H'E5
I/O ports
Bit
7
PCR27
0
6
5
4
3
2
1
0
PCR26 PCR25 PCR24 PCR23 PCR22 PCR21 PCR20
Initial value
Read/Write
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 2 input/output select
0
1
Input pin
Output pin
442
PCR3—Port control register 3
H'E6
I/O ports
Bit
7
PCR37
0
6
5
4
3
2
1
0
PCR36 PCR35 PCR34 PCR33 PCR32 PCR31 PCR30
Initial value
Read/Write
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 3 input/output select
0
1
Input pin
Output pin
PCR4—Port control register 4
H'E7
I/O ports
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
2
1
0
—
1
PCR42 PCR41 PCR40
Initial value
Read/Write
0
0
0
—
—
—
—
—
W
W
W
Port 4 input/output select
0
1
Input pin
Output pin
PCR5—Port control register 5
H'E8
I/O ports
Bit
7
PCR57
0
6
5
4
3
2
1
0
PCR56 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50
Initial value
Read/Write
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 5 input/output select
0
1
Input pin
Output pin
443
PCR6—Port control register 6
H'E9
I/O ports
Bit
7
6
5
4
3
2
1
0
PCR67 PCR66 PCR65 PCR64 PCR63 PCR62 PCR61 PCR60
Initial value
Read/Write
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 6 input/output select
0
1
Input pin
Output pin
PCR7—Port control register 7
H'EA
I/O ports
Bit
7
PCR77
0
6
5
4
3
2
1
0
PCR76 PCR75 PCR74 PCR73 PCR72 PCR71 PCR70
Initial value
Read/Write
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 7 input/output select
0
1
Input pin
Output pin
PCR8—Port control register 8
H'EB
I/O ports
Bit
7
PCR87
0
6
5
4
3
2
1
0
PCR86 PCR85 PCR84 PCR83 PCR82 PCR81 PCR80
Initial value
Read/Write
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 8 input/output select
0
1
Input pin
Output pin
444
PCR9—Port control register 9
H'EC
I/O ports
Bit
7
PCR97
0
6
5
4
3
2
1
0
PCR96 PCR95 PCR94 PCR93 PCR92 PCR91 PCR90
Initial value
Read/Write
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
Port 9 input/output select
0
1
Input pin
Output pin
PCRA—Port control register A
H'ED
I/O ports
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
2
1
0
PCRA3 PCRA2 PCRA1 PCRA0
Initial value
Read/Write
0
0
0
0
—
—
—
—
W
W
W
W
Port A input/output select
0
1
Input pin
Output pin
445
SYSCR1—System control register 1
H'F0
System control
Bit
7
SSBY
0
6
STS2
0
5
STS1
0
4
STS0
0
3
2
—
1
1
—
1
0
—
1
LSON
0
Initial value
Read/Write
R/W
R/W
R/W
R/W
R/W
—
—
—
Low speed on flag
0
1
The CPU operates on the system clock (ø)
The CPU operates on the subclock (øSUB
)
Standby timer select 2 to 0
0
0
1
*
0
1
0
1
Wait time = 8,192 states
Wait time = 16,384 states
Wait time = 32,768 states
Wait time = 65,536 states
Wait time = 131,072 states
1
*
Software standby
0
When a SLEEP instruction is executed in active mode, a transition is
made to sleep mode.
When a SLEEP instruction is executed in subactive mode, a transition is
made to subsleep mode.
1
When a SLEEP instruction is executed in active mode, a transition is
made to standby mode or watch mode.
When a SLEEP instruction is executed in subactive mode, a transition is
made to watch mode.
Note: *Don’t care
446
SYSCR2—System control register 2
H'F1
System control
Bit
7
—
1
6
—
1
5
—
1
4
3
2
1
0
NESEL DTON MSON
SA1
0
SA0
0
Initial value
Read/Write
0
0
0
—
—
—
R/W
R/W
R/W
R/W
R/W
Medium speed on flag
Subactive mode clock select
0
1
Operates in active (high-speed) mode
Operates in active (medium-speed) mode
0
0
1
øW/8
øW/4
øW/2
1
*
Direct transfer on flag
0
When a SLEEP instruction is executed in active mode, a transition is
made to standby mode, watch mode, or sleep mode.
When a SLEEP instruction is executed in subactive mode, a transition is
made to watch mode or subsleep mode.
1
When a SLEEP instruction is executed in active (high-speed) mode, a direct
transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1.
When a SLEEP instruction is executed in active (medium-speed) mode, a direct
transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1.
When a SLEEP instruction is executed in subactive mode, a direct
transition is made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0,
and MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1,
LSON = 0, and MSON = 1.
Noise elimination sampling frequency select
0
1
Sampling rate is øOSC/16
Sampling rate is øOSC/4
Note: *Don’t care
447
IEGR—IRQ edge select register
H'F2
System control
Bit
7
—
1
6
—
1
5
—
1
4
IEG4
0
3
IEG3
0
2
1
IEG1
0
0
IEG0
0
IEG2
0
Initial value
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
IRQ0 edge select
0
1
Falling edge of IRQ0 pin input is detected
Rising edge of IRQ0 pin input is detected
IRQ1 edge select
0
1
Falling edge of IRQ1/TMIB pin input is detected
Rising edge of IRQ1/TMIB pin input is detected
IRQ2 edge select
0
1
Falling edge of IRQ2/TMIC pin input is detected
Rising edge of IRQ2/TMIC pin input is detected
IRQ3 edge select
0
1
Falling edge of IRQ3/TMIF pin input is detected
Rising edge of IRQ3/TMIF pin input is detected
IRQ4 edge select
0
1
Falling edge of IRQ4/ADTRG pin input is detected
Rising edge of IRQ4/ADTRG pin input is detected
448
IENR1—Interrupt enable register 1
H'F3
System control
Bit
7
IENTA
0
6
5
4
IEN4
0
3
IEN3
0
2
1
IEN1
0
0
IEN0
0
IENS1 IENWP
IEN2
0
Initial value
Read/Write
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IRQ4 to IRQ0 interrupt enable
0
1
Disables interrupt request IRQ n
Enables interrupt request IRQ n
(n = 4 to 0)
Wakeup interrupt enable
0
1
Disables interrupt requests from WKP7 to WKP0
Enables interrupt requests from WKP7 to WKP0
SCI1 interrupt enable
0
1
Disables SCI1 interrupts
Enables SCI1 interrupts
Timer A interrupt enable
0
1
Disables timer A interrupts
Enables timer A interrupts
449
IENR2—Interrupt enable register 2
H'F4
System control
Bit
7
IENDT
0
6
5
4
3
2
1
0
IENAD IENS2 IENTG IENTFH IENTFL IENTC IENTB
Initial value
Read/Write
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Timer B interrupt enable
0
1
Disables timer B interrupts
Enables timer B interrupts
Timer C interrupt enable
0
1
Disables timer C interrupts
Enables timer C interrupts
Timer FL interrupt enable
0
1
Disables timer FL interrupts
Enables timer FL interrupts
Timer FH interrupt enable
0
1
Disables timer FH interrupts
Enables timer FH interrupts
Timer G interrupt enable
0
1
Disables timer G interrupts
Enables timer G interrupts
SCI2 interrupt enable
0
1
Disables SCI2 interrupts
Enables SCI2 interrupts
A/D converter interrupt enable
0
1
Disables A/D converter interrupt requests
Enables A/D converter interrupt requests
Direct transfer interrupt enable
0
1
Disables direct transfer interrupt requests
Enables direct transfer interrupt requests
450
IRR1—Interrupt request register 1
H'F6
System control
Bit
7
6
5
—
1
4
3
2
1
0
IRRTA IRRS1
IRRI4
0
IRRI3
0
IRRI2
0
IRRI1
0
IRRI0
0
Initial value
Read/Write
0
0
R/W*
R/W*
—
R/W*
R/W*
R/W*
R/W*
R/W*
IRQ4 to IRQ0 interrupt request flag
0
[Clearing condition]
When IRRIn = 1, it is cleared by writing 0
1
[Setting condition]
When pin IRQn is set to interrupt input and the designated signal edge is
detected
(n = 4 to 0)
SCI1 interrupt request flag
0
[Clearing condition]
When IRRS1 = 1, it is cleared by writing 0
1
[Setting condition]
When an SCI1 transfer is completed
Timer A interrupt request flag
0
[Clearing condition]
When IRRTA = 1, it is cleared by writing 0
1
[Setting condition]
When the timer A counter overflows from H'FF to H'00
Note: * Only a write of 0 for flag clearing is possible.
451
IRR2—Interrupt request register 2
H'F7
System control
Bit
7
6
5
4
3
2
1
0
IRRDT IRRAD IRRS2 IRRTG IRRTFH IRRTFL IRRTC IRRTB
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Timer B interrupt request flag
0
1
[Clearing condition] When IRRTB = 1, it is cleared by writing 0
[Setting condition] When the timer B counter overflows from
H'FF to H'00
Timer C interrupt request flag
0
1
[Clearing condition] When IRRTC = 1, it is cleared by writing 0
[Setting condition] When the timer C counter overflows from H'FF to H'00
or underflows from H'00 to H'FF
Timer FL interrupt request flag
0
1
[Clearing condition] When IRRTFL = 1, it is cleared by writing 0
[Setting condition] When counter FL matches output compare register FL
in 8-bit mode
Timer FH interrupt request flag
0
1
[Clearing condition] When IRRTFH = 1, it is cleared by writing 0
[Setting condition] When counter FH matches output compare register FH in
8-bit mode, or when 16-bit counter F (TCFL, TCFH)
matches 16-bit output compare register F (OCRFL,
OCRFH) in 16-bit mode
Timer G interrupt request flag
0
1
[Clearing condition] When IRRTG = 1, it is cleared by writing 0
[Setting condition] When pin TMIG is set to TMIG input and the
designated signal edge is detected
SCI2 interrupt request flag
0
1
[Clearing condition] When IRRS2 = 1, it is cleared by writing 0
[Setting condition] When an SCI2 transfer is completed or aborted
A/D converter interrupt request flag
0
1
[Clearing condition] When IRRAD = 1, it is cleared by writing 0
[Setting condition] When A/D conversion is completed and ADSF is reset
Direct transfer interrupt request flag
0
1
[Clearing condition] When IRRDT = 1, it is cleared by writing 0
[Setting condition] A SLEEP instruction is executed when DTON = 1 and a direct
transfer is made
Note: * Only a write of 0 for flag clearing is possible.
452
IWPR—Wakeup interrupt request register
H'F9
System control
Bit
7
6
5
4
3
2
1
0
IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Wakeup interrupt request flag
0
[Clearing condition]
When IWPFn = 1, it is cleared by writing 0
[Setting condition]
1
When pin WKPn is set to interrupt input and a falling signal edge is detected
(n = 7 to 0)
Note: * Only a write of 0 for flag clearing is possible.
453
Appendix C I/O Port Block Diagrams
C.1 Schematic Diagram of Port 1
SBY (low level during reset and in standby mode)
Internal
data bus
PUCR1n
VCC
VCC
PMR1n
PDR1n
PCR1n
P1n
VSS
IRQn – 4
PDR1: Port data register 1
PCR1: Port control register 1
PMR1: Port mode register 1
PUCR1: Port pull-up control register 1
n = 5 to 7
Figure C-1 (a) Port 1 Block Diagram (Pins P1 to P1 )
7
5
454
PWM module
PWM
SBY
Internal
data bus
PUCR14
VCC
VCC
PMR14
PDR14
PCR14
P14
VSS
PDR1: Port data register 1
PCR1: Port control register 1
PMR1: Port mode register 1
PUCR1: Port pull-up control register 1
Figure C-1 (b) Port 1 Block Diagram (Pin P1 )
4
455
SBY
Internal
data bus
PUCR1
3
VCC
VCC
PMR13
PDR13
PCR13
P13
VSS
Timer G module
TMIG
PDR1: Port data register 1
PCR1: Port control register 1
PMR1: Port mode register 1
PUCR1: Port pull-up control register 1
Figure C-1 (c) Port 1 Block Diagram (Pin P1 )
3
456
Timer F module
TMOFH (P12 )
TMOFL (P11)
SBY
Internal
data bus
PUCR1n
PMR1n
PDR1n
PCR1n
VCC
VCC
P1n
VSS
PDR1: Port data register 1
PCR1: Port control register 1
PMR1: Port mode register 1
PUCR1: Port pull-up control register 1
n = 2, 1
Figure C-1 (d) Port 1 Block Diagram (Pins P1 and P1 )
2
1
457
Timer A module
TMOW
SBY
Internal
data bus
PUCR10
VCC
VCC
PMR10
PDR10
PCR10
P10
VSS
PDR1: Port data register 1
PCR1: Port control register 1
PMR1: Port mode register 1
PUCR1: Port pull-up control register 1
Figure C-1 (e) Port 1 Block Diagram (Pin P1 )
0
458
C.2 Schematic Diagram of Port 2
Internal
data bus
SBY
PMR4n
VCC
P2n
PDR2n
PCR2n
VSS
PDR2: Port data register 2
PCR2: Port control register 2
PMR4: Port mode register 4
n = 2 to 7
Figure C-2 (a) Port 2 Block Diagram (Pins P2 to P2 )
7
2
459
SBY
Internal
data bus
PMR41
VCC
PMR21
PDR21
PCR21
P21
VSS
Timer C module
UD
PDR2: Port data register 2
PCR2: Port control register 2
PMR2: Port mode register 2
PMR4: Port mode register 4
Figure C-2 (b) Port 2 Block Diagram (Pin P2 )
1
460
SBY
Internal
data bus
PMR40
PMR20
PDR20
PCR20
VCC
P20
VSS
IRQ4
PDR2: Port data register 2
PCR2: Port control register 2
PMR2: Port mode register 2
PMR4: Port mode register 4
Figure C-2 (c) Port 2 Block Diagram (Pin P2 )
0
461
C.3 Schematic Diagram of Port 3
SBY
Internal
data bus
PUCR37
VCC
VCC
PMR37
PDR37
PCR37
P37
VSS
SCI2 module
CS
PDR3: Port data register 3
PCR3: Port control register 3
PMR3: Port mode register 3
PUCR3: Port pull-up control register 3
Figure C-3 (a) Port 3 Block Diagram (Pin P3 )
7
462
SCI2 module
STRB
SBY
Internal
data bus
PUCR36
PMR36
PDR36
PCR36
VCC
VCC
P36
VSS
PDR3: Port data register 3
PCR3: Port control register 3
PMR3: Port mode register 3
PUCR3: Port pull-up control register 3
Figure C-3 (b) Port 3 Block Diagram (Pin P3 )
6
463
SCI2 module
HZS02N
SO2
PMR25
SBY
Internal
data bus
PUCR35
VCC
VCC
PMR35
PDR35
PCR35
P35
VSS
PDR3: Port data register 3
PCR3: Port control register 3
PMR3: Port mode register 3
PMR2: Port mode register 2
PUCR3: Port pull-up control register 3
Figure C-3 (c) Port 3 Block Diagram (Pin P3 )
5
464
SBY
Internal
data bus
PUCR3n
VCC
VCC
PMR3n
PDR3n
PCR3n
P3n
VSS
SCI module
SI
PDR3: Port data register 3
PCR3: Port control register 3
PMR3: Port mode register 3
PUCR3: Port pull-up control register 3
n = 1, 4
Figure C-3 (d) Port 3 Block Diagram (Pins P3 and P3 )
4
1
465
SCI module
EXCK
SCKO
SCKI
SBY
PUCR3n
PMR3n
PDR3n
PCR3n
VCC
VCC
P3n
VSS
PDR3: Port data register 3
PCR3: Port control register 3
PMR3: Port mode register 3
PUCR3: Port pull-up control register 3
n = 3, 0
Figure C-3 (e) Port 3 Block Diagram (Pins P3 and P3 )
3
0
466
SCI1 module
SO1
PMR22
SBY
Internal
data bus
PUCR32
VCC
VCC
PMR32
PDR32
PCR32
P32
VSS
PDR3: Port data register 3
PCR3: Port control register 3
PMR3: Port mode register 3
PMR2: Port mode register 2
PUCR3: Port pull-up control register 3
Figure C-3 (f) Port 3 Block Diagram (Pin P3 )
2
467
C.4 Schematic Diagram of Port 4
Internal
data bus
PMR23
P43
IRQ0
PMR2: Port mode register 2
Figure C-4 (a) Port 4 Block Diagram (Pin P4 )
3
SBY
SCI3 module
VCC
TE
TXD
P42
PDR42
PCR42
Internal
data bus
VSS
PDR4: Port data register 4
PCR4: Port control register 4
Figure C-4 (b) Port 4 Block Diagram (Pin P4 )
2
468
SBY
SCI3 module
VCC
RE
RXD
P41
PDR41
PCR41
VSS
PDR4: Port data register 4
PCR4: Port control register 4
Figure C-4 (c) Port 4 Block Diagram (Pin P4 )
1
469
SBY
SCI3 module
SCKIE
SCKOE
SCKO
SCKI
VCC
P40
PDR40
PCR40
VSS
PDR4: Port data register 4
PCR4: Port control register 4
Figure C-4 (d) Port 4 Block Diagram (Pin P4 )
0
470
C.5 Schematic Diagram of Port 5
SBY
Internal
data bus
PUCR5n
VCC
VCC
PMR5n
PDR5n
PCR5n
P5n
VSS
WKPn
PDR5: Port data register 5
PCR5: Port control register 5
PMR5: Port mode register 5
PUCR5: Port pull-up control register 5
n = 0 to 7
Figure C-5 Port 5 Block Diagram
471
C.6 Schematic Diagram of Port 6
SBY
Internal
data bus
PUCR6n
VCC
VCC
P6n
PDR6n
PCR6n
VSS
PDR6: Port data register 6
PCR6: Port control register 6
PUCR4: Port pull-up control register 6
n = 0 to 7
Figure C-6 Port 6 Block Diagram
472
C.7 Schematic Diagram of Port 7
SBY
Internal
data bus
VCC
PDR7n
PCR7n
P7n
VSS
PDR7: Port data register 7
PCR7: Port control register 7
n = 0 to 7
Figure C-7 Port 7 Block Diagram
473
C.8 Schematic Diagram of Port 8
SBY
Internal
data bus
VCC
PDR8n
PCR8n
P8n
VSS
PDR8: Port data register 8
PCR8: Port control register 8
n = 0 to 7
Figure C-8 Port 8 Block Diagram
474
C.9 Schematic Diagram of Port 9
SBY
Internal
data bus
VCC
PDR9n
PCR9n
P9n
VSS
PDR9: Port data register 9
PCR9: Port control register 9
n = 0 to 7
Figure C-9 Port 9 Block Diagram
475
C.10 Schematic Diagram of Port A
SBY
Internal
data bus
VCC
PDRAn
PCRAn
PAn
VSS
PDRA: Port data register A
PCRA: Port control register A
n = 0 to 3
Figure C-10 Port A Block Diagram
476
C.11 Schematic Diagram of Port B
Internal
data bus
PBn
A/D module
DEC
AMR0 to AMR3
VIN
n = 0 to 7
Figure C-11 Port B Block Diagram
C.12 Schematic Diagram of Port C
Internal
data bus
PCn
A/D module
DEC
AMR0 to AMR3
VIN
n = 0 to 3
Figure C-12 Port C Block Diagram
477
Appendix D Port States in the Different Processing States
Table D-1 Port States Overview
Port
P17 to P10 High
impedance
P27 to P20 High
impedance
P37 to P30 High
impedance
P43 to P40 High
impedance
P57 to P50 High
impedance
P67 to P60 High
impedance
P77 to P70 High
impedance
P87 to P80 High
impedance
P97 to P90 High
impedance
PA3 to PA0 High
impedance
PB7 to PB0 High
impedance impedance impedance impedance impedance impedance impedance
PC3 to PC0 High High High High High High High
Reset
Sleep
Subsleep Standby
Watch
Subactive Active
Retained
Retained High
Retained
Functions Functions
impedance*
Retained High
impedance
Retained High
impedance*
Retained High
impedance
Retained High
impedance*
Retained High
impedance*
Retained High
impedance
Retained High
impedance
Retained High
impedance
Retained High
impedance
High
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
High
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
High
Functions Functions
Functions Functions
Functions Functions
Functions Functions
Functions Functions
Functions Functions
Functions Functions
Functions Functions
Functions Functions
High
High
High
impedance impedance impedance impedance impedance impedance impedance
Note: * High level output when MOS pull-up is in on state.
478
Appendix E Product Code Lineup
Table E-1 H8/3834U Series Product Code Lineup
Package
(Hitachi
Package
Code)
Product
Type
Product
Code
Order Code
Name
Mark Code
H8/3837U ZTAT
Standard HD6473837UH HD6473837UH
products
HD6473837UH
HD6473837UF
HD6473837UX
100-pin QFP
(FP-100B)
version
HD6473837UF HD6473837UF
100-pin QFP
(FP-100A)
HD6473837UX HD6473837UX
100-pin TQFP
(TFP-100B)
Mask ROM Standard HD6433837UH HD6433837U(***)H HD6433837U(***)H 100-pin QFP
version
products
(FP-100B)
HD6433837UF HD6433837U(***)F HD6433837U(***)F 100-pin QFP
(FP-100A)
HD6433837UX HD6433837U(***)X HD6433837U(***)X 100-pin TQFP
(TFP-100B)
H8/3836U Mask ROM Standard HD6433836UH HD6433836U(***)H HD6433836U(***)H 100-pin QFP
version
products
(FP-100B)
HD6433836UF HD6433836U(***)F HD6433836U(***)F 100-pin QFP
(FP-100A)
HD6433836UX HD6433836U(***)X HD6433836U(***)X 100-pin TQFP
(TFP-100B)
H8/3835U Mask ROM Standard HD6433835UH HD6433835U(***)H HD6433835U(***)H 100-pin QFP
version
products
(FP-100B)
HD6433835UF HD6433835U(***)F HD6433835U(***)F 100-pin QFP
(FP-100A)
HD6433835UX HD6433835U(***)X HD6433835U(***)X 100-pin TQFP
(TFP-100B)
H8/3834U ZTAT
version
Standard HD6473834UH HD6473834UH
products
HD6473834UH
HD6473834UF
HD6473834UX
100-pin QFP
(FP-100B)
HD6473834UF HD6473834UF
100-pin QFP
(FP-100A)
HD6473834UX HD6473834UX
100-pin TQFP
(TFP-100B)
479
Table E-1 H8/3834U Series Product Code Lineup (cont)
Package
(Hitachi
Package
Code)
Product
Type
Product
Code
Order Code
Name
Mark Code
H8/3834U Mask ROM Standard HD6433834UH HD6433834U(***)H HD6433834U(***)H 100-pin QFP
version
products
(FP-100B)
HD6433834UF HD6433834U(***)F HD6433834U(***)F 100-pin QFP
(FP-100A)
HD6433834UX HD6433834U(***)X HD6433834U(***)X 100-pin TQFP
(TFP-100B)
H8/3833U Mask ROM Standard HD6433833UH HD6433833U(***)H HD6433833U(***)H 100-pin QFP
version
products
(FP-100B)
HD6433833UF HD6433833U(***)F HD6433833U(***)F 100-pin QFP
(FP-100A)
HD6433833UX HD6433833U(***)X HD6433833U(***)X 100-pin TQFP
(TFP-100B)
Note: 1. (***) in mask ROM versions is the ROM code.
480
Appendix F Package Dimensions
Dimensional drawings of H8/3834U Series packages FP-100B, FP-100A, and TFP-100B are
shown in figures F-1, F-2, and F-3 below.
unit: mm
16.0 ± 0.3
14
0.5 mm Pitch
75
51
50
26
76
100
25
1
0.20 ± 0.10
M
0.08
1.0
0 – 10 °
0.50 ± 0.20
0.10
Hitachi code FP-100B
JEDEC code –
EIAJ code
Weight (g)
SC-595-D
–
Figure F-1 FP-100B Package Dimensions
481
unit: mm
24.8 ± 0.4
20.0
0.65 mm Pitch
80
51
50
31
81
100
1
0.30 ± 0.10
30
0.13
0.15
M
2.40
0 – 10 °
1.20 ± 0.20
Hitachi code FP-100A
JEDEC code –
EIAJ code
Weight (g)
SC-580-J
–
Figure F-2 FP-100A Package Dimensions
482
unit: mm
0.5 mm Pitch
16.0 ± 0.2
14.0
75
51
50
26
76
100
1
0.20 ± 0.05
25
M
0.08
1.00
0 – 5°
0.10
0.50 ± 0.10
Hitachi code TFP-100B
JEDEC code –
EIAJ code
Weight (g)
–
–
Figure F-3 TFP-100B Package Dimensions
Note: In case of inconsistencies arising within figures, dimensional drawings listed in the Hitachi
Semiconductor Packages Manual take precedence and are considered correct.
483
H8/3834U Series Hardware Manual
Publication Date: 1st Edition, September 1995
Published by:
Semiconductor and IC Div.
Hitachi, Ltd.
Edited by:
Technical Document Center
Hitachi Microcomputer System Ltd.
Copyright © Hitachi, Ltd., 1995. All rights reserved. Printed in Japan.
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