F4482 [RENESAS]
DIFF-In / SE-Out Quad Path TX DVGA 1300MHz to 2800MHz;
| 型号： | F4482 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | DIFF-In / SE-Out Quad Path TX DVGA 1300MHz to 2800MHz |
| 文件： | 总49页 (文件大小：4251K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DIFF-In / SE-Out Quad Path TX
DVGA 1300MHz to 2800MHz
F4482
Datasheet
Description
Features
The F4482 is a 1300MHz to 2800MHz Quad Path TX DVGA
outfitted with 100Ω differential inputs and 50Ω single-ended
outputs. The device is part of a complete family of VGAs targeting
FDD and TDD applications within the 400MHz to 4200MHz
frequency range.
.
Independent Quad Channels for FDD TX applications
.
RF Range: 1300MHz to 2800MHz
• F4481: 400MHz to 1100MHz
.
.
28dB Typical Maximum Gain at 2100MHz
Precise SPI-Controlled Glitch-FreeTM Gain Adjustment
• 31.5dB Gain Range with 0.5dB Step Size
5.7dB NF at 2100MHz
Using a single 3.3V power supply and only 500mA of ICC, the F4482
provides four independent transmit paths, each with 28dB typical
maximum gain, +34dBm OIP3, +17dBm output P1dB, and 5.7dB
NF. Each channel includes a glitch-free digital step attenuator that
reduces gain by up to 31.5dB in precise 0.5dB steps.
.
.
.
.
.
.
.
.
.
.
+34dBm OIP3 at 2100MHz
+17dBm Output P1dB at 2100MHz
3.3V Supply Voltage
The F4482 is packaged in an 8 × 8 mm 56-LGA, with matched
100Ω differential input and 50Ω single-ended output impedances
for ease of integration into the signal path.
ICC = 500mA
100Ω Differential Input Impedances
50Ω Single-ended Output Impedances
1.8V and 3.3V Logic Support
Competitive Advantage
.
Combines four independent TX channels consisting of an
LPF, LNA, DSA, and Driver in a compact 8 × 8 LGA package
Independent Channel Standby Modes for Power Savings
Operating Temperature (TEP) Range: -40°C to +105°C
.
.
.
.
Low DC power
High linearity
High reliability
.
8 × 8 mm, 56-LGA package
Block Diagram
Uses Renesas’ patented Zero-DistortionTM and Glitch-FreeTM
technologies, providing superior performance and PA damage
protection over the entire RF gain range
Typical Applications
.
.
.
.
4G and 5G Multi-mode, Multi-carrier Transmitters
LTE and UMTS/WCDMA Base Stations
Active Antenna Systems
Digital Radio
© 2020 Renesas Electronics Corporation
1
December 15, 2020
F4482 Datasheet
Contents
Pin Assignments....................................................................................................................................................................................................6
Pin Descriptions.....................................................................................................................................................................................................7
Absolute Maximum Ratings...................................................................................................................................................................................9
Recommended Operating Conditions .................................................................................................................................................................10
Electrical Characteristics – General ....................................................................................................................................................................11
Electrical Characteristics – Band 1 (1300MHz to 1700MHz)...............................................................................................................................14
Electrical Characteristics – Band 2 (1700MHz to 2800MHz)...............................................................................................................................18
Thermal Characteristics.......................................................................................................................................................................................22
Typical Operating Conditions (TOC) ...................................................................................................................................................................22
Typical Performance Characteristics...................................................................................................................................................................23
Programming.......................................................................................................................................................................................................36
Serial Programming....................................................................................................................................................................................36
Device Register Maps .......................................................................................................................................................................36
Serial Mode Default Condition...........................................................................................................................................................38
Timing Associated with Programming the Serial Registers...............................................................................................................38
SPI Timing Intervals ..........................................................................................................................................................................39
Standby Mode Programming......................................................................................................................................................................40
Control Pin Interface...................................................................................................................................................................................41
Evaluation Kit Picture ..........................................................................................................................................................................................42
Evaluation Kit / Applications Circuit.....................................................................................................................................................................43
Evaluation Kit Operation......................................................................................................................................................................................45
Power Supplies...........................................................................................................................................................................................45
Power Supply Setup...................................................................................................................................................................................45
Power-On Procedure..................................................................................................................................................................................45
Power-Off Procedure..................................................................................................................................................................................45
Startup Condition........................................................................................................................................................................................45
Default Channel Power On.........................................................................................................................................................................45
Chip Select (CSb).......................................................................................................................................................................................45
Standby Mode (STBY)................................................................................................................................................................................45
Package Outline Drawings ..................................................................................................................................................................................46
Ordering Information............................................................................................................................................................................................46
Marking Diagram .................................................................................................................................................................................................46
Revision History...................................................................................................................................................................................................46
List of Figures
Figure 1. Pin Assignments for 8 × 8 × 0.65 mm LGA Package – Top View ..........................................................................................................6
Figure 2. Gain vs DSA Setting.............................................................................................................................................................................23
Figure 3. Gain vs Attenuation..............................................................................................................................................................................23
© 2020 Renesas Electronics Corporation
2
December 15, 2020
F4482 Datasheet
Figure 4. Gain at DSA = 0dB...............................................................................................................................................................................23
Figure 5. Gain at DSA = 14dB............................................................................................................................................................................23
Figure 6. Gain at DSA = 31.5dB.........................................................................................................................................................................23
Figure 7. Gain vs Channel (DSA = 0dB)..............................................................................................................................................................23
Figure 8. Reverse Isolation vs DSA Setting.........................................................................................................................................................24
Figure 9. Reverse Isolation vs Attenuation..........................................................................................................................................................24
Figure 10. Reverse Isolation at DSA = 0dB.........................................................................................................................................................24
Figure 11. Reverse Isolation at DSA = 14dB.......................................................................................................................................................24
Figure 12. Reverse Isolation at DSA = 31.5dB....................................................................................................................................................24
Figure 13. Reverse Isolation vs Channel (DSA = 0dB) .......................................................................................................................................24
Figure 14. Input Return Loss vs DSA Setting......................................................................................................................................................25
Figure 15. Input Return Loss vs Attenuation .......................................................................................................................................................25
Figure 16. Input Return Loss at DSA = 0dB ........................................................................................................................................................25
Figure 17. Input Return Loss at DSA = 14dB ......................................................................................................................................................25
Figure 18. Input Return Loss at DSA = 31.5dB ...................................................................................................................................................25
Figure 19. Input Return Loss vs Channel (DSA = 0dB).......................................................................................................................................25
Figure 20. Output Return Loss vs DSA Setting...................................................................................................................................................26
Figure 21. Output Return Loss vs Attenuation.....................................................................................................................................................26
Figure 22. Output Return Loss at DSA = 0dB .....................................................................................................................................................26
Figure 23. Output Return Loss at DSA = 14dB ...................................................................................................................................................26
Figure 24. Output Return Loss at DSA = 31.5dB ................................................................................................................................................26
Figure 25. Output Return Loss vs Channel (DSA = 0dB) ...................................................................................................................................26
Figure 26. Out of Band Rejection (w.r.t. 1.45GHz)..............................................................................................................................................27
Figure 27. Out of Band Rejection vs Channel (w.r.t. 1.45GHz)...........................................................................................................................27
Figure 28. Out of Band Rejection (w.r.t. 2.1GHz)................................................................................................................................................27
Figure 29. Out of Band Rejection vs Channel (w.r.t. 2.1GHz).............................................................................................................................27
Figure 30. Out of Band Rejection (w.r.t. 2.1GHz)................................................................................................................................................27
Figure 31. Out of Band Rejection vs Channel (w.r.t. 2.1GHz).............................................................................................................................27
Figure 32. Absolute Error (INL) ...........................................................................................................................................................................28
Figure 33. Absolute Error (INL) vs Channel.........................................................................................................................................................28
Figure 34. Step Error (DNL) ................................................................................................................................................................................28
Figure 35. Step Error (DNL) vs Channel..............................................................................................................................................................28
Figure 36. Common Mode Rejection...................................................................................................................................................................28
Figure 37. Common Mode Rejection vs Channel................................................................................................................................................28
Figure 38. Amplitude Imbalance..........................................................................................................................................................................29
Figure 39. Amplitude Imbalance vs Channel.......................................................................................................................................................29
Figure 40. Phase Imbalance................................................................................................................................................................................29
Figure 41. Phase Imbalance vs Channel.............................................................................................................................................................29
Figure 42. Phase Shift Relative to DSA = 0dB ....................................................................................................................................................29
Figure 43. Phase Shift Relative to DSA = 0dB vs Channel .................................................................................................................................29
© 2020 Renesas Electronics Corporation
3
December 15, 2020
F4482 Datasheet
Figure 44. Group Delay at DSA = 0dB ................................................................................................................................................................30
Figure 45. Group Delay vs Channel (DSA = 0dB)...............................................................................................................................................30
Figure 46. K Factor..............................................................................................................................................................................................30
Figure 47. Cross Channel vs Channel Group Delay at DSA = 0dB.....................................................................................................................30
Figure 48. Cross Channel vs Channel Group Delay at DSA = 14dB...................................................................................................................30
Figure 49. Cross Channel vs Channel Group Delay at DSA = 28dB...................................................................................................................30
Figure 50. Inter/Intra Channel Isolation at DSA = 0dB ........................................................................................................................................31
Figure 51. Supply Current ...................................................................................................................................................................................31
Figure 52. Noise Figure at DSA = 0dB ................................................................................................................................................................31
Figure 53. Noise Figure at DSA = 14dB ..............................................................................................................................................................31
Figure 54. Noise Figure at DSA = 28dB ..............................................................................................................................................................31
Figure 55. Noise Figure vs Channel (DSA = 0dB)...............................................................................................................................................31
Figure 56. Band 1 OIP3 at DSA = 0dB...............................................................................................................................................................32
Figure 57. Band 1 OIP3 at DSA = 4dB...............................................................................................................................................................32
Figure 58. Band 1 OIP3 at DSA = 14dB.............................................................................................................................................................32
Figure 59. Band 1 OIP3 at DSA = 28dB.............................................................................................................................................................32
Figure 60. Band 2 OIP3 at DSA = 0dB...............................................................................................................................................................32
Figure 61. Band 2 OIP3 at DSA = 4dB...............................................................................................................................................................32
Figure 62. Band 2 OIP3 at DSA = 14dB.............................................................................................................................................................33
Figure 63. Band 2 OIP3 at DSA = 28dB.............................................................................................................................................................33
Figure 64. Band 1 OIP3 vs Channel (DSA = 0dB)..............................................................................................................................................33
Figure 65. Band 2 OIP3 vs Channel (DSA = 0dB)..............................................................................................................................................33
Figure 66. Band 1 OP1dB at DSA = 0dB............................................................................................................................................................33
Figure 67. Band 1 OP1dB at DSA = 4dB............................................................................................................................................................33
Figure 68. Band 1 OP1dB at DSA = 14dB..........................................................................................................................................................34
Figure 69. Band 1 OP1dB at DSA = 28dB..........................................................................................................................................................34
Figure 70. Band 2 OP1dB at DSA = 0dB............................................................................................................................................................34
Figure 71. Band 2 OP1dB at DSA = 4dB............................................................................................................................................................34
Figure 72. Band 2 OP1dB at DSA = 14dB..........................................................................................................................................................34
Figure 73. Band 2 OP1dB at DSA = 28dB..........................................................................................................................................................34
Figure 74. Band 1 OP1dB vs Channel (DSA = 0dB) ..........................................................................................................................................35
Figure 75. Band 2 OP1dB vs Channel (DSA = 0dB) ..........................................................................................................................................35
Figure 76. Register Bit Map for Each Channel....................................................................................................................................................36
Figure 77. Serial Mode Default Condition Upon Initial Power-Up........................................................................................................................38
Figure 78. Timing Diagram Associated with Programming the Serial Register...................................................................................................38
Figure 79. Serial Register Timing Diagram (Timing Spec Intervals are denoted in Blue)....................................................................................39
Figure 80. Control Pin Interface for Signal Integrity.............................................................................................................................................41
Figure 81. Top View ............................................................................................................................................................................................42
Figure 82. Bottom View .......................................................................................................................................................................................42
Figure 83. Electrical Schematic...........................................................................................................................................................................43
© 2020 Renesas Electronics Corporation
4
December 15, 2020
F4482 Datasheet
List of Tables
Table 1. Pin Descriptions.......................................................................................................................................................................................7
Table 2. Absolute Maximum Ratings.....................................................................................................................................................................9
Table 3. Recommended Operating Conditions....................................................................................................................................................10
Table 4. Electrical Characteristics – General.......................................................................................................................................................11
Table 5. Electrical Characteristics – Band 1 (1300MHz to 1700MHz).................................................................................................................14
Table 6. Electrical Characteristics – Band 2 (1700MHz to 2800MHz).................................................................................................................18
Table 7. Package Thermal Characteristics..........................................................................................................................................................22
Table 8. Channel Select Truth Table...................................................................................................................................................................36
Table 9. DVGA Attenuation Word Truth Table ....................................................................................................................................................37
Table 10. SPI Timing Diagram Values for the Serial Mode.................................................................................................................................39
Table 11. STBY Logic Truth Table ......................................................................................................................................................................40
Table 12. Bill of Material (BOM) ..........................................................................................................................................................................44
© 2020 Renesas Electronics Corporation
5
December 15, 2020
F4482 Datasheet
Pin Assignments
Figure 1. Pin Assignments for 8 × 8 × 0.65 mm LGA Package – Top View
EP
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
GND
RFIN_A+
RFIN_A-
GND
GND
STBY_B
GND
RFOUT_B
GND
RFIN_B-
RFIN_B+
VCC_DIG
DATA
7
8
9
NC
GND
CLK
RFIN_C+
RFIN_C-
GND
CSb
10
11
12
13
14
GND
RFOUT_C
GND
RFIN_D-
RFIN_D+
GND
STBY_C
GND
8mm x 8mm
© 2020 Renesas Electronics Corporation
6
December 15, 2020
F4482 Datasheet
Pin Descriptions
Table 1. Pin Descriptions
Number
Name
Description
1, 4, 8, 11,
14, 15, 26,
28, 29, 31,
33, 38, 40,
42, 43, 45, 56
GND
Internally grounded. These pins must be grounded as close to the device as possible.
2
3
5
6
RFIN_A+
RFIN_A-
RFIN_B-
RFIN_B+
Channel A RF differential input. Internally matched to 100Ω. Must use external DC blocks.
Channel B RF differential input. Internally matched to 100Ω. Must use external DC blocks.
No internal connection. It is highly recommended that these pins be connected to a ground via that is located
as close to the pin as possible.
7
NC
9
RFIN_C+
RFIN_C-
RFIN_D-
RFIN_D+
Channel C RF differential input. Internally matched to 100Ω. Must use external DC blocks.
Channel D RF differential input. Internally matched to 100Ω. Must use external DC blocks.
Power Supply. Must place the bypass capacitor as close to the pin as possible.
10
12
13
16, 17, 21,
23, 25, 46,
VCC
48, 50, 54, 55
18
19
RSET_3
Connect external resistor to GND to optimize amplifier performance. Refer to Table 12, Bill of Materials (BOM).
Connect external resistor to GND to optimize amplifier performance. Refer to Table 12, Bill of Materials (BOM).
RDSET_3
Standby channel D. With Logic LOW applied to this pin (or if the pin is left unconnected), channel D enters
STBY mode and is powered off. With Logic HIGH applied to this pin, channel D is powered on and is fully
operational.
20
STBY_D
22
24
27
RSET_4
RDSET_4
RFOUT_D
Connect external resistor to GND to optimize amplifier performance. Refer to Table 12, Bill of Materials (BOM).
Connect external resistor to GND to optimize amplifier performance. Refer to Table 12, Bill of Materials (BOM).
RF output D internally matched to 50Ω. Must use external DC block.
Standby channel C. With Logic LOW applied to this pin (or if the pin is left unconnected), channel C enters
STBY mode and is powered off. With Logic HIGH applied to this pin, channel C is powered on and is fully
operational.
30
STBY_C
32
34
RFOUT_C
CSb
RF output C internally matched to 50Ω. Must use external DC block.
Serial Chip Select. CSb pin can be pulled up to VCC and down to GND. 1.8 V and 3.3 V logic compatible.
© 2020 Renesas Electronics Corporation
7
December 15, 2020
F4482 Datasheet
Number
35
Name
CLK
Description
Serial Clock Input. 1.8 V and 3.3 V logic compatible.
36
DATA
Data write for the 3-wire serial interface. 1.8V and 3.3V logic compatible.
Digital Power Supply. Must place the bypass capacitor as close to the pin as possible.
RF output B internally matched to 50Ω. Must use external DC block.
37
VCC_DIG
RFOUT_B
39
Standby channel B. With Logic LOW applied to this pin (or if the pin is left unconnected), channel B enters
STBY mode and is powered off. With Logic HIGH applied to this pin, channel B is powered on and is fully
operational.
41
STBY_B
44
47
49
RFOUT_A
RDSET_2
RSET_2
RF output A internally matched to 50Ω. Must use external DC block.
Connect external resistor to GND to optimize amplifier performance. Refer to Table 12, Bill of Materials (BOM).
Connect external resistor to GND to optimize amplifier performance. Refer to Table 12, Bill of Materials (BOM).
Standby channel A. With Logic LOW applied to this pin (or if the pin is left unconnected), channel A enters
STBY mode and is powered off. With Logic HIGH applied to this pin, channel A is powered on and is fully
operational.
51
STBY_A
52
53
RDSET_1
RSET_1
Connect external resistor to GND to optimize amplifier performance. Refer to Table 12, Bill of Materials (BOM).
Connect external resistor to GND to optimize amplifier performance. Refer to Table 12, Bill of Materials (BOM).
Exposed paddle. Internally connected to ground. Solder this exposed paddle to a printed circuit board (PCB)
pad that uses multiple ground vias to provide heat transfer out of the device into the PCB ground planes.
These multiple ground vias are also required to achieve the specified RF performance.
– EPAD
© 2020 Renesas Electronics Corporation
8
December 15, 2020
F4482 Datasheet
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device.
Functional operation of the F4482 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Symbol
VCC
Minimum
-0.3
Maximum
+3.6
Units
V
VCC to GND
DATA, CSb, CLK
STBY
VCTL
-0.3
VCC + 0.25
VCC + 0.25
0.3
V
VCTL
-0.3
V
STBY minus VCC voltage (voltage difference)
VSTBY-VCC
IRSET
IRDSET
VRFIN
V
RSET_1, RSET_2, RSET_3, RSET_4 pin maximum output DC current [a]
RDSET_1, RDSET_2, RDSET_3, RDSET_4 pin maximum output DC current [a]
RFIN_A, RFIN_B, RFIN_C, RFIN_D to GND externally applied DC voltage
+1
mA
mA
V
+1
-0.3
+0.3
RFOUT_A, RFOUT_B, RFOUT_C, RFOUT_D to GND externally applied DC
voltage
VRFOUT
VCC - 0.15
VCC + 0.15
+17
V
RF Input Power (RFIN_A, RFIN_B, RFIN_C, RFIN_D) Applied for 24 Hours
Maximum [b]
PIN_MAX24
dBm
Storage Temperature Range
TSTOR
TLEAD
VESDHBM
-65
+150
+260
°C
°C
Lead Temperature (soldering, 10s)
2000
Electrostatic Discharge – HBM
(JEDEC/ESDA JS-001-2012)
V
V
(Class 2)
250
Electrostatic Discharge – CDM
(JEDEC 22-C101F)
VESDCDM
(Class C1)
[a] RSET_1, RSET_2, RSET_3, RSET_4, RDSET_1, RDSET_2, RDSET_3, and RDSET_4 pins MUST be connected to ground with resistors;
otherwise, damage to the part may result. For suggested resistor values, see Table 12.
[b] Exposure to these maximum RF levels can result in significant VCC current draw due to overdriving the amplifier stages.
© 2020 Renesas Electronics Corporation
9
December 15, 2020
F4482 Datasheet
Recommended Operating Conditions
Table 3. Recommended Operating Conditions
Parameter
Power Supply Voltage [a]
Operating Temperature Range
Junction Temperature
Symbol
VCC
Condition
All VCC pins
Minimum
3.15
Typical
Maximum
Units
V
3.3
3.45
+105
+125
1700
2800
Note [c]
TEP
Exposed Paddle Temperature
-40
°C
TJMAX
°C
Band 1 Tuning
1300
1700
RF Frequency Range [b]
fRF
MHz
Band 2 Tuning
Maximum CW Input Power
RF Input Port Impedance
RF Output Port Impedance
PIN_MAX
ZRFI
dBm
Ω
ZS = 100 Ω, ZL = 50Ω
Differential Impedance
Single-ended Impedance
100
50
ZRFO
Ω
[a] Power-on resets will only occur for VCC < 3V. The device is designed to function with any supply voltage ≥ 3V, although performance may be
degraded when operated outside the recommended voltage range.
[b] To optimize RF performance, different matching components might be used as described in the BOM. Using external matching, gain flatness is
optimized from either 1300MHz to 1700MHz (band 1) or 1700MHz to 2800MHz (band 2).
[c] Level = Lower of (-7.5dBm + attenuation setting) or 5dBm.
© 2020 Renesas Electronics Corporation
10
December 15, 2020
F4482 Datasheet
Electrical Characteristics – General
See the F4482 Typical Application Circuit. Unless stated otherwise, specifications apply when operated with VCC = +3.3V, TEP = +25°C,
fRF = 2100MHz, STBY_A = STBY_B = STBY_C = STBY_D = HIGH, ZS = 100Ω differential, ZL = 50Ω single-ended, maximum gain setting,
and output power = 0dBm/tone. EVKit trace and connector losses are de-embedded.
Table 4. Electrical Characteristics – General
Parameter
Logic Input HIGH
Symbol
VIH
Condition
Minimum
Typical
Maximum
Units
1.07 [a]
V
V
Supports both 1.8V and 3.3V
logic
Logic Input LOW
VIL
0.63
5
3.3V Logic
1.8V Logic
3.3V Logic
-5
-5
5
SPI Logic Current
(CSb, CLK, DATA)
ICTL
µA
µA
5
Standby Logic Current
50
IIH, IIL
(STBY_A, STBY_B, STBY_C,
STBY_D)
1.8V Logic
5
30
ICC_4
ICC_3
Four channels on
Three channels on
Two channels on
One channel on
All channels off
490
374
252
135
13
600
Supply Current [b]
mA
ICC_2
ICC_1
Standby Current
ICC_STBY
18
mA
µs
50% STBY to RF output settled
to within ±0.5dB
Power ON Switching Time
tON
1
50% STBY to 35 dBc reduction
of output power
Power OFF Switching Time
tOFF
1
3
µs
Total gain variation over
fRF = 1300MHz to 1700MHz.
Referred to fRF = 1450MHz.
DSA 0dB attenuation.
Total gain variation over
Lineup Out-of-Band Rejection at
Max Gain
fREJECTION
dBc
fRF = 1700MHz to 2800MHz.
Referred to fRF = 2100MHz.
DSA 0dB attenuation.
3
1
6GHz < fRF < 11.75GHz.
Referred to fRF = 2100MHz.
DSA 0dB attenuation.
50
Any 2dB step in the 0dB to
31.5dB range. 50% of CSb to
1% / 99% RF.
Gain Settling Time [c]
GST
0.4
µs
© 2020 Renesas Electronics Corporation
11
December 15, 2020
F4482 Datasheet
Parameter
DSA Adjustment Range
DSA Step Resolution
Symbol
GRANGE
GSTEP
Condition
Minimum
Typical
31.5
0.5
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
1
Maximum
Units
dB
LSB
dB
DSA step: 5.5dB to 6dB.
DSA step: 6dB to 5.5dB.
DSA step: 11.5dB to 12dB.
DSA step: 12dB to 11.5dB.
DSA step: 17.5dB to 18dB.
DSA step: 18dB to 17.5dB.
DSA step: 23.5dB to 24dB.
DSA step: 24dB to 23.5dB.
DSA step: 29.5dB to 30dB.
DSA step: 30dB to 29.5dB.
All Other 0.5dB DSA steps.
All Other 2dB DSA steps.
fRF = 1300MHz to 1800MHz
fRF = 1800MHz to 2800MHz
Adjacent State Attenuator Glitching
ATTNG
dB
1
0.6
1
30
20
Common Mode Rejection
Amplitude Imbalance
CMR
dB
dB
Worst Case
Over fRF
Measures
RFIN- to
=
0.25
0.5
0.75
4
1300MHz to
1800MHz
RFOUT and
IMBALAMP compares
RFOUT to
Worst Case
Over fRF
1800MHz to
2800MHz
=
RFIN+
amplitude.
Measures
RFIN- to
Worst Case
Over fRF
1300MHz to
1800MHz
=
RFOUT and
compares
RFOUT to
Phase Imbalance
IMBALPH
deg
RFIN+ phase.
Deviation is
from ideal 180
degrees
Worst Case
Over fRF
1800MHz to
2800MHz
=
© 2020 Renesas Electronics Corporation
12
December 15, 2020
F4482 Datasheet
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
Serial Clock Speed
fCLK
50
MHz
SPI 3 wire bus. 50% of CSb
falling edge to 50% of CLK rising
edge
CSb to First Serial Clock Rising Edge
Serial Data Hold Time
tLS
10
10
ns
ns
ns
SPI 3 wire bus. 50% of CLK
rising edge to 50% of DATA
falling edge
tH
SPI 3 wire bus. 50% of CLK
rising edge to 50% of CSb rising
edge
Final Serial Clock Rising Edge to CSb
Stability K Factor
tLCS
10
T
EP = -40˚C to +105˚C
KFACTOR
1
10MHz to 9GHz
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these columns that are
not shown in bold italics are confirmed by design characterization.
[b] For input signal power level equal to P1dB, expect DC current to increase above typical value.
[c] Timing is measured after SPI programming is completed (data latched with CSb = HIGH).
© 2020 Renesas Electronics Corporation
13
December 15, 2020
F4482 Datasheet
Electrical Characteristics – Band 1 (1300MHz to 1700MHz)
See the F4482 Typical Application Circuit. Unless stated otherwise, specifications apply when operated with VCC = +3.3V, TEP = +25°C,
fRF = 1450MHz, STBY_A = STBY_B = STBY_C = STBY_D = HIGH, ZS = 100Ω differential, ZL = 50Ω single-ended, maximum gain setting,
and output power = 0dBm/tone. EVKit trace and connector losses are de-embedded.
Table 5. Electrical Characteristics – Band 1 (1300MHz to 1700MHz)
Parameter
RF Input Return Loss
Symbol
RLIN
Condition
Minimum
Typical
19
Maximum
Units
dB
13[a]
12
RF Output Return Loss
Maximum Gain
RLOUT
GMAX
18
dB
DSA = 0dB
26
28
30
16
dB
Mid-Range Gain
Minimum Gain
GMID
DSA = 14dB
DSA = 31.5dB
DSA = 0dB
11.5
-6
14
dB
GMIN
-3.5
-1.5
dB
+0.8 / -1.5
+0.8 / -1.1
Over TEP = -40°C to +105°C,
and relative to 25°C
Gain Variation Over Temperature
GTEMP
dB
DSA = 14dB
Over TEP = -40°C to +105°C,
and relative to 25°C
Gain Flatness
Gain Ripple
GFLAT
Any 400MHz BW
0.4
0.2
dB
dB
GRIPPLE
In any 20MHz range
Worst case difference in Gain
for any 2dB step over the 0dB
to 30dB attenuation range (with
channels A and B both set to
identical DSA attenuation
levels).
Intra-die Channel-to-Channel
Differences in Gain
GA - GB
0.2
dB
DSA = 0dB
-47
-73
Reverse Isolation
GREV
dB
dB
DSA = 31.5dB
Any RF input/output
combination involving
channel A paired with
channel B
Intra-die Channel Isolation [b]
ISOLA-B
50
50
60
60
DSA 0dB Attenuation
Any RF input/output
combination involving
channel B (die 1) paired with
channel C (die 2).
Inter-die Channel Isolation [b]
ISOLB-C
dB
DSA 0dB Attenuation
© 2020 Renesas Electronics Corporation
14
December 15, 2020
F4482 Datasheet
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
Group Delay in Passband
fRF = 1300MHz to 1700MHz
1
2
ns
τ
Any 280MHz band within
Group Delay Ripple
0.1
0.1
1
ns
ns
τRIPPLE
fRF = 1300MHz to 1700MHz
Worst case difference in Group
Delay for any 2dB step over the
0dB to 30dB attenuation range
(with channels A and B both
set to identical DSA attenuation
levels).
Intra-die Channel-to-Channel
Differences in Group Delay
τA - τB
fRF
=
1300MHz to
1700MHz
DSA = 0dB
0.6
0.4
Worst case
cross-channel
leakage
Cross Channel Group Delay in
Passband vs. Channel Group Delay
in Passband
DSA = 14dB
combinations
ns
τXCHANNEL -
τ
(A to B) - B;
(B to A) - A;
(B to C) - C;
(C to B) - B;
(C to D) - D;
(D to C) - C
DSA = 28dB
0.4
Maximum error between
adjacent steps
Step Error (DNL)
ERRORSTEP
±0.1
dB
dB
Over attenuation range
ERRORABS referenced to maximum gain
state
Absolute Error (INL)
Note [c]
ΦΔTemp at 0dB DSA 0dB Attenuation
0.5
0.5
0.5
Phase Shift Over Any 5ºC
Temperature Change Over the -40ºC ΦΔTemp at 14dB DSA 14dB Attenuation
deg
to 105ºC Range
ΦΔTemp at 28dB DSA 28dB Attenuation
Channel A or Channel B Phase
Shifts. Measuring “On State”
phase shifts occurring over
time as the device is powered
on/off via STBY mode or via
PORs (power-on resets).
ΦON-OFF-ON
2
Phase Shift Between Startups
Channel A - Channel B Phase
Shifts. Measuring “On State”
[ΦA – ΦB] ON- phase shifts occurring over
10
time as the device is powered
OFF-ON
on/off via STBY mode or via
PORs (power-on resets).
Phase Shift Between Any 2dB Step
Φ2dB Step
Worst case, any 2dB step
1.2
deg
© 2020 Renesas Electronics Corporation
15
December 15, 2020
F4482 Datasheet
Parameter
Symbol
Φ8dB Step
ΦΔMAX
Condition
Worst case, any 8dB step
DSA 31.5dB Attenuation
DSA 14dB Attenuation
ΦA @ 16dB - ΦB @ 16dB
Minimum
Typical
Maximum
Units
Phase Shift Between Any 8dB Step
5
deg
4.5
1.7
Phase Shift Relative to 0dB
Attenuation State
deg
ΦΔMID
Worst case difference in phase
with channels A and B both set
to DSA = 16dB attenuation
levels.
2.5
0.2
[ΦA @ XdB - ΦB @ XdB] -
deg
Intra-die Channel-to-Channel
Differences in Phase
ΦA - ΦB
[ΦA @ 16dB - ΦB @ 16dB
]
Worst case difference in phase
between the 16dB DSA
attenuation case and any other
state when the DSAs are set to
XdB. X = 16 ± 2N, where N is
an integer ranging from 1 to 8.
DSA = 0dB
5.2
8.4
20
6.6
Noise Figure at Room (25˚C) [d]
Noise Figure at Hot (105˚C) [d]
Noise Figure at Cold (-40˚C) [d]
NFROOM
DSA = 14dB
DSA = 28dB
DSA = 0dB
DSA = 14dB
DSA = 28dB
DSA = 0dB
DSA = 14dB
DSA = 28dB
dB
dB
dB
T
T
T
EP = 25˚C
EP = 105˚C
EP = -40˚C
6.7
10.5
22
NFHOT
4
NFCOLD
7
18.5
© 2020 Renesas Electronics Corporation
16
December 15, 2020
F4482 Datasheet
Parameter
Symbol
Condition
DSA = 0dB
Minimum
Typical
Maximum
Units
TEP = 105˚C
36
POUT = 0dBm / tone
5MHz tone separation
DSA = 4dB
T
EP = 105˚C
36
34
POUT = 0dBm / tone
5MHz tone separation
Output Third Order Intercept Point [d]
OIP3
dBm
DSA = 14dB
T
EP = 25˚C
28.5
POUT = -3dBm / tone
5MHz tone separation
DSA = 28dB
T
EP = -40˚C
20.5
POUT = -13dBm / tone
5MHz tone separation
17
DSA = 0dB, TEP = 105˚C
DSA = 4dB, TEP = 105˚C
DSA = 14dB, TEP = 25˚C
DSA = 28dB, TEP = -40˚C
16.5
14.5
0.6
Output 1dB Compression Point [d]
OP1dB
dBm
12.5
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these columns that are
not shown in bold italics are confirmed by design characterization.
[b] Signal applied to RFIN_X. Measure desired signal at RFOUT_X and compare to undesired leakage signal level at RFOUT_Y.
[c] Absolute Error = +[0.1 + 0.05*(DSA Attenuator Setting)].
[d] Measured by terminating one differential RFIN port to 50Ω load and applying RF signal to second RFIN port.
© 2020 Renesas Electronics Corporation
17
December 15, 2020
F4482 Datasheet
Electrical Characteristics – Band 2 (1700MHz to 2800MHz)
See the F4482 Typical Application Circuit. Unless stated otherwise, specifications apply when operated with VCC = +3.3V, TEP = +25°C,
fRF = 2100MHz, STBY_A = STBY_B = STBY_C = STBY_D = HIGH, ZS = 100Ω differential, ZL = 50Ω single-ended, maximum gain setting,
and output power = 0dBm/tone. EVKit trace and connector losses are de-embedded.
Table 6. Electrical Characteristics – Band 2 (1700MHz to 2800MHz)
Parameter
RF Input Return Loss
Symbol
RLIN
Condition
Minimum
8[a]
Typical
10
Maximum
Units
dB
RF Output Return Loss
Maximum Gain
RLOUT
GMAX
11.5
25.5
11
19
dB
DSA 0dB Attenuation
DSA 14dB Attenuation
DSA 31.5dB Attenuation
DSA 0dB Attenuation
28
29
16
-2
dB
Mid-Range Gain
Minimum Gain
GMID
13.5
-4
dB
GMIN
-6.5
dB
+1 / -1.25
+0.8/ -1.1
Over TEP = -40°C to +105°C,
and relative to 25°C
Gain Variation Over Temperature
GTEMP
dB
DSA 14dB Attenuation
Over TEP = -40°C to +105°C,
and relative to 25°C
Any 400MHz BW
Any 800MHz BW
In any 20MHz range
0.4
0.8
0.2
Gain Flatness
Gain Ripple
GFLAT
dB
dB
GRIPPLE
Worst case difference in Gain
for any 2dB step over the 0dB
to 30dB attenuation range (with
channels A and B both set to
identical DSA attenuation
levels).
Intra-die Channel-to-Channel
Differences in Gain
GA - GB
0.2
dB
dB
DSA 0dB Attenuation
-47
-78
Reverse Isolation
GREV
DSA 31.5dB Attenuation
Any RF input/output
combination involving
channel A paired with
channel B
Intra-die Channel Isolation [b]
ISOLA-B
45
50
50
55
dB
dB
DSA 0dB Attenuation
Any RF input/output
combination involving
channel B (die 1) paired with
channel C (die 2).
Inter-die Channel Isolation [b]
ISOLB-C
DSA 0dB Attenuation
© 2020 Renesas Electronics Corporation
18
December 15, 2020
F4482 Datasheet
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
Group Delay in Passband
fRF = 1700MHz to 2800MHz
1
2
ns
τ
Any 280MHz band within
Group Delay Ripple
0.1
0.6
1
ns
ns
τRIPPLE
fRF = 1700MHz to 2800MHz
f
RF = 170MHz
to 2800MHz
DSA = 0dB
Worst case
cross-channel
leakage
Cross Channel Group Delay in
Passband vs. Channel Group Delay
in Passband
combinations
DSA = 14dB
0.4
0.4
τXCHANNEL -
τ
(A to B) - B;
(B to A) - A;
(B to C) - C;
(C to B) - B;
(C to D) - D;
(D to C) - C
DSA = 28dB
Worst case difference in Group
Delay for any 2dB step over the
0dB to 30dB attenuation range
(with channels A and B both
set to identical DSA attenuation
levels).
Intra-die Channel-to-Channel
Differences in Group Delay
0.1
ns
τA - τB
Maximum error between
adjacent steps
Step Error (DNL)
ERRORSTEP
± 0.1
dB
dB
Over attenuation range
ERRORABS referenced to maximum gain
state
Absolute Error (INL)
Note [c]
ΦΔTemp at 0dB DSA 0dB Attenuation
0.5
0.5
0.5
Phase Shift Over Any 5ºC
Temperature Change Over the -40ºC ΦΔTemp at 14dB DSA 14dB Attenuation
deg
to 105ºC Range
ΦΔTemp at 31.5dB DSA 31.5dB Attenuation
Channel A or Channel B Phase
Shifts. Measuring “On State”
phase shifts occurring over
time as the device is powered
ΦON-OFF-ON
2
on/off via STBY mode or via
PORs (power on resets).
Phase Shift Between Startups
deg
deg
Channel A - Channel B Phase
Shifts. Measuring “On State”
[ΦA – ΦB] ON- phase shifts occurring over
10
time as the device is powered
on/off via STBY mode or via
PORs (power on resets).
OFF-ON
Phase Shift Between Any 2dB Step
Φ2dB Step
Worst case, any 2dB step.
1.2
© 2020 Renesas Electronics Corporation
19
December 15, 2020
F4482 Datasheet
Parameter
Symbol
Φ8dB Step
ΦΔMAX
Condition
Worst case 8dB step
DSA 31.5dB Attenuation
DSA 14dB Attenuation
ΦA @ 16dB - ΦB @ 16dB
Minimum
Typical
Maximum
Units
Phase Shift Between Any 8dB Step
5
deg
8.5
2.7
Phase Shift Relative to 0dB
Attenuation State
deg
deg
ΦΔMID
Worst case difference in phase
with channels A and B both set
to DSA = 16dB attenuation
levels.
2.5
0.2
[ΦA @ XdB - ΦB @ XdB] -
Intra-die Channel-to-Channel
Differences in Phase
ΦA - ΦB
[ΦA @ 16dB - ΦB @ 16dB
]
Worst case difference in phase
between the 16dB DSA
deg
attenuation case and any other
state when the DSAs are set to
XdB. X = 16 ± 2N, where N is
an integer ranging from 1 to 8.
DSA = 0dB
5.7
9
7.1 [a]
Noise Figure at Room (25˚C) [d]
Noise Figure at Hot (105˚C) [d]
Noise Figure at Cold (-40˚C) [d]
NFROOM
DSA = 14dB
DSA = 28dB
DSA = 0dB
DSA = 14dB
DSA = 28dB
DSA = 0dB
DSA = 14dB
DSA = 28dB
dB
dB
dB
T
T
T
EP = 25˚C
EP = 105˚C
EP = -40˚C
20.4
6.6
10.6
22
NFHOT
4.4
7.6
19
NFCOLD
DSA = 0dB
f = 1.8GHz
f = 2.1GHz
f = 2.6GHz
f = 1.8GHz
f = 2.1GHz
f = 2.6GHz
34
35
TEP = 105˚C
Output Third Order Intercept Point
with DSA Set to 0dB Attenuation [d]
POUT = 0dBm /
tone
OIP3 0dB Attn
dBm
dBm
5MHz tone
separation
31
DSA = 4dB
34
TEP = 105˚C
Output Third Order Intercept Point
with DSA Set to 4dB Attenuation [d]
POUT = 0dBm /
tone
OIP3 4dB Attn
33.5
30.5
5MHz tone
separation
© 2020 Renesas Electronics Corporation
20
December 15, 2020
F4482 Datasheet
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
DSA = 14dB
f = 1.8GHz
f = 2.1GHz
31
TEP = 25˚C
Output Third Order Intercept Point
with DSA Set to 14dB Attenuation [d]
POUT = -3dBm /
tone
31.5
32
OIP3 14dB Attn
dBm
5MHz tone
separation
f = 2.6GHz
DSA = 28dB
f = 1.8GHz
f = 2.1GHz
20
TEP = -40˚C
18.5
Output Third Order Intercept Point
with DSA Set to 28dB Attenuation [d]
POUT = -13dBm
/ tone
OIP3 28dB Attn
dBm
f = 2.6GHz
16.5
5MHz tone
separation
f = 1.8GHz
f = 2.1GHz
f = 2.6GHz
f = 1.8GHz
f = 2.1GHz
f = 2.6GHz
f = 1.8GHz
f = 2.1GHz
f = 2.6GHz
f = 1.8GHz
f = 2.1GHz
f = 2.6GHz
16.5
16
DSA = 0dB
Output 1dB Compression Point with
DSA Set to 0dB Attenuation [d]
OP1dB 0dB Attn
OP1dB 4dB Attn
OP1dB 14dB Attn
OP1dB 28dB Attn
dBm
dBm
dBm
dBm
TEP = 105˚C
15
16.5
16
DSA = 4dB
Output 1dB Compression Point with
DSA Set to 4dB Attenuation [d]
TEP = 105˚C
15
12.5
12
14.6
14
DSA = 14dB
Output 1dB Compression Point with
DSA Set to 14dB Attenuation [d]
TEP = 25˚C
12
14
0.9
-0.4
-0.7
DSA = 28dB
Output 1dB Compression Point with
DSA Set to 28dB Attenuation [d]
TEP = -40˚C
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these columns that are
not shown in bold italics are confirmed by design characterization.
[b] Signal applied to RFIN_X. Measure desired signal at RFOUT_X and compare to undesired leakage signal level at RFOUT_Y.
[c] Absolute Error = +[0.1 + 0.05*(DSA Attenuator Setting)].
[d] Measured by terminating one differential RFIN port to 50Ω load and applying RF signal to second RFIN port.
© 2020 Renesas Electronics Corporation
21
December 15, 2020
F4482 Datasheet
Thermal Characteristics
Table 7. Package Thermal Characteristics
Parameter
Symbol
θJA
Value
26.89
3.33
Units
Junction to Ambient Thermal Resistance
°C/W
°C/W
Junction to Case Thermal Resistance (Case is defined as the exposed paddle)
Moisture Sensitivity Rating (Per J-STD-020)
θJC-BOT
MSL 3
Typical Operating Conditions (TOC)
Unless otherwise noted, for the TOC graphs on the following pages, the following conditions apply:
.
.
.
.
.
.
.
.
.
.
.
.
Vcc = 3.3V
ZS = 100Ω Differential
ZL = 50Ω Single Ended
fRF = 1.45GHz (set 1)
fRF = 2.1GHz (set 2)
TEP = +25°C
STBY_A = STBY_B = STBY_C = STBY_D = HIGH (All channels enabled)
POUT = 0dBm / Tone unless otherwise specified for multi-tone tests
5MHz Tone Spacing
Gain setting = Maximum Gain
All temperatures are referenced to the exposed paddle
Evaluation Kit traces and connector losses are de-embedded
© 2020 Renesas Electronics Corporation
22
December 15, 2020
F4482 Datasheet
Typical Performance Characteristics
Figure 2. Gain vs DSA Setting
Figure 3. Gain vs Attenuation
Figure 4. Gain at DSA = 0dB
Figure 5. Gain at DSA = 14dB
Figure 6. Gain at DSA = 31.5dB
Figure 7. Gain vs Channel (DSA = 0dB)
© 2020 Renesas Electronics Corporation
23
December 15, 2020
F4482 Datasheet
Figure 8. Reverse Isolation vs DSA Setting
Figure 9. Reverse Isolation vs Attenuation
Figure 10. Reverse Isolation at DSA = 0dB
Figure 11. Reverse Isolation at DSA = 14dB
Figure 12. Reverse Isolation at DSA = 31.5dB
Figure 13. Reverse Isolation vs Channel (DSA =
0dB)
© 2020 Renesas Electronics Corporation
24
December 15, 2020
F4482 Datasheet
Figure 14. Input Return Loss vs DSA Setting
Figure 15. Input Return Loss vs Attenuation
Figure 16. Input Return Loss at DSA = 0dB
Figure 17. Input Return Loss at DSA = 14dB
Figure 18. Input Return Loss at DSA = 31.5dB
Figure 19. Input Return Loss vs Channel (DSA =
0dB)
© 2020 Renesas Electronics Corporation
25
December 15, 2020
F4482 Datasheet
Figure 20. Output Return Loss vs DSA Setting
Figure 21. Output Return Loss vs Attenuation
Figure 22. Output Return Loss at DSA = 0dB
Figure 23. Output Return Loss at DSA = 14dB
Figure 24. Output Return Loss at DSA = 31.5dB
Figure 25. Output Return Loss vs Channel (DSA
= 0dB)
© 2020 Renesas Electronics Corporation
26
December 15, 2020
F4482 Datasheet
Figure 26. Out of Band Rejection (w.r.t.
1.45GHz)
Figure 27. Out of Band Rejection vs Channel
(w.r.t. 1.45GHz)
Figure 28. Out of Band Rejection (w.r.t. 2.1GHz)
Figure 29. Out of Band Rejection vs Channel
(w.r.t. 2.1GHz)
Figure 30. Out of Band Rejection (w.r.t. 2.1GHz)
Figure 31. Out of Band Rejection vs Channel
(w.r.t. 2.1GHz)
© 2020 Renesas Electronics Corporation
27
December 15, 2020
F4482 Datasheet
Figure 32. Absolute Error (INL)
Figure 33. Absolute Error (INL) vs Channel
Figure 34. Step Error (DNL)
Figure 35. Step Error (DNL) vs Channel
Figure 36. Common Mode Rejection
Figure 37. Common Mode Rejection vs Channel
© 2020 Renesas Electronics Corporation
28
December 15, 2020
F4482 Datasheet
Figure 38. Amplitude Imbalance
Figure 39. Amplitude Imbalance vs Channel
Figure 40. Phase Imbalance
Figure 41. Phase Imbalance vs Channel
Figure 42. Phase Shift Relative to DSA = 0dB
Figure 43. Phase Shift Relative to DSA = 0dB vs
Channel
© 2020 Renesas Electronics Corporation
29
December 15, 2020
F4482 Datasheet
Figure 44. Group Delay at DSA = 0dB
Figure 45. Group Delay vs Channel (DSA = 0dB)
Figure 46. K Factor
Figure 47. Cross Channel vs Channel Group
Delay at DSA = 0dB
Figure 48. Cross Channel vs Channel Group
Delay at DSA = 14dB
Figure 49. Cross Channel vs Channel Group
Delay at DSA = 28dB
© 2020 Renesas Electronics Corporation
30
December 15, 2020
F4482 Datasheet
Figure 50. Inter/Intra Channel Isolation at DSA =
0dB
Figure 51. Supply Current
Figure 52. Noise Figure at DSA = 0dB
Figure 53. Noise Figure at DSA = 14dB
Figure 54. Noise Figure at DSA = 28dB
Figure 55. Noise Figure vs Channel (DSA = 0dB)
© 2020 Renesas Electronics Corporation
31
December 15, 2020
F4482 Datasheet
Figure 56. Band 1 OIP3 at DSA = 0dB
Figure 58. Band 1 OIP3 at DSA = 14dB
Figure 60. Band 2 OIP3 at DSA = 0dB
Figure 57. Band 1 OIP3 at DSA = 4dB
Figure 59. Band 1 OIP3 at DSA = 28dB
Figure 61. Band 2 OIP3 at DSA = 4dB
© 2020 Renesas Electronics Corporation
32
December 15, 2020
F4482 Datasheet
Figure 62. Band 2 OIP3 at DSA = 14dB
Figure 64. Band 1 OIP3 vs Channel (DSA = 0dB)
Figure 66. Band 1 OP1dB at DSA = 0dB
Figure 63. Band 2 OIP3 at DSA = 28dB
Figure 65. Band 2 OIP3 vs Channel (DSA = 0dB)
Figure 67. Band 1 OP1dB at DSA = 4dB
© 2020 Renesas Electronics Corporation
33
December 15, 2020
F4482 Datasheet
Figure 68. Band 1 OP1dB at DSA = 14dB
Figure 70. Band 2 OP1dB at DSA = 0dB
Figure 72. Band 2 OP1dB at DSA = 14dB
Figure 69. Band 1 OP1dB at DSA = 28dB
Figure 71. Band 2 OP1dB at DSA = 4dB
Figure 73. Band 2 OP1dB at DSA = 28dB
© 2020 Renesas Electronics Corporation
34
December 15, 2020
F4482 Datasheet
Figure 74. Band 1 OP1dB vs Channel (DSA =
0dB)
Figure 75. Band 2 OP1dB vs Channel (DSA =
0dB)
© 2020 Renesas Electronics Corporation
35
December 15, 2020
F4482 Datasheet
Programming
The F4482 uses a variety of programming options that can control the on-chip attenuators and band-select functions. The following sections
provide specific details on each unique programming mode.
Serial Programming
The F4482 includes a SPI interface that is primarily used to program the device’s on-chip attenuators.
Device Register Maps
Each channel of the VGA uses an 8-bit addressing word followed by an 8-bit data word to execute the attenuation level commands. Figure 76
shows the various bit assignments for each channel register.
Figure 76. Register Bit Map for Each Channel
Address Word A7 – A0
Data Word D7 – D0
CH
SEL
CH
SEL SEL
CH
8 dB
4 dB
2 dB
0.5 dB
16 dB
1 dB
RSV RSV RSV RSV RSV
RSV
D6
RSV
A7
A6
A5
A4
A3
A2
A1
A0
D7
D5
D4
D3
D2 D1
D0
LSB
MSB
LSB
MSB
The register address word (Bits A7-A0) includes five reserve bits (A7-A3) followed by three channel addressing bits (A2-A0). The “Channel
Select” truth table is provided in Table 8.
Table 8. Channel Select Truth Table
Reserve
A5
Address Bits
A1
Channel Select
A7
A6
A4
A3
A2
A0
Channel A
Channel B
Channel C
Channel D
X
X
X
X
X
X
X
X
0
0
0
1
1
0
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
1
0
1
Channel A and B
X
X
X
X
X
X
X
X
X
X
1
1
0
1
X
X
(Simultaneous Programming)
Channel C and D
(Simultaneous Programming)
Note that address bit A2 is used to select either individual channel programming (logic LOW) or dual channel programming (logic HIGH).
Simultaneous programming of channels A and B is achieved when setting bit A2 to a logic HIGH and A1 a logic LOW. Simultaneous
programming of channels C and D occurs when bits A2 and A1 are both logic HIGHs.
© 2020 Renesas Electronics Corporation
36
December 15, 2020
F4482 Datasheet
Table 9 represents the truth table for the attenuator control bits. A full scale DSA setting of 000000 drives the channel DSA into its minimum
attenuation state. Conversely, a setting of 111111 drives the channel DSA into its maximum attenuation state. Note that D5 is defined as the
Most Significant Bit (MSB) for the attenuator control function within each respective channel.
Table 9. DVGA Attenuation Word Truth Table
Reserve
Control Bits
D2
Attenuation
Setting (dB)
D7
X
D6
X
D5
0
D4
0
D3
0
D1
0
D0
0
0.0
0.5
0
0
0
1
0
0
0
1
X
X
0
0
0
0
1
1.0
X
X
0
0
0
1
0
2.0
X
X
0
0
0
0
0
4.0
X
X
0
0
1
0
0
8.0
X
X
0
1
0
0
0
16.0
31.5
X
X
1
0
0
0
0
X
X
1
1
1
1
1
It should also be noted that the listing above represents an abbreviated version of the complete 6-bit attenuator control truth table. Any attenuator
combination of 0.5dB, 1dB, 2dB, 4dB, 8dB, and 16dB can be achieved by simply assigning a logic HIGH in the respective control bit. For
instance, to achieve an attenuation setting of 21.5dB within a given channel, assign a logic HIGH to bits D0, D1, D3, and D5 while assigning a
logic LOW to bits D2 and D4. Doing so selects a combination of 0.5dB (D0) + 1dB (D1) + 4dB (D3) + 16dB (D5) = 21.5dB. Setting all of the
control bits to logic HIGH will step in all of the attenuator stages.
© 2020 Renesas Electronics Corporation
37
December 15, 2020
F4482 Datasheet
Serial Mode Default Condition
When the device is first powered on, each channel’s DSA will default to its Maximum Attenuation setting as shown in Figure 77. These
settings apply to a hard reset when first applying VCC.
Figure 77. Serial Mode Default Condition Upon Initial Power-Up
Channel A D7 – D0 Register Defaults
1
1
1
1
1
1
1
1
D7
D6
D5
D4
D3
D2 D1
D0
Channel B D7 – D0 Register Defaults
1
1
1
1
1
1
1
1
D7
D6
D5
D4
D3
D2 D1
D0
All Channels
Set With
31.5dB Attenuation
Channel C D7 – D0 Register Defaults
1
1
1
1
1
1
1
1
D7
D6
D5
D4
D3
D2 D1
D0
Channel D D7 – D0 Register Defaults
1
1
1
1
1
1
1
1
D7
D6
D5
D4
D3
D2 D1
D0
Timing Associated with Programming the Serial Registers
To program each channel, the Address Word and Data Word must be clocked in sequentially with the Most Significant Bit (MSB) first (see
Figure 78).
Figure 78. Timing Diagram Associated with Programming the Serial Register
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
CSb
Data Word
Latched into
Register
Address Word A7 – A0
Data Word D7 – D0
CH
CH
CH
1 dB
16 dB
D5
0.5 dB
8 dB
D4
4 dB
D3
2 dB
D2
0
DATA
0
0
0
0
0
0
SEL SEL SEL
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D1
D0
MSB
LSB
MSB
LSB
Increasing Time
© 2020 Renesas Electronics Corporation
38
December 15, 2020
F4482 Datasheet
SPI Timing Intervals
Figure 79 shows the relevant SPI timing intervals which are specified in Table 10.
Note: The F4482 includes a CLK inhibit feature designed to minimize sensitivity to CLK bus noise when the device is not being programmed.
When CSb is high (> VIH), the CLK input is disabled and serial data (DATA) is not clocked into the shift register. It is recommended that CSb be
pulled high (> VIH) when the device is not being programmed.
Figure 79. Serial Register Timing Diagram (Timing Spec Intervals are denoted in Blue)
tH
tP
tCLS
tLC
tS
tCH
tCL
CLK
DATA
MSB
LSB
tLS
CSb
tL
tL
Time
Table 10. SPI Timing Diagram Values for the Serial Mode
Parameter
CLK Frequency
Symbol
Test Condition
Minimum
Typical
Maximum
Units
MHz
ns
fC
tCH
tCL
tS
20
CLK High Duration Time
CLK Low Duration Time
DATA to CLK Setup Time
CLK Period [a]
20
20
10
40
10
ns
ns
tP
ns
CLK to DATA Hold Time
tH
ns
Final CLK Rising Edge to CSb Rising
Edge
tCLS
10
ns
CSb to CLK Setup Time
CSb Trigger Pulse Width
tLS
tL
10
10
10
ns
ns
ns
CSb Trigger to CLK Setup Time [b]
tLC
[a] (TCH + TCL) ≥ 1/FC
[b] Once all desired DATA is clocked in, tLC represents the time a CSb high needs to occur before any subsequent CLK signals.
© 2020 Renesas Electronics Corporation
39
December 15, 2020
F4482 Datasheet
Standby Mode Programming
Each F4482 channel can be placed into a standby mode via the dedicated Channel STBY pins (STBY_A, STBY_B, STBY_C, and STBY_D);
for information, see truth table shown in Table 11). Note that when a channel is disabled, the serial register for that channel will hold the last
enabled DSA state.
Table 11. STBY Logic Truth Table
STBY_X Pin
Channel
Logic
Channel Power State
0
Channel A Standby (SPI still active)
A
1
0
1
0
1
0
1
Channel A Power On
Channel B Standby (SPI still active)
Channel B Power On
B
C
D
Channel C Standby (SPI still active)
Channel C Power On
Channel D Standby (SPI still active)
Channel D Power On
© 2020 Renesas Electronics Corporation
40
December 15, 2020
F4482 Datasheet
Control Pin Interface
If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit
at the input of each control pin is recommended. This applies to all control pins. Note: The recommended resistor and capacitor values do not
necessarily match the EV kit BOM for the case of poor control signal integrity.
Figure 80. Control Pin Interface for Signal Integrity
STBY_A
STBY_B
EP
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
DATA
CLK
7
8
9
CSb
10
11
12
13
14
STBY_C
8mm x 8mm
STBY_D
© 2020 Renesas Electronics Corporation
41
December 15, 2020
F4482 Datasheet
Evaluation Kit Picture
Figure 81. Top View
Figure 82. Bottom View
© 2020 Renesas Electronics Corporation
42
December 15, 2020
F4482 Datasheet
Evaluation Kit / Applications Circuit
Figure 83. Electrical Schematic
© 2020 Renesas Electronics Corporation
43
December 15, 2020
F4482 Datasheet
Table 12. Bill of Material (BOM)
Part Reference
QTY
Description
Manufacturer Part #
Manufacturer
C10, C11, C13, C14,
C27, C37, C38, C40,
C41, C48, C53
11
10nF ±5%, 50V, X7R Ceramic Capacitor (0402)
GRM155R71H103J
Murata
C15, C20, C28, C33,
C66, C69, C72, C75,
C78, C81, C84, C87
12
10
100pF ±5%, 50V, C0G Ceramic Capacitor (0402)
1000pF ±5%, 50V, C0G Ceramic Capacitor (0402)
GRM1555C1H101J
GRM1555C1H102J
Murata
Murata
C43-C47, C49-C52,
C54
C65
1
10
8
100nF ±10%, 50V, X7R Ceramic Capacitor (0402)
10uF ±20%, 16V, X6S Ceramic Capacitor (0603)
100Ω ±1%, 1/10W, Resistor (0402)
GRM155R71H104K
GRM188C81C106M
ERJ-2RKF1000X
ERJ-2RKF1961X
ERJ-2RKF3921X
ERJ-2RKF3741X
ERJ-2RKF2261X
ERJ-2RKF2261X
ERJ-2RKF3321X
ERJ-2RKF2801X
MURATA
C55-C59, C60-C64
R1, R4, R7-11, R14
R2, R16
MURATA
PANASONIC
PANASONIC
PANASONIC
PANASONIC
PANASONIC
PANASONIC
PANASONIC
PANASONIC
2
1.96kΩ ±1%, 1/10W, Resistor (0402)
1.3GHz – 1.7GHz: 3.92kΩ ±1%, 1/10W, Resistor (0402)
1.7GHz – 2.8GHz: 3.74kΩ ±1%, 1/10W, Resistor (0402)
1.3GHz – 1.7GHz: 2.26kΩ ±1%, 1/10W, Resistor (0402)
1.7GHz – 2.8GHz: 2.26kΩ ±1%, 1/10W, Resistor (0402)
1.3GHz – 1.7GHz: 3.32kΩ ±1%, 1/10W, Resistor (0402)
1.7GHz – 2.8GHz: 2.80kΩ ±1%, 1/10W, Resistor (0402)
R3, R15
R5, R13
R6, R12
2
2
2
R17-R27, C1-C4, C6-
C9, C17, C21, C29,
C34
23
0Ω Resistors (0402)
ERJ-2GE0R00X
PANASONIC
J1
J2-J14
1
13
4
CONN HEADER VERT DBL 11 X 2 POS GOLD
Edge Launch SMA (0.375 inch pitch ground, tab)
CONN HEADER VERT DBL 2 X 2 POS GOLD
Quad Path TX DVGA 1300MHz - 2800MHz
Printed Circuit Board
67997-122HLF
142-0701-851
AMPHENOL FCI
Emerson Johnson
Molex
J26, J27, J28, J29
U1
90131-0762
1
F4482
Renesas
F4482 EVKIT DF REV01
Renesas
Bill Of Material (Rev 01)
Renesas
© 2020 Renesas Electronics Corporation
44
December 15, 2020
F4482 Datasheet
Evaluation Kit Operation
Power Supplies
A common VCC power supply should be used for all pins requiring DC power. All supply pins should be bypassed with external capacitors to
minimize noise and fast transients. Supply noise can degrade noise figure and fast transients can trigger ESD clamps and cause them to fail.
Supply voltage change or transients should have a slew rate smaller than 1V/20µs. In addition, all control pins should remain at 0V (±0.3V) or
floating while the supply voltage ramps or while it returns to zero.
Power Supply Setup
1. Connect pin 2 to pin 4, and pin 1 to pin 3 of J26-29. This ensures operation of the Distortion and Bias resistors.
2. Set up a power supply in the voltage range of 3.15V to 3.45V with the power supply output disabled. The voltage can be applied directly
to the J14 SMA.
Power-On Procedure
Set up the voltage supplies and Evaluation Board as described in the “Power Supply Setup” and enable the VCC supply.
Power-Off Procedure
1. Disable the RF input signal on all channels.
2. Disable the VCC supply.
Application Information
The F4482 is optimized for use in high-performance RF applications ranging from 1.3GHz to 2.8GHz.
Startup Condition
Upon device power-up, all channels will default to the standby mode ON. For logic levels, see Table 11.
Default Channel Power On
The default attenuation state will be 31.5dB attenuation upon powering ON each channel (i.e., standby mode OFF). For default levels, see
Figure 77.
Chip Select (CSb)
When CSb is set to logic high, the CLK input is disabled. When CSb is set to logic low, the CLK input is enabled and the DATA word can be
programmed into the shift registers. The programmed word is then latched into the F4482 on the CSb rising edge (see Figure 79).
Standby Mode (STBY)
The F4482 has a power-down feature for power savings. The SPI bus is used to operate each channel in Standby On/Off mode (see Table 11).
© 2020 Renesas Electronics Corporation
45
December 15, 2020
F4482 Datasheet
Package Outline Drawings
The package outline drawings are appended at the end of this document.
Ordering Information
Orderable Part Number
Package
MSL Rating
Shipping Packaging
Temperature
-40° to +105°C
-40° to +105°C
F4482LKGI
3
3
Tray
Reel
8 × 8 × 0.65 mm 56-LGA
8 × 8 × 0.65 mm 56-LGA
F4482LKGI8
F4482EVS-1P5
F4482EVS-2P1
Evaluation Board (Band 1)
Evaluation Board (Band 2)
Marking Diagram
.
.
.
Line 1 is the manufacturer (IDT/Renesas).
Line 2 is the part number.
IDT
F4482LKGI
#YYWW$
Line 3 indicates the following:
• # denotes device stepping
• “YY” is the last two digits of the year; “WW” is the work week that the part was assembled.
• “$” denotes the mark code
LOT
.
Line 4 is the lot number.
Revision History
Revision Date
Description of Change
December 15, 2020
October 15, 2020
October 5, 2020
August 28, 2020
August 14, 2020
Removed references to F4483.
Updated Ordering Information.
Updated Electrical Characteristics tables and Typical Performance Characteristics.
Updated Electrical Characteristics table.
Initial release.
© 2020 Renesas Electronics Corporation
46
December 15, 2020
56-LGA, Package Outline Drawing
8.0 x 8.0 x 0.65 mm Body, 0.5mm Pitch
LKG56P1, PSC-4755-01, Rev 00, Page 1
56-LGA, Package Outline Drawing
8.0 x 8.0 x 0.65 mm Body, 0.5mm Pitch
LKG56P1, PSC-4755-01, Rev 00, Page 2
Package Revision History
Description
Date Created Rev No.
June 21, 2018 Rev 00 Initial Release
IMPORTANT NOTICE AND DISCLAIMER
RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL
SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING
REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND
OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED,
INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible
for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3)
ensuring your application meets applicable standards, and any other safety, security, or other requirements. These
resources are subject to change without notice. Renesas grants you permission to use these resources only for
development of an application that uses Renesas products. Other reproduction or use of these resources is strictly
prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property.
Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims,
damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject
to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources
expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
(Rev.1.0 Mar 2020)
Corporate Headquarters
Contact Information
TOYOSU FORESIA, 3-2-24 Toyosu,
Koto-ku, Tokyo 135-0061, Japan
www.renesas.com
For further information on a product, technology, the most
up-to-date version of a document, or your nearest sales
office, please visit:
www.renesas.com/contact/
Trademarks
Renesas and the Renesas logo are trademarks of Renesas
Electronics Corporation. All trademarks and registered
trademarks are the property of their respective owners.
© 2020 Renesas Electronics Corporation. All rights reserved.
相关型号：
F448BJ392J1K6A
Film Capacitor, Polypropylene, 1600V, 5% +Tol, 5% -Tol, 0.0039uF, Through Hole Mount, 7126, RADIAL LEADED
KEMET
F448BJ392J1K6ALW0L
Film Capacitor, Polypropylene, 1600V, 5% +Tol, 5% -Tol, 0.0039uF, Through Hole Mount, 7126, RADIAL LEADED
KEMET
F448BJ392J1K6C
Film Capacitor, Polypropylene, 1600V, 5% +Tol, 5% -Tol, 0.0039uF, Through Hole Mount, 7126, RADIAL LEADED
KEMET
F448BJ392J1K6XLAF1
Film Capacitor, Polypropylene, 1600V, 5% +Tol, 5% -Tol, 0.0039uF, Through Hole Mount, 7126, RADIAL LEADED
KEMET
F448BJ392J1K6XLTF1
Film Capacitor, Polypropylene, 1600V, 5% +Tol, 5% -Tol, 0.0039uF, Through Hole Mount, 7126, RADIAL LEADED
KEMET
F448BQ222J2K0A
Film Capacitor, Polypropylene, 2000V, 5% +Tol, 5% -Tol, 0.0022uF, Through Hole Mount, 7133, RADIAL LEADED
KEMET
F448BQ222J2K0ALW0L
Film Capacitor, Polypropylene, 2000V, 5% +Tol, 5% -Tol, 0.0022uF, Through Hole Mount, 7133, RADIAL LEADED
KEMET
©2020 ICPDF网 联系我们和版权申明