F0443 [RENESAS]
Dual Matched Broadband RF DVGA 0.6GHz to 2.7GHz;
| 型号： | F0443 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Dual Matched Broadband RF DVGA 0.6GHz to 2.7GHz |
| 文件： | 总65页 (文件大小：6308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Matched Broadband RF
DVGA 0.6GHz to 2.7GHz
F0443
Datasheet
Description
Features
The F0443 is a highly integrated 0.6GHz to 2.7GHz dual channel
RF digital variable gain amplifier designed for use in
diversity/MIMO receivers. The F0443 provides two independent
receiver paths each with 29.5dB typical maximum gain and 3.2dB
NF at 2.5GHz.
.
RF Frequency Range: 0.6GHz to 2.7GHz
Gain at 2.5GHz:
.
• 29.5dB typical max gain in non-bypass mode
• 10.9dB typical max gain in bypass mode
DSA Control
.
For each path, gain control is split into four separate digital step
attenuators: DSA0 provides 6dB of attenuation in a single step
using SPI/I3C control. Its counterpart, DSA1, also provides 6dB of
attenuation in a single step but it is programmed instead using an
external direct control pin. DSA2 yields 29dB of SPI/I3C-controlled
attenuation in 1dB steps, while its counterpart, DSA3, includes
18dB attenuation in 6dB steps programmed via two external control
pins. The device offers +39dBm nominal output IP3 at 2.5GHz
using 372mA total ICC for two active paths with a +5V supply
voltage.
• DSA0: Single 6dB step via SPI/I3C control
• DSA1: Single 6dB step via 1-bit external pin control
• DSA2: 29dB range in 1dB steps via SPI/I3C control
• DSA3: 18dB range in 6dB steps via 2-bit external pin
control
.
.
+39dBm OIP3 at 2.5GHz
NF at 2.5GHz
• 3.2dB typical in non-bypass mode
• 8.9dB typical in bypass mode
+19.7dBm OP1dB at 2.5GHz
ICC = 372mA
The F0443 is packaged in a 7 × 7 mm, 48-LGA with 50Ω single-
ended RF input and RF output impedances for ease of integration
into the signal path.
.
.
.
.
.
.
.
Standby Mode for power savings with 9mA standby current
50Ω single-ended input/output impedances
1.8V logic support
Competitive Advantage
.
High Linearity via Renesas’ patented Zero-Distortion™
Technology
Operating temperature (TEPAD) range: -40°C to +105°C
7 × 7 mm 48-LGA package
.
Exceptionally Low Gain Overshoot/Undershoot via Renesas’
patented Glitch-Free™ Technology
.
.
.
.
Low Noise Figure
Low DC Current
High Integration
High Reliability
Block Diagram
Figure 1. Block Diagram
RF AMP1_A
6dB
6dB
29dB
18dB
DSA0_A
DSA1_A
DSA2_A RF AMP2_A DSA3_A
Typical Applications
RFOUT_A
RFIN_A
.
.
.
Multi-mode, Multi-carrier Receivers
Distributed Antenna Systems
Digital Radios
Decode
Logic
Bias
Control
RFOUT_B
RFIN_B
DSA0_B
6dB
DSA1_B
6dB
DSA2_B RF AMP2_B DSA3_B
29dB
18dB
RF AMP1_B
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F0443 Datasheet
Contents
Pin Assignments....................................................................................................................................................................................................7
Pin Descriptions.....................................................................................................................................................................................................8
Absolute Maximum Ratings.................................................................................................................................................................................10
Recommended Operating Conditions .................................................................................................................................................................11
Electrical Characteristics .....................................................................................................................................................................................12
Thermal Characteristics.......................................................................................................................................................................................26
Typical Operating Conditions (TOC) ...................................................................................................................................................................26
Functional Description.........................................................................................................................................................................................44
Parallel Programming.................................................................................................................................................................................44
Standby (STBY) Mode Programming................................................................................................................................................44
Parallel Programming of DSA1..........................................................................................................................................................44
Parallel Programming of DSA3..........................................................................................................................................................45
Multi-IC Addressing Scheme.............................................................................................................................................................45
Serial Communication ................................................................................................................................................................................46
Serial Programming...........................................................................................................................................................................46
Truth Tables ......................................................................................................................................................................................46
SPI Programming ..............................................................................................................................................................................48
SPI Programming - Default................................................................................................................................................................51
I3C Programming ..............................................................................................................................................................................51
Application Information........................................................................................................................................................................................55
Power Supplies...........................................................................................................................................................................................55
Startup Condition........................................................................................................................................................................................55
Digital Pin Voltage and Resistance Values.................................................................................................................................................55
Signal Integrity.....................................................................................................................................................................................................56
Evaluation Kit Picture ..........................................................................................................................................................................................57
Evaluation Kit / Applications Circuit.....................................................................................................................................................................58
Evaluation Kit BOM .............................................................................................................................................................................................59
Evaluation Kit Operation......................................................................................................................................................................................60
Power Supply Setup...................................................................................................................................................................................60
Parallel Logic Control Setup..............................................................................................................................................................60
Serial Logic Control Setup..........................................................................................................................................................................61
Power-On Procedure..................................................................................................................................................................................61
Power-Off Procedure..................................................................................................................................................................................61
Package Outline Drawings ..................................................................................................................................................................................62
Ordering Information............................................................................................................................................................................................62
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F0443 Datasheet
List of Figures
Figure 1. Block Diagram .....................................................................................................................................................................................1
Figure 2. Pin Assignments for 7 × 7 × 0.75 mm 48-LGA Package – Top View ..................................................................................................7
Figure 3. Gain, All DSA = 0dB, Bypass OFF ....................................................................................................................................................27
Figure 4. Gain, All DSA = 0dB, Bypass ON......................................................................................................................................................27
Figure 5. Gain, DSA0 = 6dB, Bypass OFF .......................................................................................................................................................27
Figure 6. Gain, DSA0 = 6dB, Bypass ON.........................................................................................................................................................27
Figure 7. Gain, DSA1 = 6dB, Bypass OFF .......................................................................................................................................................27
Figure 8. Gain, DSA1 = 6dB, Bypass ON.........................................................................................................................................................27
Figure 9. Gain, DSA2 = 5dB, Bypass OFF .......................................................................................................................................................28
Figure 10. Gain, DSA2 = 5dB, Bypass ON.........................................................................................................................................................28
Figure 11. Gain, DSA2 = 10dB, Bypass OFF .....................................................................................................................................................28
Figure 12. Gain, DSA2 = 10dB, Bypass ON.......................................................................................................................................................28
Figure 13. Gain, DSA2 = 15dB, Bypass OFF .....................................................................................................................................................28
Figure 14. Gain, DSA2 = 15dB, Bypass ON.......................................................................................................................................................28
Figure 15. Gain, DSA2 = 25dB, Bypass OFF .....................................................................................................................................................29
Figure 16. Gain, DSA2 = 25dB, Bypass ON.......................................................................................................................................................29
Figure 17. Gain, DSA3 = 6dB, Bypass OFF .......................................................................................................................................................29
Figure 18. Gain, DSA3 = 6dB, Bypass ON.........................................................................................................................................................29
Figure 19. Gain, DSA3 = 12dB, Bypass OFF .....................................................................................................................................................29
Figure 20. Gain, DSA3 = 12dB, Bypass ON.......................................................................................................................................................29
Figure 21. Gain, DSA3 = 18dB, Bypass OFF .....................................................................................................................................................30
Figure 22. Gain, DSA3 = 18dB, Bypass ON.......................................................................................................................................................30
Figure 23. Relative Gain Error, DSA0 = 6dB, Bypass OFF ................................................................................................................................30
Figure 24. Relative Gain Error, DSA1 = 6dB, Bypass OFF ................................................................................................................................30
Figure 25. Relative Gain Error, DSA2 = 5dB, Bypass OFF ................................................................................................................................30
Figure 26. Relative Gain Error, DSA2 = 10dB, Bypass OFF ..............................................................................................................................30
Figure 27. Relative Gain Error, DSA2 = 15dB, Bypass OFF ..............................................................................................................................31
Figure 28. Relative Gain Error, DSA2 = 25dB, Bypass OFF ..............................................................................................................................31
Figure 29. Relative Gain Error, DSA3 = 6dB, Bypass OFF ................................................................................................................................31
Figure 30. Relative Gain Error, DSA3 = 12dB, Bypass OFF ..............................................................................................................................31
Figure 31. Relative Gain Error, DSA3 = 18dB, Bypass OFF ..............................................................................................................................31
Figure 32. Gain, All DSA2 Attenuation Settings, Bypass OFF, 25°C .................................................................................................................31
Figure 33. Gain, All DSA2 Attenuation Settings, Bypass ON, 25°C...................................................................................................................32
Figure 34. DSA2 INL (Absolute Attenuation Error) Bypass OFF........................................................................................................................32
Figure 35. DSA2 DNL (Step Attenuation Error) Bypass OFF............................................................................................................................32
Figure 36. DSA2 INL (Absolute Attenuation Error) Bypass ON.........................................................................................................................32
Figure 37. DSA2 DNL (Step Attenuation Error) Bypass ON...............................................................................................................................32
Figure 38. Gain, All DSA3 Attenuation Settings, Bypass OFF, 25°C .................................................................................................................32
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Figure 39. Gain, All DSA3 Attenuation Settings, Bypass ON, 25°C...................................................................................................................33
Figure 40. DSA3 INL (Absolute Attenuation Error) Bypass OFF........................................................................................................................33
Figure 41. DSA3 DNL (Step Attenuation Error) Bypass OFF .............................................................................................................................33
Figure 42. DSA3 INL (Absolute Attenuation Error) Bypass ON.........................................................................................................................33
Figure 43. DSA3 DNL (Step Attenuation Error) Bypass ON...............................................................................................................................33
Figure 44. S11, All DSA = 0dB, Bypass OFF .....................................................................................................................................................33
Figure 45. S11, All DSA = 0dB, Bypass ON .......................................................................................................................................................34
Figure 46. S11, DSA0 = 6dB, Bypass OFF ........................................................................................................................................................34
Figure 47. S11, DSA0 = 6dB, Bypass ON..........................................................................................................................................................34
Figure 48. S11, DSA1 = 6dB, Bypass OFF ........................................................................................................................................................34
Figure 49. S11, DSA1 = 6dB, Bypass ON..........................................................................................................................................................34
Figure 50. S11, DSA2 = 5dB, Bypass OFF ........................................................................................................................................................34
Figure 51. S11, DSA2 = 5dB, Bypass ON..........................................................................................................................................................35
Figure 52. S11, DSA2 = 10dB, Bypass OFF ......................................................................................................................................................35
Figure 53. S11, DSA2 = 10dB, Bypass ON........................................................................................................................................................35
Figure 54. S11, DSA2 = 15dB, Bypass OFF ......................................................................................................................................................35
Figure 55. S11, DSA2 = 15dB, Bypass ON........................................................................................................................................................35
Figure 56. S11, DSA2 = 25dB, Bypass OFF ......................................................................................................................................................35
Figure 57. S11, DSA2 = 25dB, Bypass ON........................................................................................................................................................36
Figure 58. S11, DSA3 = 6dB, Bypass OFF ........................................................................................................................................................36
Figure 59. S11, DSA3 = 6dB, Bypass ON..........................................................................................................................................................36
Figure 60. S11, DSA3 = 12dB, Bypass OFF ......................................................................................................................................................36
Figure 61. S11, DSA3 = 12dB, Bypass ON........................................................................................................................................................36
Figure 62. S11, DSA3 = 18dB, Bypass OFF ......................................................................................................................................................36
Figure 63. S11, DSA3 = 18dB, Bypass ON........................................................................................................................................................37
Figure 64. S22, All DSAs = 0dB, Bypass OFF....................................................................................................................................................37
Figure 65. S22, All DSAs = 0dB, Bypass ON .....................................................................................................................................................37
Figure 66. S22, DSA0 = 6dB, Bypass OFF ........................................................................................................................................................37
Figure 67. S22, DSA0 = 6dB, Bypass ON..........................................................................................................................................................37
Figure 68. S22, DSA1 = 6dB, Bypass OFF ........................................................................................................................................................37
Figure 69. S22, DSA1 = 6dB, Bypass ON..........................................................................................................................................................38
Figure 70. S22, DSA2 = 5dB, Bypass OFF ........................................................................................................................................................38
Figure 71. S22, DSA2 = 5dB, Bypass ON..........................................................................................................................................................38
Figure 72. S22, DSA2 = 10dB, Bypass OFF ......................................................................................................................................................38
Figure 73. S22, DSA2 = 10dB, Bypass ON........................................................................................................................................................38
Figure 74. S22, DSA2 = 15dB, Bypass OFF ......................................................................................................................................................38
Figure 75. S22, DSA2 = 15dB, Bypass ON........................................................................................................................................................39
Figure 76. S22, DSA2 = 25dB, Bypass OFF ......................................................................................................................................................39
Figure 77. S22, DSA2 = 25dB, Bypass ON........................................................................................................................................................39
Figure 78. S22, DSA3 = 6dB, Bypass OFF ........................................................................................................................................................39
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F0443 Datasheet
Figure 79. S22, DSA3 = 6dB, Bypass ON..........................................................................................................................................................39
Figure 80. S22, DSA3 = 12dB, Bypass OFF ......................................................................................................................................................39
Figure 81. S22, DSA3 = 12dB, Bypass ON........................................................................................................................................................40
Figure 82. S22, DSA3 = 18dB, Bypass OFF ......................................................................................................................................................40
Figure 83. S22, DSA3 = 18dB, Bypass ON........................................................................................................................................................40
Figure 84. S12, Max Gain, Bypass OFF.............................................................................................................................................................40
Figure 85. S12, Max Gain, Bypass ON...............................................................................................................................................................40
Figure 86. Noise figure, Max Gain, Bypass OFF................................................................................................................................................40
Figure 87. Noise Figure, DSA2 = 5dB, Bypass OFF ..........................................................................................................................................41
Figure 88. Noise Figure, DSA2 = 10dB, Bypass OFF .........................................................................................................................................41
Figure 89. Noise Figure, DSA2 = 15dB, Bypass OFF .........................................................................................................................................41
Figure 90. Noise Figure, DSA2 = 25dB, Bypass OFF .........................................................................................................................................41
Figure 91. Noise figure, Max Gain, Bypass ON...................................................................................................................................................41
Figure 92. OP1dB at Max Gain, Bypass OFF......................................................................................................................................................41
Figure 93. OP1dB at Max Gain, Bypass ON .......................................................................................................................................................42
Figure 94. OP1dB at DSA2 = 5dB, Bypass OFF.................................................................................................................................................42
Figure 95. OP1dB at DSA2 = 10dB, Bypass OFF...............................................................................................................................................42
Figure 96. OP1dB at DSA2 = 15dB, Bypass OFF...............................................................................................................................................42
Figure 97. OP1dB at DSA2 = 25dB, Bypass OFF...............................................................................................................................................42
Figure 98. OIP3 at Max Gain, Bypass OFF........................................................................................................................................................42
Figure 99. OIP3 at Max Gain, Bypass ON...........................................................................................................................................................43
Figure 100. OIP3 at DSA2 = 5dB, Bypass OFF ..................................................................................................................................................43
Figure 101. OIP3 at DSA2 = 10dB, Bypass OFF ................................................................................................................................................43
Figure 102. OIP3 at DSA2 = 15dB, Bypass OFF ................................................................................................................................................43
Figure 103. OIP3 at DSA2 = 25dB, Bypass OFF ................................................................................................................................................43
Figure 104. SPI Word..........................................................................................................................................................................................46
Figure 105. I3C Word ..........................................................................................................................................................................................46
Figure 106. Multi-IC Addressing Scheme Using SPI...........................................................................................................................................48
Figure 107. SPI Timing Diagram .........................................................................................................................................................................49
Figure 108. SPI Serial Register Timing Diagram.................................................................................................................................................50
Figure 109. SPI Programming – Default Register Settings .................................................................................................................................51
Figure 110. I3C Static Addressing Scheme.........................................................................................................................................................52
Figure 111. I3C Timing Diagram – Initialization...................................................................................................................................................53
Figure 112. I3C Timing Diagram .........................................................................................................................................................................53
Figure 113. I3C Programming – Default Register Settings for Byte1 (Programming Word)................................................................................54
Figure 114. I3C Timing Intervals (Pictorial View).................................................................................................................................................54
Figure 115. Internal Pull-up Configuration for STBY_A, STBY_B, DSA1 and DSA3 Control Pins......................................................................55
Figure 116. Internal Pull-down Configuration for the SPI_I3C_SEL, ID_0, and ID_1 Control Pins .....................................................................55
Figure 117. Control Pin Interface for Signal Integrity...........................................................................................................................................56
Figure 118. Top View ..........................................................................................................................................................................................57
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F0443 Datasheet
Figure 119. Bottom View .....................................................................................................................................................................................57
Figure 120. Electrical Schematic.........................................................................................................................................................................58
Figure 121. Power Supply and Logic Voltage Connections.................................................................................................................................60
Figure 122. Power Supply and Logic Voltage Connections.................................................................................................................................60
Figure 123. Serial Logic Connections..................................................................................................................................................................61
List of Tables
Table 1. Pin Descriptions...................................................................................................................................................................................8
Table 2. Absolute Maximum Ratings...............................................................................................................................................................10
Table 3. Recommended Operating Conditions ...............................................................................................................................................11
Table 4. General Electrical Characteristics .....................................................................................................................................................12
Table 5. Electrical Characteristics – Low Band (0.6GHz to 1.1GHz) Performance.........................................................................................14
Table 6. Electrical Characteristics – Mid Band (1.5GHz to 2GHz) Performance.............................................................................................18
Table 7. Electrical Characteristics – High Band (2.3GHz to 2.7GHz) Performance ........................................................................................22
Table 8. Package Thermal Characteristics......................................................................................................................................................26
Table 9. STBY Mode Truth Table....................................................................................................................................................................44
Table 10. DSA1 Truth Table..............................................................................................................................................................................44
Table 11. DSA3 Truth Table..............................................................................................................................................................................45
Table 12. Static Address Truth Table................................................................................................................................................................45
Table 13. Serial Communication Mode Truth Table..........................................................................................................................................46
Table 14. Path Select (Path A/Path B) Truth Table...........................................................................................................................................46
Table 15. Bypass Mode (Amp1_A/Amp1_B) Truth Table..................................................................................................................................47
Table 16. DSA0 Truth Table..............................................................................................................................................................................47
Table 17. DSA2 Abbreviated Truth Table..........................................................................................................................................................47
Table 18. SPI Timing Diagram Values Intervals................................................................................................................................................50
Table 19. I3C Slave Addressing........................................................................................................................................................................51
Table 20. I3C Timing Intervals (Tabulated Figures) ..........................................................................................................................................54
Table 21. Bill of Materials (BOM).......................................................................................................................................................................59
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F0443 Datasheet
Pin Assignments
Figure 2. Pin Assignments for 7 × 7 × 0.75 mm 48-LGA Package – Top View
RF AMP1_A
RFIN_A
GND
36
35
34
33
32
31
30
29
28
27
26
25
1
29dB
DSA2_A
18dB
DSA3_A
6dB
DSA0_A
6dB
DSA1_A
RF
AMP2_A
GND
SPI_I3C_SEL
STBY_A
CSb
RFOUT_A
GND
2
3
VCC_BIAS_A
RSET2
4
5
SDATA/SDA
SCLK/SCL
ID_0
VCC
6
Bias
Control
Decode Logic
GND
7
RDSET2
VCC_BIAS_B
GND
8
ID_1
9
STBY_B
GND
10
11
12
RFOUT_B
GND
RF
AMP2_B
DSA2_B
29dB
DSA3_B
18dB
DSA0_B
6dB
DSA1_B
6dB
RFIN_B
RF AMP1_B
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F0443 Datasheet
Pin Descriptions
Table 1.
Pin Descriptions
Pin Number
Name
Description
1
RFIN_A
Channel A RF input internally matched to 50Ω. Must use external DC block.
2, 11, 13,
15, 20, 22,
25, 27, 30,
34, 36, 39,
41, 46, 48
GND
Internally grounded. This pin must be grounded with a via as close to the pin as possible.
Logic control to select between SPI or I3C mode. Logic HIGH = I3C slave mode using a ‘Slave-Lite’
version of the MIPI I3C communication protocol. Logic LOW/Open = SPI slave mode. An internal pull-
down resistor of 100kΩ connects between this pin and GND.
3
SPI_I3C_SEL
Standby control for Channel A. HIGH/Open = device power OFF with SPI/I3C still powered ON, LOW =
device power ON. An internal pull-up resistor network connects between this pin and 1.67V.
4
5
STBY_A
CSb
Chip Select bar input. Used only for SPI mode. Logic LOW allows data to be shifted in. Logic HIGH
updates the programming register.
6
7
DATA/SDA
CLK/SCL
SPI slave data in or I3C data in/out.
SPI/I3C clock input.
Bit 0 for the I3C static address or used for adding static addressing capability in SPI mode. See the
8
9
ID_0
ID_1
Programming section for details. An internal pull-down resistor of 100kΩ connects between this pin and
GND.
Bit 1 for the I3C static address or used for adding static addressing capability in SPI mode. See the
Programming section for details. An internal pull-down resistor of 100kΩ connects between this pin and
GND.
Standby control for Channel B. HIGH/Open = device power OFF with SPI/I3C still powered ON, LOW =
device power ON. An internal pull-up resistor network connects between this pin and 1.67V.
10
12
14
STBY_B
RFIN_B
DSA1_B
Channel B RF input internally matched to 50Ω. Must use external DC block.
Logic control for channel B DSA1. Logic HIGH/Open = 6dB attenuation, logic LOW = 0dB attenuation. An
internal pull-up resistor network connects between this pin and 1.67V.
16
17
18
19
21
VCC_AMP1_B
RSET1_B
Channel B amplifier 1 DC supply voltage. Connect bypass capacitor(s) as close to the pin as possible.
Connect 2.67kΩ external resistor to GND to optimize amplifier bias. Used with RDSET1_B pin 18.
Connect 9.1kΩ external resistor to GND to optimize amplifier bias. Used with RSET1_B pin 17.
Connect 4.7kΩ external resistor to GND to optimize amplifier gain variation over temperature.
Channel B amplifier 2 DC supply voltage. Connect bypass capacitor(s) as close to the pin as possible.
RDSET1_B
RFET_B
VCC_AMP2_B
Logic control bit 0 for channel B DSA3. An internal pull-up resistor network connects between this pin and
1.67V.
23
24
DSA3_B_BIT0
DSA3_B_BIT1
Logic control bit 1 for channel B DSA3. An internal pull-up resistor network connects between this pin and
1.67V.
26
28
RFOUT_B
Channel B RF output internally matched to 50Ω. Must use external DC block.
VCC_BIAS_B
Channel B bias circuitry DC supply voltage. Connect bypass capacitor(s) as close to the pin as possible.
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F0443 Datasheet
Pin Number
Name
RDSET2
VCC
Description
29
31
32
33
35
Connect 13kΩ external resistor to GND to optimize amplifier bias. Used with RSET2 pin 32.
DC supply voltage. Connect bypass capacitor(s) as close to the pin as possible.
RSET2
Connect 2.94kΩ external resistor to GND to optimize amplifier bias. Used with RDSET2 pin 29.
Channel A bias circuitry DC supply voltage. Connect bypass capacitor(s) as close to the pin as possible.
Channel A RF output internally matched to 50Ω. Must use external DC block.
VCC_BIAS_A
RFOUT_A
Logic control bit 1 for channel B DSA3. An internal pull-up resistor network connects between this pin and
1.67V.
37
38
DSA3_A_BIT1
DSA3_A_BIT0
Logic control bit 0 for channel B DSA3. An internal pull-up resistor network connects between this pin and
1.67V.
40
42
43
44
45
VCC_AMP2_A
RFET_A
Channel A amplifier 2 DC supply voltage. Connect bypass capacitor(s) as close to the pin as possible.
Connect 4.7kΩ external resistor to GND to optimize amplifier gain variation over temperature.
Connect 9.1kΩ external resistor to GND to optimize amplifier bias. Used with RSET1_A pin 44.
Connect 2.67kΩ external resistor to GND to optimize amplifier bias. Used with RDSET1_A pin 43.
Channel A Amplifier 1 DC supply voltage. Connect bypass capacitor(s) as close to the pin as possible.
RDSET1_A
RSET1_A
VCC_AMP1_A
Logic control for channel A DSA1. Logic HIGH/Open = 6dB attenuation, logic LOW = 0dB attenuation. An
internal pull-up resistor network connects between this pin and 1.67V.
47
DSA1_A
– EPAD
Exposed paddle. Internally connected to ground. Solder this exposed paddle to a printed circuit board
(PCB) pad that uses multiple ground vias to provide heat transfer out of the device into the PCB ground
planes. These multiple ground vias are also required to achieve the specified RF performance.
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F0443 Datasheet
Absolute Maximum Ratings
Stresses greater than those listed below can cause permanent damage to the device. Functional operation of the device at these or any other
conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Table 2. Absolute Maximum Ratings
Parameter
Symbol
VCC
Minimum
-0.3
Maximum
+5.5
Units
VCC to GND
V
V
SDATA/SDA, SCLK/SCL, CSb
VSPI_I3C
-0.3
2.2[c]
STBY_A, STBY_B, DSA1_A, DSA1_B, DSA3_A_BIT0, DSA3_A_BIT1,
DSA3_B_BIT0, DSA3_B_BIT1, SPI_I3C_SEL, ID_0, ID_1
V LOGIC
-0.3
VCC + 0.25[c]
V
RFIN_A, RFIN_B externally applied DC voltage
VRFIN
+1.4
+1.4
+3.6
+3.6
V
V
RFOUT_A, RFOUT_B, externally applied DC voltage
VRFOUT
RF Input CW Power (RFIN_A or RFIN_B) applied for 24 hours maximum [a]
Input/Output VSWR < 2:1 in a 50Ω system
VCC = +5.0V, TEPAD = 105°C [b]
PRFMAX24_1
PRFMAX24_2
PRFMAX24_3
PRFMAX24_4
20
23
21
23
dBm
dBm
dBm
dBm
Under the Max Gain Condition (Bypass OFF)
RF Input CW Power (RFIN_A or RFIN_B) applied for 24 hours maximum [a]
Input/Output VSWR < 2:1 in a 50Ω system
VCC = +5.0V, TEPAD = 105°C [b]
Under the Max Gain Condition (Bypass OFF) with DSA0/DSA1 = 6dB Atten
RF Input CW Power (RFIN_A or RFIN_B) applied for 24 hours maximum [a]
Input/Output VSWR < 2:1 in a 50Ω system
VCC = +5.0V, TEPAD = 105°C [b]
Under the Max Gain Condition (Bypass ON)
RF Input CW Power (RFIN_A or RFIN_B) applied for 24 hours maximum [a]
Input/Output VSWR < 2:1 in a 50Ω system
VCC = +5.0V, TEPAD = 105°C [b]
Under the Max Gain Condition (Bypass ON) with DSA0/DSA1 = 6dB Atten
Storage Temperature Range
TSTOR
TLEAD
-65
+150
+260
°C
°C
Lead Temperature (soldering, 10s)
Electrostatic Discharge – HBM
(JEDEC/ESDA JS-001-2012)
VESDHBM
VESDCDM
2000
500
V
V
Electrostatic Discharge – CDM
(JEDEC 22-C101F)
[a] Exposure to these maximum RF levels can result in significant VCC current draw due to overdriving the amplifier stage.
[b] EPAD = Temperature of the exposed paddle.
[c] Control pins should remain at 0V (±0.3V) while the supply voltage ramps or while it returns to zero.
T
© 2020 Renesas Electronics Corporation
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F0443 Datasheet
Recommended Operating Conditions
Table 3.
Recommended Operating Conditions
Parameter
Symbol
VCC
Condition
All VCC pins.
Minimum
4.75
-40
Typical
Maximum
Units
V
Power Supply Voltage [a]
5.25
+105
1.1
Operating Temperature Range
TEPAD
Exposed paddle.
Tuning Set 1.
Tuning Set 2.
Tuning Set 3.
°C
0.6
RF Frequency Range [b]
fRF
1.5
2
GHz
dBm
2.3
2.7
(RFIN_A or RFIN_B)
Input/Output VSWR < 2:1 in a
50Ω system
TEPAD = 105°C
VCC = +5.0V
-23
-4
RF Input CW Power [c]
Max Gain Mode, Bypass OFF
PRF1
(RFIN_A or RFIN_B)
Input/Output VSWR < 2:1 in a
50Ω system
dBm
TEPAD = 105°C
VCC = +5.0V
Max Gain Mode, Bypass ON
Port Impedance (RFIN_A, RFIN_B,
RFOUT_A, RFOUT_B)
ZRF
TJ
Single-ended.
50
Ω
Junction Temperature
+125
°C
[a] Power-on resets will only occur for VCC < 3.75V. Device is designed to function with any supply voltage ≥ 3.75V, although performance
may be degraded when operated outside the recommended voltage range.
[b] To optimize RF performance, different matching components may be used as described in the BOM. The design will strive for one common
match that covers the entire 0.6GHz to 2.7GHz band.
[c] Recommended maximum conditions are defined as a guidance towards obtaining the datasheet specified linearity performance.
© 2020 Renesas Electronics Corporation
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F0443 Datasheet
Electrical Characteristics
See the F0443 Typical Application Circuit. Specifications apply when operated as a Dual DVGA with VCC = +5.0V, fRF = 1.75GHz, TEPAD
=
+25°C, STBY_A = STBY_B = logic LOW, ZS = ZL = 50Ω, maximum gain setting (all DSAs set to 0dB attenuation), Evaluation Board (EVKit)
traces and connectors are de-embedded, unless otherwise stated.
Table 4.
General Electrical Characteristics
Parameter
Symbol
VIH-GPIO
VIL-GPIO
VIH-SDI
Condition
Minimum
1.07 [a] [c]
0
Typical
Maximum
3.6[c]
Units
All GPIO logic input pins.
V
V
V
V
GPIO Logic Input Threshold
All GPIO logic input pins.
0.68[c]
1.95[c]
0.68[c]
All Serial Interface logic input pins.
All Serial Interface logic input pins.
1.07 [a] [c]
0
Serial Digital Interface
Logic Input Threshold
VIL-SDI
Logic Current (per GPIO pin) –
DSA1_X, DSA3_X_BIT0,
DSA3_X_BIT1, SPI_I3C_SEL,
ID_0, ID_1, STBY_X
IIH-GPIO
IIL-GPIO
IIL-SDI
3.3V logic.
1.8V logic.
1.8V logic.
60[c]
50[c]
20[c]
µA
µA
µA
Logic Current (per SDI pin) -
DATA/SDA, CLK/SCL, CSb
ICC_2CH
ICC_1CH
ICC_STBY
Both channels on.
One channel on.
Standby Mode [b].
372
192
9
400[c]
210[c]
11.5[c]
DC Current
mA
ns
50% of STBY going low to the state
where the gain is within ±1dB of its
final value with no attenuation.
Startup Time
TSTART
62
DSA0 Adjustment Range
DSA1 Adjustment Range
DSA2 Adjustment Range
DSA3 Adjustment Range
Maximum Attenuation Glitch
GADJ0
GADJ1
GADJ2
GADJ3
ATTNG
6dB step size.
6
6
dB
dB
dB
dB
dB
6dB step size.
1dB step size.
29
18
1.6
6dB step size.
Any DSA state change.
50% of CSb (SPI) or STOP command
(I3C) to within 0.1dB of final value.
DSA0 Gain Settling Time
DSA0GST
35
20
ns
50% CTL to within 0.1dB of the final
value, 0dB state to 6dB state.
35[c]
35[c]
DSA1 Gain Settling Time
DSA1GST
ns
50% CTL to within 0.1dB of the final
value, 6dB state to 0dB state.
20
70
50% of CSb (SPI) or STOP command
(I3C) to within 0.1dB of the final value.
DSA2 Gain Settling Time
DSA2GST
ns
© 2020 Renesas Electronics Corporation
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F0443 Datasheet
Parameter
Symbol
Condition
Minimum
Typical
Maximum
Units
50% CTL to within 0.1dB of the final
value, 0dB state to 18dB state.
20
35[c]
35[c]
DSA3 Gain Settling Time
DSA3GST
ns
50% CTL to within 0.1dB of the final
value, 18dB state to 0dB state.
20
Stability K Factor
KFACT
fSPI_CLK
fI3C_CLK
Over entire temperature range.
SPI interface clock.
1
unit
12.5[c]
12.5[c]
Serial Clock Speed
MHz
I3C interface clock.
CSb to First Serial Clock
Rising Edge
SPI 3 wire bus. 50% of CSb falling
edge to 50% of CLK rising edge.
tLS
tH
10[c]
10[c]
10[c]
ns
ns
ns
SPI 3 wire bus. 50% of CLK rising
edge to 50% of Data falling edge.
Serial Data Hold Time
Final Serial Clock Rising Edge
to CSb
SPI 3 wire bus. 50% of CLK rising
edge to 50% of CSb rising edge.
tCLS
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these columns
that are not shown in bold italics are guaranteed by design characterization.
[b] During standby mode, SPI is to be left ON and previous state shall be maintained when device is powered up.
[c] The attenuators can be assumed to be purely resistive elements when performing cascaded analysis calculations. Ensure to take into
account any relevant INL/DNL effects.
© 2020 Renesas Electronics Corporation
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F0443 Datasheet
Table 5.
Electrical Characteristics – Low Band (0.6GHz to 1.1GHz) Performance
See the F0443 Typical Application Circuit. Specifications apply when operated as a Dual DVGA. Typical data is with VCC = +5.0V, fRF = 0.9GHz,
TEPAD = +25°C, minimum and maximum data is over fRF = 0.6GHz to 1.1GHz and TEPAD = -40°C to +105°C, STBY_A = STBY_B = logic LOW,
ZS = ZL = 50Ω, maximum gain setting (all DSAs set to 0dB attenuation), Tone Spacing = 1MHz, Pout = 0dBm/Tone, Evaluation Board (EVKit)
traces and connectors are de-embedded, unless otherwise stated.
Parameter
Symbol
Condition
Min
Typ
12.2
10.2
13.7
12.4
Max Units
Worst case typical, TEPAD = 25°C, fRF = 0.6GHz to 1.1GHz.
Worst case typical, TEPAD = 105°C, fRF = 0.6GHz to 1.1GHz.
Worst case typical, TEPAD = 25°C, fRF = 0.6GHz to 1.1GHz.
Worst case typical, TEPAD = 105°C, fRF = 0.6GHz to 1.1GHz.
RF Input Return Loss
RLIN
dB
RF Output Return Loss
Gain Non-Bypass Mode
RLOUT
dB
27.6
GMAX
G1
Maximum Gain
30.4
24.9
19.9
32
[a, f]
Minimum and maximum values
are valid over:
DSA0, = 0dB, DSA1 = 0dB,
DSA2 = 5dB, DSA3 = 0dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 10dB, DSA3 = 0dB
21.4
16.4
26
fRF = 0.6GHz to 1.1GHz,
TEPAD = -40°C to +105°C,
VCC = 4.75V to 5.25V
Typical values valid at:
fRF = 0.9GHz,
G2
21.9
dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 15dB, DSA3 = 0dB
G3
11.1
1.4
15
17.5
TEPAD = +25°C,
VCC = 5V
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 25dB, DSA3 = 0dB
G4
4.9
7
Gain Non-Bypass Mode
Variation Over Temperature
Gain Non-Bypass Mode
Flatness
+0.9/
-1.4
GTEMP
GFLAT
TEPAD = -40ºC to +105ºC.
dB
dB
Gain Flatness. Any fixed temperature.
Any 200MHz bandwidth within fRF = 0.6GHz to 1.1GHz.
Minimum and maximum values
are valid over:
0.6
fRF = 0.6GHz to 1.1GHz,
TEPAD = -40°C to +105°C,
Gain Bypass Mode
GBYP
VCC = 4.75V to 5.25V
Typical values valid at:
fRF = 0.9GHz,
Maximum Gain
9
11.4
13
dB
TEPAD = +25°C,
VCC = 5V
Gain Bypass Mode
Variation Over Temperature
+0.7/
-1
GTEMP_BYP TEPAD = -40ºC to +105ºC.
dB
dB
Gain Bypass Mode
Flatness
Gain Flatness. Any fixed temperature.
GFLAT_BYP
0.3
Any 200MHz bandwidth within fRF = 0.6GHz to 1.1GHz.
NFMAX
NF1
Maximum Gain
2.8
3.3
4.4
6.7
15
3.8
4.6
Minimum and maximum values
are valid over:
DSA0, = 0dB, DSA1 = 0dB,
DSA2 = 5dB, DSA3 = 0dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 10dB, DSA3 = 0dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 15dB, DSA3 = 0dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 25dB, DSA3 = 0dB
fRF = 0.6GHz to 1.1GHz,
TEPAD = -40°C to +105°C,
VCC = 4.75V to 5.25V
Typical values valid at:
fRF = 0.9GHz,
Noise Figure Non-Bypass
Mode
NF2
6.1
dB
NF3
8.9
TEPAD = +25°C,
VCC = 5V
NF4
17.8
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F0443 Datasheet
Parameter
Symbol
Condition
Min
Typ
Max Units
NF Non-Bypass Mode
Variation Over Temperature
-0.5/
+0.7
NFTEMP
TEPAD = -40ºC to +105ºC.
dB
Minimum and maximum
values are valid over:
fRF = 0.6GHz to 1.1GHz,
TEPAD = -40°C to +105°C,
VCC = 4.75V to 5.25V
Typical values valid at:
fRF = 0.9GHz,
Noise Figure Bypass Mode
NFBYP
Maximum Gain
7.5
10.2
dB
dB
TEPAD = +25°C, VCC = 5V
NF Bypass Mode Variation
Over Temperature
-1.1/
+1.4
NFTEMP_BYP TEPAD = -40ºC to +105ºC.
Tone Spacing = 1MHz
OIP31
Maximum gain
35.7
35.2
39.1
Pout = 0dBm/Tone,
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 5dB, DSA3 = 0dB
Pout = -10dBm/Tone at
OIP32
38
DSA2 = 25dB Attenuation
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 10dB, DSA3 = 0dB
Output Third Order Intercept
Point
Minimum and maximum
values are valid over:
fRF = 0.6GHz to 1.1GHz,
TEPAD = -40°C to +105°C,
VCC = 4.75V to 5.25V
Typical values valid at:
fRF = 0.9GHz,
OIP33
OIP34
33.7
30.8
36.5
34.1
dBm
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 15dB, DSA3 = 0dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 25dB, DSA3 = 0dB
OIP35
22.5
25
TEPAD = +25°C, VCC = 5V
OIP3 Variation Over
Temperature
-0.2/
+0.9
OIP3TEMP
TEPAD = -40ºC to +105ºC.
dB
dB
dB
Minimum and maximum
values are valid over:
fRF = 0.6GHz to 1.1GHz,
TEPAD = -40°C to +105°C,
VCC = 4.75V to 5.25V
Typical values valid at:
fRF = 0.9GHz,
Output Third Order Intercept
Point Bypass Mode
OIP3BYP
Maximum Gain
Maximum gain
36.3
38.7
TEPAD = +25°C, VCC = 5V
OIP3 Bypass Mode Variation
Over Temperature
-0.2/
0.2
OIP3TEMP_BYP TEPAD = -40ºC to 105ºC.
OP1dB1
17.8
19.1
Minimum and maximum
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 5dB, DSA3 = 0dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 10dB, DSA3 = 0dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 15dB, DSA3 = 0dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 25dB, DSA3 = 0dB
values are valid over:
fRF = 0.6GHz to 1.1GHz,
TEPAD = -40°C to +105°C,
VCC = 4.75V to 5.25V
Typical values valid at:
fRF = 0.9GHz,
OP1dB2
OP1dB3
OP1dB4
OP1dB5
17.6
18.9
Output 1dB Compression
Non-Bypass Mode[b]
17.6
14.9
5.5
18.8
18.4
9.1
dBm
dB
TEPAD = +25°C, VCC = 5V
OP1dB Variation Over
Temperature
+0.1/
-0.2
OP1dBTEMP TEPAD = -40ºC to +105ºC.
© 2020 Renesas Electronics Corporation
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F0443 Datasheet
Parameter
Symbol
Condition
Min
Typ
Max Units
Minimum and maximum
values are valid over:
fRF = 0.6GHz to 1.1GHz,
TEPAD = -40°C to +105°C,
VCC = 4.75V to 5.25V
Typical values valid at:
fRF = 0.9GHz,
Output 1dB Compression
Bypass Mode
OP1dBBYP
Maximum Gain
18
19.1
dBm
TEPAD = +25°C, VCC = 5V
OP1dB Bypass Mode
Variation Over Temperature
+0.2/
-0.3
OP1dBTEMP_BYP TEPAD = -40ºC to +105ºC.
dB
dB
ISOREV1
ISOREV2
ISOREV3
ISOREV4
ISOCH-CH1
ISOCH-CH2
Maximum gain, Non-Bypass mode.
Maximum gain, Bypass mode.
42.4
24
44
25.8
83.6
91
Reverse Isolation
Minimum gain, Non-Bypass mode.
Minimum gain, Bypass mode.
82.3
88
Maximum gain on both channels.
Minimum gain on both channels, Bypass OFF.
49
57
55
Ch A: Max Gain
Ch B: Note [d]
Ch A: Note [d]
Ch B: Max Gain
Ch A: Min Gain
Ch B: Note [e]
Ch A: Note [e]
Ch B: Min Gain
ISOCH-CH3
ISOCH-CH4
ISOCH-CH5
ISOCH-CH6
ERRDSA0ABS
41
41
Channel-to-Channel
Isolation [c]
dB
43
43
DSA1, DSA2, DSA3 = 0dB
DSA0 = 6dB
±0.3
DSA0, DSA2, DSA3 = 0dB
DSA1 = 6dB
ERRDSA1ABS
±0.3
+0.6
+0.6
+0.6
+0.6
+0.6
+0.1
+0.1
+0.15
DSA0, DSA1, DSA3 = 0dB
DSA2 = 5dB
DSA0, DSA1, DSA3 = 0dB
DSA2 = 10dB
Minimum and maximum
values are valid over:
fRF = 0.6GHz to 1.1GHz,
TEPAD = -40°C to +105°C
VCC = 4.75V to 5.25V
Typical values valid at:
fRF = 0.9GHz,
DSA0, DSA1, DSA3 = 0dB
DSA2 = 15dB
ERRDSA2ABS
DSA Attenuation Error (INL)[f]
dB
DSA0, DSA1, DSA3 = 0dB
DSA2 = 20dB
TEPAD = +25°C,
VCC = 5V
DSA0, DSA1, DSA3 = 0dB
DSA2 = 25dB
DSA0, DSA1, DSA2 = 0dB
DSA3 = 6dB
DSA0, DSA1, DSA2 = 0dB
DSA3 = 12dB
ERRDSA3ABS
DSA0, DSA1, DSA2 = 0dB
DSA3 = 18dB
© 2020 Renesas Electronics Corporation
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F0443 Datasheet
Parameter
Symbol
Condition
Min
Typ
±0.2
±0.2
3
Max Units
DSA2 Step Error (DNL)[f]
DSA3 Step Error (DNL)[f]
Relative Phase DSA0
Relative Phase DSA1
Phase Deviation DSA2
ERRDSA2SE Between adjacent states.
ERRDSA3SE Between adjacent states.
dB
ΦDSA0REL
ΦDSA1REL
ΦDSA2ADJ
Any state, relative to 0dB attenuation state.
Any state, relative to 0dB attenuation state.
Between adjacent states.
3
1.5
5
deg
ΦDSA2RELMAX DSA set to 29dB, relative to 0dB attenuation state.
ΦDSA2RELMID DSA set to 14dB, relative to 0dB attenuation state.
Relative Phase DSA2
3
Relative Phase DSA3
ΦDSA3REL
Any state, relative to 0dB attenuation state.
2
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these columns that are
not shown in bold italics are guaranteed by design characterization.
[b] 1dB compression point is a linearity figure of merit. Refer to Abs Max Ratings table for maximum RF input power.
[c] Signal applied to RFIN_A (RFIN_B) and measure desired signal at RFOUT_B (RFOUT_A) and compare to signal level at RFOUT_A
(RFOUT_B).
[d] Channel A or Channel B DSA combinations which yield 24dB in total attenuation. DSA2_A or DSA2_B settings limited to the following: 0dB,
6dB, 12dB, 18dB, and 24dB.
[e] Channel A or Channel B DSA combinations yielding 35dB in total attenuation. DSA2_A or DSA2_B settings limited to the following: 5dB, 11dB,
17dB, 23dB, and 29dB. Since the maximum attenuation state totals 59dB, this will yield a 24dB difference between the two channels.
[f] The attenuators can be assumed to be purely resistive elements when performing cascaded analysis calculations. Be sure to take into account
any relevant INL/DNL effects
© 2020 Renesas Electronics Corporation
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F0443 Datasheet
Table 6.
Electrical Characteristics – Mid Band (1.5GHz to 2GHz) Performance
See the F0443 Typical Application Circuit. Specifications apply when operated as a Dual DVGA. Typical data is with VCC = +5.0V, fRF = 1.75GHz,
TEPAD = +25°C, minimum and maximum data is over fRF = 1.5GHz to 2GHz and TEPAD = -40°C to +105°C, STBY_A = STBY_B = logic LOW,
ZS = ZL = 50Ω, maximum gain setting (all DSAs set to 0dB attenuation), Tone Spacing = 1MHz, Pout = 0dBm/Tone, Evaluation Board (EVKit)
traces and connectors are de-embedded, unless otherwise stated.
Parameter
Symbol
Condition
Min
Typ
12.5
10.3
11
Max Units
Worst case typical, TEPAD = 25°C, fRF = 1.5GHz to 2GHz.
Worst case typical, TEPAD = 105°C, fRF = 1.5GHz to 2GHz.
Worst case typical, TEPAD = 25°C, fRF = 1.5GHz to 2GHz.
Worst case typical, TEPAD = 105°C, fRF = 1.5GHz to 2GHz.
RF Input Return Loss
RLIN
dB
RF Output Return Loss
Gain Non-Bypass Mode
RLOUT
dB
10.4
26.8
GMAX
G1
Maximum Gain
29.5
24.7
19.8
31.5
[a, f]
Minimum and maximum values
are valid over:
DSA0, = 0dB, DSA1 = 0dB,
DSA2 = 5dB, DSA3 = 0dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 10dB, DSA3 = 0dB
22
27
fRF = 1.5GHz to 2GHz,
TEPAD = -40°C to +105°C,
VCC = 4.75V to 5.25V
Typical values valid at:
fRF = 1.75GHz,
G2
17.1
22.2
dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 15dB, DSA3 = 0dB
G3
12
14.9
5.1
17.2
TEPAD = +25°C,
VCC = 5V
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 25dB, DSA3 = 0dB
G4
2.1
7.5
dB
dB
Gain Non-Bypass Mode
Variation Over Temperature
Gain Non-Bypass Mode
Flatness
+0.9/
-1.3
GTEMP
GFLAT
TEPAD = -40ºC to +105ºC.
Gain Flatness. Any fixed temperature.
Any 200MHz bandwidth within fRF = 1.5GHz to 2GHz.
Minimum and maximum values
are valid over:
0.2
fRF = 1.5GHz to 2GHz,
TEPAD = -40°C to +105°C,
Gain Bypass Mode
GBYP
VCC = 4.75V to 5.25V
Typical values valid at:
fRF = 1.75GHz,
Maximum Gain
7.8
10.9
12.4
dB
TEPAD = +25°C,
VCC = 5V
Gain Bypass Mode
Variation Over Temperature
+0.8/
-1.0
GTEMP_BYP TEPAD = -40ºC to +105ºC.
dB
dB
Gain Bypass Mode
Flatness
Gain Flatness. Any fixed temperature.
GFLAT_BYP
0.4
Any 200MHz bandwidth within fRF = 1.5GHz to 2GHz.
NFMAX
NF1
Maximum Gain
3.2
3.7
4.5
5.2
Minimum and maximum values
are valid over:
DSA0, = 0dB, DSA1 = 0dB,
DSA2 = 5dB, DSA3 = 0dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 10dB, DSA3 = 0dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 15dB, DSA3 = 0dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 25dB, DSA3 = 0dB
fRF = 1.5GHz to 2GHz,
TEPAD = -40°C to +105°C,
VCC = 4.75V to 5.25V
Typical values valid at:
fRF = 1.75GHz,
Noise Figure Non-Bypass
Mode
NF2
4.8
6.7
dB
NF3
7.1
9.6
TEPAD = +25°C,
VCC = 5V
NF4
15.2
18.2
© 2020 Renesas Electronics Corporation
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F0443 Datasheet
Parameter
Symbol
Condition
Min
Typ
Max Units
NF Non-Bypass Mode
Variation Over Temperature
-0.6/
+0.9
NFTEMP
TEPAD = -40ºC to +105ºC.
dB
Minimum and maximum
values are valid over:
fRF = 1.5GHz to 2GHz,
TEPAD = -40°C to +105°C,
VCC = 4.75V to 5.25V
Typical values valid at:
fRF = 1.75GHz,
Noise Figure Bypass Mode
NFBYP
Maximum Gain
8.9
12
dB
dB
TEPAD = +25°C, VCC = 5V
NF Bypass Mode Variation
Over Temperature
-1.2/
+1.6
NFTEMP_BYP TEPAD = -40ºC to +105ºC.
Tone Spacing = 1MHz
OIP31
Maximum gain
34.5
33.7
41.7
Pout = 0dBm/Tone,
Pout = -10dBm/Tone at
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 5dB, DSA3 = 0dB
OIP32
40.1
DSA2 = 25dB Attenuation
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 10dB, DSA3 = 0dB
OIP33
32
29
38.7
36.1
27
Output Third Order Intercept
Point
Minimum and maximum
values are valid over:
fRF = 1.5GHz to 2GHz,
TEPAD = -40°C to +105°C,
VCC = 4.75V to 5.25V
Typical values valid at:
fRF = 1.75GHz,
TEPAD = +25°C, VCC = 5V
dBm
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 15dB, DSA3 = 0dB
OIP34
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 25dB, DSA3 = 0dB
OIP35
22.7
OIP3 Variation Over
Temperature
-1.8/
+0.3
OIP3TEMP
TEPAD = -40ºC to +105ºC.
dB
dB
dB
Minimum and maximum
values are valid over:
fRF = 1.5GHz to 2GHz,
TEPAD = -40°C to +105°C,
VCC = 4.75V to 5.25V
Typical values valid at:
fRF = 1.75GHz,
Output Third Order Intercept
Point Bypass Mode
OIP3BYP
Maximum Gain
Maximum gain
34.3
39
TEPAD = +25°C, VCC = 5V
OIP3 Bypass Mode Variation
Over Temperature
-1.8/
+1.0
OIP3TEMP_BYP TEPAD = -40ºC to +105ºC.
OP1dB1
18.3
19.7
Minimum and maximum
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 5dB, DSA3 = 0dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 10dB, DSA3 = 0dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 15dB, DSA3 = 0dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 25dB, DSA3 = 0dB
values are valid over:
fRF = 1.5GHz to 2GHz,
TEPAD = -40°C to +105°C,
VCC = 4.75V to 5.25V
Typical values valid at:
fRF = 1.75GHz,
OP1dB2
OP1dB3
OP1dB4
OP1dB5
17.8
19.5
Output 1dB Compression
Non-Bypass Mode[b]
17.8
15.6
7
19.6
18.3
9.1
dBm
dB
TEPAD = +25°C, VCC = 5V
OP1dB Variation Over
Temperature
+0.4/
-0.7
OP1dBTEMP TEPAD = -40ºC to +105ºC.
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F0443 Datasheet
Parameter
Symbol
Condition
Min
Typ
Max Units
Minimum and maximum
values are valid over:
fRF = 1.5GHz to 2GHz,
TEPAD = -40°C to +105°C,
VCC = 4.75V to 5.25V
Typical values valid at:
fRF = 1.75GHz,
Output 1dB Compression
Bypass Mode
OP1dBBYP
Maximum Gain
18.8
19.9
dBm
TEPAD = +25°C, VCC = 5V
OP1dB Bypass Mode
Variation Over Temperature
+0.3/
-0.6
OP1dBTEMP_BYP TEPAD = -40ºC to +105ºC.
dB
dB
ISOREV1
ISOREV2
ISOREV3
ISOREV4
ISOCH-CH1
ISOCH-CH2
Maximum gain, Non-Bypass mode.
Maximum gain, Bypass mode.
43
24
45
26.4
77.6
77
Reverse Isolation
Minimum gain, Non-Bypass mode.
Minimum gain, Bypass mode.
74.9
70.7
44
Maximum gain on both channels.
Minimum gain on both channels, Bypass OFF.
51
50
Ch A: Max Gain
Ch B: Note [d]
Ch A: Note [d]
Ch B: Max Gain
Ch A: Min Gain
Ch B: Note [e]
Ch A: Note [e]
Ch B: Min Gain
ISOCH-CH3
ISOCH-CH4
ISOCH-CH5
ISOCH-CH6
ERRDSA0ABS
38
38
Channel-to-Channel
Isolation [c]
dB
38
38
DSA1, DSA2, DSA3 = 0dB
DSA0 = 6dB
±0.3
DSA0, DSA2, DSA3 = 0dB
DSA1 = 6dB
ERRDSA1ABS
±0.3
-0.4
-0.5
-0.4
-0.6
-0.7
0.1
DSA0, DSA1, DSA3 = 0dB
DSA2 = 5dB
DSA0, DSA1, DSA3 = 0dB
DSA2 = 10dB
Minimum and maximum
values are valid over:
fRF = 1.5GHz to 2GHz,
TEPAD = -40°C to +105°C
VCC = 4.75V to 5.25V
Typical values valid at:
fRF = 1.75GHz,
DSA0, DSA1, DSA3 = 0dB
DSA2 = 15dB
ERRDSA2ABS
DSA Attenuation Error (INL)[f]
dB
DSA0, DSA1, DSA3 = 0dB
DSA2 = 20dB
TEPAD = +25°C,
VCC = 5V
DSA0, DSA1, DSA3 = 0dB
DSA2 = 25dB
DSA0, DSA1, DSA2 = 0dB
DSA3 = 6dB
DSA0, DSA1, DSA2 = 0dB
DSA3 = 12dB
ERRDSA3ABS
0.1
DSA0, DSA1, DSA2 = 0dB
DSA3 = 18dB
0.1
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F0443 Datasheet
Parameter
Symbol
Condition
Min
Typ
±0.3
±0.3
3
Max Units
DSA2 Step Error (DNL)[f]
DSA3 Step Error (DNL)[f]
Relative Phase DSA0
Relative Phase DSA1
Phase Deviation DSA2
ERRDSA2SE Between adjacent states.
ERRDSA3SE Between adjacent states.
dB
ΦDSA0REL
ΦDSA1REL
ΦDSA2ADJ
Any state, relative to 0dB attenuation state.
Any state, relative to 0dB attenuation state.
Between adjacent states.
3
2.5
16
deg
ΦDSA2RELMAX DSA set to 29dB, relative to 0dB attenuation state.
ΦDSA2RELMID DSA set to 14dB, relative to 0dB attenuation state.
Relative Phase DSA2
6.5
13
Relative Phase DSA3
ΦDSA3REL
Any state, relative to 0dB attenuation state.
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these columns that are
not shown in bold italics are guaranteed by design characterization.
[b] 1dB compression point is a linearity figure of merit. Refer to Abs Max Ratings table for maximum RF input power.
[c] Signal applied to RFIN_A (RFIN_B) and measure desired signal at RFOUT_B (RFOUT_A) and compare to signal level at RFOUT_A
(RFOUT_B).
[d] Channel A or Channel B DSA combinations which yield 24dB in total attenuation. DSA2_A or DSA2_B settings limited to the following: 0dB,
6dB, 12dB, 18dB, and 24dB.
[e] Channel A or Channel B DSA combinations yielding 35dB in total attenuation. DSA2_A or DSA2_B settings limited to the following: 5dB, 11dB,
17dB, 23dB, and 29dB. Since the maximum attenuation state totals 59dB, this will yield a 24dB difference between the two channels.
[f] The attenuators can be assumed to be purely resistive elements when performing cascaded analysis calculations. Be sure to take into account
any relevant INL/DNL effects.
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F0443 Datasheet
Table 7.
Electrical Characteristics – High Band (2.3GHz to 2.7GHz) Performance
See the F0443 Typical Application Circuit. Specifications apply when operated as a Dual DVGA. Typical data is with VCC = +5.0V, fRF = 2.5GHz,
TEPAD = +25°C, minimum and maximum data is over fRF = 2.3GHz to 2.7GHz and TEPAD = -40°C to +105°C, STBY_A = STBY_B = logic LOW,
ZS = ZL = 50Ω, maximum gain setting (all DSAs set to 0dB attenuation), Tone Spacing = 1MHz, Pout = 0dBm/Tone, Evaluation Board (EVKit)
traces and connectors are de-embedded, unless otherwise stated.
Parameter
Symbol
Condition
Min
Typ
13.7
12
Max Units
Worst case typical, TEPAD = 25°C, fRF = 2.3GHz to 2.7GHz.
Worst case typical, TEPAD = 105°C, fRF = 2.3GHz to 2.7GHz.
Worst case typical, TEPAD = 25°C, fRF = 2.3GHz to 2.7GHz.
Worst case typical, TEPAD = 105°C, fRF = 2.3GHz to 2.7GHz.
RF Input Return Loss
RLIN
dB
12
RF Output Return Loss
Gain Non-Bypass Mode
RLOUT
dB
12
26.4
GMAX
G1
Maximum Gain
30.1
25
33
[a, f]
Minimum and maximum values
are valid over:
DSA0, = 0dB, DSA1 = 0dB,
DSA2 = 5dB, DSA3 = 0dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 10dB, DSA3 = 0dB
21.6
16.6
28
fRF = 2.3GHz to 2.7GHz,
TEPAD = -40°C to +105°C,
VCC = 4.75V to 5.25V
Typical values valid at:
fRF = 2.5GHz,
G2
20
23
dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 15dB, DSA3 = 0dB
G3
11.5
1.6
14.5
5
17
TEPAD = +25°C,
VCC = 5V
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 25dB, DSA3 = 0dB
G4
8.5
dB
dB
Gain Non-Bypass Mode
Variation Over Temperature
Gain Non-Bypass Mode
Flatness
+1.0/
-1.5
GTEMP
GFLAT
TEPAD = -40ºC to +105ºC.
Gain Flatness. Any fixed temperature.
Any 200MHz bandwidth within fRF = 2.3GHz to 2.7GHz.
Minimum and maximum values
are valid over:
0.3
fRF = 2.3GHz to 2.7GHz,
TEPAD = -40°C to +105°C,
Gain Bypass Mode
GBYP
VCC = 4.75V to 5.25V
Typical values valid at:
fRF = 2.5GHz,
Maximum Gain
6.4
9.2
12
dB
TEPAD = +25°C,
VCC = 5V
Gain Bypass Mode
Variation Over Temperature
+0.8/
-1.0
GTEMP_BYP TEPAD = -40ºC to +105ºC.
dB
dB
Gain Bypass Mode
Flatness
Gain Flatness. Any fixed temperature.
GFLAT_BYP
0.6
Any 200MHz bandwidth within fRF = 2.3GHz to 2.7GHz.
NFMAX
NF1
Maximum Gain
3.6
4
5.1
5.8
Minimum and maximum values
are valid over:
DSA0, = 0dB, DSA1 = 0dB,
DSA2 = 5dB, DSA3 = 0dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 10dB, DSA3 = 0dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 15dB, DSA3 = 0dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 25dB, DSA3 = 0dB
fRF = 2.3GHz to 2.7GHz,
TEPAD = -40°C to +105°C,
VCC = 4.75V to 5.25V
Typical values valid at:
fRF = 2.5GHz,
Noise Figure Non-Bypass
Mode
NF2
5.1
7.5
15.4
7.3
dB
NF3
10.4
19.2
TEPAD = +25°C,
VCC = 5V
NF4
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F0443 Datasheet
Parameter
Symbol
Condition
Min
Typ
Max Units
NF Non-Bypass Mode
Variation Over Temperature
-0.7/
+0.9
NFTEMP
TEPAD = -40ºC to +105ºC.
dB
Minimum and maximum
values are valid over
fRF = 2.3GHz to 2.7GHz,
TEPAD = -40°C to +105°C,
VCC = 4.75V to 5.25V
Typical values valid at
fRF = 2.5GHz,
Noise Figure Bypass Mode
NFBYP
Maximum Gain
10
13.3
dB
dB
TEPAD = +25°C, VCC = 5V
NF Bypass Mode Variation
Over Temperature
-1.3/
+1.8
NFTEMP_BYP TEPAD = -40ºC to +105ºC.
Tone Spacing = 1MHz
OIP31
Maximum gain
33.4
32
40
Pout = 0dBm/Tone,
Pout = -10dBm/Tone at
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 5dB, DSA3 = 0dB
OIP32
40
DSA2 = 25dB Attenuation
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 10dB, DSA3 = 0dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 15dB, DSA3 = 0dB
OIP33
31.2
28.7
39.6
37.9
Output Third Order Intercept
Point
Minimum and maximum
dBm
OIP34
values are valid over
fRF = 2.3GHz to 2.7GHz,
TEPAD = -40°C to +105°C,
VCC = 4.75V to 5.25V
Typical values valid at
fRF = 2.5GHz,
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 25dB, DSA3 = 0dB
OIP35
19
27
TEPAD = +25°C, VCC = 5V
OIP3 Variation Over
Temperature
-1.9/
+0.2
OIP3TEMP
TEPAD = -40ºC to +105ºC.
dB
dB
dB
Minimum and maximum
values are valid over
fRF = 2.3GHz to 2.7GHz,
TEPAD = -40°C to +105°C,
VCC = 4.75V to 5.25V
Typical values valid at
fRF = 2.5GHz,
Output Third Order Intercept
Point Bypass Mode
OIP3BYP
Maximum Gain
Maximum gain
33.6
39
TEPAD = +25°C, VCC = 5V
OIP3 Bypass Mode Variation
Over Temperature
-2.2/
+2.0
OIP3TEMP_BYP TEPAD = -40ºC to +105ºC.
OP1dB1
17.6
19.2
Minimum and maximum
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 5dB, DSA3 = 0dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 10dB, DSA3 = 0dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 15dB, DSA3 = 0dB
DSA0 = 0dB, DSA1 = 0dB,
DSA2 = 25dB, DSA3 = 0dB
values are valid over
fRF = 2.3GHz to 2.7GHz,
TEPAD = -40°C to +105°C,
VCC = 4.75V to 5.25V
Typical values valid at
fRF = 2.5GHz,
OP1dB2
OP1dB3
OP1dB4
OP1dB5
17.6
19.2
Output 1dB Compression
Non-Bypass Mode[b]
17.4
15.5
4
19.2
17.8
7.7
dBm
dB
TEPAD = +25°C, VCC = 5V
OP1dB Variation Over
Temperature
+0.5/
-0.8
OP1dBTEMP TEPAD = -40ºC to +105ºC.
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F0443 Datasheet
Parameter
Symbol
Condition
Min
Typ
Max Units
Minimum and maximum
values are valid over
fRF = 2.3GHz to 2.7GHz,
TEPAD = -40°C to +105°C,
VCC = 4.75V to 5.25V
Typical values valid at
fRF = 2.5GHz,
Output 1dB Compression
Bypass Mode
OP1dBBYP
Maximum Gain
16.8
19.5
dBm
TEPAD = +25°C, VCC = 5V
OP1dB Bypass Mode
Variation Over Temperature
+0.4/
-0.8
OP1dBTEMP_BYP TEPAD = -40ºC to +105ºC.
dB
dB
ISOREV1
ISOREV2
ISOREV3
ISOREV4
ISOCH-CH1
ISOCH-CH2
Maximum gain, Non-Bypass mode.
Maximum gain, Bypass mode.
42
24
44.3
27.7
72.4
71.4
53
Reverse Isolation
Minimum gain, Non-Bypass mode.
Minimum gain, Bypass mode.
69.5
65.4
46
Maximum gain on both channels.
Minimum gain on both channels, Bypass OFF.
54
Ch A: Max Gain
Ch B: Note [d]
Ch A: Note [d]
Ch B: Max Gain
Ch A: Min Gain
Ch B: Note [e]
Ch A: Note [e]
Ch B: Min Gain
ISOCH-CH3
ISOCH-CH4
ISOCH-CH5
ISOCH-CH6
ERRDSA0ABS
38
39
Channel-to-Channel
Isolation [c]
dB
37
37
DSA1, DSA2, DSA3 = 0dB
DSA0 = 6dB
±0.3
DSA0, DSA2, DSA3 = 0dB
DSA1 = 6dB
ERRDSA1ABS
±0.3
-0.2
+0.1
+0.1
+0.2
-0.2
-0.1
-0.1
-0.1
DSA0, DSA1, DSA3 = 0dB
DSA2 = 5dB
DSA0, DSA1, DSA3 = 0dB
DSA2 = 10dB
Minimum and maximum
values are valid over
fRF = 2.3GHz to 2.7GHz,
TEPAD = -40°C to +105°C
VCC = 4.75V to 5.25V
Typical values valid at
fRF = 2.5GHz,
DSA0, DSA1, DSA3 = 0dB
DSA2 = 15dB
ERRDSA2ABS
DSA Attenuation Error (INL)[f]
dB
DSA0, DSA1, DSA3 = 0dB
DSA2 = 20dB
TEPAD = +25°C,
VCC = 5V
DSA0, DSA1, DSA3 = 0dB
DSA2 = 25dB
DSA0, DSA1, DSA2 = 0dB
DSA3 = 6dB
DSA0, DSA1, DSA2 = 0dB
DSA3 = 12dB
ERRDSA3ABS
DSA0, DSA1, DSA2 = 0dB
DSA3 = 18dB
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F0443 Datasheet
Parameter
Symbol
Condition
Min
Typ
±0.3
±0.2
4
Max Units
DSA2 Step Error (DNL)[f]
DSA3 Step Error (DNL)[f]
Relative Phase DSA0
Relative Phase DSA1
Phase Deviation DSA2
ERRDSA2SE Between adjacent states.
ERRDSA3SE Between adjacent states.
dB
ΦDSA0REL
ΦDSA1REL
ΦDSA2ADJ
Any state, relative to 0dB attenuation state.
Any state, relative to 0dB attenuation state.
Between adjacent states.
5
3
deg
ΦDSA2RELMAX DSA set to 29dB, relative to 0dB attenuation state.
ΦDSA2RELMID DSA set to 14dB, relative to 0dB attenuation state.
16
6
Relative Phase DSA2
Relative Phase DSA3
ΦDSA3REL
Any state, relative to 0dB attenuation state.
15
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these columns that are
not shown in bold italics are guaranteed by design characterization.
[b] 1dB compression point is a linearity figure of merit. Refer to Abs Max Ratings table for maximum RF input power.
[c] Signal applied to RFIN_A (RFIN_B) and measure desired signal at RFOUT_B (RFOUT_A) and compare to signal level at RFOUT_A
(RFOUT_B).
[d] Channel A or Channel B DSA combinations which yield 24dB in total attenuation. DSA2_A or DSA2_B settings limited to the following: 0dB,
6dB, 12dB, 18dB, and 24dB.
[e] Channel A or Channel B DSA combinations yielding 35dB in total attenuation. DSA2_A or DSA2_B settings limited to the following: 5dB, 11dB,
17dB, 23dB, and 29dB. Since the maximum attenuation state totals 59dB, this will yield a 24dB difference between the two channels.
[f] The attenuators can be assumed to be purely resistive elements when performing cascaded analysis calculations. Be sure to take into account
any relevant INL/DNL effects.
© 2020 Renesas Electronics Corporation
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F0443 Datasheet
Thermal Characteristics
Table 8.
Package Thermal Characteristics
Parameter
Symbol
Value
Units
θJA
Junction to Ambient Thermal Resistance.
16
°C/W
Junction to Case Thermal Resistance.
(Case is defined as the exposed paddle)
θJC-BOT
6
°C/W
Moisture Sensitivity Rating (Per J-STD-020)
MSL 3
Typical Operating Conditions (TOC)
Unless otherwise noted, for the TOC graphs on the following pages, the following conditions apply:
.
.
.
.
.
.
.
.
VCC = +5V
TEPAD = 25°C
ZL = ZS = 50Ω
Small signal parameters measured with PIN = -35dBm
ATTN setting = 0dB (Maximum Gain; DSA0 = DSA1 = DSA2 = DSA3 = 0dB)
POUT = 0dBm/tone
All temperatures are referenced to the exposed paddle
Evaluation Kit traces and connector losses are de-embedded
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F0443 Datasheet
Typical Performance Characteristics
Figure 3.
Gain, All DSA = 0dB, Bypass OFF
Figure 4.
Gain, All DSA = 0dB, Bypass ON
Figure 5.
Gain, DSA0 = 6dB, Bypass OFF
Figure 6.
Gain, DSA0 = 6dB, Bypass ON
Figure 7.
Gain, DSA1 = 6dB, Bypass OFF
Figure 8.
Gain, DSA1 = 6dB, Bypass ON
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F0443 Datasheet
Figure 9.
Gain, DSA2 = 5dB, Bypass OFF
Figure 10. Gain, DSA2 = 5dB, Bypass ON
Figure 11. Gain, DSA2 = 10dB, Bypass OFF
Figure 12. Gain, DSA2 = 10dB, Bypass ON
Figure 13. Gain, DSA2 = 15dB, Bypass OFF
Figure 14. Gain, DSA2 = 15dB, Bypass ON
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F0443 Datasheet
Figure 15. Gain, DSA2 = 25dB, Bypass OFF
Figure 16. Gain, DSA2 = 25dB, Bypass ON
Figure 17. Gain, DSA3 = 6dB, Bypass OFF
Figure 18. Gain, DSA3 = 6dB, Bypass ON
Figure 19. Gain, DSA3 = 12dB, Bypass OFF
Figure 20. Gain, DSA3 = 12dB, Bypass ON
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F0443 Datasheet
Figure 21. Gain, DSA3 = 18dB, Bypass OFF
Figure 22. Gain, DSA3 = 18dB, Bypass ON
Figure 23. Relative Gain Error, DSA0 = 6dB,
Bypass OFF
Figure 24. Relative Gain Error, DSA1 = 6dB,
Bypass OFF
Figure 25. Relative Gain Error, DSA2 = 5dB,
Bypass OFF
Figure 26. Relative Gain Error, DSA2 = 10dB,
Bypass OFF
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F0443 Datasheet
Figure 27. Relative Gain Error, DSA2 = 15dB,
Bypass OFF
Figure 28. Relative Gain Error, DSA2 = 25dB,
Bypass OFF
Figure 29. Relative Gain Error, DSA3 = 6dB,
Bypass OFF
Figure 30. Relative Gain Error, DSA3 = 12dB,
Bypass OFF
Figure 31. Relative Gain Error, DSA3 = 18dB,
Bypass OFF
Figure 32. Gain, All DSA2 Attenuation Settings,
Bypass OFF, 25°C
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Figure 33. Gain, All DSA2 Attenuation Settings,
Bypass ON, 25°C
Figure 34. DSA2 INL (Absolute Attenuation
Error) Bypass OFF
Figure 35. DSA2 DNL (Step Attenuation Error)
Bypass OFF
Figure 36. DSA2 INL (Absolute Attenuation
Error) Bypass ON
Figure 37. DSA2 DNL (Step Attenuation Error)
Bypass ON
Figure 38. Gain, All DSA3 Attenuation Settings,
Bypass OFF, 25°C
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F0443 Datasheet
Figure 39. Gain, All DSA3 Attenuation Settings,
Bypass ON, 25°C
Figure 40. DSA3 INL (Absolute Attenuation
Error) Bypass OFF
Figure 41. DSA3 DNL (Step Attenuation Error)
Bypass OFF
Figure 42. DSA3 INL (Absolute Attenuation
Error) Bypass ON
Figure 43. DSA3 DNL (Step Attenuation Error)
Bypass ON
Figure 44. S11, All DSA = 0dB, Bypass OFF
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F0443 Datasheet
Figure 45. S11, All DSA = 0dB, Bypass ON
Figure 47. S11, DSA0 = 6dB, Bypass ON
Figure 49. S11, DSA1 = 6dB, Bypass ON
Figure 46. S11, DSA0 = 6dB, Bypass OFF
Figure 48. S11, DSA1 = 6dB, Bypass OFF
Figure 50. S11, DSA2 = 5dB, Bypass OFF
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Figure 51. S11, DSA2 = 5dB, Bypass ON
Figure 53. S11, DSA2 = 10dB, Bypass ON
Figure 55. S11, DSA2 = 15dB, Bypass ON
Figure 52. S11, DSA2 = 10dB, Bypass OFF
Figure 54. S11, DSA2 = 15dB, Bypass OFF
Figure 56. S11, DSA2 = 25dB, Bypass OFF
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Figure 57. S11, DSA2 = 25dB, Bypass ON
Figure 59. S11, DSA3 = 6dB, Bypass ON
Figure 61. S11, DSA3 = 12dB, Bypass ON
Figure 58. S11, DSA3 = 6dB, Bypass OFF
Figure 60. S11, DSA3 = 12dB, Bypass OFF
Figure 62. S11, DSA3 = 18dB, Bypass OFF
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Figure 63. S11, DSA3 = 18dB, Bypass ON
Figure 65. S22, All DSAs = 0dB, Bypass ON
Figure 67. S22, DSA0 = 6dB, Bypass ON
Figure 64. S22, All DSAs = 0dB, Bypass OFF
Figure 66. S22, DSA0 = 6dB, Bypass OFF
Figure 68. S22, DSA1 = 6dB, Bypass OFF
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Figure 69. S22, DSA1 = 6dB, Bypass ON
Figure 71. S22, DSA2 = 5dB, Bypass ON
Figure 73. S22, DSA2 = 10dB, Bypass ON
Figure 70. S22, DSA2 = 5dB, Bypass OFF
Figure 72. S22, DSA2 = 10dB, Bypass OFF
Figure 74. S22, DSA2 = 15dB, Bypass OFF
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F0443 Datasheet
Figure 75. S22, DSA2 = 15dB, Bypass ON
Figure 77. S22, DSA2 = 25dB, Bypass ON
Figure 79. S22, DSA3 = 6dB, Bypass ON
Figure 76. S22, DSA2 = 25dB, Bypass OFF
Figure 78. S22, DSA3 = 6dB, Bypass OFF
Figure 80. S22, DSA3 = 12dB, Bypass OFF
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F0443 Datasheet
Figure 81. S22, DSA3 = 12dB, Bypass ON
Figure 83. S22, DSA3 = 18dB, Bypass ON
Figure 85. S12, Max Gain, Bypass ON
Figure 82. S22, DSA3 = 18dB, Bypass OFF
Figure 84. S12, Max Gain, Bypass OFF
Figure 86. Noise figure, Max Gain, Bypass OFF
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F0443 Datasheet
Figure 87. Noise Figure, DSA2 = 5dB, Bypass
OFF
Figure 88. Noise Figure, DSA2 = 10dB, Bypass
OFF
Figure 89. Noise Figure, DSA2 = 15dB, Bypass
OFF
Figure 90. Noise Figure, DSA2 = 25dB, Bypass
OFF
Figure 91. Noise figure, Max Gain, Bypass ON
Figure 92. OP1dB at Max Gain, Bypass OFF
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F0443 Datasheet
Figure 93. OP1dB at Max Gain, Bypass ON
Figure 95. OP1dB at DSA2 = 10dB, Bypass OFF
Figure 97. OP1dB at DSA2 = 25dB, Bypass OFF
Figure 94. OP1dB at DSA2 = 5dB, Bypass OFF
Figure 96. OP1dB at DSA2 = 15dB, Bypass OFF
Figure 98. OIP3 at Max Gain, Bypass OFF
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F0443 Datasheet
Figure 99. OIP3 at Max Gain, Bypass ON
Figure 101. OIP3 at DSA2 = 10dB, Bypass OFF
Figure 103. OIP3 at DSA2 = 25dB, Bypass OFF
Figure 100. OIP3 at DSA2 = 5dB, Bypass OFF
Figure 102. OIP3 at DSA2 = 15dB, Bypass OFF
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F0443 Datasheet
Functional Description
The F0443 employs a variety of programming options to control the device’s standby (STBY) operation, the on-chip digital step attenuators
(DSAs) and the amplifier bypass. The standby (STBY) function and four of the DSAs are programmed using external control pins (parallel
mode), while the remaining DSAs and amplifiers are programmed serially via a SPI or I3C interface. The following sections provide specific
details on each programming mode.
Parallel Programming
Standby (STBY) Mode Programming
The F0443 allows for the independent shutdown of each signal path. Simply apply the logic shown in Table 9 to control paths A and B.
Table 9.
STBY Mode Truth Table
Path
Pin
Logic
0
Path Power State
Path A Power On
STBY_A
(Pin 4)
A
B
1 (NC)
0
Path A Standby (SPI/I3C still active)
Path B Power On
STBY_B
(Pin 10)
1 (NC)
Path B Standby (SPI/I3C still active)
When the STBY_A and STBY_B pins are toggled between the logic LOW and Logic HIGH modes, the register settings remain unchanged.
Therefore the bypass setting and DSA2 attenuators will retain their settings during standby. The only exception is if a new programming
command is received (via the SPI or I3C interface) during the STBY state. Since the SPI/I3C interface remains active during the Standby mode,
the attenuator and bypass registers can still be reprogrammed during this time. When each path is brought out of Standby, the attenuators will
be set per the latest register settings.
The default state for each of these pins is a logic HIGH which leaves the RF paths in the off state.
Parallel Programming of DSA1
DSA1_A and DSA1_B programming is accomplished by applying the desired logic to the external control pins described below. By using parallel
programming, fast switching of these DSAs can take place without experiencing the delays commonly associated with serial programming.
Logic HIGH selects the 6dB attenuation state, while logic LOW selects the 0dB attenuation state as seen in Table 10.
Upon startup the DSA1 attenuator will be set per the logic level. If the pin is left floating (e.g. left in a ‘no connect’ or ‘NC’ state) the attenuator
will be set for the maximum value of 6dB since the pin is set to logic HIGH internally.
Table 10. DSA1 Truth Table
DSA1_A Logic (Pin 47)
Attenuation
DSA1_B Logic (Pin 14)
0
0dB
6dB
1 (NC)
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F0443 Datasheet
Parallel Programming of DSA3
DSA3 uses 2-bit logic to select up to 4 different states per attenuator with a 6dB step. By using parallel programming, fast switching of these
DSAs can take place without experiencing the delays commonly associated with serial programming. Logic HIGH selects the 6dB attenuation
state for Bit 0, while logic HIGH selects the 12dB attenuation state for Bit 1. When both pins are set for logic LOW, the DSA is set to the 0dB
attenuation state. In all cases, the logic for each control bit will default to the HIGH state when the control pin is left floating (e.g. left in a ‘no
connect’ or ‘NC’ state). The DSA states are listed in Table 11.
Upon startup, the DSA3 attenuator will be set per the logic level. If the pins are left floating (e.g. left in a ‘no connect’ or ‘NC’ state), the attenuator
will be set for the maximum value of 18dB since the pin is set HIGH internally.
Table 11. DSA3 Truth Table
DSA3_A_BIT1 (Pin 37)
DSA3_B_BIT1 (Pin 24)
DSA3_A_BIT0 (Pin 38)
DSA3_B_BIT0 (Pin 23)
Attenuation
0
0
0dB
6dB
0
1 (NC)
0
1 (NC)
1 (NC)
12dB
18dB
1 (NC)
Multi-IC Addressing Scheme
The F0443 has the ability to share the serial interface lines for up to four devices. This is accomplished by giving the device a specific, or static,
address using pins ID_0 (pin 8), and ID_1 (pin 9). Use of these pins is specific to whether the serial programming is done using standard serial
programming (SPI) or serial I3C programming.
Upon startup, the static address is set per the logic levels. If the pins are left floating (e.g. left in a ‘no connect’ or ‘NC’ state), the static address
will be set to ‘00’ since the pins are set to logic LOW internally.
Table 12. Static Address Truth Table
ID_1 (Pin 9)
ID_0 (Pin 8)
Static Identifier
0
0
1
1
0
1
0
1
0
1
2
3
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F0443 Datasheet
Serial Communication
The F0443 has been designed to use standard 3-wire serial communication (SPI) or a ‘Slave-Lite’ version of the I3C protocol communication
(l3C). The communication mode is set using SPI_I3C_SEL (pin 3). Logic LOW is for SPI and logic HIGH is for I3C.
Upon startup, the serial communication is set per the logic level. If the pin is left floating (e.g. left in a ‘no connect’ or ‘NC’ state), SPI
communication is used since the pin is set to logic LOW internally.
Table 13. Serial Communication Mode Truth Table
SPI_I3C_SEL (Pin 3)
Communication
0
1
SPI
I3C
Serial Programming
The serial programming is different for the SPI (SPI_I3C_SEL is logic LOW) or I3C (SPI_I3C_SEL is logic HIGH) modes of operation. The SPI
interface requires a 16-bit word, whereas the I3C interface utilizes 23 bits. In both cases the information is shifted with the most significant bit
(MSB) first.
Figure 104. SPI Word
Path
Select
0 or
6 dB
ID_1
ID_0
A6
0
1
1
0
0
1
16 dB 8 dB 4 dB
2 dB 1 dB
Bypass
A7
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
MSB
LSB
Figure 105. I3C Word
Path
Select
0 or
6 dB
0
0
1
0
0
ID_1
A1
ID_0
0
0
0
0
0
0
0
1
16 dB 8 dB 4 dB
2 dB 1 dB
Bypass
A6
A5
A4
A3
A2
A0
S7
S6
S5
S4
S3
S2
S1
S0
D7
D6
D5
D4
D3
D2
D1
D0
MSB
LSB
Truth Tables
The settings for path selection (Path Select), bypassing the amplifier (AMP1_A and AMP1_B), the first attenuator (DSA0_A and DSA0_B), and
the third attenuator (DSA2_A, and DSA2_B) are all programmed serially via the F0443’s SPI or I3C interface. The truth tables for each digital
bit or word remains the same regardless of the serial interface being used.
The Path Select bit, which uses one bit, directs the data word to control one of the two paths, A or B, in the F0443. All the serially controlled
components, DSA0, DSA2 and Bypass Mode are controlled simultaneously.
Table 14. Path Select (Path A/Path B) Truth Table
Path Select
Logic
Path
A
0
1
A5 (SPI)
S0 (I3C)
B
The Bypass mode which uses one bit will reduce the overall gain of the F0443 and is directed to the correct path (channel) with Path Select.
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F0443 Datasheet
Table 15. Bypass Mode (Amp1_A/Amp1_B) Truth Table
Bypass
Logic
Bypass Mode Setting
Bypass OFF (full gain)
Bypass ON (reduced gain)
0
1
D0
The first digital attenuator, DSA0, is programmed using one bit and is used in conjunction with the Path Select bit.
Table 16. DSA0 Truth Table
DSA0
Attenuation Setting
DSA0
Logic
0
1
0dB
6dB
D1
The third attenuator, DSA2, has 29dB of attenuation with 1 dB steps. DSA2 is programmed with a 5-bit data word. The maximum attenuation
is 29dB and states greater than 29 (30, 31) will set the attenuator for 29dB. These bits are used in conjunction with the Path Select bit.
Table 17. DSA2 Abbreviated Truth Table
DSA2
D6
D5
D4
D3
D2
Attenuation Setting
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
1
1
0
0
0
1
0
0
1
1
1
0
0
1
0
0
0
0
1
1
0
1
0
0
0
0
1
0
1
0dB
1dB
2dB
4dB
8dB
16dB
29dB (max)
29dB (max)
29dB (max)
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F0443 Datasheet
SPI Programming
Programming the F0443 using the SPI communication requires that SPI_I3C_SEL be set to logic LOW.
Standard SPI operation is possible using a dedicated control line CSb, SDATA and SCLK. Since ID_0 and ID_1 pins default to logic LOW
(forming address 00), the serial bits ID_0 and ID_1 must also be set for logic LOW during the programming process.
The F0443 can also utilize the ID_0 and ID_1 addressing bits to support multi-chip SPI programming. Note that this alternative SPI addressing
mode is completely optional. However, when used, this feature enables a single CSb control line to program up to four separate F0443 devices,
thereby reducing the number of dedicated IC control lines by a factor of four. This is accomplished by:
.
.
.
Sharing the CSb, SDATA, and SCLK control line for all devices
Setting ID_0 and ID_1 to give each device a unique identification.
Using the appropriate identification bits to control the device.
Most common applications would employ a static implementation where the bits are hardwired to a preset address based on the part’s location
on the circuit board. See Figure 106 for details. The logic present on pins ID_0 and ID_1 will be compared with the relevant sub-addressing bits
that are delivered as part of the DATA payload. (Refer to the complete payload bit assignments shown in Figure 104). If the addressing in the
payload matches the logic on ID_0 and ID_1, then the device recognizes the programming within the payload as being relevant, and the SPI
commands are executed accordingly. If the addresses do not match, then the device simply ignores the programming command.
Figure 106. Multi-IC Addressing Scheme Using SPI
CSb
SCLK
SDATA
Static Addresses
ID_1 ID_0
ID_1
ID_0
F0443 - 0
0
0
0
1
ID_1
ID_0
F0443 - 1
VCC
VCC
ID_1
ID_0
1
1
0
1
F0443 - 2
ID_1
ID_0
VCC
VCC
F0443 - 3
The SPI’s DATA payload consists of an 8-bit addressing word followed by an 8-bit data word. See the SPI Timing Diagram in Figure 107. The
serial words are clocked in with the most significant bit with the address word first (MSB A7).
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F0443 Datasheet
Figure 107. SPI Timing Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
SCLK
Data Word
Latched into
Active Register
CSb
Path
Select
Bypass
On/Off
0dB or
6dB
ID_1
ID_0
0
1
1
1
0
0
16 dB 8 dB
4 dB
2 dB
1 dB
SDATA
A7
MSB
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
LSB
Chip Selection
Addressing Bits
Reserved
DSA2
Data Word D2 – D6
DSA0
0 = 0dB
1 = 6dB
Path Programming Selection
0 = Path A
Bypass Selection
0 = Amp Enabled
1 = Bypass Enabled
1 = Path B
Clock in MSB first
Increasing Time
The addressing word includes three essential ‘selection’ bits, namely A7, A6 and A5. A7 and A6 pertain to the chip selection (using ID_0 and
ID_1, as described above), whereas A5 selects the specific path to be programmed with the write command. Setting bit A5 to logic LOW selects
Path A, and logic HIGH selects Path B. Note that the SPI payload only allows for the programming of a SINGLE PATH per write command.
Separate, unique write commands will therefore be needed to fully program both paths on the F0443.
Bits A4-A0 and D7 are reserved. The values configured for these bits are set to extract optimal performance from the part. They MUST be
included with each SPI command.
The 8-bit data word follows the addressing word. D6-D2 sets the attenuation level of DSA2, D1 sets the attenuation of DSA0, and D0 selects
the amplifier bypass option. Refer to the truth tables (Table 14 to Table 17 listed above) for each block’s programming code. The entire data
word gets latched into the active register with the rising edge of CSb. One Additional clock cycle (Clock 17 in Figure 107) is required after
setting the CSb high to reinitialize the SPI for further programming.
Note: After the SPI payload is delivered and latched into the active register, the F0443 must encounter at least two clock pulses before accepting
a new SPI command. These additional clock cycles are required to reset the device’s microcontroller, essentially clearing the buffer to accept
a new payload.
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F0443 Datasheet
Figure 108 shows the relevant SPI timing intervals.
Figure 108. SPI Serial Register Timing Diagram
Table 18. SPI Timing Diagram Values Intervals
Parameter
Symbol
Condition
Minimum
Typical
Maximum
12.5 [a]
Units
MHz
ns
CLK Frequency
fC
tCH
tCL
tS
CLK High Duration Time
CLK Low Duration Time
DATA to CLK Setup Time
CLK Period [b]
20
20
10
40
10
ns
ns
tP
ns
CLK to DATA Hold Time
tH
ns
Final CLK Rising Edge to CSb
Rising Edge
tCLS
10
ns
CSb to CLK Setup Time
CSb Trigger Pulse Width
tLS
tL
10
10
10
ns
ns
ns
CSb Trigger to CLK Setup Time [c]
tLC
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these columns
that are not shown in bold italics are guaranteed by design characterization.
[b] (tCH + tCL) ≥ 1/fC
[c] Once all desired DATA is clocked in, tLC represents the time a CSb high needs to occur before any subsequent CLK signals.
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F0443 Datasheet
SPI Programming - Default
When the device is first powered on, it will default to the register settings shown in Figure 109. Please note that these default settings are the
recommended conditions for the F0443. DSA0 and DSA2 will be set to their maximum attenuation states, the amplifier will be enabled. These
settings apply to a hard reset when first applying VCC and SPI_I3C_SE is set for logic LOW.
Figure 109. SPI Programming – Default Register Settings
0
0
0
0
1
1
00
0
1
1
1
1
1
1
1
0
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
MSB
LSB
I3C Programming
The F0443 also supports a ‘Slave-Lite’ version of the I3C serial programming protocol where the addressing and data payloads are transferred
between the master and slave via a single SDA line. Programming the device using the I3C bus will require the use of the SCL, SDA, ID_0 and
ID_1pins.
To enable I3C communication on the F0443, the SPI_I3C_SEL pin must be set to logic HIGH.
The addressing of each I3C slave requires a total of 7 bits. The F0443’s first 5 addressing bits are internally fixed per Table 19, while the
remaining 2 bits are defined by the external logic applied to pins ID_0 and ID_1. Most common applications will employ a static addressing
implementation where these two bits are hardwired to a preset address based on the part’s location on the circuit board. Since two bits are
being used to set the address, a total of four F0443’s can be included on any given I3C bus. See Figure 110 for details. Note that the ID_0 and
ID_1 pins are internally pulled down to ground per the configuration shown in Figure 115 so these pins will default to a static address of 00
when left unconnected.
Table 19. I3C Slave Addressing
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F0443 Datasheet
Figure 110. I3C Static Addressing Scheme
I3C Static Addresses
SDA
SCL
ID_1 ID_0
Preset Address Bits
ID_1
ID_0
F0443 - 0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
ID_1
ID_0
F0443 - 1
VCC
VCC
ID_1
ID_0
F0443 - 2
0
0
0
0
1
1
0
0
0
0
1
1
0
1
ID_1
ID_0
VCC
VCC
F0443 - 3
During the Initialization of the I3C bus, the master performs a “Dynamic Address Assignment” to assign addresses to slave devices. The method
to do this uses the command code “Set dynamic address from static address” (SETDASA) to assign a predefined dynamic address to each
slave which has a predefined static address. This can be seen in Figure 111. The slave static address is a sub-addressing word which
determines the specific path (A or B) to be programmed. Bits D7 to D1 are reserved within this word; only bit D0 is used to select between paths
A or B.
Programming the F0443 requires that the addressing word be sent across the SDA line first, followed by a 2-byte write command. See Figure
112 for details surrounding the required I3C payload. As shown, the first byte is the dynamic address that has been predefined in the Initialization
phase.
The second byte contains the same 8 control bits which were defined in the SPI section above. As with the SPI mode, the I3C payload only
allows for the programming of a SINGLE PATH per write command. Separate, unique write commands will therefore be needed to fully program
both paths on the F0443.
For the 8-bit programming word, D6-D2 sets the attenuation level of DSA2, D1 sets the attenuation of DSA0, and D0 selects the amplifier
bypass option. Refer to the truth tables listed above for each block’s programming code. When the device is first powered on, it will default to
the Byte1 register settings shown in Figure 113 below. DSA0 and DSA2 will be set to their maximum attenuation states, the Amplifier will be
fully enabled. These settings apply to a hard reset when first applying VCC.
The entire data word gets latched into the active register with the execution of the STOP bit.
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F0443 Datasheet
Figure 111. I3C Timing Diagram – Initialization
7-bit Slave Static
Address
7-bit Dynamic
Address
SETDASA CCC
7'h7E
STOP(P)
START(S)
SDA
T
W
ACK
D7 D6 D5 D4 D3 D2
D1
D0
Sr
A6
A5 A4 A3 A2 A1
A0
W ACK
A6
A5 A4 A3 A2
A1
A0
0
T
D6
D0
D5 D4 D3 D2 D1
SCL
ID_1 ID_0
1
1
1
0
0
1
0
0
1
1
1
1
0
0
0
0
1
1
1
0
D6
MSB
D5
D4
D3
D2
D1
D0
LSB
S7
MSB
S6
S5
S4
S3
S2
S1
S0
LSB
A6
MSB
A5
A4
A2
A2
A1
A0
LSB
A6
MSB
A5
A4
A2
A2
A1
A0
LSB
Chip Selection
Addressing Bits
Dynamic Address
Clock in MSB first
Increasing Time
Figure 112. I3C Timing Diagram
Sub-Addressing Word
(Path Selection)
Programming Word
7-bit Dynamic
Address
Wr_Byte
_
0
Wr Byte1
START(S)
STOP(P)
SDA
T
D0
D7 D6
D5 D4 D3 D2
D1
D0
A6
A5 A4 A3 A2 A1
A0 RnW ACK D7 D6 D5 D4 D3 D2 D1
T
SCL
Bypass
On/Off
Path
Select
0dB or
6dB
0
0
0
0
0
0
0
16 dB 8 dB
4 dB
D4
2 dB
D3
1 dB
D2
1
A6
MSB
A5
A4
A2
A2
A1
A0
LSB
S7
S6
S5
S4
S3
S2
S1
S0
D7
D6
D5
D1
D0
LSB
LSB
MSB
MSB
RESERVED
DSA2
Data Word
D2 – D6
DSA0
0 = 0dB
1 = 6dB
RESERVED
Dynamic Address
Bypass Selection
0 = Amp Enabled
1 = Bypass Enabled
Path Programming Selection
0 = Path A
1 = Path B
Clock in MSB first
Increasing Time
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F0443 Datasheet
Figure 113. I3C Programming – Default Register Settings for Byte1 (Programming Word)
1
1
1
1
1
1
1
0
D7
MSB
D6
D5
D4
D3
D2
D1
D0
LSB
Note: Applies to the register settings for paths A and B.
Figure 114 shows the relevant I3C timing intervals which are specified in Table 20.
Figure 114. I3C Timing Intervals (Pictorial View)
tp
ts
th
tch
tcl
SCLK
SDATA
Time
MSB
LSB
Table 20. I3C Timing Intervals (Tabulated Figures)
Parameter
SCL Frequency
Symbol
Condition
Minimum
Typical
Maximum
Units
MHz
ns
fC
tCH
tCL
tS
12.5 [a]
SCL High Duration Time
SCL Low Duration Time
SDA to SCL Setup Time
SCL Period [b]
20
20
10
40
10
ns
ns
tP
ns
SCL to SDA Hold Time
tH
ns
[a] Specifications in the minimum/maximum columns that are shown in bold italics are guaranteed by test. Specifications in these columns
that are not shown in bold italics are guaranteed by design characterization.
[b] (tCH + tCL) ≥ 1/fC
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F0443 Datasheet
Application Information
The F0443 has been optimized for use in high performance RF applications ranging in frequency from 0.6GHz to 2.7GHz in individual frequency
bands.
Power Supplies
A common VCC power supply should be used for all pins requiring DC power. All supply pins should be bypassed with external capacitors to
minimize noise and fast transients. Supply noise can degrade noise figure and fast transients can trigger ESD clamps and cause them to fail.
Supply voltage change or transients should have a slew rate smaller than 1V/20μs (50mV/μs). In addition, all control pins should remain at 0V
(±0.3V) while the supply voltage ramps or while it returns to zero.
Startup Condition
Upon device power-up, both channels will default to the STBY mode.
Digital Pin Voltage and Resistance Values
The logic for the control bits (STBY_A, STBY_B, DSA1_A, DSA1_B, DSA3_A and DSA3_B) will default to the HIGH state, 1.67 V when the
control pin is left floating (i.e. left in a ‘no connect’ or ‘NC’ state). A simplified internal circuit is shown in Figure 114.
Figure 115. Internal Pull-up Configuration for STBY_A, STBY_B, DSA1 and DSA3 Control Pins
5V
5V
200kΩ
100kΩ
1.67V
100kΩ
200Ω
External Pin
To enable SPI communication on the F0443, the SPI_I3C_SEL pin must be set to logic LOW or left open in a ‘no connect’ state. Internally, the
SPI_I3C_SEL pin is pulled down to ground per the configuration shown in Figure 115.
Figure 116. Internal Pull-down Configuration for the SPI_I3C_SEL, ID_0, and ID_1 Control Pins
5V
100kΩ
200Ω
External Pin
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F0443 Datasheet
Signal Integrity
If control signal integrity is a concern and clean signals cannot be guaranteed due to overshoot, undershoot, ringing, etc., the following circuit
at the input of each control pin is recommended. This applies to pins for the SPI (16, 17, 18), parallel (1, 19-24) and VMODE pin (3) as shown
below. Note the recommended resistor and capacitor values do not necessarily match the EVKit BOM for the case of poor control signal integrity.
For multiple devices driven by a single control line, the component values will need to be adjusted accordingly so as not to load down the control
line.
Figure 117. Control Pin Interface for Signal Integrity
2pF
5kΩ
1
2
36
35
34
33
32
31
30
29
28
27
26
25
STBY_A
2pF
3
5kΩ
CSB
4
5
2pF
5kΩ
5kΩ
SDATA
SCLK
6
F0443
Exposed Pad (GND)
7
2pF
8
9
5kΩ
2pF
ID0
10
11
12
5kΩ
2pF
ID1
5kΩ
2pF
STBY_B
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F0443 Datasheet
Evaluation Kit Picture
Figure 118. Top View
Figure 119. Bottom View
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F0443 Datasheet
Evaluation Kit / Applications Circuit
Figure 120. Electrical Schematic
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F0443 Datasheet
Evaluation Kit BOM
Table 21. Bill of Materials (BOM)
Part Reference
QTY
Description
Manufacturer Part #
Manufacturer
C1, C8, C11, C13, C18,
C19, C21, C23, C26,
C29, C31, C47, C48, C49
C20, C22, C24
C34
C12, C14, C30, C32
R1-R6, R10, R11, R14,
R15, R19, R27, R28, R29
R20-R26, C2, C9, C17,
C25
14
100pF ±5%, 50V, C0G Ceramic Capacitor (0402)
GRM1555C1H101J
MURATA
3
1
4
1000pF ±5%, 50V, C0G Ceramic Capacitor (0402)
100nF ±10%, 50V (0603)
100nF ±10%, 16V, X7R Ceramic Capacitor (0402)
GRM1555C1H102J
GRM188R7H104KA93D
GRM155R71H104K
MURATA
MURATA
MURATA
14
11
100Ω ±1%, 1/10W, Resistor (0402)
ERJ-2RKF1000X
ERJ-2GE0R00X
PANASONIC
PANASONIC
0Ω Resistors (0402)
J1-J5
5
9
5
2
1
Edge Launch SMA (0.375 inch pitch ground, tab)
CONN HEADER VERT SGL 2 X 1 POS GOLD
CONN HEADER VERT SGL 3 X 1 POS GOLD
CONN HEADER VERT DBL 3 X 2 POS GOLD
CONN HEADER VERT DBL 11 X 2 POS GOLD
142-0701-851
961102-6404-AR
961103-6404-AR
67997-106HLF
67997-122HLF
Emerson Johnson
3M
J9, J11-J17, J19
J6, J7, J8, J22, J23
J10, J18
3M
AMPHENOL FCI
AMPHENOL FCI
J21
C3,C4,C5,C6,C7,C10,
C15,C16,C27,C28,C33
R36
11
2pF ±0.1pF, 50V, C0G Ceramic Capacitor (0402)
GJM1555C1H2R0B
MURATA
1
1
2
2
2
1
1
2
13 KΩ
2.94 KΩ
2.67 KΩ
9.1 KΩ
4.7 KΩ
ERK-2RKF1302X
ERJ-2RKF2941X
ERJ-2RKF2671X
ERJ-2RKF9101X
ERJ-2GEJ472X
F0443LGRI
PANASONIC
PANASONIC
PANASONIC
PANASONIC
PANASONIC
RENESAS
R37
R30, R35
R31, R34
R32, R33
U1
Dual Broadband RF DVGA
Printed Circuit Board Rev 01
DNP
F0443 EVKit Rev 01
RENESAS
J24, J25
C35-C38, L1-L4, R12,
R13, R7-R9, R16-R18
16
DNP
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F0443 Datasheet
Evaluation Kit Operation
Power Supply Setup
Set up a power supply in the voltage range of 4.75V to 5.25V with the power supply output disabled. The voltage can be applied via one of the
following connections (see Figure 121):
.
.
Directly to J5 SMA connector
Individually to J9, J11, J12, J14, J15, J17 and J19 header connections (note the polarity of the GND pin on this connector)
Figure 121. Power Supply and Logic Voltage Connections
Parallel Logic Control Setup
The Evaluation Board can control the F0443 in the Parallel Mode. For external control, apply logic voltages to the J21 header pins 11 through
21 (see Figure 122). The logic voltage can be applied directly to connector J21.
Figure 122. Power Supply and Logic Voltage Connections
The F0443 uses parallel programming for its DSA1 and DSA3 Attenuators. The rest are controlled through SPI or I3C programming.
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F0443 Datasheet
Serial Logic Control Setup
The Evaluation Board has the ability to control the F0443 in the Serial Mode. Connect the serial controller to the J21 header (Pins 1 through 8)
connection as shown in Figure 123.
The attenuation settings for DSA0 and DSA2 can be programmed according to Table 16 and Table 17, respectively.
Figure 123. Serial Logic Connections
Power-On Procedure
Set up the voltage supplies and Evaluation Board as described in the “Power Supply Setup” section and either the “Parallel Logic Control Setup”
and/or “Serial Logic Control Setup” sections above.
Enable the VCC supply.
Enable the proper attenuation setting for DSA0 and DSA2 through Serial Programming and for DSA1 and DSA3 through Parallel Programming
as discussed earlier in the datasheet.
Power-Off Procedure
Set the logic control pins to a logic LOW and Disable the VCC supply.
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F0443 Datasheet
Package Outline Drawings
The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is
the most current data available.
www.idt.com/document/psc/lga-48-package-outline-drawing-70-x-70-mm-body-epad-50-x-50-mm-0mm-pitch-lgr48
Ordering Information
Orderable Part Number
Package
MSL Rating
Shipping Packaging
Temperature
-40° to +105°C
-40° to +105°C
F0443LGRI
7 × 7 × 0.7 mm 48-LGA
7 × 7 × 0.7 mm 48-LGA
1
1
Tray
Reel
F0443LGRI8
F0443EVBI
Evaluation Board
Marking Diagram
.
.
.
Line 1 indicates the manufacturer.
Lines 2 and 3 indicate the part number.
Line 4:
IDT
F0443
LGRI
ZS1629L
Q54E042PY
• “ZS” is for die version.
• 1629 has two digits for the year and week that the part was assembled.
• “L” denotes assembly site.
.
Line 5: “Q54E042PY” is the assembly lot number.
Revision History
Revision Date
Description of Change
Sep 1, 2020
July 2, 2020
May 18, 2020
April 29, 2020
April 1, 2020
Added Footnote [c] to Recommended Operating Conditions table.
Minor corrections to the DNL/INL plots made. NF plot with Bypass ON added.
Logic control specifications updated in Table 4.
Updated SPI/I3C timing diagram.
Initial release.
© 2020 Renesas Electronics Corporation
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