EL8170 [RENESAS]

Micropower, Single Supply, Rail-to-Rail Input-Output Instrumentation Amplifiers;
EL8170
型号: EL8170
厂家: RENESAS TECHNOLOGY CORP    RENESAS TECHNOLOGY CORP
描述:

Micropower, Single Supply, Rail-to-Rail Input-Output Instrumentation Amplifiers

文件: 总14页 (文件大小:985K)
中文:  中文翻译
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DATASHEET  
EL8170, EL8173  
Micropower, Single Supply, Rail-to-Rail Input-Output Instrumentation Amplifiers  
FN7490  
Rev 8.00  
August 11, 2015  
The EL8170 and EL8173 are micropower instrumentation  
Features  
amplifiers optimized for single supply operation over the  
• 95µA maximum supply current  
+2.4V to +5.5V range. Inputs and outputs can operate  
rail-to-rail. As with all instrumentation amplifiers, a pair of  
inputs provide very high common-mode rejection and are  
completely independent from a pair of feedback terminals.  
The feedback terminals allow zero input to be translated to any  
output offset, including ground. A feedback divider controls the  
overall gain of the amplifier.  
• Maximum offset voltage  
- 200µV (EL8170)  
- 1000µV (EL8173)  
• Maximum 3nA input bias current  
• 396kHz -3dB bandwidth (G = 10)  
• 192kHz -3dB bandwidth (G = 100)  
The EL8170 is compensated for a gain of 100 or more, and the  
EL8173 is compensated for a gain of 10 or more. The EL8170  
and EL8173 have bipolar input devices for best offset and  
1/f noise performance.  
• Single supply operation  
- Input voltage range is rail-to-rail  
- Output swings rail-to-rail  
The amplifiers can be operated from one lithium cell or two  
Ni-Cd batteries. The EL8170 and EL8173 input range includes  
ground to slightly above positive rail. The output stage swings  
to ground and positive supply (no pull-up or pull-down resistors  
are needed).  
• Pb-Free (RoHS Compliant)  
Applications  
• Battery- or Solar-Powered Systems  
• Strain Gauges  
Pin Configurations  
• Current Monitors  
EL8170  
(8 LD SOIC)  
TOP VIEW  
• Thermocouple Amplifiers  
Ordering Information  
+
DNC  
IN-  
1
2
3
4
8
7
6
5
FB+  
V+  
-
PART NUMBER  
PART  
PACKAGE  
PKG.  
DWG. #  
-
+
(Notes 2, 3)  
MARKING  
(RoHS Compliant)  
IN+  
V-  
VOUT  
FB-  
EL8170FSZ (Note 1)  
8170FSZ 8 Ld SOIC  
8173FSZ 8 Ld SOIC  
M8.15E  
M8.15E  
EL8173FSZ (Note 1)  
(No longer available  
or supported)  
EL8173  
(8 LD SOIC)  
TOP VIEW  
EL8170FWZ-EVAL  
Evaluation Board  
Evaluation Board  
EL8173EV1Z (No  
longer available or  
supported)  
+
-
DNC  
IN-  
1
2
3
4
8
7
6
5
FB+  
V+  
-
EL8173FWZ-EVAL  
(No longer available or  
supported)  
Evaluation Board  
+
IN+  
V-  
VOUT  
FB-  
NOTES:  
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on  
reel specifications.  
2. These Intersil Pb-free plastic packaged products employ special  
Pb-free material sets, molding compounds/die attach materials, and  
100% matte tin plate plus anneal (e3 termination finish, which is  
RoHS compliant and compatible with both SnPb and Pb-free  
soldering operations). Intersil Pb-free products are MSL classified at  
Pb-free peak reflow temperatures that meet or exceed the Pb-free  
requirements of IPC/JEDEC J STD-020.  
3. For Moisture Sensitivity Level (MSL), please see device information  
page for EL8170, EL8173 For more information on MSL, please see  
tech brief TB363.  
FN7490 Rev 8.00  
August 11, 2015  
Page 1 of 14  
EL8170, EL8173  
Absolute Maximum Ratings (T = +25°C)  
Thermal Information  
A
Supply Voltage Range, V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.75V, 1V/µs  
Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA  
Differential Input Voltage  
EL8170. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5V  
EL8173. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.0V  
ESD Rating  
Thermal Resistance (Typical)  
(°C/W)  
122  
JA  
8 Ld SOIC Package (Note 4) . . . . . . . . . . . . . . . . . . . . . .  
Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indefinite  
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . .-40°C to +125°C  
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C  
Human Body Model (EL8173). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2500V  
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250V  
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below  
http://www.intersil.com/pbfree/Pb-FreeReflow.asp  
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product  
reliability and result in failures not covered by warranty.  
NOTE:  
4. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.  
JA  
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise  
noted, all tests are at the specified temperature and are pulsed tests, therefore: T = T = T  
J
C
A
Electrical Specifications V = +5V, V = GND, VCM = 1/2V , R = Open, T = +25°C, unless otherwise specified. Boldface limits apply  
+
-
+
L
A
over the operating temperature range, -40°C to +125°C.  
MIN  
MAX  
PARAMETER  
DESCRIPTION  
CONDITIONS  
(Note 5)  
TYP  
(Note 5)  
UNIT  
DC SPECIFICATIONS  
V
Input Offset Voltage  
EL8170  
EL8173  
-200  
-300  
±50  
200  
300  
µV  
µV  
OS  
-1000  
±200  
1000  
-1500  
1500  
TCV  
OS  
Input Offset Voltage Temperature  
Coefficient  
EL8170  
EL8173  
0.24  
2.5  
µV/°C  
µV/°C  
nA  
I
I
Input Offset Current between IN+, and IN-  
and between FB+ and FB-  
-2  
-3  
±0.2  
2
3
OS  
Input Bias Current (IN+, IN-, FB+, and FB-  
terminals)  
-3  
-4  
±0.7  
3
4
nA  
B
V
Input Voltage Range  
Guaranteed by CMRR test  
0
5
V
IN  
CMRR  
Common Mode Rejection Ratio  
EL8170  
EL8173  
EL8170  
EL8173  
EL8170  
EL8173  
V
= 0V to +5V  
90  
85  
114  
106  
106  
90  
dB  
CM  
85  
80  
dB  
dB  
dB  
%
PSRR  
Power Supply Rejection Ratio  
V
= +2.4V to +5.5V  
85  
80  
+
75  
70  
E
Gain Error  
R
= 100kΩ to +2.5V  
L
-1.5  
2
+0.35  
+0.1  
1.5  
2
G
-0.4  
0.4  
%
-0.8  
0.8  
FN7490 Rev 8.00  
August 11, 2015  
Page 2 of 14  
EL8170, EL8173  
Electrical Specifications V = +5V, V = GND, VCM = 1/2V , R = Open, T = +25°C, unless otherwise specified. Boldface limits apply  
+
-
+
L
A
over the operating temperature range, -40°C to +125°C. (Continued)  
MIN  
MAX  
PARAMETER  
OUT  
DESCRIPTION  
CONDITIONS  
(Note 5)  
TYP  
4
(Note 5)  
UNIT  
mV  
V
V
Maximum Voltage Swing  
Output low, R = 100kΩ to +2.5V  
10  
L
Output low, R = 1kΩ to +2.5V  
0.13  
0.2  
L
0.25  
Output high, R = 100kΩ to +2.5V  
4.985  
4.996  
V
L
4.980  
Output high, R = 1kΩto +2.5V  
4.75  
4.887  
65  
V
L
I
Supply Current  
45  
95  
µA  
S
38  
110  
V
Supply Operating Range  
V
V
to V  
-
2.4  
5.5  
V
SUPPLY  
+
I
I
Output Source Current into 10to V /2  
= +5V  
23  
19  
32  
8
mA  
O+  
+
+
V
V
V
= +2.4V  
= +5V  
6
4.5  
mA  
mA  
mA  
+
+
+
Output Sink Current into 10to V /2  
19  
15  
26  
7
O-  
+
= +2.4V  
5
4
AC SPECIFICATIONS  
-3dB BW -3dB Bandwidth  
EL8170  
EL8173  
Gain = 100  
Gain = 200  
Gain = 500  
Gain = 1000  
Gain = 10  
192  
93  
kHz  
kHz  
kHz  
kHz  
kHz  
kHz  
kHz  
kHz  
30  
13  
396  
221  
69  
Gain = 20  
Gain = 50  
Gain = 100  
f = 0.1Hz to 10Hz  
30  
e
Input Noise Voltage  
EL8170  
EL8173  
EL8170  
EL8173  
EL8170  
EL8173  
EL8170  
EL8173  
EL8170  
EL8173  
3.5  
3.6  
58  
µV  
µV  
N
P-P  
P-P  
Input Noise Voltage Density  
Input Noise Current Density  
Input Common Mode Rejection Ratio  
f = 1kHz  
nV/Hz  
nV/Hz  
pA/Hz  
pA/Hz  
dB  
o
220  
0.38  
0.8  
100  
84  
i
f
= 1kHz  
= 1kHz  
N
o
f
o
CMRR @ 60Hz  
V
R
= 1V  
,
P-P  
CM  
= 10kΩ to V  
L
CM  
dB  
PSRR+ @  
120Hz  
Power Supply Rejection Ratio (V )  
V , V = ±2.5V,  
98  
dB  
+
+
-
V
= 1V  
,
SOURCE  
P-P  
78  
dB  
R
= 10kΩto V  
L
CM  
PSRR- @  
120Hz  
Power Supply Rejection Ratio (V )  
EL8170  
EL8173  
V , V = ±2.5V,  
106  
82  
dB  
dB  
-
+
-
V
= 1V  
,
SOURCE  
P-P  
R
= 10kΩ to V  
L
CM  
TRANSIENT RESPONSE  
SR  
Slew Rate  
R = 1kΩ to GND  
0.4  
0.55  
0.7  
V/µs  
L
0.35  
0.7  
NOTE:  
5. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization  
and are not production tested.  
FN7490 Rev 8.00  
August 11, 2015  
Page 3 of 14  
EL8170, EL8173  
Typical Performance Curves  
V
= +5V, V = 0V, V = +2.5V, R = Open, unless otherwise specified.  
CM  
+
-
L
90  
70  
60  
50  
40  
30  
20  
10  
COMMON-MODE INPUT = 1/2V  
COMMON-MODE INPUT = 1/2V  
+
+
GAIN = 1000  
GAIN = 500  
GAIN = 10,000V/V  
80  
70  
60  
50  
40  
30  
GAIN = 5,000V/V  
GAIN = 2,000V/V  
GAIN = 200  
GAIN = 100  
GAIN = 50  
GAIN = 1,000V/V  
GAIN = 500V/V  
GAIN = 200V/V  
GAIN = 100V/V  
GAIN = 20  
GAIN = 10  
1
10  
100  
1k  
10k  
100k  
1M  
10k  
FREQUENCY (Hz)  
100k  
1
100  
1k  
1M  
10  
FREQUENCY (Hz)  
FIGURE 1. EL8170 FREQUENCY RESPONSE vs CLOSED LOOP  
GAIN  
FIGURE 2. EL8173 FREQUENCY RESPONSE vs CLOSED LOOP  
GAIN  
45  
25  
V
= 5V  
+
40  
35  
30  
V = 5V  
+
20  
15  
10  
5
V
= 3.3V  
V
= 3.3V  
+
+
25  
20  
15  
10  
5
V
= 2.4V  
+
A
R
C
= 100  
= 10kΩ  
= 10pF  
100  
V
V = 2.4V  
+
A
R
C
= 10  
= 10kΩ  
= 10pF  
V
L
L
L
L
R /R = 99.02  
R
R
F
F
G
G
R /R = 99.08Ω  
R
R
F
F
G
G
= 221kΩ  
= 178kΩ  
= 2.23kΩ  
= 19.6kΩ  
0
0
100  
1k  
10k  
100  
100k  
1M  
1k  
10k  
FREQUENCY (Hz)  
100k  
1M  
FREQUENCY (Hz)  
FIGURE 4. EL8173 FREQUENCY RESPONSE vs SUPPLY VOLTAGE  
FIGURE 3. EL8170 FREQUENCY RESPONSE vs SUPPLY VOLTAGE  
50  
45  
30  
25  
20  
15  
10  
5
C
= 100 F  
P
L
C
= 47 F  
P
L
C
= 820 F  
P
L
C
= 470 F  
P
L
C
= 27 F  
40  
35  
L
P
C
= 220 F  
P
L
A
= 10  
C
= 2.7 F  
P
A
= 100  
V
L
V
V+ = 5V  
R
R /R = 9.08Ω  
R
R
V+, V- = ±2.5V  
= 10kΩ  
C
= 56 F  
P
L
= 10kΩ  
R
L
L
R /R = 99.02  
R
R
F
F
G
G
F
F
G
G
= 221kΩ  
= 178kΩ  
30  
25  
= 19.6kΩ  
= 2.23kΩ  
0
1k  
100  
1M  
10k  
FREQUENCY (Hz)  
100k  
100k  
100  
1k  
1M  
10k  
FREQUENCY (Hz)  
FIGURE 6. EL8173 FREQUENCY RESPONSE vs C  
LOAD  
FIGURE 5. EL8170 FREQUENCY RESPONSE vs C  
LOAD  
FN7490 Rev 8.00  
August 11, 2015  
Page 4 of 14  
EL8170, EL8173  
Typical Performance Curves  
V
= +5V, V = 0V, V = +2.5V, R = Open, unless otherwise specified. (Continued)  
CM  
+
-
L
120  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
100  
80  
CMRR  
CMRR  
60  
40  
20  
0
-10  
10  
100  
1k  
10k  
100k  
1M  
10  
100  
1k  
10k  
100k  
1M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
FIGURE 8. EL8173 CMRR vs FREQUENCY  
FIGURE 7. EL8170 CMRR vs FREQUENCY  
140  
120  
100  
80  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
PSRR+  
PSRR+  
PSRR-  
PSRR-  
60  
40  
20  
0
10  
100  
1k  
10k  
100k  
1M  
10  
100  
1k  
10k  
100k  
1M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
FIGURE 10. EL8173 PSRR vs FREQUENCY  
FIGURE 9. EL8170 PSRR vs FREQUENCY  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
250  
200  
150  
100  
50  
1
10  
100  
1k  
10k  
100k  
1
10  
100  
1k  
10k  
100k  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
FIGURE 12. EL8173 VOLTAGE NOISE DENSITY  
FIGURE 11. EL8170 VOLTAGE NOISE DENSITY  
FN7490 Rev 8.00  
August 11, 2015  
Page 5 of 14  
EL8170, EL8173  
Typical Performance Curves  
V
= +5V, V = 0V, V = +2.5V, R = Open, unless otherwise specified. (Continued)  
CM  
+
-
L
1.0  
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
1
10  
100  
1k  
10k  
100k  
1
10  
100  
1k  
10k  
100k  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
FIGURE 13. EL8170 CURRENT NOISE DENSITY  
FIGURE 14. EL8173 CURRENT NOISE DENSITY  
TIME (1s/DIV)  
TIME (1s/DIV)  
FIGURE 16. EL8173 0.1Hz TO 10Hz INPUT VOLTAGE NOISE  
(GAIN = 10)  
FIGURE 15. EL8170 0.1Hz TO 10Hz INPUT VOLTAGE NOISE  
(GAIN = 100)  
85  
90  
N = 2000  
80  
N = 1000  
85  
MAX  
80  
75  
MAX  
75  
70  
MEDIAN  
70  
65  
60  
55  
50  
45  
40  
65  
MEDIAN  
60  
MIN  
55  
MIN  
50  
45  
40  
-40  
100  
-20  
0
20  
40  
60  
80  
120  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
FIGURE 17. EL8170 SUPPLY CURRENT vs TEMPERATURE,  
V = ±2.5V, V = 0V  
FIGURE 18. EL8173 SUPPLY CURRENT vs TEMPERATURE,  
V = ±2.5V, V = 0V  
V
+,  
-
IN  
V
+,  
-
IN  
FN7490 Rev 8.00  
August 11, 2015  
Page 6 of 14  
EL8170, EL8173  
Typical Performance Curves  
V
= +5V, V = 0V, V = +2.5V, R = Open, unless otherwise specified. (Continued)  
CM  
+
-
L
300  
1000  
500  
N = 2000  
N = 1000  
MAX  
200  
MAX  
100  
MEDIAN  
0
MEDIAN  
0
-500  
-1000  
-1500  
-100  
MIN  
MIN  
-200  
-300  
-40  
-20  
0
20  
40  
60  
80  
100 120  
-40  
-20  
0
20  
40  
60  
80  
100 120  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
FIGURE 20. EL8173 V vs TEMPERATURE, V V = ±2.5V,  
FIGURE 19. EL8170 V vs TEMPERATURE, V V = ±2.5V,  
OS  
+,  
-
OS  
+,  
-
V
= 0V  
V
= 0V  
IN  
IN  
400  
300  
200  
100  
0
1000  
500  
N = 1000  
N = 2000  
MAX  
MAX  
0
MEDIAN  
MIN  
MEDIAN  
-500  
-1000  
-1500  
-100  
-200  
-300  
MIN  
-40  
-20  
0
20  
40  
60  
80  
100 120  
-40  
-20  
0
20  
40  
60  
80  
100 120  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
FIGURE 21. EL8170 V vs TEMPERATURE, V V = ±1.2V,  
FIGURE 22. EL8173 V vs TEMPERATURE, V V = ±1.2V,  
OS +,  
OS  
+,  
-
-
V
= 0V  
V
= 0V  
IN  
IN  
140  
130  
120  
110  
100  
90  
140  
130  
120  
110  
100  
90  
N = 2000  
N = 1000  
MAX  
MAX  
MEDIAN  
MEDIAN  
MIN  
80  
MIN  
80  
80  
-40  
-20  
0
20  
40  
60  
100  
120  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
FIGURE 23. EL8170 CMRR vs TEMPERATURE,  
= +2.5V TO -2.5V, V V = ±2.5V  
FIGURE 24. EL8173 CMRR vs TEMPERATURE,  
= +2.5V TO -2.5V, V V = ±2.5V  
V
V
CM  
CM  
+,  
-
+, -  
FN7490 Rev 8.00  
August 11, 2015  
Page 7 of 14  
EL8170, EL8173  
Typical Performance Curves  
V
= +5V, V = 0V, V = +2.5V, R = Open, unless otherwise specified. (Continued)  
+
-
CM  
L
140  
140  
130  
120  
110  
100  
90  
N = 2000  
MAX  
N = 1000  
MAX  
130  
120  
110  
100  
90  
MEDIAN  
MEDIAN  
80  
80  
MIN  
MIN  
40  
70  
70  
60  
60  
-40  
-20  
0
20  
60  
80  
100  
120  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
FIGURE 26. EL8173 PSRR vs TEMPERATURE,  
V = ±1.2V TO ±2.5V  
FIGURE 25. EL8170 PSRR vs TEMPERATURE,  
V
V
V = ±1.2V TO ±2.5V  
+,  
-
+,  
-
2.4  
1.9  
1.4  
0.9  
0.4  
-0.1  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
N = 1000  
N = 2000  
MAX  
MAX  
MEDIAN  
MEDIAN  
MIN  
-20  
MIN  
-20  
-0.1  
-40  
-40  
0
20  
40  
60  
80  
100  
120  
0
20  
40  
60  
80  
100  
120  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
FIGURE 27. EL8170 %GAIN ERROR vs TEMPERATURE,  
FIGURE 28. EL8173 %GAIN ERROR vs TEMPERATURE,  
R = 100k  
R = 100k  
L
L
4.91  
4.91  
N = 2000  
N = 1000  
4.90  
4.90  
MAX  
MAX  
4.89  
4.89  
4.88  
MEDIAN  
MEDIAN  
4.88  
4.87  
4.87  
MIN  
4.86  
MIN  
4.86  
4.85  
4.84  
4.85  
4.84  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
FIGURE 30. EL8173 V  
OUT  
HIGH vs TEMPERATURE,  
FIGURE 29. EL8170 V  
OUT  
HIGH vs TEMPERATURE,  
R = 1k, V V = ±2.5V  
R = 1k, V V = ±2.5V  
L
+,  
-
L
+, -  
FN7490 Rev 8.00  
August 11, 2015  
Page 8 of 14  
EL8170, EL8173  
Typical Performance Curves  
V
= +5V, V = 0V, V = +2.5V, R = Open, unless otherwise specified. (Continued)  
+
-
CM  
L
200  
200  
180  
160  
140  
120  
100  
80  
N = 2000  
N = 1000  
180  
160  
MAX  
MAX  
140  
MEDIAN  
MEDIAN  
120  
100  
80  
MIN  
MIN  
-40  
-20  
0
20  
40  
80  
100  
120  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
60  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
FIGURE 32. EL8173 V  
OUT  
LOW vs TEMPERATURE,  
FIGURE 31. EL8170 V  
OUT  
LOW vs TEMPERATURE,  
R = 1k, V V = ±2.5V  
R = 1k, V V = ±2.5V  
L
+, -  
L
+, -  
0.70  
0.65  
0.60  
0.55  
0.50  
0.45  
0.40  
0.65  
0.60  
0.55  
0.50  
0.45  
0.40  
0.35  
0.30  
N = 2000  
N = 1000  
MAX  
MAX  
MEDIAN  
MEDIAN  
MIN  
MIN  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
FIGURE 34. EL8173 + SLEW RATE vs TEMPERATURE,  
INPUT ±0.015V @ GAIN + 100  
FIGURE 33. EL8170 + SLEW RATE vs TEMPERATURE,  
INPUT ±0.015V @ GAIN + 100  
0.70  
0.70  
MAX  
N = 2000  
N = 1000  
MAX  
0.65  
0.65  
0.60  
MEDIAN  
MEDIAN  
MIN  
0.60  
0.55  
0.50  
0.45  
0.40  
0.55  
0.50  
MIN  
0.45  
0.40  
0.35  
0.30  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
-40  
-20  
0
20  
40  
60  
80  
100  
120  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
FIGURE 36. EL8173 - SLEW RATE vs TEMPERATURE,  
INPUT ±0.015V @ GAIN + 100  
FIGURE 35. EL8170 - SLEW RATE vs TEMPERATURE,  
INPUT ±0.015V @ GAIN + 100  
FN7490 Rev 8.00  
August 11, 2015  
Page 9 of 14  
EL8170, EL8173  
Pin Descriptions  
EL8170  
EL8173  
PIN NAME  
EQUIVALENT CIRCUIT  
PIN FUNCTION  
1
2
3
1
2
3
DNC  
Do Not Connect; Internal connection - Must be left floating.  
IN-  
Circuit 1A, Circuit 1B High impedance input terminals. The EL8170 input circuit is shown in Circuit 1A,  
and the EL8173 input circuit is shown in Circuit 1B.  
IN+  
Circuit 1A, Circuit 1B  
The EL8173: to avoid offset drift, it is recommended that the terminals are not  
overdriven beyond 1V and the input current must never exceed 5mA.  
4
5
8
4
5
8
V-  
Circuit 3  
Negative supply terminal.  
FB-  
FB+  
Circuit 1A, Circuit 1B High impedance feedback terminals. The EL8170 input circuit is shown in  
Circuit 1A, and the EL8173 input circuit is shown in Circuit 1B.  
Circuit 1A, Circuit 1B  
The EL8173: to avoid offset drift, it is recommended that the terminals are not  
overdriven beyond 1V and the input current must never exceed 5mA.  
7
6
7
6
V+  
Circuit 3  
Circuit 2  
Positive supply terminal.  
Output voltage.  
VOUT  
V+  
V-  
V+  
V+  
CAPACITIVELY  
COUPLED  
ESD CLAMP  
IN+  
FB+  
IN-  
FB-  
OUT  
V-  
V-  
CIRCUIT 1A  
CIRCUIT 2  
CIRCUIT 3  
V+  
IN-  
IN+  
FB-  
FB+  
V-  
CIRCUIT 1B  
additional back-to-back diodes across the input terminals and  
also across the feedback terminals. If overdriving the inputs is  
necessary, the external input current must never exceed 5mA. On  
the other hand, the EL8173 has no clamps to limit the  
differential voltage on the input terminals allowing higher  
differential input voltages at lower gain applications. It is  
recommended however, that the input terminals of the EL8173  
are not overdriven beyond 1V to avoid offset drift. An external  
series resistor may be used as an external protection to limit  
excessive external voltage and current from damaging the  
inputs.  
Description of Operation and  
Applications Information  
Product Description  
The EL8170 and EL8173 are micropower instrumentation  
amplifiers (in-amps) which deliver rail-to-rail input amplification and  
rail-to-rail output swing on a single +2.4V to +5.5V supply. The  
EL8170 and EL8173 also deliver excellent DC and AC specifications  
while consuming only 65µA typical supply current. The EL8170 and  
EL8173 provides an independent pairs of feedback terminals to set  
the gain and to adjust output level, these in-amps achieve high  
common-mode rejection ratio regardless of the tolerance of the gain  
setting resistors. The EL8173 is internally compensated for a  
minimum closed loop gain of 10 or greater, well suited for moderate  
to high gains. For higher gains, the EL8170 is internally  
Input Stage and Input Voltage Range  
The input terminals (IN+ and IN-) of the EL8170 and EL8173 are  
single differential pair bipolar PNP devices aided by an Input  
Range Enhancement Circuit to increase the headroom of  
operation of the common-mode input voltage. The feedback  
terminals (FB+ and FB-) also have a similar topology. As a result,  
the input common-mode voltage range of both the EL8170 and  
EL8173 is rail-to-rail. These in-amps are able to handle the input  
voltages that are at or slightly beyond the supply and ground  
making these in-amps well suited for single +5V or +3.3V low  
voltage supply systems. There is no need to move the  
common-mode input of the in-amps to achieve symmetrical input  
voltage.  
compensated for a minimum gain of 100.  
Input Protection  
All input and feedback terminals of the EL8170 and EL8173 have  
internal ESD protection diodes to both positive and negative  
supply rails, limiting the input voltage to within one diode drop  
beyond the supply rails. The inverting inputs and FB- have ESD  
diodes to the V-rail, and the non-inverting inputs and FB+  
terminals have ESD diodes to the V+ rail. The EL8170 has  
FN7490 Rev 8.00  
August 11, 2015  
Page 10 of 14  
EL8170, EL8173  
Input Bias Cancellation, Input  
Bias Compensation  
R
F
(EQ. 1)  
--------  
V
=
1 +  
V
OUT  
IN  
R
G
The EL8170 and EL8173 are features an Input Bias Cancellation  
and Input Bias Compensation Circuit for both the input and  
feedback terminals (IN+, IN-, FB+ and FB-), achieving a low input  
bias current all throughout the input common-mode range and the  
operating temperature range. While the PNP bipolar input stages  
are biased with an adequate amount of biasing current for speed  
and increased noise performance, the Input Bias Cancellation and  
the Input Bias Compensation Circuit, sinks most of the base  
current of the input transistor leaving a small portion as input bias  
current, typically 500pA. In addition, the Input Bias Cancellation  
and Input Bias Compensation Circuit, maintains a smooth and flat  
behavior of the input bias current over the common mode range  
and over the operating temperature range. The Input Bias  
Cancellation and Input Bias Compensation Circuit, operates from  
the input voltages of 10mV above the negative supply to the input  
voltages slightly above the positive supply. See “Average Input Bias  
Current vs Common-Mode Input Voltage” in the “Typical  
In Figure 37, the FB+ pin and one end of resistor R are connected  
G
to GND. With this configuration, Equation 1 is only true for a positive  
swing in VIN; negative input swings will be ignored and the output  
will be at ground.  
Reference Connection  
Unlike a three op amp instrumentation amplifier, a finite series  
resistance seen at the REF terminal does not degrade the  
EL8170 and EL8173's high CMRR performance, eliminating the  
need for an additional external buffer amplifier. The circuit shown  
in Figure 38 uses the FB+ pin as a REF terminal to center or to  
adjust the output. Because the FB+ pin is a high impedance  
input, an economical resistor divider can be used to set the  
voltage at the REF terminal. The reference voltage error due to  
the input bias current is minimized by keeping the values of the  
voltage divider resistors, R and R , as low as possible. Any  
1
2
voltage applied to the REF terminal will shift V  
by VREF times  
the closed loop gain, which is set by resistors R and R  
OUT  
F
Performance Curves” beginning on page 4.  
G
according to Equation 2. Note that any noise or unwanted signals  
on the reference supply will be amplified at the output according  
to Equation 2.  
Output Stage and Output Voltage Range  
A pair of complementary MOSFET devices drives the output V  
OUT  
to within a few millivolts of the supply rails. At a 100kload, the  
PMOS sources current and pulls the output up to 4mV below the  
positive supply, while the NMOS sinks current and pulls the  
output down to 4mV above the negative supply, or ground in the  
case of a single supply operation. The current sinking and  
sourcing capability of the EL8170 and EL8173 are internally  
limited to 26mA.  
R
R
F
R
G
F
(EQ. 2)  
--------  
--------  
V
=
1 +  
V + 1 +  
V  
REF  
OUT  
IN  
R
G
+2.4V TO +5.5V  
7
1
VIN/2  
VIN/2  
V+  
3
2
8
5
IN+  
IN-  
Gain Setting  
+
-
6
V
, the potential difference across IN+ and IN-, is replicated (less  
EL8170,  
EL8173  
IN  
VOUT  
FB+  
FB-  
the input offset voltage) across FB+ and FB-. The objective of the  
EL8170 and EL8173 in-amp is to maintain the differential  
voltage across FB+ and FB- equal to IN+ and IN-; (FB- - FB+) =  
(IN+ - IN-). Consequently, the transfer function can be derived.  
The gain of the EL8170 and EL8173 is set by two external  
resistors, the feedback resistor R , and the gain resistor R .  
+
-
+2.4V TO +5.5V  
VCM  
V-  
R1  
4
REF  
R2  
F
G
RG  
RF  
+2.4V TO +5.5V  
FIGURE 38. GAIN SETTING AND REFERENCE CONNECTION  
7
1
VIN/2  
VIN/2  
V+  
3
2
8
5
IN+  
IN-  
The FB+ pin can also be connected to the other end of resistor,  
(see Figure 39). Keeping the basic concept that the EL8170  
and EL8173 in-amps maintain constant differential voltage  
across the input terminals and feedback terminals  
+
R
G
-
6
EL8170,  
EL8173  
VOUT  
FB+  
FB-  
+
-
(IN+ - IN- = FB+ - FB-), the transfer function of Figure 39 can be  
VCM  
V-  
derived (Equation 3). Note that the V  
gain term is eliminated,  
and susceptibility to external noise is reduced.  
REF  
4
RG  
RF  
FIGURE 37. GAIN IS SET BY TWO EXTERNAL RESISTORS, R  
F
AND R  
G
FN7490 Rev 8.00  
August 11, 2015  
Page 11 of 14  
EL8170, EL8173  
.
The term [1 - (E + E + E )] is the deviation from the  
RG RF  
G
+2.4V TO +5.5V  
theoretical gain. Thus, (E + E + E ) is the total gain error. For  
RG RF  
G
example, if 1% resistors are used for the EL8170, the total gain  
error would be as shown in Equation 5:  
7
1
VIN/2  
VIN/2  
V+  
3
2
8
5
IN+  
IN-  
+
= E  
+ E  
+ E typical  
RF G  
RG  
(EQ. 5)  
-
6
EL8170,  
EL8173  
= 0.01 + 0.01 + 0.003  
= 2.3%  
VOUT  
FB+  
FB-  
+
-
VCM  
V-  
4
Power Dissipation  
It is possible to exceed the +150°C maximum junction  
temperatures under certain load and power-supply conditions. It  
is therefore important to calculate the maximum junction  
RG  
RF  
VREF  
temperature (T  
) for all applications to determine if power  
JMAX  
supply voltages, load conditions, or package type need to be  
modified to remain in the safe operating area. These parameters  
are related in Equation 6:  
FIGURE 39. REFERENCE CONNECTION WITH AN AVAILABLE V  
REF  
T
= T  
+  xPD  
MAXTOTAL  
(EQ. 6)  
JMAX  
MAX  
JA  
R
F
(EQ. 3)  
--------  
V
=
1 +  
V + V  
REF  
OUT  
IN  
R
G
where:  
• P  
is the sum of the maximum power dissipation of  
External Resistor Mismatches  
DMAXTOTAL  
each amplifier in the package (PD  
)
MAX  
Because of the independent pair of feedback terminals provided  
by the EL8170 and EL8173, the CMRR is not degraded by any  
resistor mismatches. Hence, unlike a three op amp and  
especially a two op amp in-amp, the EL8170 and EL8173 reduce  
the cost of external components by allowing the use of 1% or  
more tolerance resistors without sacrificing CMRR performance.  
The EL8170 and EL8173 CMRR is maintained regardless of the  
tolerance of the resistors used.  
• PD  
for each amplifier can be calculated as shown in  
Equation 7:  
MAX  
V
OUTMAX  
R
L
----------------------------  
PD  
= 2*V I  
+ V - V    
OUTMAX  
MAX  
S
SMAX  
S
(EQ. 7)  
where:  
• T  
MAX  
= Maximum ambient temperature  
Gain Error and Accuracy  
= Thermal resistance of the package  
JA  
The EL8173 has a Gain Error, E , of 0.2% typical. The EL8170 has  
G
• PD  
MAX  
= Maximum power dissipation of 1 amplifier  
an E of 0.3% typical. The gain error indicated in the “Electrical  
G
Specifications” table on page 2 is the inherent gain error of the  
EL8170 and EL8173 and does not include the gain error  
contributed by the resistors. There is an additional gain error due  
to the tolerance of the resistors used. The resulting non-ideal  
transfer function effectively becomes Equation 4:  
• V = Supply voltage (Magnitude of V and V )  
S
+
-
• I  
= Maximum supply current of 1 amplifier  
MAX  
• V  
= Maximum output voltage swing of the application  
• R = Load resistance  
OUTMAX  
L
R
F
(EQ. 4)  
--------  
V
=
1 +  
 1 E  
+ E  
+ E   V  
RF G IN  
OUT  
RG  
R
G
Where:  
E
E
E
= Tolerance of R  
RG  
G
= Tolerance of R  
RF  
F
= Gain Error of the EL8170 or EL8173  
G
FN7490 Rev 8.00  
August 11, 2015  
Page 12 of 14  
EL8170, EL8173  
Revision History  
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that  
you have the latest revision.  
DATE  
REVISION  
FN7490.8  
CHANGE  
August 11, 2015  
Added Revision History beginning with Rev 8.  
Added About Intersil Verbiage.  
Updated Ordering Information on page 1.  
About Intersil  
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products  
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.  
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product  
information page found at www.intersil.com.  
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.  
Reliability reports are also available from our website at www.intersil.com/support  
© Copyright Intersil Americas LLC 2009-2015. All Rights Reserved.  
All trademarks and registered trademarks are the property of their respective owners.  
For additional products, see www.intersil.com/en/products.html  
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted  
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html  
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such  
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are  
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its  
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
FN7490 Rev 8.00  
August 11, 2015  
Page 13 of 14  
EL8170, EL8173  
Package Outline Drawing  
M8.15E  
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE  
Rev 0, 08/09  
4
4.90 ± 0.10  
A
DETAIL "A"  
0.22 ± 0.03  
B
6.0 ± 0.20  
3.90 ± 0.10  
4
PIN NO.1  
ID MARK  
5
(0.35) x 45°  
4° ± 4°  
0.43 ± 0.076  
1.27  
0.25 M C A B  
SIDE VIEW “B”  
TOP VIEW  
1.75 MAX  
1.45 ± 0.1  
0.25  
GAUGE PLANE  
C
SEATING PLANE  
0.175 ± 0.075  
SIDE VIEW “A  
0.10 C  
0.63 ±0.23  
DETAIL "A"  
(0.60)  
(1.27)  
NOTES:  
(1.50)  
1. Dimensions are in millimeters.  
Dimensions in ( ) for Reference Only.  
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.  
3.  
Unless otherwise specified, tolerance : Decimal ± 0.05  
(5.40)  
4. Dimension does not include interlead flash or protrusions.  
Interlead flash or protrusions shall not exceed 0.25mm per side.  
The pin #1 identifier may be either a mold or mark feature.  
Reference to JEDEC MS-012.  
5.  
6.  
TYPICAL RECOMMENDED LAND PATTERN  
FN7490 Rev 8.00  
August 11, 2015  
Page 14 of 14  

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