EL5421CY-T7 [RENESAS]
EL5421CY-T7;
| 型号： | EL5421CY-T7 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | EL5421CY-T7 |
| 文件： | 总12页 (文件大小：557K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
EL5421
FN7198
Rev 2.00
August 2, 2007
Quad 12MHz Rail-to-Rail Input-Output Buffer
The EL5421 is a quad, low power, high voltage rail-to-rail
input-output buffer. Operating on supplies ranging from 5V to
15V, while consuming only 500µA per channel, the EL5421
has a bandwidth of 12MHz (-3dB). The EL5421 also
provides rail-to-rail input and output ability, giving the
maximum dynamic range at any supply voltage.
Features
• 12MHz -3dB bandwidth
• Unity gain buffer
• Supply voltage = 4.5V to 16.5V
• Low supply current (per buffer) = 500µA
• High slew rate = 10V/µs
The EL5421 also features fast slewing and settling times, as
well as a high output drive capability of 30mA (sink and
source). These features make the EL5421 ideal for use as
voltage reference buffers in Thin Film Transistor Liquid
Crystal Displays (TFT-LCD). Other applications include
battery power, portable devices and anywhere low power
consumption is important.
• Rail-to-rail operation
• “Mini” SO package (MSOP)
• Pb-free plus anneal available (RoHS compliant)
Applications
The EL5421 is available in a space saving 10 Ld MSOP
package and operates over a temperature range of -40°C to
+85°C.
• TFT-LCD drive circuits
• Electronics notebooks
• Electronics games
Pinout
EL5421
(10 LD MSOP)
TOP VIEW
• Personal communication devices
• Personal digital assistants (PDA)
• Portable instrumentation
• Wireless LANs
VOUTA
VINA
1
2
3
4
5
10 VOUTD
9
8
7
6
VIND
VS-
• Office automation
VS+
• Active filters
VINB
VINC
VOUTC
• ADC/DAC buffers
VOUTB
Ordering Information
PART
PART
NUMBER
MARKING
PACKAGE
10 Ld MSOP
10 Ld MSOP
10 Ld MSOP
PKG. DWG. #
MDP0043
MDP0043
MDP0043
MDP0043
EL5421CY
F
EL5421CY-T7*
EL5421CY-T13*
F
F
EL5421CYZ
(Note)
BCAAA
10 Ld MSOP
(Pb-Free)
EL5421CYZ-T7* BCAAA
(Note)
10 Ld MSOP
(Pb-Free)
MDP0043
MDP0043
EL5421CYZ-T13* BCAAA
(Note)
10 Ld MSOP
(Pb-Free)
*Please refer to TB347 for details on reel specifications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
FN7198 Rev 2.00
August 2, 2007
Page 1 of 12
EL5421
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
Supply Voltage between V + and V -. . . . . . . . . . . . . . . . . . . .+18V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
S
S
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .V - -0.5V, V + +0.5V
S
S
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
Electrical Specifications V + = +5V, V - = -5V, R = 10k and C = 10pF to 0V, T = +25°C unless otherwise specified.
S
S
L
L
A
MIN
MAX
PARAMETER
DESCRIPTION
CONDITION
(Note 4)
TYP
(Note 4)
UNIT
INPUT CHARACTERISTICS
V
Input Offset Voltage
V
= 0V
2
5
12
50
mV
µV/°C
nA
OS
CM
(Note 1)
= 0V
TCV
Average Offset Voltage Drift
Input Bias Current
Input Impedance
OS
I
V
2
B
CM
R
1
G
IN
IN
C
Input Capacitance
Voltage Gain
1.35
pF
A
-4.5V V
OUT
4.5V
0.995
1.005
-4.85
V/V
V
OUTPUT CHARACTERISTICS
V
V
Output Swing Low
Output Swing High
Short Circuit Current
I = -5mA
-4.92
4.92
V
V
OL
L
I = 5mA
4.85
±80
OH
L
I
Short to GND (Note 2)
±120
mA
SC
POWER SUPPLY PERFORMANCE
PSRR Power Supply Rejection Ratio
Supply Current (Per Buffer)
DYNAMIC PERFORMANCE
SR Slew Rate (Note 3)
V
is moved from ±2.25V to ±7.75V
60
7
80
dB
µA
S
I
No load
500
750
S
-4.0V V
4.0V, 20% to 80%
10
500
12
V/µs
ns
OUT
t
Settling to +0.1%
-3dB Bandwidth
V = 2V step
O
S
BW
CS
R
= 10k, C = 10pF
MHz
dB
L
L
Channel Separation
f = 5MHz
75
FN7198 Rev 2.00
August 2, 2007
Page 2 of 12
EL5421
Electrical Specifications V + = +5V, V - = 0V, R = 10k and C = 10pF to 2.5V, T = +25°C unless otherwise specified.
S
S
L
L
A
MIN
MAX
PARAMETER
DESCRIPTION
CONDITION
(Note 4)
TYP
(Note 4)
UNIT
INPUT CHARACTERISTICS
V
Input Offset Voltage
V
= 2.5V
2
5
10
50
mV
µV/°C
nA
OS
CM
(Note 1)
= 2.5V
TCV
Average Offset Voltage Drift
Input Bias Current
Input Impedance
OS
I
V
2
B
CM
R
1
GW
pF
IN
IN
C
Input Capacitance
Voltage Gain
1.35
A
0.5 V
4.5V
OUT
0.995
1.005
150
V/V
V
OUTPUT CHARACTERISTICS
V
V
Output Swing Low
Output Swing High
Short Circuit Current
I = -5mA
80
mV
V
OL
L
I = 5mA
4.85
±80
4.92
±120
OH
L
I
Short to GND (Note 2)
mA
SC
POWER SUPPLY PERFORMANCE
PSRR Power Supply Rejection Ratio
Supply Current (Per Buffer)
DYNAMIC PERFORMANCE
SR Slew Rate (Note 3)
V
is moved from 4.5V to 15.5V
60
7
80
dB
µA
S
I
No load
500
750
S
1V V
4V, 20% to 80%
10
500
12
V/µs
ns
OUT
V = 2V step
O
t
Settling to +0.1%
-3dB Bandwidth
S
BW
CS
R
= 10k, C = 10pF
MHz
dB
L
L
Channel Separation
f = 5MHz
75
FN7198 Rev 2.00
August 2, 2007
Page 3 of 12
EL5421
Electrical Specifications V + = +15V, V - = 0V, R = 10k and C = 10pF to 7.5V, T = +25°C unless otherwise specified.
S
S
L
L
A
MIN
MAX
PARAMETER
DESCRIPTION
CONDITION
(Note 4)
TYP
(Note 4) UNIT
INPUT CHARACTERISTICS
V
Input Offset Voltage
V
= 7.5V
2
5
14
50
mV
µV/°C
nA
OS
CM
(Note 1)
= 7.5V
TCV
Average Offset Voltage Drift
Input Bias Current
Input Impedance
OS
I
V
2
B
CM
R
1
G
IN
IN
C
Input Capacitance
Voltage Gain
1.35
pF
A
0.5 V
14.5V
OUT
0.995
1.005
150
V/V
V
OUTPUT CHARACTERISTICS
V
V
Output Swing Low
Output Swing High
Short Circuit Current
I = -5mA
80
mV
V
OL
L
I = 5mA
14.85
±80
14.92
±120
OH
L
I
Short to GND (Note 2)
mA
SC
POWER SUPPLY PERFORMANCE
PSRR Power Supply Rejection Ratio
Supply Current (Per Buffer)
DYNAMIC PERFORMANCE
SR Slew Rate (Note 3)
V
is moved from 4.5V to 15.5V
60
7
80
dB
µA
S
I
No load
500
750
S
1V V
14V, 20% to 80%
10
500
12
V/µs
ns
OUT
V = 2V step
O
t
Settling to +0.1%
-3dB Bandwidth
S
BW
R
= 10k, C = 10pF
MHz
dB
L
L
CS
Channel Separation
f = 5MHz
75
NOTES:
1. Measured over the operating temperature range
2. Limits established by characterization and are not production tested.
3. Slew rate is measured on rising and falling edges
4. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested
FN7198 Rev 2.00
August 2, 2007
Page 4 of 12
EL5421
Typical Performance Curves
1800
70
60
50
40
30
20
10
0
V =±5V
TYPICAL
PRODUCTION
DISTRIBUTION
V =±5V
TYPICAL
PRODUCTION
DISTRIBUTION
S
S
1600
1400
1200
1000
800
600
400
200
0
T =25°C
A
INPUT OFFSET VOLTAGE (mV)
INPUT OFFSET VOLTAGE DRIFT, TCV
(µV/°C)
OS
FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION
FIGURE 2. INPUT OFFSET VOLTAGE DRIFT
10
2.0
V =±5V
S
V =±5V
S
5
0
0.0
-2.0
-5
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 3. INPUT OFFSET VOLTAGE vs TEMPERATURE
FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE
4.97
4.96
4.95
4.94
-4.91
V =±5V
S
I
=-5mA
OUT
-4.92
-4.93
-4.94
-4.95
-4.96
-4.97
V =±5V
S
I
=5mA
OUT
4.93
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 5. OUTPUT HIGH VOLTGE vs TEMPERATURE
FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE
FN7198 Rev 2.00
August 2, 2007
Page 5 of 12
EL5421
Typical Performance Curves
10.40
10.35
10.30
10.25
V =±5V
S
V =±5V
S
1.0005
1.0000
0.9995
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 7. VOLTAGE GAIN vs TEMPERATURE
FIGURE 8. SLEW RATE vs TEMPERATURE
700
T =25°C
V =±5V
S
A
0.55
0.5
600
500
400
300
0.45
-50
0
50
100
150
0
5
10
15
20
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
FIGURE 9. SUPPLY CURRENT PER CHANNEL vs
TEMPERATURE
FIGURE 10. SUPPLY CURRENT PER CHANNEL vs SUPPLY
VOLTAGE
5
20
R =10k
S
L
V =±5V
10k
10
0
0
12pF
50pF
1k
560
-5
150
-10
-20
-30
100pF
-10
1000pF
1M
C =10pF
L
V =±5V
S
-15
100K
1M
10M
100M
100K
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 11. FREQUENCY RESPONSE FOR VARIOUS R
FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS C
L
L
FN7198 Rev 2.00
August 2, 2007
Page 6 of 12
EL5421
Typical Performance Curves
200
12
10
8
T =25°C
A
V =±5V
S
160
120
80
6
V =±5V
S
4
T =25°C
A
R =10k
L
40
2
C =12pF
L
DISTORTION <1%
0
10K
0
10K
100K
1M
10M
100K
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 13. OUT PUT IMPEDANCE vs FREQUENCY
FIGURE 14. MAXIMUM OUTPUT SWING vs FREQUENCY
80
600
PSRR+
PSRR-
60
100
10
1
40
20
T =25°C
A
V =±5V
S
0
100
100
1K
10K
100K
1M
10M
100M
1K
10K
100K
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 15. PSRR vs FREQUENCY
FIGURE 16. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs
FREQUENCY
0.010
0.009
0.008
0.007
0.006
0.005
0.004
0.003
0.002
0.001
-60
V =±5V
S
DUAL MEASURED CH A TO B
QUAD MEASURED CH A TO D OR B TO C
OTHER COMBINATIONS YIELD IMPROVED
R =10k
L
IN
V
=1V
RMS
-80
-100
-120
-140
REJECTION
V =±5V
S
R =10k
L
IN
V
=220mV
RMS
1K
10K
100K
FREQUENCY (Hz)
1M
6M
1K
10K
100K
FREQUENCY (Hz)
FIGURE 17. TOTAL HARMONIC DISTORTION + NOISE vs
FREQUENCY
FIGURE 18. CHANNEL SEPARATION vs FREQUENCY
RESPONSE
FN7198 Rev 2.00
August 2, 2007
Page 7 of 12
EL5421
Typical Performance Curves
5
3
V =±5V
S
V =±5V
S
90
R =10k
R =10k
L
L
0.1%
V
=±50mV
C =12pF
IN
T =25°C
L
T =25°C
A
A
70
50
30
10
1
-1
-3
-5
0.1%
10
100
1K
0
200
400
600
800
LOAD CAPACITANCE (pF)
SETTLING TIME (ns)
FIGURE 19. SMALL SIGNAL OVERSHOOT vs LOAD
CAPACITANCE
FIGURE 20. SETTLING TIME vs STEP SIZE
1V
1µs
50mV
200ns
V =±5V
S
T =25°C
A
V =±5V
S
R =10k
L
T =25°C
C =12pF
A
L
R =10k
L
C =12pF
L
FIGURE 21. LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 22. SMALL SIGNAL TRANSIENT REPOSNE
FN7198 Rev 2.00
August 2, 2007
Page 8 of 12
EL5421
Pin Descriptions
PIN NUMBER
PIN NAME
FUNCTION
EQUIVALENT CIRCUIT
1
VOUTA
Buffer A Output
V +
S
V -
S
GND
CIRCUIT 1
2
VINA
Buffer A Input
V +
S
V -
S
CIRCUIT 2
3
4
VS+
VINB
Positive Power Supply
Buffer B Input
(Reference Circuit 1)
(Reference Circuit 2)
(Reference Circuit 2)
(Reference Circuit 1)
5
VOUTB
VOUTC
VINC
Buffer B Output
Buffer C Output
Buffer C Input
6
7
8
VS-
Negative Power Supply
Buffer D Input
9
VIND
(Reference Circuit 2)
(Reference Circuit 1)
10
VOUTD
Buffer D Output
voltage range even closer to the supply rails. Figure 23
shows the input and output waveforms for the device.
Operation is from ±5V supply with a 10kloadconnected to
Applications Information
Product Description
The EL5421 unity gain buffer is fabricated using a high
voltage CMOS process. It exhibits rail-to-rail input and
output capability, and has low power consumption (500µA
per buffer). These features make the EL5421 ideal for a wide
range of general-purpose applications. When driving a load
of 10k and 12pF, the EL5421 has a -3dB bandwidth of
12MHz and exhibits 10V/µs slew rate.
GND. The input is a 10V
sinusoid. The output voltage is
P-P
approximately 9.985V
.
P-P
10µs
5V
Operating Voltage, Input, and Output
The EL5421 is specified with a single nominal supply voltage
from 5V to 15V or a split supply with its total range from 5V
to 15V. Correct operation is guaranteed for a supply range of
4.5V to 16.5V. Most EL5421 specifications are stable over
both the full supply range and operating temperatures of
-40°C to +85°C. Parameter variations with operating voltage
and/or temperature are shown in the typical performance
curves.
V =±5V
S
T =25°C
A
IN
V
=10V
P-P
5V
FIGURE 23. OPERATION WITH RAIL-TO-RAIL INPUT AND
OUTPUT
Short Circuit Current Limit
The output swings of the EL5421 typically extend to within
80mV of positive and negative supply rails with load currents
of 5mA. Decreasing load currents will extend the output
The EL5421 will limit the short circuit current to ±120mA if
the output is directly shorted to the positive or the negative
supply. If an output is shorted indefinitely, the power
FN7198 Rev 2.00
August 2, 2007
Page 9 of 12
EL5421
dissipation could easily increase such that the device may
be damaged. Maximum reliability is maintained if the output
continuous current never exceeds ±30mA. This limit is set by
the design of the internal metal interconnects.
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the loads, or:
(EQ. 2)
P
= iV I
+ V + – V
i I
i
LOAD
DMAX
S
SMAX
S
OUT
Output Phase Reversal
The EL5421 is immune to phase reversal as long as the
when sourcing, and:
input voltage is limited from V - -0.5V to V + +0.5V. Figure
S
S
24 shows a photo of the output of the device with the input
voltage driven beyond the supply rails. Although the device's
output will not change phase, the input's overvoltage should
be avoided. If an input voltage exceeds supply voltage by
more than 0.6V, electrostatic protection diodes placed in the
input stage of the device begin to conduct and overvoltage
damage could occur.
(EQ. 3)
P
= iV I
+ V
i – V - I
i
LOAD
DMAX
S
SMAX
OUT
S
when sinking.
Where:
i = 1 to 4 for quad
V
= Total supply voltage
S
10µs
1V
I
= Maximum supply current per channel
SMAX
V
i = Maximum output voltage of the application
OUT
I
i = Load current
LOAD
If we set the two P
can solve for R
and 26 provide a convenient way to see if the device will
overheat. The maximum safe power dissipation can be
found graphically, based on the package type and the
ambient temperature. By using the previous equation, it is a
equations equal to each other, we
i to avoid device overheat. Figures 25
DMAX
V =±2.5V
LOAD
S
T =25°C
A
IN
V
=6V
P-P
1V
FIGURE 24. OPERATION WITH BEYOND-THE-RAILS INPUT
simple matter to see if P
exceeds the device's power
DMAX
Power Dissipation
derating curves. To ensure proper operation, it is important
to observe the recommended derating curves shown in
Figures 25 and 26.
With the high-output drive capability of the EL5421 buffer, it
is possible to exceed the +125°C 'absolute-maximum
junction temperature' under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for the application to determine if load
conditions need to be modified for the buffer to remain in the
safe operating area.
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1
0.9
870mW
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
The maximum power dissipation allowed in a package is
determined according to:
T
– T
AMAX
JMAX
(EQ. 1)
--------------------------------------------
P
=
DMAX
JA
where:
0
25
50
75 85 100
125
T
T
= Maximum junction temperature
= Maximum ambient temperature
JMAX
AMBIENT TEMPERATURE (°C)
AMAX
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
= Thermal resistance of the package
JA
P
= Maximum power dissipation in the package
DMAX
FN7198 Rev 2.00
August 2, 2007
Page 10 of 12
EL5421
Power Supply Bypassing and Printed Circuit
Board Layout
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.6
0.5
0.4
0.3
0.2
0.1
0
The EL5421 can provide gain at high frequency. As with any
high-frequency device, good printed circuit board layout is
necessary for optimum performance. Ground plane
construction is highly recommended, lead lengths should be
as short as possible and the power supply pins must be well
bypassed to reduce the risk of oscillation. For normal single
486mW
supply operation, where the V - pin is connected to ground,
S
a 0.1µF ceramic capacitor should be placed from V + to pin
S
to V - pin. A 4.7µF tantalum capacitor should then be
S
connected in parallel, placed in the region of the buffer. One
4.7µF capacitor may be used for multiple devices. This same
capacitor combination should be placed at each supply pin
to ground if split supplies are to be used.
0
25
50
75 85 100
125
AMBIENT TEMPERATURE (°C)
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Unused Buffers
It is recommended that any unused buffer have the input tied
to the ground plane.
Driving Capacitive Loads
The EL5421 can drive a wide range of capacitive loads. As
load capacitance increases, however, the -3dB bandwidth of
the device will decrease and the peaking increase. The
buffers drive 10pF loads in parallel with 10k with just 1.5dB
of peaking, and 100pF with 6.4dB of peaking. If less peaking
is desired in these applications, a small series resistor
(usually between 5 and 50) can be placed in series with
the output. However, this will obviously reduce the gain
slightly. Another method of reducing peaking is to add a
"snubber" circuit at the output. A snubber is a shunt load
consisting of a resistor in series with a capacitor. Values of
150 and 10nF are typical. The advantage of a snubber is
that it does not draw any DC load current or reduce the gain.
FN7198 Rev 2.00
August 2, 2007
Page 11 of 12
EL5421
Mini SO Package Family (MSOP)
MDP0043
0.25 M C A B
A
MINI SO PACKAGE FAMILY
D
(N/2)+1
MILLIMETERS
N
SYMBOL
MSOP8
1.10
0.10
0.86
0.33
0.18
3.00
4.90
3.00
0.65
0.55
0.95
8
MSOP10
1.10
0.10
0.86
0.23
0.18
3.00
4.90
3.00
0.50
0.55
0.95
10
TOLERANCE
Max.
NOTES
A
A1
A2
b
-
±0.05
-
E
E1
PIN #1
I.D.
±0.09
-
+0.07/-0.08
±0.05
-
c
-
D
±0.10
1, 3
1
B
(N/2)
E
±0.15
-
E1
e
±0.10
2, 3
Basic
-
e
H
C
L
±0.15
-
SEATING
PLANE
L1
N
Basic
-
Reference
-
M
C A B
b
0.08
0.10 C
Rev. D 2/07
N LEADS
NOTES:
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
L1
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
A
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
SEE DETAIL "X"
A2
GAUGE
PLANE
0.25
L
DETAIL X
A1
3° ±3°
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FN7198 Rev 2.00
August 2, 2007
Page 12 of 12
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