EL5329IREZ-T7 [RENESAS]
10 BUFFER AMPLIFIER, PDSO28, ROHS COMPLIANT, MO-153, HTSSOP-20;
| 型号： | EL5329IREZ-T7 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 10 BUFFER AMPLIFIER, PDSO28, ROHS COMPLIANT, MO-153, HTSSOP-20 放大器 光电二极管 |
| 文件： | 总13页 (文件大小：1005K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
EL5129, EL5329
Multi-Channel Buffers
FN7430
Rev 1.00
May 13, 2005
The EL5129 and EL5329 integrate multiple gamma buffers
Features
and a single V
buffer for use in large panel LCD
COM
• Multiple gamma buffers
- 6 channels (EL5129)
- 10 channels (EL5329)
displays of 10” and greater. The EL5129 integrates 6 gamma
channels and the EL5329 integrates 10 gamma channels.
Half of the gamma channels in each device are designed to
swing to the upper supply rail, with the other half designed to
swing to the lower rail. The output capability of each channel
is 10mA continuous, with 120mA peak. The gamma buffers
feature a 10MHz 3dB bandwidth specification and a 9V/µs
slew rate.
• Single V
COM
amplifier
• Low supply current
- 3.5mA (EL5129)
- 5.5mA (EL5329)
• For higher speed or higher output power, see the EL5x24
family
The V
amplifier is designed to swing from rail to rail. The
output current capability of the V in the EL5129 and
COM
COM
EL5329 is 30mA continuous, 150mA peak and a slew rate of
10V/µs.
• Pb-free available (RoHS compliant)
Applications
Ordering Information
• TFT-LCD monitors
• LCD televisions
TAPE &
REEL
PART NUMBER
EL5129IRE
PACKAGE
PKG DWG. #
MDP0048
MDP0048
MDP0048
MDP0048
• Industrial flat panel displays
20-Pin HTSSOP
20-Pin HTSSOP
20-Pin HTSSOP
-
7”
13”
-
EL5129IRE-T7
EL5129IRE-T13
EL5129IREZ
(See Note)
20-Pin HTSSOP
(Pb-free)
EL5129IREZ-T7
(See Note)
20-Pin HTSSOP
(Pb-free)
7”
13”
-
MDP0048
MDP0048
MDP0044
MDP0044
MDP0044
MDP0048
MDP0048
MDP0048
MDP0044
MDP0044
MDP0044
EL5129IREZ-T13
(See Note)
20-Pin HTSSOP
(Pb-free)
EL5129IRZ
(See Note)
20-Pin TSSOP
(Pb-free)
EL5129IRZ-T7
(See Note)
20-Pin TSSOP
(Pb-free)
7”
13”
-
EL5129IRZ-T13
(See Note)
20-Pin TSSOP
(Pb-free)
EL5329IREZ
(See Note)
28-Pin HTSSOP
(Pb-free)
EL5329IREZ-T7
(See Note)
28-Pin HTSSOP
(Pb-free)
7”
13”
-
EL5329IREZ-T13
(See Note)
28-Pin HTSSOP
(Pb-free)
EL5329IRZ
(See Note)
28-Pin TSSOP
(Pb-free)
EL5329IRZ-T7
(See Note)
28-Pin TSSOP
(Pb-free)
7”
13”
EL5329IRZ-T13
(See Note)
28-Pin TSSOP
(Pb-free)
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which are
RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN7430 Rev 1.00
May 13, 2005
Page 1 of 13
EL5129, EL5329
Pinouts
EL5129
(20-PIN TSSOP, HTSSOP)
TOP VIEW
EL5329
(28-PIN TSSOP, HTSSOP)
TOP VIEW
VS+
1
2
3
4
5
6
7
8
9
20 VS+
19 IN1
18 IN2
17 IN3
16 IN4
15 IN5
14 IN6
13 NC
VS+
NC
1
2
3
4
5
6
7
8
9
28 VS+
27 NC
OUT1
OUT2
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
26 IN1
25 IN2
24 IN3
23 IN4
22 IN5
21 IN6
20 IN7
19 IN8
18 IN9
17 IN10
16 INCOM
15 VS-
OUT3
OUT4
THERMAL
PAD*
OUT5
OUT5
THERMAL
PAD*
NC
OUTCOM
12 INCOM
11 VS-
VS- 10
OUT8 10
OUT9 11
* THERMAL PAD CONNECTED TO PIN 10 OR 11 (V -)
S
OUT10 12
OUTCOM 13
VS- 14
* THERMAL PAD CONNECTED TO PIN 14 OR 15 (V -)
S
FN7430 Rev 1.00
May 13, 2005
Page 2 of 13
EL5129, EL5329
Absolute Maximum Ratings (T = 25°C)
A
Supply Voltage between V + and V -. . . . . . . . . . . . . . . . . . . .+18V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
S
S
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .V - -0.5V, V + +0.5V
S
S
Maximum Continuous Output Current (V
Maximum Continuous Output Current (V
) . . . . . . . . . . 15mA
OUT0-9
). . . . . . . . . . . 100mA
OUTA
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications V + = +15V, V - = 0, R = 10k, C = 10pF to 0V, T = 25°C unless otherwise specified
S
S
L
L
A
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
20
UNIT
INPUT CHARACTERISTICS (REFERENCE BUFFERS)
V
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Impedance
V
= 0V
CM
2
5
mV
µV/C
nA
OS
TCV
(Note 1)
= 0V
OS
I
V
2
50
B
CM
R
C
10
1.35
M
pF
IN
IN
Input Capacitance
Voltage Gain
A
1V V
14V
OUT
0.992
1.5
1.5
0
1.008
V/V
V
V
CMIR
Input Voltage Range
EL5129, IN1 to IN3
EL5329, IN1 to IN5
EL5129, IN4 to IN6
V +
S
V +
V
S
V +
S
V
-1.5
EL5329, IN6 to IN10
0
V +
S
V
-1.5
INPUT CHARACTERISTICS (V
BUFFER)
COM
V
Input Offset Voltage
V
= 7.5V
1
3
20
mV
µV/C
nA
OS
CM
TCV
Average Offset Voltage Drift
Input Bias Current
Input Impedance
(Note 1)
OS
I
V
V
V
= 7.5V
2
50
B
CM
R
C
10
1.35
M
pF
IN
IN
Input Capacitance
Load Regulation
V
= 7.5V, -60mA < I < 60mA
-20
0
+20
mV
V
REG
COM
L
CMIR
Input Voltage Range V
COM
V +
S
COM
OUTPUT CHARACTERISTICS (REFERENCE BUFFERS)
V
V
High Output Voltage - EL5129 & EL5329
(Output 1)
= 15V, I = 5mA
14.85
14.8
14.9
14.85
13.5
1.5
V
V
OH
IN
O
High Output Voltage - EL5129 (Output 2, 3),
EL5329 (Output 2-5)
High Output Voltage - EL5129 (Output 4-6),
EL5329 (Output 6-10)
V
V
V
= 13.5V, I = 5mA
13.45
V
IN
IN
IN
O
Low Output Voltage - EL5129 (Output 1-3),
EL5329 (Output 1-5)
= 1.5V, I = 5mA
1.55
200
150
V
OL
O
Low Output Voltage - EL5129 (Output 4-5),
EL5329 (Output 6-9)
= 0V, I = 5mA
150
mV
mV
mA
O
Low Output Voltage - EL5129 (Output 6),
EL5329 (Output 10)
100
I
Short Circuit Current
100
120
SC
FN7430 Rev 1.00
May 13, 2005
Page 3 of 13
EL5129, EL5329
Electrical Specifications V + = +15V, V - = 0, R = 10k, C = 10pF to 0V, T = 25°C unless otherwise specified (Continued)
S
S
L
L
A
PARAMETER
DESCRIPTION
CONDITIONS
MIN
14.85
150
TYP
MAX
UNIT
OUTPUT CHARACTERISTICS (V
BUFFER)
COM
V
V
High Level Saturated Output Voltage
Low Level Saturated Output Voltage
Short Circuit Current
V + = 15V, I = -5mA, V = 15V
14.9
0.1
V
V
OH
OL
S
O
I
V + = 15V, I = -5mA, V = 0V
0.15
S
O
I
I
170
mA
SC
POWER SUPPLY PERFORMANCE
PSRR Power Supply Rejection Ratio
Reference buffer V from 5V to 15V
50
55
80
80
dB
dB
S
V
buffer, V from 5V to 15V
S
COM
I
Total Supply Current
EL5129
EL5329
3.5
5.5
4.5
7
mA
mA
S
DYNAMIC PERFORMANCE (BUFFER AMPLIFIERS)
SR Slew Rate (Note 2)
5
7
9
V/µs
ns
t
Settling to +0.1% (A = +1)
V
(A = +1), V = 2V step
500
10
S
V
O
BW
CS
-3dB Bandwidth
R
= 10k, C = 10pF
MHz
dB
L
L
Channel Separation
f = 5MHz
75
EL5129 & EL5329 DYNAMIC PERFORMANCE (V
AMPLIFIERS)
COM
SR
Slew Rate (Note 2)
-4V V
4V, 20% to 80%
10
350
15
V/µs
ns
OUT
t
Settling to +0.1% (A = +1)
V
(A = +1), V = 2V step
V O
S
BW
-3dB Bandwidth
R
= 10k, C = 10pF
MHz
dB
L
L
CS
Channel Separation
f = 5MHz
75
NOTES:
1. Measured over operating temperature range
2. Slew rate is measured on rising and falling edges
FN7430 Rev 1.00
May 13, 2005
Page 4 of 13
EL5129, EL5329
Pin Descriptions
EL5129
EL5329
1, 28
3
PIN NAME
VS+
PIN FUNCTION
1, 20
2
Positive supply voltage
Output gamma channel 1
Output gamma channel 2
Output gamma channel 3
Output gamma channel 4
Output gamma channel 5
Output gamma channel 6
No connect
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
NC
3
4
4
5
5
6
6
7
7
8
8, 13
9
2, 27
13
14, 15
16
21
22
23
24
25
26
9
OUTCOM
VS-
Output, V
COM
Negative supply
Input, V
10, 11
12
14
15
16
17
18
19
INCOM
IN6
COM
Input gamma channel 6
Input gamma channel 5
Input gamma channel 4
Input gamma channel 3
Input gamma channel 2
Input gamma channel 1
Output gamma channel 7
Output gamma channel 8
Output gamma channel 9
Output gamma channel 10
Input gamma channel 10
Input gamma channel 9
Input gamma channel 8
Input gamma channel 7
IN5
IN4
IN3
IN2
IN1
OUT7
OUT8
OUT9
OUT10
IN10
10
11
12
17
18
19
20
IN9
IN8
IN7
FN7430 Rev 1.00
May 13, 2005
Page 5 of 13
EL5129, EL5329
Block Diagram
V +
S
EL5129
COLUMN
DRIVER
V
COM
Typical Performance Curves
5
10
V =±7.5V
V =±7.5V
S
L
S
C =10pF
R =10k
L
3
1
6
2
C =100pF
L
R =10k
L
C =47pF
L
R =1k
L
-1
-3
-5
-2
R =562
C =12pF
L
L
-6
R =150
L
-10
1K
100
1K
10K
100K
1M
10M
100M
10K
100K
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE FOR VARIOUS R
(BUFFER)
FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS C
(BUFFER)
LOAD
LOAD
FN7430 Rev 1.00
May 13, 2005
Page 6 of 13
EL5129, EL5329
Typical Performance Curves (Continued)
V =±7.5V
V =±7.5V
S
S
R =10k
R =10k
L
L
C =8pF
C =8pF
L
L
V
V
V
V
IN
IN
2V/DIV
50mV/DIV
OUT
OUT
1µs/DIV
100ns/DIV
FIGURE 3. LARGE SIGNAL TRANSIENT RESPONSE (BUFFER)
FIGURE 4. SMALL SIGNAL TRANSIENT RESPONSE (BUFFER)
20
V =±7.5V
V =±7.5V
S
S
R =1k
L
C =1.5pF
L
0
-20
-40
-60
-80
100
PSRR+
PSRR-
10
10K
100K
1M
10M
100M
1K
10K
100K
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. INPUT NOISE SPECIAL DENSITY vs FREQUENCY
(BUFFER)
FIGURE 6. PSRR vs FREQUENCY (BUFFER)
60
5
V =±7.5V
V =±7.5V
S
L
S
R =10k
C =10pF
L
OPP
50
40
30
20
10
0
V
=1V
3
1
R =10k
L
R =1k
L
R =562
-1
-3
-5
L
R =150
L
0
500
1K
1.5K
2K
100
1K
10K
100K
1M
10M
100M
C
(pF)
FREQUENCY (Hz)
LOAD
FIGURE 7. OVERSHOOT vs CAPACITANCE LOAD (BUFFER)
FIGURE 8. FREQUENCY RESPONSE FOR VARIOUS R
LOAD
(V
)
COM
FN7430 Rev 1.00
May 13, 2005
Page 7 of 13
EL5129, EL5329
Typical Performance Curves (Continued)
10
10
6
V =±7.5V
V =±7.5V
S
L
S
R =10k
R =1k
L
C =100pF
L
6
2
C =47pF
L
C =47pF
C =100pF
L
L
2
-2
-2
-6
-10
C =12pF
C =12pF
L
L
-6
-10
1K
10K
100K
1M
10M
100M
1G
1K
10K
100K
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 9. FREQUENCY RESPONSE FOR VARIOUS C
FIGURE 10. FREQUENCY RESPONSE FOR VARIOUS C
LOAD
LOAD
(V
)
(V
)
COM
COM
V =±7.5V
V =±7.5V
S
S
R =10k
R =10k
L
L
V
C =8pF
C =8pF
IN
L
L
V
IN
2V/DIV
50mV/DIV
V
V
OUT
OUT
1µs/DIV
100ns/DIV
FIGURE 11. LARGE SIGNAL TRANSIENT RESPONSE (V
)
FIGURE 12. SMALL SIGNAL TRANSIENT RESPONSE (V
)
COM
COM
-20
V =±7.5V
V =±7.5V
S
S
R =1k
L
C =1.5pF
L
0
-20
-40
-60
-80
100
PSRR+
PSRR-
10
1K
10K
100K
1M
10M
10K
100K
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 13. PSRR vs FREQUENCY (V
)
FIGURE 14. INPUT NOISE SPECIAL DENSITY vs FREQUENCY
(V
COM
)
COM
FN7430 Rev 1.00
May 13, 2005
Page 8 of 13
EL5129, EL5329
Typical Performance Curves (Continued)
50
1K
100
10
1
V =±7.5V
S
R =10k
L
OPP
V
=1V
V =±5V
40
30
20
10
0
S
BUFFER
V
COM
0
1K
0
200
400
600
800
10K
100K
FREQUENCY (Hz)
1M
10M
C
(pF)
LOAD
FIGURE 15. OVERSHOOT vs CAPACITANCE LOAD (V
)
FIGURE 16. OUTPUT IMPEDANCE vs FREQUENCY
COM
800
0
V =±7.5V
S
V =±5V
S
R =10k
A =+1
-10
-20
-30
-40
-50
-60
-70
-80
L
V
700
600
500
400
300
200
C =8pF
R =1k
L
L
FREQ=200kHz
BUFFER
V
COM
BUFFER
V
COM
2
3
4
STEP SIZE (+V)
5
6
1
2
3
4
5
6
7
8
9
10
V
(V)
OPP
FIGURE 17. SETTLING TIME vs STEP SIZE
FIGURE 18. TOTAL HARMONIC DISTORTION vs OUTPUT
VOLTAGE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - HTSSOP
EXPOSED DIEPAD SOLDERED TO PCB PER
JESD51-5
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1
3.5
909mW
833mW
HTSSOP28
HTSSOP28
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3.333W
3
=110°C/W
JA
TSSOP28
=120°C/W
=30°C/W
JA
800mW
714mW
2.857W
2.5
2
HTSSOP20
=35°C/W
JA
JA
HTSSOP20
=125°C/W
1.333W
1.111W
1.5
1
JA
TSSOP28
=75°C/W
TSSOP20
JA
=140°C/W
JA
TSSOP20
=90°C/W
JA
0.5
0
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7430 Rev 1.00
May 13, 2005
Page 9 of 13
EL5129, EL5329
need to be modified for the buffer to remain in the safe
operating area.
Description of Operation and Application
Information
The maximum power dissipation allowed in a package is
determined according to:
Product Description
The EL5129 and EL5329 are fabricated using a high voltage
CMOS process. They exhibit rail to rail input and output
capability and have very low power consumption. When driving
a load of 10K and 12pF, the buffers have a
T
- T
AMAX
JMAX
--------------------------------------------
P
=
DMAX
JA
where:
-3dB bandwidth of 10MHz and exhibit 9V/µs slew rate. The
V
amplifier has a -3dB bandwidth of 12MHz and exhibit
COM
• T
• T
= Maximum junction temperature
= Maximum ambient temperature
JMAX
10V/µs slew rate.
AMAX
Input, Output, and Supply Voltage Range
• = Thermal resistance of the package
JA
The EL5129 and EL5329 are specified with a single nominal
supply voltage from 5V to 15V or a split supply with its total
range from 5V to 15V. Correct operation is guaranteed for a
supply range from 4.5V to 16.5V.
• P
DMAX
= Maximum power dissipation in the package
The maximum power dissipation actually produced by an IC is
the total quiescent supply current times the total power supply
voltage, plus the power in the IC due to the loads, or:
The input common-mode voltage range of the EL5129 and
EL5329 within 500mV beyond the supply rails. The output
swings of the buffers and V
within 100mV of the positive and negative supply rails with load
currents of 5mA. Decreasing load currents will extend the
output voltage even closer to each supply rails.
P
= V I + i V + – V
i I
i +
LOAD
amplifier typically extend to
DMAX
S
S
S
OUT
COM
V + – V
I
S
OUT
LA
when sourcing, and:
Output Phase Reversal
P
= V I + i V
i – V - I
i +
LOAD
DMAX
S
S
OUT
S
V
– V - I
The EL5129 and EL5329 are immune to phase reversal as
OUT
S
LA
long as the input voltage is limited from V - -0.5V to V +
S
S
+0.5V. Although the device's output will not change phase, the
input's over-voltage should be avoided. If an input voltage
exceeds supply voltage by more than 0.6V, electrostatic
protection diode placed in the input stage of the device begin to
conduct and over-voltage damage could occur.
when sinking.
where:
• i = 1 to total number of buffers
• V = Total supply voltage of buffer and V
S
COM
Output Drive Capability
• I
= Total quiescent current
SMAX
The EL5129 and EL5329 do not have internal short-circuit
protection circuitry. The buffers will limit the short circuit current
• V
• V
i = Maximum output voltage of the application
OUT
OUT
to ±120mA and the V
amplifier will limit the short circuit
= Maximum output voltage of V
COM
COM
current to ±170mA if the outputs are directly shorted to the
positive or the negative supply. If the output is shorted
indefinitely, the power dissipation could easily increase such
that the part will be destroyed. Maximum reliability is
maintained if the output continuous current never exceeds
• I
i = Load current of buffer
LOAD
• I = Load current of V
LA
COM
If we set the two P
DMAX
solve for the R
equations equal to each other, we can
's to avoid device overheat. The package
LOAD
±15mA for the buffers and ±100mA for the V
amplifier.
COM
power dissipation curves provide a convenient way to see if the
device will overheat. The maximum safe power dissipation can
be found graphically, based on the package type and the
ambient temperature. By using the previous equation, it is a
simple matter to see if P
derating curves.
These limits are set by the design of the internal metal
interconnections.
The Unused Buffers
exceeds the device's power
DMAX
It is recommended that any unused buffers should have their
inputs tied to ground plane.
Power Dissipation
With the high-output drive capability of the EL5129 and
EL5329, it is possible to exceed the 125°C “absolute-maximum
junction temperature” under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for the application to determine if load conditions
FN7430 Rev 1.00
May 13, 2005
Page 10 of 13
EL5129, EL5329
Power Supply Bypassing and Printed Circuit Board
Layout
As with any high frequency device, good printed circuit board
layout is necessary for optimum performance. Ground plane
construction is highly recommended, lead lengths should be as
short as possible, and the power supply pins must be well
bypassed to reduce the risk of oscillation. For normal single
supply operation, where the V - pin is connected to ground,
S
one 0.1µF ceramic capacitor should be placed from the V +
S
pin to ground. A 4.7µF tantalum capacitor should then be
connected from the V + pin to ground. One 4.7µF capacitor
S
may be used for multiple devices. This same capacitor
combination should be placed at each supply pin to ground if
split supplies are to be used.
Important Note: The metal plane used for heat sinking of
the device is electrically connected to the negative supply
potential (V -). If V - is tied to ground, the thermal pad can
S
S
be connected to ground. Otherwise, the thermal pad must
be isolated from any other power planes.
FN7430 Rev 1.00
May 13, 2005
Page 11 of 13
EL5129, EL5329
TSSOP Package Outline Drawing
FN7430 Rev 1.00
May 13, 2005
Page 12 of 13
EL5129, EL5329
HTSSOP Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil
website at <http://www.intersil.com/design/packages/index.asp>
© Copyright Intersil Americas LLC 2005. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7430 Rev 1.00
May 13, 2005
Page 13 of 13
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