CDP1854ACD [RENESAS]
1 CHANNEL(S), 200Kbps, SERIAL COMM CONTROLLER, CDIP40, SIDE BRAZED, DIP-40;
| 型号： | CDP1854ACD |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 1 CHANNEL(S), 200Kbps, SERIAL COMM CONTROLLER, CDIP40, SIDE BRAZED, DIP-40 CD 商用集成电路 |
| 文件： | 总20页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
CDP1854A,
CDP1854AC
Programmable Universal Asynchronous
Receiver/Transmitter (UART)
March 1997
Features
Description
• Two Operating Modes
The CDP1854A and CDP1854AC are silicon-gate CMOS
Universal Asynchronous Receiver/Transmitter (UART) cir-
cuits. They are designed to provide the necessary formatting
and control for interfacing between serial and parallel data.
For example, these UARTs can be used to interface between
a peripheral or terminal with serial I/O ports and the 8-bit
CDP1800-series microprocessor parallel data bus system.
The CDP1854A is capable of full duplex operation, i.e.,
simultaneous conversion of serial input data to parallel out-
put data and parallel input data to serial output data.
- Mode 0 - Functionally Compatible with Industry
Types Such as the TR1602A and CDP6402
- Mode 1 - Interfaces Directly with CDP1800-Series
Microprocessors without Additional Components
• Full or Half Duplex Operation
• Parity, Framing and Overrun Error Detection
• Baud Rate
- DC to 200K Bits/s at V . . . . . . . . . . . . . . . . . . . . 5V
DD
- DC to 400K Bits/s at V . . . . . . . . . . . . . . . . . . . . 10V
DD
The CDP1854A UART can be programmed to operate in
one of two modes by using the mode control input. When the
input is high (MODE = 1), the CDP1854A is directly compati-
ble with the CDP1800-series microprocessor system without
additional interface circuitry. When the mode input is low
(MODE = 0), the device is functionally compatible with indus-
try standard UART’s such as the TR1602A and CDP6402. It
is also pin compatible with these types, except that pin 2 is
used for the mode control input.
• Fully Programmable with Externally Selectable Word
Length (5-8 Bits), Parity Inhibit, Even/Odd Parity, and
1, 1-1/2, or 2 Stop Bits
• False Start Bit Detection
Ordering Information
The CDP1854A and the CDP1854AC are functionally identi-
cal. The CDP1854A has a recommended operating voltage
range of 4V to 10.5V, and the CDP1854AC has a recom-
mended operating voltage range of 4V to 6.5V.
TEMP.
RANGE
o
5V/200K
BAUD
10V/400K
BAUD
PKG.
NO.
PACKAGE
PDIP
o
-40 C to +85 C CDP1854ACE
CDP1854AE
E40.6
E40.6
N44.65
D40.6
D40.6
Burn-In
PLCC
CDP1854ACEX CDP1854AEX
o
o
-40 C to +85 C CDP1854ACQ
CDP1854AQ
CDP1854AD
-
o
o
SBDIP
-40 C to +85 C CDP1854ACD
CDP1854ACDX
Burn-In
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
File Number 1193.2
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
CDP1854A, CDP1854AC
Pinouts
40 LEAD SBDIP, PDIP (MODE 0)
40 LEAD SBDIP, PDIP (MODE 1)
TOP VIEW
TOP VIEW
V
1
2
3
4
5
6
7
8
9
40 T CLOCK
39 EPE
V
1
2
3
4
5
6
7
8
9
40 T CLOCK
DD
DD
)
MODE (V
)
MODE (V
39 CTS
SS
DD
38 WLS 1
37 WLS 2
36 SBS
V
V
38 ES
SS
SS
RRD
R BUS 7
R BUS 6
R BUS 5
R BUS 4
R BUS 3
CS2
R BUS 7
R BUS 6
R BUS 5
R BUS 4
R BUS 3
37 PS1
36 NC
35 PI
35 CS3
34 CRL
34 RD/WR
33 T BUS 7
32 T BUS 6
31 T BUS 5
30 T BUS 4
29 T BUS 3
28 T BUS 2
27 T BUS 1
26 T BUS 0
25 SD0
33 T BUS 7
32 T BUS 6
31 T BUS 5
30 T BUS 4
29 T BUS 3
28 T BUS 2
27 T BUS 1
26 T BUS 0
25 SD0
R BUS 2 10
R BUS 1 11
R BUS 0 12
PE 13
R BUS 2 10
R BUS 1 11
R BUS 0 12
INT 13
FE 14
FE 14
OE 15
PE/OE 15
RSEL 16
R CLOCK 17
TPB 18
SFD 16
R CLOCK 17
DAR 18
DA 19
24 TSRE
23 THRL
22 THRE
21 MR
24 RTS
23 CS1
DA 19
22 THRE
21 CLEAR
SDI 20
SDI 20
NC = NO CONNECT
44 LEAD PLCC (Q SUFFIX)
TOP VIEW
6
5
4
3
2
1 44 43 42 41 40
R BUS 6
R BUS 5
R BUS 4
R BUS 3
R BUS 2
NC
7
39
38
37
36
35
34
33
32
31
30
29
PI (CS3)
8
CRL(RD/WR)
T BUS 7
T BUS 6
T BUS 5
NC
9
10
11
12
13
14
15
16
17
R BUS 1
R BUS 0
PE(INT)
FE
T BUS 4
T BUS 3
T BUS 2
T BUS 1
T BUS 0
OE(PE/OE)
18 19 20 21 22 23 24 25 26 27 28
NOTE:
MODE 0(MODE 1)
2
CDP1854A, CDP1854AC
Block Diagram
Mode Input High (Mode = 1)
CDP1802
INTERFACE
1, 2 = V
3 = V
DD
SS
TRANSMITTER SECTION
RECEIVER SECTION
21 = CLEAR
36 = NC
40 24 39
34
18
16
38 37 17
SDO
25
20
SDI
TRANSMITTER
TIMING &
CONTROL
RECEIVER
TIMING &
CONTROL
SHIFT
REGISTER
RECEIVER
HOLDING
REGISTER
PARITY
GEN
TRANSMITTER
SHIFT
REGISTER
MUX
TRANSMITTER
HOLDING
REGISTER
CONTROL
REG
SELECT
LOGIC
STATUS
REGISTER
THREE-STATE
DRIVERS
INT
22 14 15 19
23
4
35
13
TRANSMITTER BUS
(26 - 33)
RECEIVER BUS
(5-12)
(SEE NOTE 1)
(SEE NOTE 1)
(SEE NOTE 1)
NOTE: 1. User Interconnect
FIGURE 1. MODE 1 BLOCK DIAGRAM (CDP1800-SERIES MICROPROCESSOR COMPATIBLE)
3
CDP1854A, CDP1854AC
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply-Voltage Range, (V
DD
)
Thermal Resistance (Typical, Note 1)
SBDIP Package. . . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . .
PLCC Package . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
θ
( C/W)
θ
( C/W)
JA
JC
(Voltages Referenced to V Terminal)
55
50
46
15
N/A
N/A
SS
CDP1854A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +11V
CDP1854AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . .-0.5 to V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Device Dissipation Per Output Transistor
+ 0.5V
DD
o
Plastic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 C
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
o
o
o
T
= Full Package-Temperature Range . . . . . . . . . . . . . . 100mW
Maximum Storage Temperature Range (T
STG
Maximum Lead Temperature (Soldering 10s):
) . . .-65 C to +150 C
A
Operating-Temperature Range (T )
Package Type D . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C
Package Type E and Q. . . . . . . . . . . . . . . . . . . . . -40 C to +85 C
A
o
o
o
At Distance 1/16 ±1/32 inch (1.59 ±0.79mm) . . . . . . . . . . +265 C
NOTE: Printed circuit board mount: 57mm x 57mm minimum area x
1.6mm thick G10 epoxy glass, or equivalent.
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
o
Static Electrical Specifications at T = -40 C to +85 C, Unless Otherwise Noted
A
CONDITIONS
LIMITS
CDP1854A
CDP1854AC
V
V
V
DD
(NOTE 1)
(NOTE 1)
O
IN
PARAMETER
Quiescent Device
(V)
(V)
(V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
µA
I
-
0, 5
5
-
-
0.01
50
-
-
0.02
200
DD
Current
-
0, 10
0, 5
10
5
1
2
4
200
-
2
-
-
-
-
µA
Output Low Drive
(Sink) Current
(Except pins 24 and
25)
I
0.4
0.5
1
2
-
-
1
-
mA
OL
0, 10
10
mA
Output High Drive
(Source) Current
I
4.6
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
-
5
10
5
-0.55
-1.1
-
-
-0.55
-1.1
-
mA
mA
mA
mA
V
OH
9.5
-1.3
1.6
3.2
-
-2.6
-
-
3.5
-
-
Output Low Drive
(Sink) Current
(Pins 24 and 25)
I
0.4
3.5
7
0
0
5
10
-
-
1.6
-
OL
0.5
10
5
-
-
-
Output Voltage
Low-Level (Note 2)
V
-
0.1
0.1
-
-
0
-
0.1
OL
-
10
5
-
-
-
V
Output Voltage
High-Level (Note 2)
V
-
4.9
9.9
-
4.9
5
-
-
-
V
OH
-
10
5
-
-
V
Input Low Voltage
Input High Voltage
Input Current
V
0.5, 4.5
0.5, 9.5
0.5, 4.5
0.5, 9.5
-
1.5
3
-
-
1.5
-
V
IL
IH
IN
-
10
5
-
-
-
-
V
V
-
3.5
7
-
-
3.5
-
-
V
-
10
5
-
-
-
-
-
-
-
V
I
0, 5
0, 10
-
-
±1
±2
-
±1
-
µA
µA
-
10
-
-
-
4
CDP1854A, CDP1854AC
o
o
Static Electrical Specifications at T = -40 C to +85 C, Unless Otherwise Noted (Continued)
A
CONDITIONS
LIMITS
CDP1854A
CDP1854AC
V
V
V
DD
(NOTE 1)
(NOTE 1)
O
IN
PARAMETER
Three-State Output
(V)
(V)
0, 5
0, 10
0, 5
0, 10
-
(V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
µA
I
0, 5
5
-
-
-
-
-
-
-
-
±1
±10
-
-
-
-
-
-
-
-
-
±1
-
OUT
Leakage Current
0, 10
10
5
µA
Operating Current
(Note 3)
I
-
-
-
-
1.5
6
1.5
-
-
mA
mA
pF
DD1
10
-
-
-
Input Capacitance
Output Capacitance
NOTES:
C
5
7.5
15
5
7.5
15
IN
C
-
-
10
10
pF
OUT
o
1. Typical values are for T = 25 C.
A
2. I = I
OL
= 1µA.
OH
3. Operating current is measured at 200kHz or V
open outputs.
= 5V and 400kHz for V = 10V in a CDP1800-series microprocessor system, with
DD
DD
Operating Conditions At T = Full Package-Temperature Range. For maximum reliability, operating conditions should be selected
A
so that operation is always within the following ranges:
CONDITIONS
LIMITS
CDP1854AC
CDP1854A
V
DD
PARAMETER
DC Operating Voltage Range
(V)
MIN
MAX
MIN
MAX
UNITS
V
-
4
10.5
4
6.5
Input Voltage Range
-
V
V
V
V
DD
V
SS
DD
SS
Baud Rate (Receive or Transmit)
5
-
200
400
-
200
-
K bits/s
K bits/s
10
-
-
5
CDP1854A, CDP1854AC
SERIAL DATA IN (SDl):
Functional Definitions for CDP1854A
Terminals Mode 1 CDP1800-Series
Microprocessor Compatible
Serial data received on this input line enters the Receiver
Shift Register at a point determined by the character length.
A high-level input voltage must be present when data is not
being received.
SIGNAL: FUNCTION
CLEAR (CLEAR):
V
:
DD
A low-level voltage at this input resets the Interrupt Flip-
Flop, Receiver Holding Register, Control Register, and
Status Register, and sets SERIAL DATA OUT (SDO) high.
Positive supply voltage.
MODE SELECT (MODE):
A high-level voltage at this input selects CDP1800-series
microprocessor Mode operation.
TRANSMlTTER HOLDING REGISTER EMPTY (THRE):
A low-level voltage at this output indicates that the
Transmitter Holding Register has transferred its contents to
the Transmitter Shift Register and may be reloaded with a
new character.
V
:
SS
Ground
CHIP SELECT 2 (CS2):
CHIP SELECT 1 (CS1):
A low-level voltage at this input together with CS1 and CS3
selects the CDP1854A UART.
A high-level voltage at this input together with CS2 and CS3
selects the UART.
RECEIVER BUS (R BUS 7 - R BUS 0):
REQUEST TO SEND (RTS):
Receiver parallel data outputs (may be externally connected
to corresponding transmitter bus terminals).
This output signal tells the peripheraI to get ready to receive
data. CLEAR TO SEND (CTS) is the response from the
peripheral. RTS is set to a low-level voltage when data is
latched in the Transmitter Holding Register or TR is set high,
and is reset high when both the Transmitter Holding Register
and Transmitter Shift Register are empty and TR is low.
INTERRUPT (INT):
A low-level voltage at this output indicates the presence of
one or more of the interrupt conditions listed in Table 1.
FRAMlNG ERROR (FE):
SERAL DATA OUTPUT (SDO):
A high-level voltage at this output indicates that the received
character has no valid stop bit, i.e., the bit following the parity
bit (if programmed) is not a high-level voltage. This output is
updated each time a character is transferred to the Receiver
Holding Register.
The contents of the Transmitter Shift Register [start bit, data
bits, parity bit, and stop bit(s)] are serially shifted out on this
output. When no character is being transmitted, a high level
is maintained. Start of transmission is defined as the
transition of the start bit from a high-level to a low-level
output voltage.
PARITY ERROR or OVERRUN ERROR (PE/OE):
A high-level voltage at this output indicates that either the PE
or OE bit in the Status Register has been set (see Status
Register Bit Assignment, Table 2).
TRANSMlTTER BUS (T BUS 0 - T BUS 7):
Transmitter parallel data input. These may be externally
connected to corresponding Receiver bus terminals.
REGISTER SELECT (RSEL):
RD/WR:
This input is used to choose either the Control/Status
Registers (high input) or the transmitter/receiver data
registers (low input) according to the truth table in Table 3.
A low-level voltage at this input gates data from the transmitter
bus to the Transmitter Holding Register or the Control Regis-
ter as chosen by register select. A high-level voltage gates
data from the Receiver Holding Register or the Status Regis-
ter, as chosen by register select, to the receiver bus.
RECEIVER CLOCK (RCLOCK):
Clock input with a frequency 16 times the desired receiver
shift rate.
CHIP SELECT 3 (CS3):
TPB:
With high-level voltage at this input together with CS1 and
CS2 selects the UART.
A positive input pulse used as a data load or reset strobe.
PERIPHERAL STATUS INTERRUPT (PSI):
DATA AVAILABLE (DA):
A high-to-low transition on this input line sets a bit in the
Status Register and causes an INTERRUPT (INT = low).
A low-level voltage at this output indicates that an entire
character has been received and transferred to the Receiver
Holding Register.
EXTERNAL STATUS (ES):
A low-level voltage at this input sets a bit in the Status
Register.
6
CDP1854A, CDP1854AC
CLEAR TO SEND (CTS):
serial data out is inhibited.
When this input from peripheral is high, transfer of a TRANSMITTER CLOCK (TCLOCK):
character to the Transmitter Shift Register and shifting of
TABLE 1. INTERRUPT SET AND RESET CONDITIONS
(NOTE 1)
SET (INT = LOW)
RESET (INT = HIGH)
CONDITION
Read of Data
CAUSE
TIME
DA (Receipt of Data)
TPB Leading Edge
TPB Leading Edge
THRE (Note 2)
(Ability to Reload)
Read of Status or Write of Character
Read of Status or Write of Character
Read of Status
THRE • TSRE
(Transmitter Done)
TPB Leading Edge
TPB Trailing Edge
TPB Leading Edge
PSI
(Negative Edge)
CTS
Read of Status
(Positive Edge when THRE • TSRE)
NOTES:
1. Interrupts will occur only after the IE bit in the Control Register (see Table 4) has been set.
2. THRE will cause an interrupt only after the TR bit in the Control Register (see Table 4) has been set.
TABLE 2. STATUS REGISTER BIT ASSIGNMENT
BIT
7
6
TSRE
-
5
PSI
-
4
ES
-
3
2
1
0
SIGNAL
THRE
22†
FE
14
PE
15
OE
15
DA
19†
ALSO AVAILABLE AT TERMINAL
† Polarity reversed at output terminal.
BIT SIGNAL: FUNCTION
0
1
2
DATA AVAILABLE (DA): When set high, this bit indicates that an entire character has been received and transferred to the Receiver
Holding Register. This signal is also available at Term. 19 but with its polarity reversed.
OVERRUN ERROR (OE): When set high, this bit indicates that the Data Available bit was not reset before the next character was
transferred to the Receiver Holding Register. This signal OR’ed with PE is output at Term. 15.
PARITY ERROR (PE): When set high, this bit indicates that the received parity bit does not compare to that programmed by the EVEN
PARITY ENABLE (EPE) control. This bit is updated each time a character is transferred to the Receiver Holding Register. This signal
OR’ed with OE is output at Term. 15.
3
FRAMlNG ERROR (FE): When set high, this bit indicates that the received character has no valid stop bit, i.e., the bit following the
parity bit (if programmed) is not a high-level voltage. This bit is updated each time a character is transferred to the Receiver Holding
Register. This signal is also available at Term. 14.
4
5
EXTERNAL STATUS (ES): This bit is set high by a low-level input at Term. 38 (ES).
PERIPHERAL STATUS INTERRUPT (PSI): This bit is set high by a high-to-low voltage transition of Term. 37 (PSI). The INTERRUPT
output (Term. 13) is also asserted (lNT = Iow) when this bit is set.
6
7
TRANSMlTTER SHIFT REGISTER EMPTY (TSRE): When set high, this bit indicates that the Transmitter Shift Register has complet-
ed serial transmission of a full character including stop bit(s). It remains set until the start of transmission of the next character.
TRANSMlTTER HOLDING REGISTER EMPTY (THRE): When set high, this bit indicates that the Transmitter Holding Register has
transferred its contents to the Transmitter Shift Register and may be reloaded with a new character. Setting this bit also sets the THRE
output (Term. 22) low and causes an INTERRUPT (lNT = low), if TR is high.
7
CDP1854A, CDP1854AC
will be loaded from the Transmitter Holding Register and
Description of Mode 1 Operation
CDP1800-Series Microprocessor
data transmission will begin. If CTS is always low, the Trans-
mitter Shift Register will be loaded on the first high-to-low
edge of the clock which occurs at least 1/2 clock period after
the trailing edge of TPB and transmission of a start bit will
occur 1/2 clock period later (see Figure 3). Parity (if pro-
grammed) and stop bit(s) will be transmitted following the
last data bit. If the word length selected is less than 8 bits,
the most significant unused bits in the transmitter shift regis-
ter will not be transmitted.
Compatible (Mode Input = V
)
DD
Initialization and Controls
In the CDP1800-series microprocessor compatible mode,
the CDP1854A is configured to receive commands and send
status via the microprocessor data bus. The register
connected to the transmitter bus or the receiver bus is
determined by the RD/WR and RSEL inputs as follows:
One transmitter clock period after the Transmitter Shift Reg-
ister is loaded from the Transmitter Holding Register, the
THRE signal will go low and an interrupt will occur (INT goes
low). The next character to be transmitted can then be
loaded into the Transmitter Holding Register for transmission
with its start bit immediately following the last stop bit of the
previous character. This cycle can be repeated until the last
character is transmitted, at which time a final THRE • TSRE
interrupt will occur. This interrupt signals the microprocessor
that TR can be turned off. This is done by reloading the orig-
inal control byte in the Control Register with the TR bit 0,
thus terminating the REQUEST TO SEND (RTS) signal.
TABLE 3. REGISTER SELECTION SUMMARY
RSEL
RD/WR
FUNCTION
Low
Low
Load Transmitter Holding Register from
Transmitter Bus
Low
High
High
High
Low
High
Read Receiver Holding Register from
Receiver Bus
Load Control Register from Transmitter
Bus
Read Status Register from Receiver Bus
In this mode the CDP1854A is compatible with
a
SERIAL DATA OUT (SDO) can be held low by setting the
BREAK bit in the Control Register (see Table 4). SDO is held
low until the BREAK bit is reset.
bidirectional bus system. The receiver and transmitter buses
are connected to the bus. CDP1800-series microprocessor
I/O control output signals can be connected directly to the
CDP1854A inputs as shown in Figure 2. The CLEAR input is
pulsed, resetting the Control, Status, and Receiver Holding
Registers and setting SERIAL DATA OUT (SDO) high. The
Control Register is loaded from the Transmitter Bus in order
to determine the operating configuration for the UART. Data
is transferred from the Transmitter Bus inputs to the Control
Register during TPB when the UART is selected (CS1• CS2
• CS3 = 1) and the Control Register is designated (RSEL =
H, RD/WR = L). The CDP1854A also has a Status Register
which can be read onto the Receiver Bus (R BUS 0 - R BUS
7) in order to determine the status of the UART. Some of
these status bits are also available at separate terminals as
indicated in Table 2.
T CLOCK R CLOCK
N0
N1
RSEL
CS1
V
V
SS
RTS
CTS
CS2
N2
CS3
DD
MRD
TPB
RD/WR
TPB
CPU
ES
INT
INT
PSI
UART
CDP1854A
THRE
EF
X
EF
EF
X
X
DA
FE
Transmitter Operation
EF
X
SDI
PE/OE
T BUS
Before beginning to transmit, the TRANSMlT REQUEST
(TR) bit in the Control Register (see bit assignment, Table 4)
is set. Loading the Control Register with TR = 1 (bit 7 = high)
inhibits changing the other control bits. Therefore two loads
are required: one to format the UART, the second to set TR.
When TR has been set, a TRANSMlTTER HOLDING REG-
ISTER EMPTY (THRE) interrupt will occur, signalling the
microprocessor that the Transmitter Holding Register is
empty and may be loaded. Setting TR also causes assertion
of a low-level on the REQUEST TO SEND (RTS) output to
the peripheral. It is not necessary to set TR for proper opera-
tion for the UART. If desired, it can be used to enable THRE
interrupts and to generate the RTS signal. The Transmitter
Holding Register is loaded from the bus by TPB during exe-
cution of an output instruction. The CDP1854A is selected
by CS1 • CS2 • CS3 = 1, and the Holding Register is
selected by RSEL = L and RD/WR = L. When the CLEAR
TO SEND (CTS) input, which can be connected to a periph-
eral device output, goes low, the Transmitter Shift Register
SDO
(8)
BUS
R BUS
CLEAR
CLEAR
MODE
V
DD
FIGURE 2. RECOMMENDED CDP1800-SERIES CONNECTION,
MODE 1 (NON-INTERRUPT DRIVEN SYSTEM)
Receiver Operation
The receive operation begins when a start bit is detected at
the SERlAL DATA IN (SDl) input. After detection of the first
high-to-low transition on the SDl line, a valid start bit is
verified by checking for a low-level input 7-1/2 receiver clock
periods later. When a valid start bit has been verified, the fol-
lowing data bits, parity bit (if programmed) and stop bit(s) are
shifted into the Receiver Shift Register by clock pulse 7-1/2
8
CDP1854A, CDP1854AC
in each bit time. The parity bit (if programmed) is checked the microprocessor and resets DATA AVAILABLE (DA) in the
and receipt of a valid stop bit is verified. On count 7-1/2 of UART. The preceding sequence is repeated for each serial
the first stop bit, the received data is loaded into the character which is received from the peripheral.
Receiver Holding Register. If the word length is less than 8
bits, zeros (low output level) are loaded into the unused most
Peripheral Interface
significant bits. If DATA AVAILABLE (DA) has not been reset
by the time the Receiver Holding Register is loaded, the
OVERRUN ERROR (OE) status bit is set. One half clock
period later, the PARITY ERROR (PE) and FRAMlNG
ERROR (FE) status bits become valid for the character in
the Receiver Holding Register. At this time, the Data
Available status bit is also set and the DATA AVAILABLE
(DA) and INTERRUPT (INT) outputs go low, signalling the
microprocessor that a received character is ready. The
microprocessor responds by executing an input instruction.
The UART’s three-state bus drivers are enabled when the
UART is selected (CS1 • CS2 • CS3 = 1) and RD/WR =
high. Status can be read when RSEL = high. Data is read
when RSEL = Iow. When reading data, TPB latches data in
In addition to serial data in and out, four signals are provided
for communication with a peripheral. The REQUEST TO
SEND (RTS) output signal alerts the peripheral to get ready
to receive data. The CLEAR TO SEND (CTS) input signal is
the response, signalling that the peripheral is ready. The
EXTERNAL STATUS (ES) input latches a peripheral status
level, and the PERIPHERAL STATUS INTERRUPT (PSI)
input senses a status edge (high-to-low) and also generates
an interrupt. For example, the modem DATA CARRIER
DETECT line could be connected to the PSI input on the
UART in order to signal the microprocessor that
transmission failed because of loss of the carrier on the
communications line. The PSI and ES bits are stored in the
Status Register (see Table 2).
TABLE 4. CONTROL REGISTER BIT ASSIGNMENT
BIT
7
6
5
4
3
2
1
0
SIGNAL
TR
BREAK
IE
WLS2
WLS1
SBS
EPE
PI
BIT SIGNAL: FUNCTION
0
PARITY INHIBIT (PI): When set high parity generation and verification are inhibited and the PE Status bit is held low. If parity is
inhibited the stop bit(s) will immediately follow the last data bit on transmission, and EPE is ignored.
1
EVEN PARITY ENABLE (EPE): When set high, even parity is generated by the transmitter and checked by the receiver. When low,
odd parity is selected.
2
3
4
5
STOP BIT SELECT (SBS): See table below.
WORD LENGTH SELECT 1 (WLS1): See table below.
WORD LENGTH SELECT 2 (WLS2): See table below.
INTERRUPT ENABLE (lE): When set high THRE, DA, THRE • TSRE, CTS, and PSI interrupts are enabled (see Interrupt Conditions,
Table 1).
6
TRANSMlT BREAK (BREAK): Holds SDO low when set. Once the break bit in the control register has been set high, SDO will stay
low until the break bit is reset low and one of the following occurs: CLEAR goes low; CTS goes high; or a word is transmitted. (The
transmitted word will not be valid since there can be no start bit if SDO is already low. SDO can be set high without intermediate
transitions by transmitting a word consisting of all zeros).
7
TRANSMlT REQUEST (TR): When set high, RTS is set low and data transfer through the transmitter is initiated by the initial THRE
interrupt. (When loading the Control Register from the bus, this (TR) bit inhibits changing of other control flip-flops).
BIT 4
WLS2
BIT 3
WLS1
BIT 2
SBS
FUNCTION
5 data bits, 1 stop bit
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
5 data bits, 1.5 stop bits
6 data bits, 1 stop bit
6 data bits, 2 stop bits
7 data bits, 1 stop bit
7 data bits, 2 stop bits
8 data bits, 1 stop bit
8 data bits, 2 stop bits
9
CDP1854A, CDP1854AC
o
o
Dynamic Electrical Specifications T = -40 C to +85 C, V ±5%, t , t = 20ns, V = 0.7 V , V = 0.3 V , C = 100pF,
A
DD
R
F
IH
DD IL
DD
L
(See Figure 3)
LIMITS
CDP1854A
CDP1854AC
V
(NOTE 1)
(NOTE 2)
(NOTE 1)
(NOTE 2)
DD
PARAMETER
TRANSMITTER TIMING - MODE 1
Minimum Clock Period
(V)
TYP
MAX
TYP
MAX
UNITS
t
t
t
5
250
125
310
155
250
-
310
-
ns
ns
CC
10
Minimum Pulse Width
Clock Low Level
t
5
10
5
100
75
125
100
125
100
150
75
100
125
ns
ns
ns
ns
ns
ns
CL
-
100
-
-
125
-
Clock High Level
TPB
100
75
CH
10
5
t
100
50
100
-
150
-
TT
TC
CD
10
Minimum Setup Time
TPB to Clock
5
175
90
225
150
175
-
225
-
ns
ns
10
Propagation Delay Time
Clock to Data Start Bit
t
5
10
5
300
150
200
100
200
100
450
225
300
150
300
150
300
450
ns
ns
ns
ns
ns
ns
-
200
-
-
300
-
TPB to THRE
Clock to THRE
t
TTH
CTH
10
5
t
200
-
300
-
10
NOTES:
1. Typical values for T = 25 C and nominal voltages.
o
A
2. Maximum limits of minimum characteristics are the values above which all devices function.
TRANSMITTER HOLDING
REGISTER LOADED
(NOTE 1)
TRANSMITTER SHIFT
REGISTER LOADED
(NOTE 2)
t
CC
t
t
CL
CH
T CLOCK
1
2
3
4
5
6
7
14
15
16
1
2
3
4
t
t
CD
TC
WRITE (TPB)
(NOTE 3)
t
t
TT
CTH
t
TTH
THRE
SDO
t
CD
1ST DATA BIT
NOTES:
1. The holding register is loaded on the trailing edge of TPB.
2. The Transmitter Shift Register is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock period + t after
TC
the trailing edge of TPB and transmission of a start bit occurs 1/2 clock period + t
3. Write is the overlap of TPB, CS1, and CS3 = 1 and CS3, RD/WR = 0.
later.
CD
FIGURE 3. TRANSMITTER TIMING DIAGRAM - MODE 1
10
CDP1854A, CDP1854AC
o
o
Dynamic Electrical Specifications T = -40 C to +85 C, V ±5%, t , t = 20ns, V = 0.7 V , V = 0.3 V , C = 100pF,
A
DD
R
F
IH
DD IL
DD
L
(See Figure 4)
LIMITS
CDP1854A
CDP1854AC
V
(NOTE 1)
(NOTE 2)
(NOTE 1)
(NOTE 2)
DD
PARAMETER
RECEIVER TIMING - MODE 1
Minimum Clock Period
(V)
TYP
MAX
TYP
MAX
UNITS
t
t
t
5
250
125
310
155
250
-
310
-
ns
ns
CC
10
Minimum Pulse Width
Clock Low Level
t
5
10
5
100
75
125
100
125
100
150
75
100
125
ns
ns
ns
ns
ns
ns
CL
-
100
-
-
125
-
Clock High Level
TPB
100
75
CH
10
5
t
100
50
100
-
150
-
TT
10
Minimum Setup Time
Data Start Bit to Clock
5
100
50
150
75
100
-
150
-
ns
ns
DC
10
Propagation Delay Time
TPB to DATA AVAILABLE
t
5
10
5
220
110
220
110
210
105
240
120
200
100
325
175
325
175
300
150
375
175
300
150
220
325
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TDA
CDA
COE
-
220
-
-
325
-
Clock to DATA AVAILABLE
Clock to Overrun Error
Clock to Parity Error
t
10
5
t
210
-
300
-
10
5
t
240
-
375
-
CPE
10
5
Clock to Framing Error
t
200
-
300
-
CFE
10
NOTES:
1. Typical values for T = 25 C and nominal voltages.
o
A
2. Maximum limits of minimum characteristics are the values above which all devices function.
11
CDP1854A, CDP1854AC
CLOCK 7 1/2
CLOCK 7 1/2 LOAD
HOLDING REGISTER
t
CC
SAMPLE
t
t
CL
CH
R CLOCK
1
2
3
4
5
6
7
16
1
2
3
4
5
6
7
8
9
t
DC
(NOTE 1)
START BIT
TDA
PARITY
STOP BIT 1
SDI
t
CDA
t
DA
READ
(NOTE 2)
t
TT
TPB
t
COE
OE
(NOTE 3)
t
CPE
PE
(NOTE 3)
t
CFE
FE
NOTES:
1. If a start bit occurs at a time less than t
before a high-to-low transition of the clock, the start bit may not be recognized until the next
DC
high-to-low transition of the clock. The start bit may be completely asynchronous with the clock.
2. Read is the overlap of CS1, CS3, RD/WR = 1 and CS2 = 0. If a pending DA has not been cleared by a read of the Receiver Holding
Register by the time a new word is loaded into the Receiver Holding Register, the OE signal will come true.
3. OE and PE share terminal 15 and are also available as two separate bits in the status register.
FIGURE 4. MODE 1 RECEIVER TIMING DIAGRAM
t
TT
TPB
(NOTE 1)
t
WRS
t
RSW
RSEL
t
t
WD
DW
T BUS 0-
T BUS 7
CS3, CS1
(NOTE 1)
RD/WR, CS2
(NOTE 1)
NOTE:
1. Write is the overlap of TPB, CS1, CS3 = 1 and CS2, RD/WR = 0.
FIGURE 5. MODE 1 CPU INTERFACE (WRITE) TIMING DIAGRAM
12
CDP1854A, CDP1854AC
o
o
Dynamic Electrical Specifications T = -40 C to +85 C, V ±5%, t , t = 20ns, V = 0.7 V , V = 0.3 V , C = 100pF,
A
DD
R
F
IH
DD IL
DD
L
(See Figure 5)
LIMITS
CDP1854A
CDP1854AC
V
(NOTE 1)
(NOTE 2)
(NOTE 1)
(NOTE 2)
DD
PARAMETER
(V)
TYP
MAX
TYP
MAX
UNITS
CPU INTERFACE - WRITE TIMING - MODE 1
Minimum Pulse Width
TPB
t
5
100
50
150
75
100
-
150
-
ns
ns
TT
10
Minimum Setup Time
RSEL to Write
t
t
5
10
5
50
25
75
40
0
50
-
75
-
ns
ns
ns
ns
RSW
Data to Write
t
-30
-15
-30
-
0
-
DW
10
0
Minimum Hold Time
RSEL after Write
5
10
5
50
25
75
40
75
40
50
-
75
ns
ns
ns
ns
WRS
-
125
-
Data after Write
t
125
60
75
-
WD
10
NOTES:
1. Typical values for T = 25 C and nominal voltages.
o
2. Maximum limits of minimum characteristics are the values above which all devices function.
A
o
o
Dynamic Electrical Specifications T = -40 C to +85 C, V ±5%, t , t = 20ns, V = 0.7 V , V = 0.3 V , C = 100pF,
A
DD
R
F
IH
DD IL
DD
L
(See Figure 6)
LIMITS
CDP1854A
CDP1854AC
(NOTE 1) (NOTE 2)
V
(NOTE 1) (NOTE 2)
DD
PARAMETER
(V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
CPU INTERFACE - READ TIMING - MODE 1
Minimum Pulse Width
TPB
t
5
-
-
100
50
150
75
-
-
100
-
150
-
ns
ns
TT
10
Minimum Setup Time
RSEL to TPB
t
t
5
-
-
50
25
75
40
-
-
50
-
75
-
ns
ns
RST
TRS
10
Minimum Hold Time
RSEL after TPB
5
10
5
-
-
-
-
-
-
-
-
50
25
75
-
-
-
-
-
-
-
-
50
75
ns
ns
ns
ns
ns
40
-
200
-
-
300
-
Read to Data Access Time
Read to Data Valid Time
RESEL to Data Valid Time
t
t
200
100
200
100
150
75
300
150
300
150
225
125
RDDA
10
5
t
200
-
300
-
RDV
10
5
150
-
225
-
ns
ns
RSDV
10
Hold Time
Data after Read
t
5
50
25
150
75
-
-
50
-
150
-
-
-
ns
ns
RDH
10
NOTES:
o
1. Typical values for T = 25 C and nominal voltages.
A
2. Maximum limits of minimum characteristics are the values above which all devices function.
13
CDP1854A, CDP1854AC
t
TT
TPB
t
TRS
t
RST
RSEL
t
RSDV
R BUS 0-
R BUS 7
t
t
RDDA
RDH
t
RDV
RD/WR, CS1, CS3
(NOTE 1)
CS2
NOTE:
1. Read is the overlap of CS1, CS3, RD/WR = 1 and CS2 = 0.
FIGURE 6. MODE 1 CPU INTERFACE (READ) TIMING DIAGRAM
Mode Input Low (Mode = 0)
1 = V
DD
2, 3 = V
T CLOCK
40
R CLOCK
17
SS
21 = MR
SDO
RECEIVER
SHIFT
REGISTER
TRANSMITTER
TIMING AND
CONTROL
RECEIVER
TIMING AND
CONTROL
20
SDI
RECEIVER
HOLDING
REGISTER
PARITY
GEN
TRANSMITTER
SHIFT
REGISTER
25
CONTROL
REGISTER
STATUS
REGISTER
TRANSMITTER
HOLDING REGISTER
THREE-STATE
DRIVERS
34
16
18
4
26 27 28 29 30 31 32 33
35 36 39 38 37
22 24 13 14 15 19
5
6
7
8
9 10 11 12
23
THRL
CRL
SFD
DAR
RRD
TRANSMITTER BUS
RECEIVER BUS
TRANSMITTER SECTION
RECEIVER SECTION
FIGURE 7. MODE 0 BLOCK DIAGRAM (INDUSTRY STANDARD COMPATIBLE)
14
CDP1854A, CDP1854AC
DATA AVAILABLE (DA):
Functional Definitions for CDP1854A
Terminals Standard Mode 0
A high-level voltage at this output indicates that an entire
character has been received and transferred to the Receiver
Holding Register.
SIGNAL: FUNCTION
V
:
SERIAL DATA IN (SDl):
DD
Positive supply voltage.
Serial data received at this input enters the receiver shift
register at a point determined by the character length. A
high-level voltage must be present when data is not being
received.
MODE SELECT (MODE):
A low-level voltage at this input selects Standard Mode 0
Operation.
MASTER RESET (MR):
V
:
SS
A high-level voltage at this input resets the Receiver Holding
Register, Control Register, and Status Register, and sets the
serial data output high.
Ground.
RECEIVER REGISTER DISCONNECT (RRD):
TRANSMlTTER HOLDING REGISTER EMPTY (THRE):
A high-level voltage applied to this input disconnects the
Receiver Holding Register from the Receiver Bus.
A high-level voltage at this output indicates that the Trans-
mitter Holding Register has transferred its contents to the
Transmitter Shift Register and may be reloaded with a new
character.
RECEIVER BUS (R BUS 7 - R BUS 0):
Receiver parallel data outputs.
PARITY ERROR (PE):
TRANSMlTTER HOLDING REGISTER LOAD (THRL):
A high-level voltage at this output indicates that the received A low-level voltage applied to this input enters the character
parity does not compare to that programmed by the EVEN on the bus into the Transmitter Holding Register. Data is
PARITY ENABLE (EPE) control. This output is updated each latched on the trailing edge of this signal.
time a character is transferred to the Receiver Holding Reg-
TRANSMlTTER SHIFT REGISTER EMPTY (TSRE):
ister. PE lines from a number of arrays can be bused
together since an output disconnect capability is provided by
the STATUS FLAG DISCONNECT (SFD) line.
A high-level voltage at this output indicates that the Trans-
mitter Shift Register has completed serial transmission of a
full character including stop bit(s). It remains at this level until
the start of transmission of the next character.
FRAMING ERROR (FE):
A high-level voltage at this output indicates that the received
character has no valid stop bit, i.e., the bit following the parity
bit (if programmed) is not a high-level voltage. This output is
updated each time a character is transferred to the Receiver
Holding Register. FE lines from a number of arrays can be
bused together since an output disconnect capability is pro-
vided by the STATUS FLAG DISCONNECT (SFD) line.
SERIAL DATA OUTPUT (SDO):
The contents of the Transmitter Shift Register (start bit, data
bits, parity bit, and stop bit(s)) are serially shifted out on this
output. When no character is being transmitted, a high-level
is maintained. Start of transmission is defined as the
transition of the start bit from a high-level to a low-level
output voltage.
OVERRUN ERROR (OE):
TRANSMlTTER BUS (T BUS 0 - T BUS 7):
Transmitter parallel data inputs.
A high-level voltage at this output indicates that the DATA
AVAILABLE (DA) flag was not reset before the next charac-
ter was transferred to the Receiver Holding Register. OE
lines from a number of arrays can be bused together since
an output disconnect capability is provided by the STATUS
FLAG DISCONNECT (SFD) line.
CONTROL REGISTER LOAD (CRL):
A high-level voltage at this input loads the Control Register
with the control bits (PI, EPE, SBS, WLS1, WLS2). This line
may be strobed or hardwired to a high-level input voltage.
STATUS FLAG DISCONNECT (SFD):
PARITY INHIBIT (PI):
A high-level voltage applied to this input disables the three-
state output drivers for PE, FE, OE, DA, and THRE, allowing
these status outputs to be bus connected.
A high-level voltage at this input inhibits the parity generation
and verification circuits and will clamp the PE output low. If
parity is inhibited the stop bit(s) will immediately follow the
last data bit on transmission.
RECEIVER CLOCK (RCLOCK):
Clock input with a frequency 16 times the desired receiver
shift rate.
STOP BIT SELECT (SBS):
This input selects the number of stop bits to be transmitted
after the parity bit. A high-level selects two stop bits, a low-
level selects one stop bit. Selection of two stop bits with five
data bits programmed selects 1.5 stop bits.
DATA AVAILABLE RESET (DAR):
A low-level voltage applied to this input resets the DA flip-
flop.
15
CDP1854A, CDP1854AC
V
) instead of being dynamically set and CRL may be
DD
hardwired to V . The CDP1854A is then ready for
transmitter and/or receiver operation.
DD
T CLOCK R CLOCK
PI
TPA
SCI
DAR
SBS
Transmitter Operation
WLS1
RRD
For the transmitter timing diagram refer to Figure 10. At the
beginning of a typical transmitting sequence the Transmitter
Holding Register is empty (THRE is HIGH). A character is
transferred from the transmitter bus to the Transmitter Hold-
ing Register by applying a low pulse to the TRANSMITTER
HOLDING REGISTER LOAD (THRL) input causing THRE to
go low. If the Transmitter Shift Register is empty (TSRE is
HIGH) and the clock is low, on the next high-to-low transition
of the clock the character is loaded into the Transmitter Shift
Register preceded by a start bit. Serial data transmission
begins 1/2 clock period later with a start bit and 5-8 data bits
followed by the parity bit (if programmed) and stop bit(s).
The THRE output signal goes high 1/2 clock period later on
the high-to-low transition of the clock. When THRE goes
high, another character can be loaded into the Transmitter
Holding Register for transmission beginning with a start bit
immediately following the last stop bit of the previous char-
acter. This process is repeated until all characters have been
transmitted. When transmission is complete, THRE and
Transmitter Shift Register Empty (TSRE) will both be high.
The format of serial data is shown in Figure 12. Duration of
each serial output data bit is determined by the transmitter
WLS2
EPE
THRL
TPB
N0
UART
CPU
CDP1854A
CDP1800
EF3
TSRE
DMAI
DA
SDI
SDO
(8)
BUS
T BUS
R BUS
CLEAR
MR
MODE
V
SS
FIGURE 8. MODE 0 CONNECTION DIAGRAM
WORD LENGTH SELECT 2 (WLS2):
WORD LENGTH SELECT 1 (WLS1):
These two inputs select the character length (exclusive of
parity) as follows:
WLS2
Low
WLS1
Low
WORD LENGTH
5 Bits
f
clock frequency ( CLOCK) and will be 16/f CLOCK.
Receiver Operation
Low
High
Low
6 Bits
The receive operation begins when a start bit is detected at
the SERIAL DATA IN (SDl) input. After the detection of a
high-to-low transition on the SD line, a divide-by-16 counter
is enabled and a valid start bit is verified by checking for a
low-level input 7-1/2 receiver clock periods later. When a
valid start bit has been verified, the following data bits, parity
bit (if programmed), and stop bit(s) are shifted into the
Receiver Shift Register at clock pulse 7-1/2 in each bit time.
If programmed, the parity bit is checked, and receipt of a
valid stop bit is verified. On count 7-1/2 of the first stop bit,
the received data is loaded into the Receiver Holding Regis-
ter. If the word length is less than 8 bits, zeros (low output
voltage level) are loaded into the unused most significant
bits. If DATA AVAILABLE (DA) has not been reset by the
time the Receiver Holding Register is loaded, the OVER-
RUN ERROR (OE) signal is raised. One-half clock period
later, the PARITY ERROR (PE) and FRAMlNG ERROR (FE)
signals become valid for the character in the Receiver Hold-
ing Register. The DA signal is also raised at this time. The
three-state output drivers for DA, OE, PE and FE are
enabled when STATUS FLAG DISCONNECT (SFD) is low.
When RECEIVER REGISTER DISCONNECT (RRD) goes
low, the receiver bus three-state output drivers are enabled
and data is available at the RECEIVER BUS (R BUS 0 - R
BUS 7) outputs. Applying a negative pulse to the DATA
AVAILABLE RESET (DAR) resets DA. The preceding
sequence of operation is repeated for each serial character
received. A receiver timing diagram is shown in Figure 11.
High
High
7 Bits
High
8 Bits
EVEN PARITY ENABLE (EPE):
A high-level voltage at this input selects even parity to be
generated by the transmitter and checked by the receiver. A
low-level input selects odd parity.
TRANSMITTER CLOCK (TCLOCK):
Clock input with a frequency 16 times the desired transmitter
shift rate.
Description of Standard Mode 0 Operation
(Mode Input = V
)
SS
Initialization and Controls
The MASTER RESET (MR) input is pulsed, resetting the
Control, Status, and Receiver Holding Registers and setting
the SERlAL DATA OUTPUT (SDO) signal high. Timing is
generated from the clock inputs, Transmitter Clock
(TCLOCK) and Receiver Clock (RCLOCK), at a frequency
equal to 16 times the serial data bit rate. When the receiver
data input rate and the transmitter data output rate are the
same, the TCLOCK and RCLOCK inputs may be connected
together. The CONTROL REGISTER LOAD (CRL) input is
pulsed to store the control inputs PARITY INHIBIT (PI),
EVEN PARITY ENABLE (EPE), STOP BIT SELECT (SBS),
and WORD LENGTH SELECTs (WLS1 and WLS2). These
inputs may be hardwired to the proper voltage levels (V or
SS
16
CDP1854A, CDP1854AC
o
o
Dynamic Electrical Specifications T = -40 C to +85 C, V ±5%, t , t = 20ns, V = 0.7 V , V = 0.3 V , C = 100pF,
A
DD
R
F
IH
DD IL
DD
L
(See Figure 9)
LIMITS
CDP1854A
CDP1854AC
V
(NOTE 1)
(NOTE 2)
(NOTE 1)
(NOTE 2)
DD
PARAMETER
(V)
TYP
MAX
TYP
MAX
UNITS
INTERFACE TIMING - MODE 0
Minimum Pulse Width
CRL
t
5
10
5
100
50
150
75
100
150
ns
ns
ns
ns
CRL
-
200
-
-
400
-
MR
t
200
100
400
200
MR
10
Minimum Setup Time
Control Word to CRL
t
t
5
40
20
80
50
40
-
80
-
ns
ns
CWC
CCW
10
Minimum Hold Time
Control Word after CRL
5
100
50
150
75
100
-
150
-
ns
ns
10
Propagation Delay Time
SFD High to SOD
t
5
10
5
200
100
75
300
150
120
60
200
300
ns
ns
ns
ns
ns
ns
ns
ns
SFDH
-
75
-
-
120
-
SFD Low to SOD
t
SFDL
10
5
40
RRD High to Receiver Register
High Impedance
t
200
100
100
50
300
150
150
75
200
-
300
-
RRDH
10
5
RRD Low to Receiver Register Active
t
100
-
150
-
RRDL
10
NOTES:
1. Typical values for T = 25 C and nominal voltages.
o
A
2. Maximum limits of minimum characteristics are the values above which all devices function.
CONTROL INPUT WORD TIMING
CONTROL WORD INPUT
t
t
CCW
CWC
CRL
t
CRL
STATUS OUTPUT TIMING
STATUS OUTPUTS
SFD
t
t
SFDL
SFDH
RECEIVER REGISTER DISCONNECT TIMING
R BUS 0
R BUS 7
t
t
RRDL
RRDH
RRD
FIGURE 9. MODE 0 INTERFACE TIMING DIAGRAM
17
CDP1854A, CDP1854AC
o
o
Dynamic Electrical Specifications T = -40 C to +85 C, V ±5%, t , t = 20ns, V = 0.7 V , V = 0.3 V , C = 100pF,
A
DD
R
F
IH
DD IL
DD
L
(See Figure 10)
LIMITS
CDP1854A
(NOTE 1) (NOTE 2)
CDP1854AC
V
(NOTE 1)
(NOTE 2)
DD
PARAMETER
TRANSMITTER TIMING - MODE 0
Minimum Clock Period
(V)
TYP
MAX
TYP
MAX
UNITS
t
5
250
125
310
155
250
-
310
-
ns
ns
CC
10
Minimum Pulse Width
Clock Low Level
t
5
10
5
100
75
125
100
125
100
150
75
100
125
ns
ns
ns
ns
ns
ns
CL
-
100
-
-
125
-
Clock High Level
THRL
t
100
75
CH
10
5
t
THTH
100
50
100
-
150
-
10
Minimum Setup Time
THRL to Clock
t
5
10
5
175
90
20
0
275
150
50
175
275
ns
ns
ns
ns
THC
-
20
-
-
50
-
Data to THRL
t
DT
TD
CD
10
40
Minimum Hold Time
Data after THRL
t
5
80
40
120
60
80
-
120
-
ns
ns
10
Propagation Delay Time
Clock to Data Start Bit
t
5
10
5
300
150
200
100
200
100
200
100
450
225
300
150
300
150
300
150
300
450
ns
ns
ns
ns
ns
ns
ns
ns
-
200
-
-
300
-
Clock to THRE
THRL to THRE
Clock to TSRE
t
CT
10
5
t
TTHR
200
-
300
-
10
5
t
200
-
300
-
TTS
10
NOTES:
1. Typical values for T = 25 C and nominal voltages.
o
A
2. Maximum limits of minimum characteristics are the values above which all devices function.
18
CDP1854A, CDP1854AC
o
o
Dynamic Electrical Specifications T = -40 C to +85 C, V ±5%, t , t = 20ns, V = 0.7 V , V = 0.3 V , C = 100pF,
A
DD
R
F
IH
DD IL
DD
L
(See Figure 11)
LIMITS
CDP1854A
CDP1854AC
V
(NOTE 1) (NOTE 2)
(NOTE 1)
(NOTE 2)
DD
PARAMETER
RECEIVER TIMING - MODE 0
Minimum Clock Period
(V)
TYP
MAX
TYP
MAX
UNITS
t
5
250
125
310
155
250
-
310
-
ns
ns
CC
10
Minimum Pulse Width
Clock Low Level
t
5
10
5
100
75
125
100
125
100
75
100
125
ns
ns
ns
ns
ns
ns
CL
CH
DD
-
100
-
-
125
-
Clock High Level
t
t
100
75
10
5
DATA AVAILABLE RESET
50
50
-
75
-
10
25
40
Minimum Setup Time
Data Start Bit to Clock
t
5
100
50
150
75
100
-
150
-
ns
ns
DC
10
Propagation Delay Time
DATA AVAILABLE RESET to
Data Available
t
t
t
5
10
5
150
75
225
125
325
175
325
175
300
150
375
175
300
150
150
225
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DDA
CDV
CDA
COE
-
225
-
-
325
-
Clock to Data Valid
225
110
225
110
210
100
240
120
200
100
10
5
Clock to Data Available
Clock to Overrun Error
Clock to Parity Error
Clock to Framing Error
225
-
325
-
10
5
t
210
-
300
-
10
5
t
240
-
375
-
CPE
10
5
t
200
-
300
-
CFE
10
NOTES:
1. Typical values for T = 25 C and nominal voltages.
o
A
2. Maximum limits of minimum characteristics are the values above which all devices function.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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19
CDP1854A, CDP1854AC
TRANSMITTER HOLDING
REGISTER LOADED
(NOTE 1)
TRANSMITTER SHIFT
REGISTER LOADED
(NOTE 2)
t
CC
t
t
CL
CH
T CLOCK
1
2
3
4
5
6
7
14
15
16
1
2
3
t
THC
THRL
SDO
t
t
t
THTH
CD
t
CD
1ST DATA BIT
t
TTHR
CT
THRE
TSRE
t
TTS
t
t
TD
DT
T BUS 0
T BUS 7
DATA
NOTES:
1. The holding register is loaded on the trailing edge of THRL.
2. The transmitter shift register, if empty, is loaded on the first high-to-low transition of the clock which occurs at least 1/2 clock period + t
THC
after the trailing edge of THRL and transmission of a start bit occurs 1/2 clock period + t
later.
CD
FIGURE 10. MODE 0 TRANSMITTER TIMING DIAGRAM
CLOCK 7 1/2
SAMPLE
CLOCK 7 1/2 LOAD
HOLDING REGISTER
t
CC
t
t
CL
CH
R CLOCK
1
2
3
4
5
6
7
16
1
2
3
4
5
6
7
8
9
t
DC
(NOTE 1)
START BIT
PARITY
STOP BIT 1
SDI
t
CDV
R BUS 0 -
R BUS 7
DA
t
t
t
DDA
CDA
DAR
t
COE
DD
OE
(NOTE 2)
t
CPE
PE
FE
t
CFE
NOTES:
1. If a start bit occurs at a time less than t
before a high-to-low transition of the clock, the start bit may not be recognized until the next
DC
high-to-low transition of the clock. The start bit may be completely asynchronous with the clock.
2. If a pending DA has not been cleared by a read of the receiver holding register by the time a new word is loaded into the receiver holding
register, the OE signal will come true.
FIGURE 11. MODE 0 RECEIVER TIMING DIAGRAM
16 / f
CLOCK
NEXT DATA WORD
5 - 8 DATA BITS
STOP BITS 1, 1-1/2 OR 2
START BIT
DATA
LSB
DATA
MSB
PARITY BIT
FIGURE 12. SERIAL DATA WORD FORMAT
20
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