CDP1822CE [RENESAS]
256X4 STANDARD SRAM, 450ns, PDIP22;
| 型号： | CDP1822CE |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 256X4 STANDARD SRAM, 450ns, PDIP22 静态存储器 光电二极管 |
| 文件： | 总8页 (文件大小：44K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDP1822,
CDP1822C
256-Word x 4-Bit
LSI Static RAM
March 1997
Features
Description
• Low Operating Current
- V = 5V, Cycle Time 1µs . . . . . . . . . . . . . . . . . . 8mA
The CDP1822 and CDP1822C are 256-word by 4-bit static
random-access memories designed for use in memory sys-
tems where high speed, low operating current, and simplicity
in use are desirable. The CDP1822 features high speed and
a wide operating voltage range. Both types have separate
data inputs and outputs and utilize single power supplies of
4V to 6.5V for the CDP1822C and 4V to 10.5V for the
CDP1822.
DD
• Industry Standard Pinout
• Two Chip-Select Inputs-Simple Memory Expansion
• Memory Retention for Standby Battery Voltage of 2V
Minimum
• Output-Disable for Common I/O Systems
• Three-State Data Output for Bus-Oriented Systems
• Separate Data Inputs and Outputs
Two Chip-Select inputs are provided to simplify system
expansion. An Output Disable control provides Wire-OR
capability and is also useful in common Input/Output sys-
tems. The Output Disable input allows these RAMs to be
used in common data Input/Output systems by forcing the
output into a high-impedance state during a write operation
independent of the Chip-Select input condition. The output
assumes a high-impedance state when the Output Disable is
at high level or when the chip is deselected by CS1 and/or
CS2.
Ordering Information
PKG.
5V
10V
PACKAGE TEMP. RANGE
NO.
o
o
CDP1822CE
CDP1822E
PDIP
-40 C to +85 C
E22.4
CDP1822CEX CDP1822EX
CDP1822CD CDP1822D
Burn-In
SBDIP
Burn-In
E22.4
The high noise immunity of the CMOS technology is pre-
served in this design. For TTL interfacing at 5V operation,
excellent system noise margin is preserved by using an
external pull-up resistor at each input.
o
o
-40 C to +85 C
D22.4A
D22.4A
CDP1822CDX
-
Pinout
CDP1822, CDP1822C
(PDIP, SBDIP)
TOP VIEW
OPERATIONAL MODES
INPUTS
CHIP
SELECT SELECT OUTPUT READ/
DISABLE WRITE
CHIP
A3
A2
A1
A0
A5
A6
A7
1
2
22
V
DD
1
2
21 A4
MODE
Read
(CS )
1
(CS )
2
(OD)
(R/W)
OUTPUT
Read
3
20 R/W
0
0
0
1
1
1
0
0
1
1
0
0
4
19
18
17
16
15
14
13
12
CS1
O. D.
CS2
DO4
DI4
Write
Write
Data In
5
High
Imped-
ance
6
7
8
V
Standby
Standby
1
X
X
X
0
X
X
1
X
X
X
High
Imped-
ance
SS
9
DI1
DO3
DI3
10
11
DO1
DI2
High
Imped-
ance
DO2
Output
X
High
Disable
Imped-
ance
NOTE:
Logic 1 = High, Logic 0 = Low, X = Don’t Care.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 1074.2
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-11
CDP1822, CDP1822C
Absolute Maximum Ratings
Thermal Information
o
o
DC Supply Voltage Range, (V
DD
)
Thermal Resistance (Typical)
θ
( C/W)
θ
( C/W)
JA
JC
(All Voltages Referenced to V Terminal)
CDP1822 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
PDIP Package . . . . . . . . . . . . . . . . . . .
SBDIP Package. . . . . . . . . . . . . . . . . .
75
80
N/A
21
SS
CDP1822C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Maximum Operating Temperature Range (T )
A
o
o
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to V
+0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . .-55 C to +125 C
Package Type E. . . . . . . . . . . . . . . . . . . . . . . . . . .-40 C to +85 C
Maximum Junction Temperature
DD
o
o
o
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 C
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C
o
o
o
Storage Temperature Range (T
). . . . . . . . . . . .-65 C to +150 C
T = -40 C to +60 C (Package Type E) . . . . . . . . . . . . . . 500mW
STG
o
o
A
o
o
T = +60 C to +85 C (Package Type E) . . . . . . Derate Linearly at
A
o
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12mW/ C to 200mW
Lead Temperature (During Soldering). . . . . . . . . . . . . . . . . . . 300 C
o
Recommended Operating Conditions At T = Full Package Temperature Range. For maximum reliability, operating conditions
A
should be selected so that operation is always within the following ranges:
LIMITS
CDP1822
CDP1822C
PARAMETER
DC Operating Voltage Range
Input Voltage Range
SYMBOL
MIN
MAX
MIN
MAX
UNITS
4
10.5
4
6.5
V
V
V
V
V
V
DD
SS
DD
SS
o
o
Static Electrical Specifications At T = -40 C to +85 C, Except as Noted
A
CONDITIONS
LIMITS
CDP1822
CDP1822C
V
V
V
DD
(NOTE 1)
(NOTE 1)
O
IN
PARAMETER
SYMBOL
(V)
(V)
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
0, 5
0, 10
-
(V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Quiescent Device
Current
I
-
5
-
-
-
-
500
-
-
-
500
µA
µA
mA
mA
mA
mA
V
DD
-
10
5
1000
-
-
Output Low (Sink)
Current
I
0.4
2
4
-
-
2
4
-
-
OL
0.5
10
5
4.5
-1
-2.2
-
9
-
-
Output High (Source)
Current
I
4.6
-2
-4.4
0
-
-1
-2
-
-
OH
9.5
10
5
-
-
-
Output Voltage
Low-Level
V
-
0.1
0.1
-
-
0
-
0.1
OL
-
10
5
-
0
-
-
V
Output Voltage
High-Level
V
-
4.9
9.9
-
5
4.9
5
-
-
-
V
OH
-
10
5
10
-
-
-
V
Input Low Voltage
Input High Voltage
Input Leakage Current
V
0.5, 4.5
0.5, 9.5
0.5, 9.5
0.5, 9.5
-
1.5
3
-
-
1.5
-
V
IL
IH
IN
-
10
5
-
-
-
-
V
V
-
3.5
7
-
-
3.5
-
-
V
-
10
5
-
-
-
-
-
-
-
V
I
0, 5
0, 10
-
-
±5
±10
-
±5
-
µA
µA
-
10
-
-
-
6-12
CDP1822, CDP1822C
o
o
Static Electrical Specifications At T = -40 C to +85 C, Except as Noted (Continued)
A
CONDITIONS
LIMITS
CDP1822
CDP1822C
V
V
V
DD
(NOTE 1)
(NOTE 1)
O
IN
PARAMETER
SYMBOL
(V)
(V)
0, 5
0, 10
0, 5
0, 10
-
(V)
MIN
TYP
MAX
8
MIN
TYP
MAX
8
UNITS
mA
mA
µA
Operating Current
(Note 2)
I
-
5
-
-
-
-
-
-
4
8
-
-
-
-
-
-
4
-
DD1
-
0, 5
0, 10
-
10
5
16
-
Three-State Output
Leakage Current
I
-
±5
-
±5
-
OUT
10
-
-
±10
7.5
15
-
µA
Input Capacitance
Output Capacitance
NOTES:
C
5
5
10
7.5
15
pF
IN
C
-
-
-
10
pF
OUT
o
1. Typical values are for T = +25 C and nominal V
A
.
DD
2. Outputs open circuited; Cycle time = 1µs.
o
Dynamic Electrical Specifications At T + -40 to +85 C, V ±5%, Input t , t = 20ns, V = 0.7 V , V = 0.3 V
,
A
DD
R
F
IH
DD IL
DD
C
= 100 pF
L
TEST
CONDITIONS
LIMITS
CD1822
CDP1822C
V
(NOTE 1)
(NOTE 2)
(NOTE 1) (NOTE 2)
DD
PARAMETER
Read Cycle Times (Figure 1)
Read Cycle
(V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
t
t
t
t
5
10
5
450
250
-
-
-
-
450
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
-
-
-
-
-
Access from Address
250
450
250
450
250
450
250
200
110
-
250
450
AA
10
5
-
150
-
-
-
Output Valid from Chip-Select 1
Output Valid from Chip-Select 2
-
250
-
250
450
DOA1
DOA2
DOA3
DOH1
DOH2
DOH3
10
5
-
150
-
-
-
-
250
-
250
450
10
5
-
150
-
-
-
-
-
-
-
-
-
-
-
Output Valid from Output Disable t
-
-
-
-
-
-
-
-
-
-
200
10
5
-
-
-
-
-
-
-
-
-
Output Hold from Chip-Select 1
Output Hold from Chip-Select 2
Output Hold from Output Disable
NOTES:
t
t
t
20
20
20
20
20
20
20
-
10
5
-
-
20
-
10
5
-
-
20
-
10
-
1. Time required by a limit device to allow for indicated function.
o
2. Typical values are for T = 25 C and nominal V
.
A
DD
6-13
CDP1822, CDP1822C
t
RC
A0 - A7
t
DOA1
t
CHIP-SELECT 1
DOH1
CHIP-SELECT 2
OUTPUT DISABLE
READ/WRITE
t
t
DOH2
DOA2
t
DOA3
t
DOH3
t
AA
DATA OUT
VALID
DATA OUT
HIGH
IMPEDANCE
HIGH
IMPEDANCE
FIGURE 1. READ CYCLE TIMING WAVEFORMS
o
Dynamic Electrical Specifications At T + -40 to +85 C, V ±5%, Input t , t = 20ns, V = 0.7 V , V = 0.3 V
,
A
DD
R
F
IH
DD IL
DD
C
= 100 pF.
L
LIMITS
TEST
CONDITIONS
CD1822
CDP1822C
V
(NOTE 1)
(NOTE 2)
(NOTE 1)
(NOTE 2)
DD
PARAMETER
(V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Read Cycle Times (Figure 2)
Write Cycle
t
5
10
5
500
300
200
110
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
500
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
-
200
-
Address Setup
Write Recovery
Write Width
t
t
t
t
t
t
t
AS
10
5
50
-
WR
10
5
40
250
150
250
150
50
250
-
WRW
DS
10
5
Input Data Setup Time
Data Hold
250
-
10
5
50
-
DH
10
5
40
Chip-Select 1 Setup
Chip-Select 2 Setup
200
110
200
110
200
-
CS1S
CS2S
10
5
200
-
10
6-14
CDP1822, CDP1822C
o
Dynamic Electrical Specifications At T + -40 to +85 C, V ±5%, Input t , t = 20ns, V = 0.7 V , V = 0.3 V
,
A
DD
R
F
IH
DD IL
DD
C
= 100 pF. (Continued)
L
LIMITS
TEST
CONDITIONS
CD1822
CDP1822C
V
(NOTE 1)
(NOTE 2)
(NOTE 1)
(NOTE 2)
DD
PARAMETER
Chip-Select 1 Hold
(V)
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
t
t
t
5
0
0
-
-
-
-
-
-
-
-
-
-
-
-
0
0
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
CS1H
CS2H
ODS
10
5
Chip-Select 2 Hold
Output Disable Set-Up
NOTES:
0
0
10
5
0
0
200
110
200
-
10
1. Time required by a limit device to allow for indicated function.
o
2. Typical values are for T = 25 C and nominal V
A
.
DD
t
WC
t
WR
A0-A7
t
t
CSIS
CSIH
CHIP-SELECT 1
CHIP-SELECT 2
t
t
CS2H
CS2S
(NOTE)
OUTPUT DISABLE
DI1-DI4
t
t
t
DH
ODS
DS
DATA IN STABLE
t
WRW
READ/WRITE
t
AS
DON’T CARE
NOTE: t
ODS
is required for common I/O operation only. For separate I/O operations, output disable is don’t care.
FIGURE 2. WRITE CYCLE TIME WAVEFORMS
6-15
CDP1822, CDP1822C
o
Data Retention Specifications At T = -40 to +85 C, see Figure 3.
A
LIMITS
TEST CONDITIONS
CDP1822
CDP1822C
V
V
(NOTE 1)
(NOTE 1)
DR
DD
PARAMETER
(V)
(V)
MIN
TYP
MAX
MIN
TYP
MAX
2
UNITS
V
Min. Data Retention Voltage
V
-
-
-
-
-
1.5
30
2
-
-
1.5
30
DR
Data Retention Quiescent
Current
2
100
100
µA
I
t
DD
Chip Deselect to Data Retention
Time
-
-
5
10
5
600
300
600
300
1
-
-
-
-
-
-
-
-
-
-
600
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
µA
CDR
-
600
-
Recovery to Normal Operation
Time
-
t
t
RC
-
10
5
V
to VDR Rise and Fall Time
t
R, F
2
1
DD
o
NOTE: Typical values are for T = 25 C and nominal V
A
.
DD
V
DD
DATA RETENTION
MODE
V
DD
0.95 V
0.95 V
DD
DD
V
DR
V
SS
t
t
t
t
RC
CDR
f
r
C
WRITE
ADDRESS
DECODER
READ
ADDRESS
DECODER
S2
V
V
IH
IH
V
IL
V
IL
V
DD
FIGURE 3. LOW V
DATA RETENTION TIME WAVEFORMS
FIGURE 4. MEMORY CELL CONFIGURATION
DD
6-16
CDP1822, CDP1822C
†
†
†
†
†
4
3
(32)
ROW
(5)
INPUT
BUFFERS
AND
ALL ROWS
DESELECT
FUNCTION
A0
A1
A2
A3
A4
† † †
22
2
V
DD
DECODERS
1
21
(8 x 32)
STORAGE
ARRAY
(8 x 32)
STORAGE
ARRAY
(8 x 32)
STORAGE
ARRAY
(8 x 32)
STORAGE
ARRAY
(4)
†
†
†
†
††
9
10
12
DI1
DI2
DI3
DI4
D01
BUFFER
DRIVERS
††
11
BITS
(1-4)
D02
(4)
GATES
††
13
15
14
16
D03
††
D04
BIT (1)
(8)
BIT (2)
(8)
BIT (3)
(8)
BIT (4)
(8)
(3)
INPUT
BUFFERS
AND
ALL COLUMNS
DESELECT
FUNCTION
†
†
†
5
6
COLUMN
DECODERS
COLUMN
DECODERS
COLUMN
DECODERS
COLUMN
DECODERS
A5
A6
A7
7
†
20
CONTROL
B
R/W
† † †
8
†
19
CONTROL
A
CONTROL
C
V
SS
CSI
CS2
OD
†
17
†
18
V
V
V
DD
DD
DD
V
V
V
SS
SS
SS
INPUT PROTECTION
NETWORK
OUTPUT
PROTECTION
CIRCUIT
OVER VOLTAGE
PROTECTION
CIRCUIT
†
††
† ††
FIGURE 5. FUNCTIONAL BLOCK DIAGRAM FOR CDP1822 AND CDP1822C
6-17
CDP1822, CDP1822CS
C
CONTROL A
CS1
CS2
19
17
A
CHIP-SELECT
CONTROL
CONTROL B
CONTROL C
B
R/W
20
CHIP-SELECT AND
R/W CONTROL
C
OUTPUT
DISABLE
CONTROL
OUTPUT
DISABLE
18
FIGURE 6. LOGIC DIAGRAM OF CONTROLS FOR CDP1822 AND CDP1822C
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
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6-18
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