CD4508BKMSR [RENESAS]
4000/14000/40000 SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, CDFP24;
| 型号： | CD4508BKMSR |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 4000/14000/40000 SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, CDFP24 驱动 CD 输出元件 逻辑集成电路 |
| 文件： | 总9页 (文件大小：87K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD4508BMS
CMOS Dual 4-Bit Latch
December 1992
Features
Pinout
CD4508BMS
TOP VIEW
• High-Voltage Types (20-Volt Rating)
• Two Independent 4-Bit Latches
• Individual Master Reset for Each 4-Bit Latch
1
2
3
4
5
6
7
8
9
24
VDD
RESET A
23 Q3B
STROBE A
• 3-State Outputs with High-Impedance State for Bus
Line Applications
22 D3B
OUTPUT DISABLE A
21 Q2B
D0A
Q0A
D1A
Q1A
• Medium-Speed Operation: tPHL = tPLH = 70nS (Typ.)
at VDD = 10V and CL = 50pF
20 D2B
19 Q1B
• 100% Tested for Quiescent Current at 20V
• 5V, 10V, and 15V Parametric Ratings
18 D1B
17 Q0B
D2A
Q2A
16 D0B
• Standardized, Symmetrical Output Characteristics
D3A 10
Q3A 11
VSS 12
15 OUTPUT DISABLE B
14 STROBE B
13 RESET B
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and 25oC
• Noise Margin (Full Package-Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
Functional Diagram
• Meets all Requirements of JEDEC Tentative Standard
No. 13B, "Standard Specifications for Description of
‘B’ Series CMOS Devices"
OUTPUT
DISABLE
D0A
Q0A
D1A
Q1A
Applications
4-BIT
LATCH
3-STATE
OUTUTS
Q2A
D2A
D3A
• Buffer Storage
Q3A
• Holding Registers
• Data Storage and Multiplexing
STROBE
RESET
OUTPUT
DISABLE
Description
D0B
D1B
Q0B
CD4508BMS dual 4-bit latch contains two identical 4-bit
latches with separate STROBE, RESET, and OUTPUT
DISABLE controls. With the STROBE line in the high state,
the data on the "D" inputs appear at the corresponding "Q"
outputs provided the DISABLE line is in the low state.
Changing the STROBE line to the low state locks the data
into the latch. A high on the reset line forces the outputs to a
low level regardless of the state of the STROBE input. The
outputs are forced to the high-impedance state for bus line
applications by a high level on the DISABLE input.
Q1B
4-BIT
LATCH
3-STATE
OUTUTS
Q2B
D2B
Q3B
D3B
STROBE
RESET
The CD4508BMS is supplied in these 24 lead outline
packages:
Braze Seal DIP
Frit Seal DIP
H4V
H1Z
Ceramic Flatpack H4P
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3337
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1148
Specifications CD4508BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Thermal Resistance . . . . . . . . . . . . . . . .
Ceramic DIP and FRIT Package . . . . . 80 C/W
Flatpack Package . . . . . . . . . . . . . . . . 70 C/W
θ
θ
jc
ja
o
o
20 C/W
o
o
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
20 C/W
o
Maximum Package Power Dissipation (PD) at +125 C
o
o
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Package Types D, F, K, H
For T = -55 C to +100 C (Package Type D, F, K) . . . . . . 500mW
A
o
o
For T = +100 C to +125 C (Package Type D, F, K). . . . . .Derate
A
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
Linearity at 12mW/ C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265 C
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
For T = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
A
o
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN MAX UNITS
GROUP A
SUBGROUPS
PARAMETER
Supply Current
SYMBOL
CONDITIONS (NOTE 1)
TEMPERATURE
o
IDD
VDD = 20V, VIN = VDD or GND
1
+25 C
-
10
1000
10
µA
µA
µA
nA
nA
nA
nA
nA
nA
mV
V
o
2
+125 C
-
o
VDD = 18V, VIN = VDD or GND
3
-55 C
-
o
Input Leakage Current
Input Leakage Current
IIL
VIN = VDD or GND
VIN = VDD or GND
VDD = 20
1
+25 C
-100
-
o
2
+125 C
-1000
-
o
VDD = 18V
VDD = 20
3
-55 C
-100
-
o
IIH
1
+25 C
-
-
-
-
100
1000
100
50
o
2
+125 C
o
VDD = 18V
3
-55 C
o
o
o
Output Voltage
VOL15 VDD = 15V, No Load
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25 C, +125 C, -55 C
o
o
o
Output Voltage
1, 2, 3
+25 C, +125 C, -55 C 14.95
-
o
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
IOL5
IOL10
IOL15
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1
+25 C
0.53
1.4
3.5
-
-
mA
mA
mA
mA
mA
mA
mA
V
o
1
+25 C
-
o
1
+25 C
-
o
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25 C
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
o
1
+25 C
-
o
1
+25 C
-
o
1
1
+25 C
-
o
N Threshold Voltage
P Threshold Voltage
Functional
VNTH
VPTH
F
VDD = 10V, ISS = -10µA
+25 C
-2.8
0.7
o
VSS = 0V, IDD = 10µA
1
+25 C
V
o
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V, VOH > 4.5V, VOL < 0.5V
7
+25 C
VOH > VOL <
VDD/2 VDD/2
V
o
7
+25 C
o
8A
8B
1, 2, 3
+125 C
o
-55 C
o
o
o
Input Voltage Low
(Note 2)
VIL
VIH
VIL
+25 C, +125 C, -55 C
-
1.5
V
V
V
V
o
o
o
Input Voltage High
(Note 2)
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C 3.5
-
4
-
o
o
o
Input Voltage Low
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
-
o
o
o
Input Voltage High
(Note 2)
VIH
IOZL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
11
o
Tri-State Output
Leakage
VIN = VDD or GND
VOUT = 0V
VDD = 20V
1
2
3
1
2
3
+25 C
-0.4
-
-
µA
µA
µA
µA
µA
µA
o
+125 C
-12
o
VDD = 18V
VDD = 20V
-55 C
-0.4
-
o
Tri-State Output
Leakage
IOZH
VIN = VDD or GND
VOUT = VDD
+25 C
-
-
-
0.4
12
0.4
o
+125 C
o
VDD = 18V
-55 C
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. Foraccuracy, voltageismeasureddifferentiallytoVDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
7-1149
Specifications CD4508BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN
GROUP A
SUBGROUPS TEMPERATURE
PARAMETER
SYMBOL
CONDITIONS
MAX
260
351
200
270
UNITS
ns
o
Propagation Delay
Strobe In to Data Out
TPHL1 VDD = 5V, VIN = VDD or GND
TPLH1 (Note 1, 2)
9
+25 C
-
-
-
-
o
o
10, 11
9
+125 C, -55 C
ns
o
Transition Time
NOTES:
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
(Note 1, 2)
+25 C
ns
o
o
10, 11
+125 C, -55 C
ns
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
o
o
2. -55 C and +125 C limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
5
UNITS
µA
o
o
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55 C, +25 C
-
-
-
-
-
-
-
o
+125 C
150
10
µA
o
o
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
1, 2
1, 2
-55 C, +25 C
µA
o
+125 C
300
10
µA
o
o
-55 C, +25 C
µA
o
+125 C
600
50
µA
o
o
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
VOL
VOL
VOH
VOH
IOL5
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, VOUT = 0.4V
1, 2
1, 2
1, 2
1, 2
1, 2
+25 C, +125 C,
mV
o
-55 C
o
o
+25 C, +125 C,
-
50
-
mV
V
o
-55 C
o
o
+25 C, +125 C,
4.95
9.95
o
-55 C
o
o
+25 C, +125 C,
-
V
o
-55 C
o
+125 C
0.36
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
o
-55 C
0.64
o
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOL10
IOL15
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
+125 C
0.9
-
o
-55 C
1.6
-
o
+125 C
2.4
-
o
-55 C
4.2
-
o
IOH5A VDD = 5V, VOUT = 4.6V
IOH5B VDD = 5V, VOUT = 2.5V
+125 C
-
-
-
-
-
-
-
-
-
-0.36
-0.64
-1.15
-2.0
-0.9
-1.6
-2.4
-4.2
3
o
-55 C
o
+125 C
o
-55 C
o
IOH10
IOH15
VDD = 10V, VOUT = 9.5V
VDD =15V, VOUT = 13.5V
+125 C
o
-55 C
o
+125 C
o
-55 C
o
o
Input Voltage Low
Input Voltage High
VIL
VDD = 10V, VOH > 9V, VOL <
1V
1, 2
1, 2
+25 C, +125 C,
o
-55 C
o
o
VIH
VDD = 10V, VOH > 9V, VOL <
1V
+25 C, +125 C,
+7
-
V
o
-55 C
o
Propagation Delay
Strobe In to Data Out
TPHL1 VDD = 10V
1, 2, 3
1, 2, 3
+25 C
-
-
140
100
ns
ns
o
TPLH1
VDD = 15V
+25 C
7-1150
Specifications CD4508BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
MIN
PARAMETER
SYMBOL
CONDITIONS
NOTES
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 4
1, 2, 4
1, 2, 4
1, 2, 4
1, 2, 4
1, 2, 4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
TEMPERATURE
MAX
210
120
90
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
o
Propagation Delay
Data In to Data Out
TPHL2 VDD = 5V
TPLH2
+25 C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
o
VDD = 10V
+25 C
o
VDD = 15V
+25 C
o
Propagation Delay
Reset to Data Out
TPHL3 VDD = 5V
TPLH3
+25 C
180
100
80
o
VDD = 10V
+25 C
o
VDD = 15V
+25 C
o
Propagation Delay
3-State
TPHZ
TPZH
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
Any Input
+25 C
180
100
70
o
+25 C
o
+25 C
o
Transition Time
3-State
TPLZ
TPZL
+25 C
180
100
70
o
+25 C
o
+25 C
o
Transition Time
TTHL
TTLH
+25 C
100
80
o
+25 C
o
Minimum Strobe Pulse
Width
TWS
+25 C
140
80
o
+25 C
o
+25 C
70
o
Minimum Data Setup
Time
TS
+25 C
50
o
+25 C
30
o
+25 C
20
o
Minimum Data Hold Time
TH
+25 C
0
o
+25 C
0
o
+25 C
0
o
Minimum Reset Pulse
Width
TWR
CIN
+25 C
200
140
100
7.5
o
+25 C
o
+25 C
o
Input Capacitance
NOTES:
+25 C
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
N Threshold Voltage
SYMBOL
IDD
CONDITIONS
NOTES
1, 4
TEMPERATURE
MIN
-
MAX
25
UNITS
µA
o
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
+25 C
o
VNTH
1, 4
+25 C
-2.8
-0.2
V
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
1151
Specifications CD4508BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
o
N Threshold Voltage
Delta
∆VTN
VDD = 10V, ISS = -10µA
1, 4
+25 C
-
±1
V
o
P Threshold Voltage
VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
1, 4
1, 4
+25 C
0.2
-
2.8
V
V
o
P Threshold Voltage
Delta
∆VTP
+25 C
±1
o
Functional
F
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
1
+25 C
VOH >
VDD/2
VOL <
VDD/2
V
o
Propagation Delay Time
TPHL
TPLH
1, 2, 3, 4
+25 C
-
1.35 x
ns
o
+25 C
Limit
o
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25 C limit.
4. Read and Record
o
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 C
PARAMETER
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
DELTA LIMIT
± 1.0µA
IOL5
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
IOH5A
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
METHOD
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
Sample 5005
Sample 5005
Sample 5005
Sample 5005
GROUP A SUBGROUPS
READ AND RECORD
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
PDA (Note 1)
1, 7, 9
IDD, IOL5, IOH5A
1, 7, 9, Deltas
Final Test
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
Group A
Group B
Subgroup B-5
Subgroup B-6
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
Group D
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
MIL-STD-883
METHOD
CONFORMANCE GROUPS
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Table 4
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
7-1152
Specifications CD4508BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
Static Burn-In 1 5, 7, 9, 11, 17, 19,
Note 1 21, 23
Static Burn-In 2 5, 7, 9, 11, 17, 19,
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
1-4, 6, 8, 10,
12-16, 18, 20, 22
24
12
1, 3, 12, 13, 15
12
1-4, 6, 8, 10, 13-
16, 18, 20, 22, 24
Note 1
21, 23
Dynamic Burn-
In Note 1
-
2, 14, 24
5, 7, 9, 11, 17, 19, 4, 6, 8, 10, 16, 18,
21, 23 20, 22
-
Irradiation
Note 2
5, 7, 9, 11, 17, 19,
21, 23
1-4, 6, 8, 10, 13-
16, 18, 20, 22, 24
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
Logic Diagram
OUTPUT DISABLE
TYPICAL LATCH
OUTPUT DISABLE
VDD
*
3
OUTPUT
DISABLE - A
*
1
Qn-A
5(7, 9, 11)
RESET - A
ST
OUTPUT
*
p
n
4(6, 8, 10)
Dn - A
VDD
VSS
ST
ST
ST
ST
p
n
*
2
STROBE - A
ST
VSS
* All inputs protected by CMOS protection network.
FIGURE 1. LOGIC DIAGRAM (A-SECTION), 1 OF 4 IDENTICAL LATCHES
WITH COMMON OUTPUT DISABLE, RESET AND STROBE
TRUTH TABLE
RESET
DISABLE
STROBE
D INPUT
Q OUTPUT
0
0
0
1
X
0
0
0
0
1
1
1
0
X
X
1
0
1
0
X
X
X
LATCHED
0
Z
1 = HIGH LEVEL
0 = LOW LEVEL
X = DON’T CARE
Z = HIGH IMPEDANCE
7-1153
CD4508BMS
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
15.0
30
25
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
7.5
20
15
10V
10V
10
5
5.0
2.5
5V
5V
0
5
10
15
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
0
-15
-10
-5
0
0
0
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-5
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-10
-15
-20
-25
-30
-5
-10V
-10V
-10
-15
-15V
-15V
FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
AMBIENT TEMPERATURE (TA) = +25oC
175
AMBIENT TEMPERATURE (TA) = +25oC
150
SUPPLY VOLTAGE (VDD) = 5V
200
125
100
SUPPLY VOLTAGE (VDD) = 5V
150
75
100
10V
10V
15V
50
50
15V
25
0
0
20
40
60
80
100
0
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
LOAD CAPACITANCE (CL) (pF)
FIGURE 6. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
FIGURE 7. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE (STROBE TO
DATA OUT)
7-1154
CD4508BMS
Typical Performance Characteristics (Continued)
105
AMBIENT TEMPERATURE
(TA) = +25oC, tr, tf = 20ns
RL = 200kΩ
8
6
4
2
SUPPLY VOLTAGE
(VDD) = 15V
104
103
8
6
4
10V
10V
5V
2
8
6
4
2
102
10
8
6
4
CL = 50pF
CL = 15pF
2
2
4 6 8
2
4
6 8
101
2
4
6 8
102
2
4 6 8
10
103
104
INPUT FREQUENCY (fIN) (kHz)
FIGURE 8. TYPICAL POWER DISSIPATION AS A FUNCTION OF FREQUENCY
Waveforms and Test Circuits
tW(st)
STROBE
INPUT
tSU
tH
Dn
INPUT
tW(R)
RESET
OUTPUT
DISABLE
tPHL
tPLH
Qn OUTPUT
tPHL
tPLH
tTLH
tTHL
FIIGURE 9. TEST WAVEFORMS
VDD
VDD
50%
50%
VSS
VDD
VOL
OUTPUT DISABLE
tPLZ
tPLZ
90%
10%
Q OUTPUT
Q OUTPUT
STROBE
DISABLE
D0
D1
D2
Q0
Q1
Q2
Q3
PULSE
GEN
TEST ANY
OUTPUT
VOH
VSS
90%
1kΩ
10%
Q
D
tPHZ
tPZH
TEST VOLT.
50pF
D3
RESET
CHAR.
AT D
AT Q
VSS
VDD
VDD
VSS
tPHZ
tPLZ
tPZL
tPZH
VDD
VSS
VSS
VDD
VSS
FIGURE 10. OUTPUT DISABLE TEST CIRCUIT AND WAVEFORMS
7-1155
CD4508BMS
Bus Registers
CD4508BMS
CD4508BMS
3-STATE
4 BIT LATCH
3-STATE
4 BIT LATCH
DATA BUS
4-LINE
DATA BUS
RESET
CLOCK
CD4019BMS
4-LINE
DATA BUS
4 BIT SHIFT
REGISTER
4 BIT SHIFT
REGISTER
CD4015BMS
SERIAL
DATA
A
B
3-STATE
4 BIT LATCH
3-STATE
4 BIT LATCH
STROBE
QUAD LATCH
(3 STATE)
QUAD LATCH
(3 STATE)
FUNCTON SELECT
CD4508BMS
DISABLE
DISABLE
A
0
1
0
1
B
0
0
1
1
FUNCTION
Inhibit (All 0)
Select A Bus
Select B Bus
AI + BI
4-LINE
DATA
BUS
FIGURE 11. BUS REGISTER
FIGURE 12. DUAL MULTIPLEXED BUS REGISTER WITH FUNC-
TION SELECT
Chip Dimensions and Pad Layouts
0
10
20
30
40
50
60
70
80
90 96
94
90
80
70
60
50
40
30
91-99
(2.311-2.515)
20
10
0
4-10
(0.102-0.254)
93-101
(2.362-2.565)
Dimensions in parentheses are in milimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch.)
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-1156
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