CD4073BDMSR [RENESAS]
4000/14000/40000 SERIES, TRIPLE 3-INPUT AND GATE, CDIP14;
| 型号： | CD4073BDMSR |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 4000/14000/40000 SERIES, TRIPLE 3-INPUT AND GATE, CDIP14 栅 CD 输入元件 逻辑集成电路 触发器 |
| 文件： | 总10页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD4073BMS, CD4081BMS
CD4082BMS
CMOS AND Gate
January 1993
Features
Pinout
CD4073BMS
TOP VIEW
• High-Voltage Types (20V Rating)
• CD4073BMS Triple 3-Input AND Gate
• CD4081BMS Quad 2-Input AND Gate
• CD4082BMS Dual 4-Input AND Gate
A
1
2
3
4
5
6
7
14 VDD
B
13
12
11
G
H
I
• Medium Speed Operation:
D
- tPLH, tPHL = 60ns (typ) at VDD = 10V
E
• 100% Tested for Quiescent Current at 20V
F
K = D • E • F
VSS
10 L = G • H • I
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
9
8
J = A • B • C
C
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
CD4081BMS
TOP VIEW
- 2.5V at VDD = 15V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
A
1
2
3
4
5
6
7
14 VDD
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
B
J = A • B
K = C • D
C
13
12
H
G
11 M = G • H
10 L = E • F
Description
CD4073BMS, CD4081BMS and CD4082BMS AND gates
provide the system designer with direct implementation of
the AND function and supplement the existing family of
CMOS gates.
D
9
8
F
E
VSS
The CD4073BMS, CD4081BMS and CD4082BMS are supplied
in these 14 lead outline packages:
CD4082BMS
TOP VIEW
Braze Seal DIP
Frit Seal DIP
*H4Q †H4H
*H1B
J = A • B • C • D
1
2
3
4
5
6
7
14 VDD
D
C
13 K = E • F • G • H
Ceramic Flatpack
*H3W
12
11
10
9
H
*CD4073B, CD4081B †CD4082B
B
G
F
A
NC
VSS
E
8
NC
NC = NO CONNECTION
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3324
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-433
CD4073BMS, CD4081BMS, CD4082BMS
Functional Diagram
VDD
14
1
A
9
6
2
J
B
8
3
C
D
4
K
L
E
5
11
F
I
10
12
13
H
G
7
VSS
CD4073BMS
VDD
14
1
2
3
4
A
J
B
5
6
C
D
K
L
8
9
10
E
F
12
13
11
G
H
M
7
VSS
CD4081BMS
VDD
14
2
D
3
1
C
J
4
5
B
A
9
10
E
F
13
K
11
12
G
H
7
VSS
CD4082BMS
7-434
Specifications CD4073BMS, CD4081BMS, CD4082BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Thermal Resistance . . . . . . . . . . . . . . . .
Ceramic DIP and FRIT Package . . . . . 80 C/W
Flatpack Package . . . . . . . . . . . . . . . . 70 C/W
θ
θ
jc
ja
o
o
20 C/W
o
o
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
20 C/W
o
Maximum Package Power Dissipation (PD) at +125 C
o
o
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Package Types D, F, K, H
For TA = -55 C to +100 C (Package Type D, F, K) . . . . . . 500mW
o
o
For TA = +100 C to +125 C (Package Type D, F, K) . . . . .Derate
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
Linearity at 12mW/ C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265 C
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
o
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN MAX UNITS
GROUP A
SUBGROUPS
PARAMETER
Supply Current
SYMBOL
CONDITIONS (NOTE 1)
TEMPERATURE
o
IDD
VDD = 20V, VIN = VDD or GND
1
+25 C
-
.5
50
.5
µA
µA
µA
nA
nA
nA
nA
nA
nA
mV
V
o
2
+125 C
-
o
VDD = 18V, VIN = VDD or GND
3
-55 C
-
o
Input Leakage Current
Input Leakage Current
IIL
VIN = VDD or GND
VIN = VDD or GND
VDD = 20
1
+25 C
-100
-
o
2
+125 C
-1000
-
o
VDD = 18V
VDD = 20
3
-55 C
-100
-
o
IIH
1
+25 C
-
-
-
-
100
1000
100
50
-
o
2
+125 C
o
VDD = 18V
3
-55 C
o
o
o
Output Voltage
VOL15 VDD = 15V, No Load
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25 C, +125 C, -55 C
o
o
o
Output Voltage
1, 2, 3
+25 C, +125 C, -55 C 14.95
o
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
IOL5
IOL10
IOL15
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1
+25 C
0.53
1.4
3.5
-
-
mA
mA
mA
mA
mA
mA
mA
V
o
1
+25 C
-
o
1
+25 C
-
o
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25 C
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
o
1
+25 C
-
o
1
+25 C
-
o
1
1
+25 C
-
o
N Threshold Voltage
P Threshold Voltage
Functional
VNTH
VPTH
F
VDD = 10V, ISS = -10µA
+25 C
-2.8
0.7
o
VSS = 0V, IDD = 10µA
1
+25 C
V
o
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V, VOH > 4.5V, VOL < 0.5V
7
+25 C
VOH > VOL <
VDD/2 VDD/2
V
o
7
+25 C
o
8A
8B
1, 2, 3
+125 C
o
-55 C
o
o
o
Input Voltage Low
(Note 2)
VIL
VIH
VIL
VIH
+25 C, +125 C, -55 C
-
1.5
V
V
V
V
o
o
o
Input Voltage High
(Note 2)
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C 3.5
-
4
-
o
o
o
Input Voltage Low
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
-
o
o
o
Input Voltage High
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
11
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. Foraccuracy, voltageismeasureddifferentiallytoVDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
7-435
Specifications CD4073BMS, CD4081BMS, CD4082BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN
GROUP A
SUBGROUPS TEMPERATURE
PARAMETER
SYMBOL
CONDITIONS (NOTES 1, 2)
MAX
250
338
200
270
UNITS
ns
o
Propagation Delay
TPHL
TPLH
VDD = 5V, VIN = VDD or GND
9
+25 C
-
-
-
-
o
o
10, 11
9
+125 C, -55 C
ns
o
Transition Time
NOTES:
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
+25 C
ns
o
o
10, 11
+125 C, -55 C
ns
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
o
o
2. -55 C and +125 C limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
.25
7.5
.5
UNITS
µA
o
o
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55 C, +25 C
-
-
-
-
-
-
-
o
+125 C
µA
o
o
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
1, 2
1, 2
-55 C, +25 C
µA
o
+125 C
15
µA
o
o
-55 C, +25 C
.5
µA
o
+125 C
30
µA
o
o
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
VOL
VOL
VOH
VOH
IOL5
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, VOUT = 0.4V
1, 2
1, 2
1, 2
1, 2
1, 2
+25 C, +125 C,
50
mV
o
-55 C
o
o
+25 C, +125 C,
-
50
-
mV
V
o
-55 C
o
o
+25 C, +125 C,
4.95
9.95
o
-55 C
o
o
+25 C, +125 C,
-
V
o
-55 C
o
+125 C
0.36
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
o
-55 C
0.64
o
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOL10
IOL15
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
+125 C
0.9
-
o
-55 C
1.6
-
o
+125 C
2.4
-
o
-55 C
4.2
-
o
IOH5A VDD = 5V, VOUT = 4.6V
IOH5B VDD = 5V, VOUT = 2.5V
+125 C
-
-
-
-
-
-
-
-
-
-0.36
-0.64
-1.15
-2.0
-0.9
-2.6
-2.4
-4.2
3
o
-55 C
o
+125 C
o
-55 C
o
IOH10
IOH15
VDD = 10V, VOUT = 9.5V
VDD =15V, VOUT = 13.5V
+125 C
o
-55 C
o
+125 C
o
-55 C
o
o
Input Voltage Low
Input Voltage High
Propagation Delay
VIL
VDD = 10V, VOH > 9V, VOL < 1V
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
1, 2
+25 C, +125 C,
o
-55 C
o
o
VIH
+25 C, +125 C,
7
-
V
o
-55 C
o
TPHL
TPLH
VDD = 10V
VDD = 15V
1, 2, 3
1, 2, 3
+25 C
-
-
120
90
ns
ns
o
+25 C
7-436
Specifications CD4073BMS, CD4081BMS, CD4082BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
Transition Time
SYMBOL
CONDITIONS
VDD = 10V
NOTES
1, 2, 3
1, 2, 3
1, 2
TEMPERATURE
MIN
MAX
100
80
UNITS
ns
o
TTHL
TTLH
+25 C
-
-
-
o
VDD = 15V
Any Input
+25 C
ns
o
Input Capacitance
NOTES:
CIN
+25 C
7.5
pF
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
1, 4
TEMPERATURE
MIN
MAX
2.5
UNITS
o
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
VDD = 10V, ISS = -10µA
+25 C
-
-2.8
-
µA
V
o
N Threshold Voltage
VNTH
∆VTN
1, 4
+25 C
-0.2
±1
o
N Threshold Voltage
Delta
1, 4
+25 C
V
o
P Threshold Voltage
VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
1, 4
1, 4
+25 C
0.2
-
2.8
V
V
o
P Threshold Voltage
Delta
∆VTP
+25 C
±1
o
Functional
F
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
1
+25 C
VOH >
VDD/2
VOL <
VDD/2
V
o
Propagation Delay Time
TPHL
TPLH
1, 2, 3, 4
+25 C
-
1.35 x
ns
o
+25 C
Limit
o
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25 C limit.
4. Read and Record
O
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 C
PARAMETER
Supply Current - SSI
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
DELTA LIMIT
±0.1µA
IOL5
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
IOH5A
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
METHOD
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
Sample 5005
GROUP A SUBGROUPS
READ AND RECORD
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9, Deltas
1, 7, 9
Interim Test 3 (Post Burn-In)
PDA (Note 1)
IDD, IOL5, IOH5A
1, 7, 9, Deltas
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Final Test
Group A
7-437
Specifications CD4073BMS, CD4081BMS, CD4082BMS
TABLE 6. APPLICABLE SUBGROUPS (Continued)
MIL-STD-883
CONFORMANCE GROUP
METHOD
GROUP A SUBGROUPS
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
READ AND RECORD
Group B
Subgroup B-5
Subgroup B-6
Sample 5005
Sample 5005
Sample 5005
Subgroups 1, 2, 3, 9, 10, 11
Group D
1, 2, 3, 8A, 8B, 9
Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
MIL-STD-883
METHOD
CONFORMANCE GROUPS
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
PART NUMBER CD4073BMS
Static Burn-In 1
Note 1
6, 9, 10
6, 9, 10
-
1 - 5, 7, 8, 11 - 13
14
Static Burn-In 2
Note 1
7
7
7
1 - 5, 8, 11 - 14
14
Dynamic Burn-
In Note 1
6, 9, 10
1, 5, 8, 11 - 13
Irradiation
Note 2
6, 9, 10
1 - 5, 8, 11 - 14
PART NUMBER CD4081BMS
Static Burn-In 1
Note 1
3, 4, 10, 11
3, 4, 10, 11
-
1, 2, 5 - 9, 12, 13
14
Static Burn-In 2
Note 1
7
7
7
1, 2, 5, 6, 8, 9,
12 - 14
Dynamic Burn-
In Note 1
14
3, 4, 10, 11
1, 2, 5, 6, 8, 9, 12,
13
Irradiation
Note 2
3, 4, 10, 11
1, 2, 5, 6, 8, 9,
12 - 14
PART NUMBER CD4082BMS
Static Burn-In 1
Note 1
1, 6, 8, 13
1, 6, 8, 13
6, 8
2 - 5, 7, 9 - 12
14
Static Burn-In 2
Note 1
7
7
7
2 - 5, 9 - 12, 14
14
Dynamic Burn-
In Note 1
1, 3
2 - 5, 9 - 12
Irradiation
Note 2
1, 6, 8, 13
2 - 5, 9 - 12, 14
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
7-438
CD4073BMS, CD4081BMS, CD4082BMS
VDD
p
*
*
p
8 (5, 11)
1 (4, 12)
2 (3, 13)
n
p
n
p
p
p
p
*
p
VDD
9 (6, 10)
n
n
n
n
n
n
VSS
VSS
ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
FIGURE 1. SCHEMATIC DIAGRAM FOR CD4073BMS (1 OF 3 IDENTICAL GATES)
A
1 (4, 12)
J
B
2 (3, 13)
9 (6, 10)
C
8 (5, 11)
FIGURE 2. LOGIC DIAGRAM FOR CD4073BMS (1 OF 3 IDENTICAL GATES)
VDD
VDD
p
*
p
p
n
n
2 (5, 9, 12)
p
n
p
n
VSS
p
*
1 (6, 8, 13)
3 (4, 10, 11)
ALL INPUTS PROTECTED BY
n
*
n
CMOS PROTECTION NETWORK
VSS
FIGURE 3. SCHEMATIC DIAGRAM FOR CD4081BMS (1 OF 4 IDENTICAL GATES)
A
1 (6, 8, 13)
2 (5, 9, 12)
J
B
3 (4, 10, 11)
FIGURE 4. LOGIC DIAGRAM FOR CD4081BMS (1 OF 4 IDENTICAL GATES)
7-439
CD4073BMS, CD4081BMS, CD4082BMS
p
VDD
p
*
*
3 (11)
2 (12)
p
n
n
p
n
p
p
p
n
n
n
n
VSS
VDD
p
n
VSS
p
*
*
VDD
4 (10)
5 (9)
p
n
p
n
n
*
VSS
ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
VSS
FIGURE 5. SCHEMATIC DIAGRAM FOR CD4082BMS (1 OF 2 IDENTICAL GATES)
D
2 (12)
C
3 (11)
J
1 (13)
B
4 (10)
A
5 (9)
FIGURE 6. LOGIC DIAGRAM FOR CD4082BMS (1 OF 2 IDENTICAL GATES)
Typical Performance Characteristics
200
175
20
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VDD) = 15V
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VDD) = 15V
150
125
100
75
15
10V
10
5
10V
5V
5V
50
25
0
5
10
15
20
25
0
10
20 30
40
50
60 70
80 90
100
INPUT VOLTAGE (VIN) (V)
LOAD CAPACITANCE (CL) (pF)
FIGURE 7. TYPICAL VOLTAGE TRANSFER
CHARACTERISTICS
FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE
7-440
CD4073BMS, CD4081BMS, CD4082BMS
Typical Performance Characteristics (Continued)
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
15.0
12.5
10.0
7.5
30
25
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
20
15
10V
10V
5.0
10
5
2.5
5V
5V
0
5
10
15
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 9. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 10. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
0
-15
-10
-5
0
0
0
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-5
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-10
-15
-20
-25
-30
-5
-10V
-10V
-10
-15
-15V
-15V
FIGURE 11. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 12. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
105
AMBIENT TEMPERATURE (TA) = +25oC
8
AMBIENT TEMPERATURE (TA) = +25oC
6
4
SUPPLY VOLTAGE (VDD) = 15V
2
104
103
10V
10V
8
6
4
200
5V
2
SUPPLY VOLTAGE (VDD) = 5V
150
8
6
4
2
100
102
10
10V
5V
8
6
4
50
CL = 50pF
CL = 15pF
2
0
2
4 6 8
2
4
6 8
2
4
6 8
102
2
4 6 8
0
20
40
60
80
100
1
10
INPUT FREQUENCY (fI) (kHz)
103
104
LOAD CAPACITANCE (CL) (pF)
FIGURE 13. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
FIGURE 14. TYPICAL DYNAMIC POWER DISSIPATIONPER
GATE AS A FUNCTION OF FREQUENCY
7-441
CD4073BMS, CD4081BMS, CD4082BMS
Chip Dimensions and Pad Layouts
CD4081BMS
CD4082BMS
CD4073BMS
Dimensions in parentheses are in millimeters and are
derived from the basic inch dimensions as indicated.
-3
Grid graduations are in mils (10 inch)
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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