BB301M [RENESAS]

Built in Biasing Circuit MOS FET IC VHF RF Amplifier; 内置偏置电路MOS FET的IC甚高频射频放大器
BB301M
型号: BB301M
厂家: RENESAS TECHNOLOGY CORP    RENESAS TECHNOLOGY CORP
描述:

Built in Biasing Circuit MOS FET IC VHF RF Amplifier
内置偏置电路MOS FET的IC甚高频射频放大器

射频放大器
文件: 总8页 (文件大小:181K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
BB301M  
Built in Biasing Circuit MOS FET IC  
VHF RF Amplifier  
REJ03G0824-0300  
(Previous ADE-208-506A)  
Rev.3.00  
Aug.10.2005  
Features  
Built in Biasing Circuit; To reduce using parts cost & PC board space.  
Low noise characteristics;  
(NF = 1.3 dB typ. at f = 200 MHz)  
Withstanding to ESD;  
Built in ESD absorbing diode. Withstand up to 200V at C=200pF, Rs=0 conditions.  
Provide mini mold packages; MPAK-4(SOT-143Rmod)  
Outline  
RENESAS Package code: PLSP0004ZA-A  
(Package name: MPAK-4)  
2
1. Source  
2. Gate1  
3. Gate2  
4. Drain  
3
1
4
Notes:  
1. Marking is “AW–”.  
2. BB301M is individual type number of RENESAS BBFET.  
Rev.3.00 Aug 10, 2005 page 1 of 7  
BB301M  
Absolute Maximum Ratings  
(Ta = 25°C)  
Item  
Drain to source voltage  
Gate1 to source voltage  
Symbol  
VDS  
Ratings  
Unit  
6
V
V
VG1S  
+6  
–0  
±6  
Gate2 to source voltage  
Drain current  
VG2S  
ID  
V
mA  
mW  
°C  
25  
Channel power dissipation  
Channel temperature  
Storage temperature  
Pch  
Tch  
Tstg  
150  
150  
–55 to +150  
°C  
Electrical Characteristics  
(Ta = 25°C)  
Item  
Symbol  
Min  
6
Typ  
Max  
Unit  
V
Test conditions  
Drain to source breakdown voltage  
Gate1 to source breakdown voltage  
Gate2 to source breakdown voltage  
Gate1 to source cutoff current  
Gate2 to source cutoff current  
Gate1 to source cutoff voltage  
V(BR)DSS  
V(BR)G1SS  
V(BR)G2SS  
IG1SS  
ID = 200 µA, VG1S = VG2S = 0  
IG1 = +10 µA, VG2S = VDS = 0  
IG2 = ±10 µA, VG1S = VDS = 0  
VG1S = +5 V, VG2S = VDS = 0  
VG2S = ±5 V, VG1S = VDS = 0  
+6  
±6  
V
V
+100  
±100  
1.0  
nA  
nA  
V
IG2SS  
VG1S(off)  
0.4  
VDS = 5 V, VG2S = 4 V  
ID = 100 µA  
Gate2 to source cutoff voltage  
Drain current  
VG2S(off)  
ID(op)  
0.4  
10  
15  
15  
20  
1.0  
20  
V
VDS = 5 V, VG1S = 5 V  
ID = 100 µA  
mA  
mS  
VDS = 5 V, VG1 = 5 V  
VG2S = 4 V, RG = 100 kΩ  
Forward transfer admittance  
|yfs|  
VDS = 5 V, VG1 = 5 V, VG2S =4 V  
RG = 100 k, f = 1 kHz  
Input capacitance  
Output capacitance  
Reverse transfer capacitance  
Power gain  
Ciss  
Coss  
Crss  
PG  
2.2  
0.9  
3.0  
1.2  
3.9  
1.6  
0.04  
pF  
pF  
pF  
dB  
dB  
VDS = 5 V, VG1 = 5 V  
VG2S =4 V, RG = 100 kΩ  
f = 1 MHz  
0.018  
26  
22  
VDS = 5 V, VG1 = 5 V, VG2S =4 V  
RG = 100 k, f = 200 MHz  
Noise figure  
NF  
1.3  
1.9  
Rev.3.00 Aug 10, 2005 page 2 of 7  
BB301M  
Main Characteristics  
Test Circuit for Operating Items (ID(op) , |yfs|, Ciss, Coss, Crss, NF, PG)  
VG2  
VG1  
RG  
Gate 1  
Gate 2  
Drain  
Source  
A
ID  
Equivalent Circuit  
Gate 2  
Drain  
Source  
Gate 1  
Application Circuit  
AGC = 4 to 0.3 V  
VDS = 5 V  
V
RFC  
BBFET  
Output  
Input  
RG  
VGG = 5 V  
Rev.3.00 Aug 10, 2005 page 3 of 7  
BB301M  
Maximum Channel Power  
Dissipation Curve  
Typical Output Characteristics  
VG2S = 4 V  
30  
25  
20  
15  
10  
5
200  
150  
100  
50  
VG1 = VDS  
0
0
50  
100  
150  
200  
1
2
3
4
5
Ambient Temperature Ta (°C)  
Drain to Source Voltage VDS (V)  
Drain Current vs.  
Gate2 to Source Voltage  
Drain Current vs. Gate1 Voltage  
VDS = 5 V  
20  
16  
12  
8
25  
20  
15  
10  
5
R
G = 82 k  
4
VG2S = 1 V  
VDS = VG1 = 5 V  
0
0
1
2
3
4
5
1
2
3
4
5
Gate2 to Source Voltage VG2S (V)  
Gate1 Voltage VG1 (V)  
Drain Current vs. Gate1 Voltege  
VDS = 5 V  
Drain Current vs. Gate1 Voltege  
VDS = 5 V  
20  
16  
12  
8
20  
16  
12  
8
RG = 100 kΩ  
R
G = 150 kΩ  
3 V  
4 V  
2 V  
VG2S = 1 V  
4
4
VG2S = 1 V  
0
0
1
2
3
4
5
1
2
3
4
5
Gate1 Voltage VG1 (V)  
Gate1 Voltage VG1 (V)  
Rev.3.00 Aug 10, 2005 page 4 of 7  
BB301M  
Forward Transfer Admittance  
vs. Gate1 Voltage  
Forward Transfer Admittance  
vs. Gate1 Voltage  
30  
25  
20  
15  
10  
5
30  
25  
20  
15  
10  
5
VDS = 5 V  
VDS = 5 V  
RG = 82 k  
R
G = 100 kΩ  
f = 1 kHz  
f = 1 kHz  
2 V  
2 V  
VG2S = 1 V  
4
VG2S = 1 V  
4
0
0
1
2
3
5
1
2
3
5
Gate1 Voltage VG1 (V)  
Gate1 Voltage VG1 (V)  
Forward Transfer Admittance  
vs. Gate1 Voltage  
Power Gain vs. Gate Resistance  
30  
25  
20  
15  
10  
20  
16  
12  
8
VDS = 5 V  
RG = 150 kΩ  
f = 1 kHz  
2 V  
VDS = 5 V  
4
V
V
G1 = 5 V  
G2S = 4 V  
5
0
VG2S = 1 V  
4 5  
f = 200 MHz  
0
10  
20 50 100 200  
500 1000  
1
2
3
Gate1 Voltage VG1 (V)  
Gate Resistance RG (k)  
Noise Figure vs. Gate Resistance  
VDS = 5 V  
Power Gain vs. Drain Current  
4
3
2
30  
25  
20  
15  
10  
5
VG1= 5 V  
VG2S = 4 V  
f = 200 MHz  
VDS = 5 V  
V
V
G1 = 5 V  
G2S = 4 V  
1
0
RG = variable  
f = 200 MHz  
0
10  
20  
50 100 200  
500 1000  
5
10  
15  
20  
25  
30  
Gate Resistance RG (k)  
Drain Current ID (mA)  
Rev.3.00 Aug 10, 2005 page 5 of 7  
BB301M  
Drain Current vs. Gate Resistance  
Noise Figure vs. Drain Current  
VDS = 5 V  
4
3
2
1
30  
25  
20  
15  
10  
V
V
G1 = 5 V  
G2S = 4 V  
RG = variable  
f = 200 MHz  
VDS = 5 V  
V
V
G1 = 5 V  
G2S = 4 V  
5
0
0
5
10  
15  
20  
25  
10  
20  
50 100 200  
500 1000  
30  
Drain Current ID (mA)  
Gate Resistance RG (k)  
Input Capacitance vs.  
Gate2 to Source Voltage  
Gain Reduction vs.  
Gate2 to Source Voltage  
VDS = 5 V  
60  
50  
40  
30  
20  
10  
4
3
2
1
V
V
G1 = 5 V  
G2S = 4 V  
R
G = 100 k  
f = 200 MHz  
VDS = 5 V  
G1 = 5 V  
V
RG = 100 kΩ  
f = 1 MHz  
0
0
1
2
3
4
1
2
3
4
5
5
Gate2 to Source Voltage VG2S (V)  
Gate2 to Source Voltage VG2S (V)  
Rev.3.00 Aug 10, 2005 page 6 of 7  
BB301M  
Package Dimensions  
JEITA Package Code  
SC-61AA  
RENESAS Code  
PLSP0004ZA-A  
Package Name  
MASS[Typ.]  
0.013g  
MPAK-4 / MPAK-4V  
D
A
e
2
e
b
1
Q
c
B
B
E
HE  
Dimension in Millimeters  
Reference  
Symbol  
Min  
1.0  
0
Nom  
Max  
1.3  
0.1  
1.2  
A
A
A
A
1
2
3
L
L
P
L
1
1.0  
1.1  
0.25  
0.42  
0.62  
0.4  
A
A
A
3
b
0.35  
0.55  
0.5  
0.7  
b
b
1
2
3
x
S
A
M
e
2
e
b
b
0.6  
c
0.1  
0.13  
0.11  
0.15  
c
1
I1  
A
A
2
1
D
E
e
2.7  
3.1  
A
1.35  
1.5  
0.95  
0.85  
2.8  
1.65  
b
5
e
2
H
E
2.2  
3.0  
e
1
y
S
L
0.35  
0.15  
0.25  
0.75  
0.55  
0.65  
0.05  
0.05  
0.55  
0.75  
S
L
1
b
b1  
b3  
L
P
b
2
x
c1  
c
1
I1  
y
b
4
5
1
c
c
b
e
b
4
1.95  
0.3  
I1  
1.05  
A-A Section  
B-B Section  
Pattern of terminal position areas  
Q
Ordering Information  
Part Name  
Quantity  
Shipping Container  
φ 178 mm Reel, 8 mm Emboss Taping  
BB301MAW-TL-E  
3000  
Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of  
production before ordering the product.  
Rev.3.00 Aug 10, 2005 page 7 of 7  
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan  
Keep safety first in your circuit designs!  
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble  
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.  
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary  
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.  
Notes regarding these materials  
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's  
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.  
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,  
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.  
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publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is  
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product  
information before purchasing a product listed herein.  
The information described here may contain technical inaccuracies or typographical errors.  
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.  
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor  
home page (http://www.renesas.com).  
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to  
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes  
no responsibility for any damage, liability or other loss resulting from the information contained herein.  
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is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a  
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cannot be imported into a country other than the approved destination.  
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.  
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.  
RENESAS SALES OFFICES  
http://www.renesas.com  
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.  
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Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501  
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© 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.  
Colophon .3.0  

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