ACTS573KTR-02-T [RENESAS]

ACT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDFP20;
ACTS573KTR-02-T
型号: ACTS573KTR-02-T
厂家: RENESAS TECHNOLOGY CORP    RENESAS TECHNOLOGY CORP
描述:

ACT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDFP20

驱动 CD 输出元件 逻辑集成电路
文件: 总3页 (文件大小:48K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
ACTS573T  
Semiconductor  
Data Sheet  
January 1999  
File Number 4613  
Radiation Hardened Octal Three-State  
Transparent Latch  
Features  
• QML Class T, Per MIL-PRF-38535  
Harris’ Satellite Applications FlowTM (SAF) devices are fully  
tested and guaranteed to 100kRAD total dose. These QML  
Class T devices are processed to a standard flow intended  
to meet the cost and shorter lead-time needs of large  
volume satellite manufacturers, while maintaining a high  
level of reliability.  
• Radiation Performance  
5
- Gamma Dose (γ) 1 x 10 RAD(Si)  
- Latch-Up Free Under Any Conditions  
-10  
- Single Event Upset (SEU) Immunity: <1 x 10  
Errors/Bit/Day (Typ)  
2
- SEU LET Threshold . . . . . . . . . . . . .>100 MEV-cm /mg  
• 1.25 Micron Radiation Hardened SOS CMOS  
• Significant Power Reduction Compared to ALSTTL Logic  
• DC Operating Voltage Range. . . . . . . . . . . . 4.5V to 5.5V  
• Input Logic Levels  
The Harris ACTS573T is a Radiation Hardened Octal  
Transparent Latch with an active low output enable. The  
outputs are transparent to the inputs when the latch enable  
(LE) is High. When the latch goes low the data is latched.  
The output enable controls the three-state outputs. When  
the output enable pins (OE) are high the output is in a high  
impedance state. The latch operation is independent of the  
state of output enable.  
- V = 0.8V Max  
IL  
- V = VCC/2 Min  
IH  
• Fast Propagation Delay . . . . . . . . 18ns (Max), 12ns (Typ)  
Specifications  
Specifications for Rad Hard QML devices are controlled by  
the Defense Supply Center in Columbus (DSCC). The SMD  
numbers listed below must be used when ordering.  
Pinouts  
ACTS573T (SBDIP), CDIP2-T20  
TOP VIEW  
Detailed Electrical Specifications for the ACTS573T are  
contained in SMD 5962-96725. A “hot-link” is provided from  
our website for downloading.  
1
2
3
4
5
6
7
8
9
V
OE  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
20  
19  
CC  
Q0  
18 Q1  
17 Q2  
16 Q3  
15 Q4  
14 Q5  
13 Q6  
http://www.semi.harris.com/families/smdrh.htm  
Harris’ Quality Management Plan (QM Plan), listing all Class  
T screening operations, is also available on our website.  
http://www.semi.harris.com/quality/manuals.htm  
Ordering Information  
12  
Q7  
TEMP.  
GND 10  
11 LE  
ORDERING  
INFORMATION  
PART  
NUMBER  
RANGE  
( C)  
o
5962R9672502TRC  
ACTS573D/Sample-02  
5962R9672502TXC  
ACTS573K/Sample-02  
ACTS573DTR-02  
-55 to 125  
25  
ACTS573T (FLATPACK), CDFP4-F20  
TOP VIEW  
ACTS573D/Sample-02  
ACTS573KTR-02  
OE  
D0  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
-55 to 125  
25  
V
CC  
Q0  
Q1  
Q2  
Q3  
Q4  
Q5  
Q6  
ACTS573K/Sample-02  
D1  
D2  
NOTE: Minimum order quantity for -T is 1000 units  
Orders must be placed through Harris Sales or Rep Offices.  
D3  
D4  
D5  
D6  
D7  
Q7  
LE  
GND  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-800-4-HARRIS | Copyright © Harris Corporation 1999  
1
Satellite Applications Flow™ (SAF) is a trademark of Harris Corporation.  
ACTS573T  
Functional Diagram  
1 OF 8 IDENTICAL CIRCUITS  
VCC  
p
LE  
p
Dn  
n
OE  
LE  
LE  
p
Qn  
n
LE  
n
OE  
V
SS  
COMMON CONTROLS  
LE  
LE  
LE  
OE  
OE  
OE  
TRUTH TABLE  
OE  
L
LE  
DATA  
OUTPUT  
H
H
L
H
L
l
H
L
L
L
L
L
L
h
X
H
Z
H
X
NOTE: L = Low Logic Level, H = High Logic Level, X = Don’t Care, Z = High Impedance, l = Low Voltage Level Prior to High-to-Low Latch Enable  
Transition, h = High Voltage Level Prior to High-to-Low Latch Enable Transition.  
2
ACTS573T  
Die Characteristics  
DIE DIMENSIONS:  
PASSIVATION:  
Type: Silox (S O )  
(2600µm x 2600µm x 533µm ±51µm)  
102 x 102 x 21mils ±2mil  
i
2
Thickness: 8kÅ ±1kÅ  
METALLIZATION:  
Type: Al Si Cu  
WORST CASE CURRENT DENSITY:  
2
< 2.0e5 A/cm  
Thickness: 10kÅ ±2kÅ  
TRANSISTOR COUNT:  
SUBSTRATE POTENTIAL:  
Unbiased (Silicon on Sapphire)  
Bond Pad #20 First  
190  
PROCESS:  
CMOS SOS  
BACKSIDE FINISH:  
Sapphire  
Metallization Mask Layout  
ACTS573T  
(17) Q2  
(16) Q3  
NC  
D2 (4)  
D3 (5)  
NC  
NC  
NC  
D4 (6)  
D5 (7)  
(15) Q4  
(14) Q5  
All Harris Semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.  
Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specifications at any time  
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is believed to be accurate  
and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may  
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries.  
For information regarding Harris Semiconductor and its products, call 1-800-4-HARRIS or see web site http://www.semi.harris.com  
3

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