3SK295 [RENESAS]
Silicon N-Channel Dual Gate MOS FET; 硅N沟道双栅MOS FET![3SK295](http://pdffile.icpdf.com/pdf1/p00123/img/icpdf/3SK295ZQ-TL-E_676941_icpdf.jpg)
型号: | 3SK295 |
厂家: | ![]() |
描述: | Silicon N-Channel Dual Gate MOS FET |
文件: | 总7页 (文件大小:89K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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3SK295
Silicon N-Channel Dual Gate MOS FET
REJ03G0814-0300
(Previous ADE-208-387A)
Rev.3.00
Aug. 10, 2005
Application
•
UHF RF amplifier
Features
•
Low noise figure.
NF = 2.0 dB typ. at f = 900 MHz
Capable of low voltage operation
•
Outline
RENESAS Package code: PLSP0004ZA-A
(Package name: MPAK-4)
2
1. Source
2. Gate1
3. Gate2
4. Drain
3
1
4
Note: Marking is “ZQ–”
Attention:
This device is very sensitive to electro static discharge.
It is recommended to adopt appropriate cautions when handling this transistor.
Rev.3.00, Aug 10.2005, page 1 of 6
3SK295
Absolute Maximum Ratings
(Ta = 25°C)
Item
Drain to source voltage
Gate 1 to source voltage
Gate 2 to source voltage
Drain current
Symbol
VDS
Ratings
Unit
V
12
VG1S
VG2S
ID
±8
±8
V
V
25
mA
mW
°C
°C
Channel power dissipation
Channel temperature
Storage temperature
Pch
150
Tch
150
Tstg
–55 to +150
Electrical Characteristics
(Ta = 25°C)
Item
Symbol
Min
Typ
Max
Unit
Test conditions
Drain to source breakdown voltage
V(BR)DSX
12
—
—
V
ID = 200 µA , VG1S = –3 V,
VG2S = –3 V
Gate 1 to source breakdown voltage V(BR)G1SS
Gate 2 to source breakdown voltage V(BR) G2SS
±8
±8
—
—
—
—
—
—
—
—
V
V
IG1 = ±10 µA, VG2S = VDS = 0
IG2 = ±10 µA, VG1S = VDS = 0
VG1S = ±6 V, VG2S = VDS = 0
VG2S = ±6 V, VG1S = VDS = 0
Gate 1 cutoff current
Gate 2 cutoff current
Drain current
IG1SS
IG2SS
IDS(on)
±100
±100
10
nA
nA
mA
—
0.5
VDS = 6 V, VG1S = 0.5 V,
VG2S = 3 V
Gate 1 to source cutoff voltage
Gate 2 to source cutoff voltage
Forward transfer admittance
VG1S(off)
VG2S(off)
|yfs|
–0.5
0
—
—
+0.5
+1.0
—
V
V
VDS = 10 V, VG2S = 3 V,
ID = 100 µA
VDS = 10 V, VG1S = 3 V,
ID = 100 µA
16
20.8
mS
VDS = 6 V, VG2S = 3 V,
ID = 10 mA, f = 1 kHz
Input capacitance
Output capacitance
Reverse transfer capacitance
Power gain
Ciss
Coss
Crss
PG
1.2
0.6
—
1.5
0.9
2.2
1.2
0.03
—
pF
pF
pF
dB
dB
VDS = 6 V, VG2S = 3 V,
ID = 10 mA, f = 1 MHz
0.01
19.5
2.0
16
—
VDS = 4 V, VG2S = 3 V,
ID = 10 mA, f = 900 MHz
Noise figure
NF
3
Rev.3.00, Aug 10.2005, page 2 of 6
3SK295
Main Characteristics
Maximum Channel Power
Dissipation Curve
Typical Output Characteristics
20
16
12
8
200
150
100
50
Pulse test
VG2S = 3 V
1.2 V
1.0 V
0.8 V
0.6 V
4
VG1S = 0.4 V
0
2
4
6
8
10
0
50
100
150
200
Drain to Source Voltage VDS (V)
Ambient Temperature Ta (°C)
Drain Current vs. Gate1 to Source Voltage
20
Drain Current vs. Gate2 to Source Voltage
20
2.0 V
VDS = 6 V
3.0 V
VDS = 6 V
2.0 V
1.5 V
Pulse test
Pulse test
2.5 V
16
12
8
16
12
8
1.5 V
1.0 V
1.0 V
VG1S = 0.5 V
4
4
VG2S = 0.5 V
0
0
1
2
3
4
5
1
2
3
4
5
Gate1 to Source Voltage VG1S (V)
Gate2 to Source Voltage VG2S (V)
Forward Transfer Admittance vs.
Gate1 to Source Voltage
Power Gain vs. Drain Current
25
20
15
10
30
24
18
12
6
VDS = 6 V
f = 1 kHz
VG2S = 3.0 V
2.5 V
2.0 V
1.5 V
VDS = 4 V
5
0
1.0 V
0.5 V
VG2S = 3 V
f = 900 MHz
0
2.0
20
0.4
0.8
1.2
1.6
1
2
5
10
Gate1 to Source Voltage VG1S (V)
Drain Current ID (mA)
Rev.3.00, Aug 10.2005, page 3 of 6
3SK295
Noise Figure vs. Drain Current
VDS = 4 V
Power Gain vs. Drain to Source Voltage
25
5
4
3
2
V
G2S = 3 V
20
15
10
5
f = 900 MHz
VG2S = 3 V
D = 10 mA
1
0
I
f = 900 MHz
0
20
10
1
2
5
10
2
4
6 8
Drain Current ID (mA)
Drain to Source Voltage VDS (V)
Noise Figure vs. Drain to Source Voltage
5
4
3
2
VG2S = 3 V
D = 10 mA
1
I
f = 900 MHz
0
10
2
4
6 8
Drain to Source Voltage VDS (V)
Rev.3.00, Aug 10.2005, page 4 of 6
3SK295
S11 Parameter vs. Frequency
S21 Parameter vs. Frequency
Scale: 0.5 / div.
1
.8
90°
1.5
.6
60°
120°
2
.4
3
4
30°
150°
.2
5
10
.2
.4 .6 .8 1.0 1.5 2 3 4 5 10
0
180°
0°
–10
–5
–4
–.2
–30°
–150°
–3
–.4
–2
–60°
–.6
–120°
–1.5
–.8
–1
–90°
Condition:
V
I
= 4 V, V
= 10 mA, Zo = 50 Ω
= 3 V
G2S
Condition:
V
I
= 4 V, V = 3 V
= 10 mA, Zo = 50 Ω
DS
DS
G2S
D
D
100 to 1000 MHz (50 MHz step)
100 to 1000 MHz (50 MHz step)
S12 Parameter vs. Frequency
S22 Parameter vs. Frequency
Scale: 0.002/ div.
90°
1
.8
1.5
60°
120°
.6
2
.4
3
30°
150°
4
5
.2
0
10
.2
.4 .6 .8 1.0 1.5 2 3 4 5 10
180°
0°
–10
–5
–4
–.2
–30°
–150°
–3
–.4
–2
–60°
–120°
–.6
–1.5
–.8
–90°
–1
Condition:
V
I
= 4 V, V = 3 V
= 10 mA, Zo = 50 Ω
Condition:
V
I
= 4 V, V
= 10 mA, Zo = 50 Ω
= 3 V
G2S
DS
G2S
DS
D
D
100 to 1000 MHz (50 MHz step)
100 to 1000 MHz (50 MHz step)
Rev.3.00, Aug 10.2005, page 5 of 6
3SK295
Package Dimensions
JEITA Package Code
SC-61AA
RENESAS Code
Package Name
MASS[Typ.]
0.013g
PLSP0004ZA-A
MPAK-4 / MPAK-4V
D
A
e
2
e
b
1
Q
c
B
B
E
HE
Dimension in Millimeters
Reference
Symbol
Min
1.0
0
Nom
Max
1.3
0.1
1.2
A
A
A
A
1
2
3
L
L
P
L
1
1.0
1.1
0.25
0.42
0.62
0.4
A
A
A
3
b
0.35
0.55
0.5
0.7
b
b
1
2
3
x
S
A
M
e
2
e
b
b
0.6
c
0.1
0.13
0.11
0.15
c
1
I1
A
A
2
1
D
E
e
2.7
3.1
A
1.35
1.5
0.95
0.85
2.8
1.65
b
5
e
2
H
E
2.2
3.0
e
1
y
S
L
0.35
0.15
0.25
0.75
0.55
0.65
0.05
0.05
0.55
0.75
S
L
1
b
b1
b3
L
P
b
2
x
c1
c
1
I1
y
b
4
5
1
c
c
b
e
b
4
1.95
0.3
I1
1.05
A-A Section
B-B Section
Pattern of terminal position areas
Q
Ordering Information
Part Name
Quantity
Shipping Container
φ178 mm Reel, 8 mm Emboss Taping
3SK295ZQ-TL-E
3000
Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of
production before ordering the product.
Rev.3.00, Aug 10.2005, page 6 of 6
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
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application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
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Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
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RENESAS SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
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Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
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© 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .3.0
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