3850 [RENESAS]
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER; 单片8位CMOS微机
| 型号： | 3850 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 文件： | 总101页 (文件大小：1318K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀThis data sheet describes Spec. H and Spec. A of 3850 Group. The header of each page shows which specification is explained in
the page. The page explaining about both specifications shows the header of “Spec. H/A”.
3850 Group (Spec.H/A)
REJ03B0036-0301Z
Rev.3.01
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
2003.06.20
3850 Group (Spec.H)
ꢀClock generating circuit..................................... Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
ꢀPower source voltage
DESCRIPTION
The 3850 group (spec. H) is the 8-bit microcomputer based on the
740 family core technology.
In high-speed mode .................................................. 4.0 to 5.5 V
(at 8 MHz oscillation frequency)
The 3850 group (spec. H) is designed for the household products
and office automation equipment and includes serial I/O functions,
8-bit timer, and A-D converter.
In middle-speed mode............................................... 2.7 to 5.5 V
(at 8 MHz oscillation frequency)
In low-speed mode .................................................... 2.7 to 5.5 V
(at 32 kHz oscillation frequency)
FEATURES
ꢀBasic machine-language instructions ...................................... 71
ꢀMinimum instruction execution time .................................. 0.5 µs
(at 8 MHz oscillation frequency)
ꢀPower dissipation
In high-speed mode ..........................................................34 mW
(at 8 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode
ꢀMemory size
ROM ................................................................... 8K to 32K bytes
RAM ................................................................. 512 to 1024 bytes
ꢀProgrammable input/output ports ............................................ 34
ꢀInterrupts ................................................. 15 sources, 14 vectors
ꢀTimers ............................................................................. 8-bit ꢀ 4
ꢀSerial I/O1 .................... 8-bit ꢀ 1(UART or Clock-synchronized)
ꢀSerial I/O2 ................................... 8-bit ꢀ 1(Clock-synchronized)
ꢀPWM ............................................................................... 8-bit ꢀ 1
ꢀA-D converter ............................................... 10-bit ꢀ 5 channels
ꢀWatchdog timer ............................................................ 16-bit ꢀ 1
Except M38507F8FP/SP................................................... 60 µW
M38507F8FP/SP ............................................................. 450 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
ꢀOperating temperature range....................................–20 to 85°C
APPLICATION
Office automation equipment, FA equipment, Household products,
Consumer electronics, etc.
PIN CONFIGURATION (TOP VIEW)
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P3
P3
P3
P3
P3
0
1
2
3
4
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
V
CC
V
REF
AVSS
/PWM
2/SCMP2
/INT
/INT
/CNTR
/SRDY1
/SCLK1
/TxD
3
4
P4
4
/INT
/INT
P4
P4
P4
/CNTR
P2
P2
P2
3
5
P4
3
2
1
0
1
6
P0
P0
P0
P0
0/SIN2
1
7
1
2
3
/SOUT2
/SCLK2
/SRDY2
0
8
P2
7
0
9
6
10
11
12
13
14
15
16
17
18
19
20
21
P0
P0
P0
P0
4
5
5
6
7
4
/RxD
P2
P2
3
2
P1
P1
P1
P1
P1
P1
P1
P1
0
1
2
3
4
5
6
7
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
0
1
2
3
4
5
6
7
)
)
)
)
)
)
)
)
CNVSS
P2 /XCIN
P2 /XCOUT
V
PP
1
0
RESET
X
IN
OUT
SS
X
V
: Flash memory version
Package type : FP ........................... 42P2R-A/E (42-pin plastic-molded SSOP)
Package type : SP ........................... 42P4B (42-pin plastic-molded SDIP)
Fig. 1 M38503MXH-XXXFP/SP pin configuration (spec. H)
Rev.3.01 2003.06.20 page 1 of 98
1
3850 Group (Spec.A)
ꢀClock generating circuit..................................... Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
ꢀPower source voltage
DESCRIPTION
The 3850 group (spec. A) is the 8-bit microcomputer based on the
740 family core technology.
In high-speed mode .................................................. 4.0 to 5.5 V
(at 12.5 MHz oscillation frequency)
The 3850 group (spec. A) is designed for the household products
and office automation equipment and includes serial I/O functions,
8-bit timer, and A-D converter.
In high-speed mode .................................................. 2.7 to 5.5 V
(at 6 MHz oscillation frequency)
In middle-speed mode............................................... 2.7 to 5.5 V
(at 12.5 MHz oscillation frequency)
FEATURES
ꢀBasic machine-language instructions ...................................... 71
ꢀMinimum instruction execution time ................................ 0.32 µs
(at 12.5 MHz oscillation frequency)
In low-speed mode .................................................... 2.7 to 5.5 V
(at 32 kHz oscillation frequency)
ꢀPower dissipation
ꢀMemory size
In high-speed mode
ROM ................................................................... 8K to 16K bytes
RAM .............................................................................. 512 bytes
ꢀProgrammable input/output ports ............................................ 34
ꢀOn-chip software pull-up resistor
Except M38507F8FP/SP................................................ 32.5mW
M38507F8FP/SP ............................................................ 37.5mW
(at 12.5 MHz oscillation frequency, at 5 V power source voltage)
In low-speed mode
ꢀInterrupts ................................................. 15 sources, 14 vectors
ꢀTimers ............................................................................. 8-bit ꢀ 4
ꢀSerial I/O1 .................... 8-bit ꢀ 1(UART or Clock-synchronized)
ꢀSerial I/O2 ................................... 8-bit ꢀ 1(Clock-synchronized)
ꢀPWM ............................................................................... 8-bit ꢀ 1
ꢀA-D converter ............................................... 10-bit ꢀ 9 channels
ꢀWatchdog timer ............................................................ 16-bit ꢀ 1
Except M38507F8FP/SP................................................... 60 µW
M38507F8FP/SP ............................................................. 450 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
ꢀOperating temperature range....................................–20 to 85°C
APPLICATION
Office automation equipment, FA equipment, Household products,
Consumer electronics, etc.
PIN CONFIGURATION (TOP VIEW)
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P3
P3
P3
P3
P3
0
1
2
3
4
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
V
CC
V
REF
AVSS
/PWM
2/SCMP2
/INT
/INT
/CNTR
/SRDY1
/SCLK1
/TxD
3
4
P4
4
/INT
/INT
P4
P4
P4
/CNTR
P2
P2
P2
3
5
P4
3
2
1
0
1
6
P0
P0
P0
P0
0/SIN2
1
7
1
2
3
/SOUT2
/SCLK2
/SRDY2
/AN
/AN
0
8
P2
7
0
9
6
10
11
12
13
14
15
16
17
18
19
20
21
P04
5
5
P05
6
4
/RxD
P2
P2
P0
6
/AN
7
3
2
P07
/AN
8
P1
P1
P1
P1
P1
P1
P1
P1
0
1
2
3
4
5
6
7
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
0
1
2
3
4
5
6
7
)
)
)
)
)
)
)
)
CNVSS
P2 /XCIN
P2 /XCOUT
V
PP
1
0
RESET
X
IN
OUT
SS
X
V
: Flash memory version
Package type : FP ........................... 42P2R-A/E (42-pin plastic-molded SSOP)
Package type : SP ........................... 42P4B (42-pin plastic-molded SDIP)
Fig. 2 M38503MXA-XXXFP/SP pin configuration (spec. A)
Rev.3.01 2003.06.20 page 2 of 98
3850 Group (Spec.H)
FUNCTIONAL BLOCK
Fig. 3 Functional block diagram (spec. H)
Rev.3.01 2003.06.20 page 3 of 98
3850 Group (Spec.A)
Fig. 4 Functional block diagram (spec. A)
Rev.3.01 2003.06.20 page 4 of 98
3850 Group (Spec.H)
Table 1 Pin description (spec. H)
Functions
Pin
VCC, VSS
CNVSS
Name
Power source
CNVSS input
Reset input
Clock input
Function except a port function
•Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss.
•This pin controls the operation mode of the chip.
•Normally connected to VSS.
•Reset input pin for active “L”.
RESET
XIN
•Input and output pins for the clock generating circuit.
•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT
pin open.
XOUT
Clock output
•8-bit CMOS I/O port.
P00/SIN2
• Serial I/O2 function pin
•I/O direction register allows each pin to be individually
programmed as either input or output.
P01/SOUT2
P02/SCLK2
P03/SRDY2
P04–P07
I/O port P0
I/O port P1
•CMOS compatible input level.
•CMOS 3-state output structure.
•P10 to P17 (8 bits) are enabled to output large current for LED drive.
P10–P17
P20/XCOUT
P21/XCIN
P22
• Sub-clock generating circuit I/O
pins (connect a resonator)
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•CMOS compatible input level.
P23
I/O port P2
•P20, P21, P24 to P27: CMOS3-state output structure.
•P22, P23: N-channel open-drain structure.
• Serial I/O1 function pin
P24/RxD
P25/TxD
P26/SCLK1
• Serial I/O1 function pin/
Timer X function pin
P27/CNTR0/
SRDY1
•8-bit CMOS I/O port with the same function as port P0.
•CMOS compatible input level.
• A-D converter input pin
P30/AN0–
I/O port P3
I/O port P4
P34/AN4
•CMOS 3-state output structure.
P40/CNTR1
•8-bit CMOS I/O port with the same function as port P0.
•CMOS compatible input level.
• Timer Y function pin
• Interrupt input pins
P41/INT0
P42/INT1
•CMOS 3-state output structure.
• Interrupt input pin
• SCMP2 output pin
• Interrupt input pin
• PWM output pin
P43/INT2/SCMP2
P44/INT3/PWM
Rev.3.01 2003.06.20 page 5 of 98
3850 Group (Spec.A)
Table 2 Pin description (spec. A)
Functions
Pin
VCC, VSS
CNVSS
Name
Power source
CNVSS input
Reset input
Clock input
Function except a port function
•Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss.
•This pin controls the operation mode of the chip.
•Normally connected to VSS.
•Reset input pin for active “L”.
RESET
XIN
•Input and output pins for the clock generating circuit.
•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT
pin open.
XOUT
Clock output
•8-bit CMOS I/O port.
P00/SIN2
• Serial I/O2 function pin
• A-D converter input pin
•I/O direction register allows each pin to be individually
programmed as either input or output.
P01/SOUT2
P02/SCLK2
P03/SRDY2
I/O port P0
I/O port P1
•CMOS compatible input level.
•CMOS 3-state output structure.
•Pull-up control is enabled in a byte unit.
P04/AN5–P07/AN8
P10–P17
•P10 to P17 (8 bits) are enabled to output large current
for LED drive.
P20/XCOUT
P21/XCIN
P22
• Sub-clock generating circuit I/O
pins (connect a resonator)
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•CMOS compatible input level.
P23
I/O port P2
•P20, P21, P24 to P27: CMOS3-state output structure.
•P22, P23: N-channel open-drain structure.
P24/RxD
P25/TxD
P26/SCLK1
• Serial I/O1 function pin
•Pull-up control of P20, P21, P24–P27 is enabled in a
byte unit.
P27/CNTR0/
SRDY1
• Serial I/O1 function pin/
Timer X function pin
P30/AN0–
•8-bit CMOS I/O port with the same function as port P0.
•CMOS compatible input level.
• A-D converter input pin
P34/AN4
I/O port P3
•CMOS 3-state output structure.
•Pull-up control is enabled in a bit unit.
•8-bit CMOS I/O port with the same function as port P0.
•CMOS compatible input level.
• Timer Y function pin
• Interrupt input pins
P40/CNTR1
P41/INT0
P42/INT1
•CMOS 3-state output structure.
•Pull-up control is enabled in a bit unit.
I/O port P4
• Interrupt input pin
• SCMP2 output pin
• Interrupt input pin
• PWM output pin
P43/INT2/SCMP2
P44/INT3/PWM
Rev.3.01 2003.06.20 page 6 of 98
3850 Group (Spec.H/A)
PART NUMBERING
Product name
M3850 3
M
4
A– XXX SP
Package type
SP : 42P4B
FP : 42P2R-A/E
SS : 42S1B-A
ROM number
Omitted in One Time PROM version shipped in blank,
EPROM version, and flash memory version.
– : standard
Omitted in One Time PROM version shipped in blank, EPROM
version, and flash memory version.
H–: Partial specification changed version
A–: High-speed version
ROM/PROM/Flash memory size
: 4096 bytes
: 8192 bytes
: 12288 bytes
: 16384 bytes
: 20480 bytes
: 24576 bytes
: 28672 bytes
: 32768 bytes
9: 36864 bytes
A: 40960 bytes
B: 45056 bytes
C: 49152 bytes
D: 53248 bytes
E: 57344 bytes
F: 61440 bytes
1
2
3
4
5
6
7
8
The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they
cannot be used as a user’s ROM area.
However, they can be programmed or erased in the flash memory version,
so that the users can use them.
Memory type
M : Mask ROM version
E : EPROM or One Time PROM version
F : Flash memory version
RAM size
5: 768 bytes
6: 896 bytes
7: 1024 bytes
8: 1536 bytes
9: 2048 bytes
0
1
2
3
4
: 192 bytes
: 256 bytes
: 384 bytes
: 512 bytes
: 640 bytes
Fig. 5 Part numbering
Rev.3.01 2003.06.20 page 7 of 98
3850 Group (Spec.H/A)
GROUP EXPANSION
Renesas Technology plans to expand the 3850 group (spec. H/A)
Packages
as follows.
42P4B ......................................... 42-pin shrink plastic-molded DIP
42P2R-A/E ........................................... 42-pin plastic-molded SOP
42S1B-A .................. 42-pin shrink ceramic DIP (EPROM version)
Memory Type
Support for mask ROM, One Time PROM, and flash memory ver-
sions.
Memory Size
Flash memory size ......................................................... 32 K bytes
Mask ROM size ................................... 8 K to 32 K bytes (spec. H)
8 K to 16 K bytes (spec. A)
RAM size ...............................................512 to 1 K bytes (spec. H)
512 bytes (spec. A)
Memory Expansion Plan
ROM size (bytes)
ROM
exteranal
Mass production
32K
M38507M8/F8
28K
24K
20K
16K
12K
8K
Mass production
M38504M6/E6
Mass production
M38503M4H
M38503M4A
Mass production
Mass production
M38503M2H
M38503M2A
Mass production
384
512
640
768
896
1024
1152
1280
1408
1536
2048
RAM size (bytes)
Fig. 6 Memory expansion plan
Rev.3.01 2003.06.20 page 8 of 98
3850 Group (Spec.H/A)
Currently planning products are listed below.
Table 3 Support products (spec. H)
ROM size (bytes)
Product name
RAM size (bytes)
Package
Remarks
ROM size for User in (
)
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
M38503M2H-XXXSP
M38503M2H-XXXFP
M38503M4H-XXXSP
M38503M4H-XXXFP
M38504M6-XXXSP
M38504E6-XXXSP
M38504E6SP
42P4B
42P2R-A/E
42P4B
8192
(8062)
512
512
16384
(16254)
42P2R-A/E
One Time PROM version
One Time PROM version (blank)
EPROM version
424P4B
42S1B-A
24576
(24446)
M38504E6SS
640
Mask ROM version
M38504M6-XXXFP
M38504E6-XXXFP
M38504E6FP
One Time PROM version
One Time PROM version (blank)
Mask ROM version
42P2R-A/E
M38507M8-XXXSP
M38507M8-XXXFP
M38507F8SP
42P4B
42P2R-A/E
42P4B
Mask ROM version
32768
(32638)
1024
Flash memory version
Flash memory version
M38507F8FP
42P2R-A/E
Table 4 Support products (spec. A)
ROM size (bytes)
Product name
RAM size (bytes)
512
Package
Remarks
ROM size for User in (
)
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Flash memory version
Flash memory version
M38503M2A-XXXSP
M38503M2A-XXXFP
M38503M4A-XXXSP
M38503M4A-XXXFP
M38507F8SP
42P4B
42P2R-A/E
42P4B
8192
(8062)
16384
(16254)
512
42P2R-A/E
42P4B
1024
32768
M38507F8FP
42P2R-A/E
Table 5 Differences among 3850 group (standard), 3850 group (spec. H), and 3850 group (spec. A)
3850 group (spec. H)
3850 group (spec. A)
3850 group (standard)
1: Serial I/O
2: Serial I/O1 (UART or Clock-synchronized) 2: Serial I/O1 (UART or Clock-synchronized)
Serial I/O
Serial I/O2 (Clock-synchronized)
Serviceable in low-speed mode
Serial I/O2 (Clock-synchronized)
Serviceable in low-speed mode
(UART or Clock-synchronized)
Unserviceable in low-speed mode
Analog channel............................. 5
5: P13–P17
A-D converter
Analog channel................................ 5 Analog channel................................ 9
8: P10–P17
8: P10–P17
Large current port
Software pull-up
resistor
Not available
Built-in (Port P0–P4)
Not available
8 MHz
12.5 MHz
Maximum operating
frequency
8 MHz
(3) Do not write any data to the reserved area and the reserved
bit. (Do not change the contents after reset.)
Notes on differences among 3850 group
(standard), 3850 group (spec. H), and 3850
group (spec. A)
(4) Fix bit 3 of the CPU mode register to “1”.
(5) Be sure to perform the termination of unused pins.
(1) The absolute maximum ratings of 3850 group (spec. H/A) is
smaller than that of 3850 group (standard).
•Power source voltage Vcc = –0.3 to 6.5 V
•CNVss input voltage VI = –0.3 to Vcc +0.3 V
(2) The oscillation circuit constants of XIN-XOUT, XCIN-XCOUT may
be some differences among 3850 group (standard), 3850
group (spec. H), and 3850 group (spec. A).
Rev.3.01 2003.06.20 page 9 of 98
3850 Group (Spec.H/A)
FUNCTIONAL DESCRIPTION
[Stack Pointer (S)]
CENTRAL PROCESSING UNIT (CPU)
The 3850 group (spec. H/A) uses the standard 740 Family instruc-
tion set. Refer to the table of 740 Family addressing modes and
machine instructions or the 740 Family Software Manual for de-
tails on the instruction set.
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack ad-
dress are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “0016”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“0116”.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 8.
Store registers other than those described in Figure 8 with pro-
gram when the user needs them during interrupts or subroutine
calls.
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
Accumulator
b0
b0
b0
b0
b0
b7
X
Index register X
Index register Y
b7
Y
b7
S
Stack pointer
b15
b7
PC
H
PC
L
Program counter
b7
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 7 740 Family CPU register structure
Rev.3.01 2003.06.20 page 10 of 98
3850 Group (Spec.H/A)
On-going Routine
Execute JSR
Interrupt request
(Note)
M (S) (PC
(S) (S) – 1
M (S) (PC
H
)
Push return address
on stack
M (S) (PC
(S) (S) – 1
M (S) (PC
H)
L
)
(S) (S) – 1
M (S) (PS)
(S) (S) – 1
Push return address
on stack
Push contents of processor
status register on stack
L
)
(S) (S)– 1
Subroutine
Interrupt
Service Routine
I Flag is set from “0” to “1”
Execute RTS
(S) (S) + 1
Fetch the jump vector
Execute RTI
(S) (S) + 1
POP return
address from stack
POP contents of
processor status
register from stack
(PC
(S) (S) + 1
(PC M (S)
L)
M (S)
(PS)
(S) (S) + 1
(PC M (S)
(S) (S) + 1
(PC M (S)
M (S)
H)
L)
POP return
address
from stack
H)
Note: Condition for acceptance of an interrupt
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 8 Register push and pop at interrupt generation and subroutine call
Table 6 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PHP
PLA
PLP
Processor status register
Rev.3.01 2003.06.20 page 11 of 98
3850 Group (Spec.H/A)
•Bit 4: Break flag (B)
[Processor status register (PS)]
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera-
tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
Table 7 Set and clear instructions of each bit of processor status register
C flag
Z flag
I flag
D flag
B flag
T flag
V flag
_
N flag
_
_
_
_
_
_
Set instruction
SEC
CLC
SEI
CLI
SED
CLD
SET
CLT
Clear instruction
CLV
Rev.3.01 2003.06.20 page 12 of 98
3850 Group (Spec.H/A)
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, etc.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
1
(
CPUM : address 003B16)
Processor mode bits
b1 b0
0
0
1
1
0 : Single-chip mode
1 :
0 : Not available
1 :
Stack page selection bit
0 : 0 page
1 : 1 page
Fix this bit to “1”.
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
0
0
1
1
0 : φ = f(XIN)/2 (high-speed mode)
1 : φ = f(XIN)/8 (middle-speed mode)
0 : φ = f(XCIN)/2 (low-speed mode)
1 : Not available
Fig. 9 Structure of CPU mode register
Rev.3.01 2003.06.20 page 13 of 98
3850 Group (Spec.H/A)
MEMORY
Zero Page
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains
control registers such as I/O ports and timers.
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
Special Page
RAM
Access to this area with only 2 bytes is possible in the special
RAM is used for data storage and for stack area of subroutine
page addressing mode.
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area
Address
XXXX16
RAM size
(bytes)
000016
SFR area
192
256
384
512
640
768
896
1024
1536
2048
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
Zero page
004016
010016
RAM
XXXX16
Not used
0FF016
SFR area (Note)
0FFF16
Not used
YYYY16
ROM area
Reserved ROM area
(128 bytes)
Address
YYYY16
Address
ZZZZ16
ROM size
(bytes)
ZZZZ16
4096
8192
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
ROM
FF0016
FFDC16
Special page
Interrupt vector area
FFFE16
Reserved ROM area
FFFF16
Note: Flash memory version only
Fig. 10 Memory map diagram
Rev.3.01 2003.06.20 page 14 of 98
3850 Group (Spec.H)
Port P0 (P0)
000016
Prescaler 12 (PRE12)
Timer 1 (T1)
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
Port P0 direction register (P0D)
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
Port P1 (P1)
Timer 2 (T2)
Port P1 direction register (P1D)
Port P2 (P2)
Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Port P2 direction register (P2D)
Port P3 (P3)
Prescaler Y (PREY)
Timer Y (TY)
Port P3 direction register (P3D)
Port P4 (P4)
Timer count source selection register (TCSS)
Port P4 direction register (P4D)
002B16 Reserved ꢀ
Reserved ꢀ
002C16
002D16 Reserved ꢀ
002E16 Reserved ꢀ
002F16 Reserved ꢀ
003016 Reserved ꢀ
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Reserved ꢀ
Reserved ꢀ
001316 Reserved ꢀ
001416 Reserved ꢀ
A-D control register (ADCON)
A-D conversion low-order register (ADL)
A-D conversion high-order register (ADH)
Serial I/O2 control register 1 (SIO2CON1)
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
Serial I/O2 control register 2 (SIO2CON2)
Serial I/O2 register (SIO2)
Reserved ꢀ
Transmit/Receive buffer register (TB/RB)
Serial I/O1 status register (SIOSTS)
Serial I/O1 control register (SIOCON)
UART control register (UARTCON)
MISRG
Watchdog timer control register (WDTCON)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Baud rate generator (BRG)
PWM control register (PWMCON)
PWM prescaler (PREPWM)
PWM register (PWM)
Flash memory control register (FMCR)
0FFE16
ꢀ Reserved : Do not write any data to this addresses, because these areas are reserved.
Fig. 11 Memory map of special function register (SFR) (spec. H)
Rev.3.01 2003.06.20 page 15 of 98
3850 Group (Spec.A)
Port P0 (P0)
000016
Prescaler 12 (PRE12)
Timer 1 (T1)
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
Port P0 direction register (P0D)
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
Port P1 (P1)
Timer 2 (T2)
Port P1 direction register (P1D)
Port P2 (P2)
Timer XY mode register (TM)
Prescaler X (PREX)
Port P2 direction register (P2D)
Port P3 (P3)
Timer X (TX)
Prescaler Y (PREY)
Port P3 direction register (P3D)
Port P4 (P4)
Timer Y (TY)
Timer count source selection register (TCSS)
Port P4 direction register (P4D)
Reserved ꢀ
Reserved ꢀ
002D16 Reserved ꢀ
002E16 Reserved ꢀ
002F16
003016
Reserved ꢀ
Reserved ꢀ
003116 Reserved ꢀ
003216
Port P0, P1, P2 pull-up control register (PULL012)
001316 Port P3 pull-up control register (PULL3)
003316
A-D control register (ADCON)
Port P4 pull-up control register (PULL4)
Serial I/O2 control register 1 (SIO2CON1)
001416
001516
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
A-D conversion low-order register (ADL)
A-D conversion high-order register (ADH)
001616 Serial I/O2 control register 2 (SIO2CON2)
001716 Serial I/O2 register (SIO2)
A-D input selection register (ADSEL)
MISRG
Transmit/Receive buffer register (TB/RB)
Serial I/O1 status register (SIOSTS)
Serial I/O1 control register (SIOCON)
UART control register (UARTCON)
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
Watchdog timer control register (WDTCON)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Baud rate generator (BRG)
PWM control register (PWMCON)
PWM prescaler (PREPWM)
PWM register (PWM)
0FFE16 Flash memory control register (FMCR)
ꢀ Reserved : Do not write any data to this addresses, because these areas are reserved.
Fig. 12 Memory map of special function register (SFR) (spec. A)
Rev.3.01 2003.06.20 page 16 of 98
3850 Group (Spec.H)
I/O PORTS
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction
register corresponds to one pin, and each pin can be set to be
input port or output port.
When “0” is written to the bit corresponding to a pin, that pin
becomes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
Table 8 I/O port function (spec. H)
Input/Output
Related SFRs
Name
I/O Structure
Non-Port Function
Pin
P00/SIN2
Ref.No.
(1)
(2)
P01/SOUT2
P02/SCLK2
P03/SRDY2
P04–P07
P10–P17
P20/XCOUT
P21/XCIN
P22
Serial I/O2 control register
Serial I/O2 function I/O
Port P0
(3)
CMOS compatible
input level
CMOS 3-state output
(4)
(5)
Port P1
Port P2
Sub-clock generating
circuit
(6)
(7)
CPU mode register
CMOS compatible
input level
N-channel open-drain
output
P23
(8)
P24/RxD
(9)
P25/TxD
Input/output,
individual
bits
(10)
(11)
Serial I/O1 function I/O
Serial I/O1 control register
P26/SCLK1
P27/CNTR0/SRDY1
Serial I/O1 function I/O
Timer X function I/O
Serial I/O1 control register
Timer XY mode register
(12)
P30/AN0–
P34/AN4
(13)
(14)
(15)
A-D control register
Port P3
Port P4
A-D conversion input
Timer Y function I/O
CMOS compatible
input level
CMOS 3-state output
Timer XY mode register
P40/CNTR1
P41/INT0
Interrupt edge selection
register
External interrupt input
P42/INT1
P43/INT2/SCMP2
Interrupt edge selection
register
External interrupt input
SCMP2 output
(16)
(17)
Serial I/O2 control register
P44/INT3/PWM
Interrupt edge selection
register
PWM control register
External interrupt input
PWM output
Rev.3.01 2003.06.20 page 17 of 98
3850 Group (Spec.A)
I/O PORTS
By setting the port P0, P1, P2 pull-up control register (address
001216), the port P3 pull-up control register (address 001316), or
the port P4 pull-up control register (address 001416), ports can
control pull-up with a program. However, the contents of these
registers do not affect ports programmed as the output ports.
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction
register corresponds to one pin, and each pin can be set to be
input port or output port.
When “0” is written to the bit corresponding to a pin, that pin
becomes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
Table 9 I/O port function (spec. A)
Input/Output
Related SFRs
Name
I/O Structure
Non-Port Function
Ref.No.
Pin
P00/SIN2
(1)
(2)
P01/SOUT2
Serial I/O2 function I/O
A-D conversion input
Serial I/O2 control register
Port P0
P02/SCLK2
(3)
(4)
CMOS compatible
input level
CMOS 3-state output
P03/SRDY2
P04/AN5–P07AN8
A-D control register
A-D input selection register
(13)
(5)
(6)
(7)
Port P1
P10–P17
P20/XCOUT
P21/XCIN
P22
Sub-clock generating
circuit
CPU mode register
CMOS compatible
input level
N-channel open-drain
output
P23
(8)
Port P2
Port P3
(9)
P24/RxD
Serial I/O1 control register
Serial I/O1 function I/O
Input/output,
individual
bits
(10)
(11)
P25/TxD
P26/SCLK1
P27/CNTR0/SRDY1
Serial I/O1 control register
Timer XY mode register
A-D control register
Serial I/O1 function I/O
Timer X function I/O
(12)
P30/AN0–
P34/AN4
A-D conversion input
(13)
(14)
(15)
A-D input selection register
CMOS compatible
input level
CMOS 3-state output
Port P4
P40/CNTR1
P41/INT0
Timer Y function I/O
Timer XY mode register
(Note)
Interrupt edge selection
register
External interrupt input
P42/INT1
P43/INT2/SCMP2
Interrupt edge selection
register
External interrupt input
SCMP2 output
(16)
(17)
Serial I/O2 control register
Interrupt edge selection
register
PWM control register
P44/INT3/PWM
External interrupt input
PWM output
Note: When bits 5 to 7 of Ports P3 and P4 are read out, the contents are undefined.
Rev.3.01 2003.06.20 page 18 of 98
3850 Group (Spec.H)
(2) Port P0
1
(1) Port P0
0
P01/SOUT2 P-channel output disable bit
Direction
register
Serial I/O2 Transmit completion signal
Serial I/O2 port selection bit
Direction
register
Port latch
Data bus
Data bus
Port latch
Serial I/O2 input
Serial I/O2 output
(3) Port P0
2
(4) Port P0
3
P0
2/SCLK2 P-channel output disable bit
Serial I/O2 synchronous
clock selection bit
S
RDY2 output enable bit
Direction
register
Serial I/O2 port selection bit
Direction
register
Port latch
Data bus
Data bus
Port latch
Serial I/O2 ready output
Serial I/O2 clock output
Serial I/O2 external clock input
(6) Port P2
0
(5) Ports P04-P07,P1
Port XC switch bit
Direction
register
Direction
register
Port latch
Data bus
Data bus
Port latch
Oscillator
Port P2
1
(7) Port P2
1
Port XC switch bit
Port X
C
switch bit
(8) Ports P22,P2
3
Direction
register
Direction
register
Data bus
Port latch
Port latch
Data bus
Sub-clock generating circuit input
Fig. 13 Port block diagram (1) (spec. H)
Rev.3.01 2003.06.20 page 19 of 98
3850 Group (Spec.H)
(10) Port P25
(9) Port P24
Serial I/O1 enable bit
Receive enable bit
P-channel output disable bit
Serial I/O1 enable bit
Transmit enable bit
Direction
register
Direction
register
Port latch
Data bus
Port latch
Data bus
Serial I/O1 input
Serial I/O1 output
Pulse output mode
(11) Port P26
(12) Port P27
Serial I/O1 synchronous
clock selection bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Serial I/O1 enable bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
S
RDY1 output enable bit
Direction
Direction
register
register
Data bus
Port latch
Data bus
Port latch
Pulse output mode
Serial ready output
Serial I/O1 clock output
Timer output
External clock input
CNTR
0
interrupt
input
(13) Ports P30-P34
(14) Port P40
Direction
register
Direction
register
Data bus
Port latch
Port latch
Data bus
Pulse output mode
Timer output
A-D converter input
Analog input pin selection bit
CNTR
1
interrupt
input
(16) Port P43
Serial I/O2 I/O
comparison signal control bit
(15) Ports P41,P42
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Serial I/O2 I/O
Interrupt input
comparison signal output
Interrupt input
Fig. 14 Port block diagram (2) (spec. H)
Rev.3.01 2003.06.20 page 20 of 98
3850 Group (Spec.H)
(17) Port P4
4
PWM output enable bit
Direction
register
Port latch
Data bus
PWM output
Interrupt input
Fig. 15 Port block diagram (3) (spec. H)
Rev.3.01 2003.06.20 page 21 of 98
3850 Group (Spec.A)
(2) Port P01
(1) Port P00
Pull-up control bit
Pull-up control bit
P01/SOUT2 P-channel output disable bit
Direction
register
Serial I/O2 Transmit completion signal
Serial I/O2 port selection bit
Direction
register
Port latch
Data bus
Port latch
Data bus
Serial I/O2 input
Pull-up control bit
Serial I/O2 output
(4) Port P03
(3) Port P02
Pull-up control bit
P02/SCLK2 P-channel output disable bit
Serial I/O2 synchronous
clock selection bit
Serial I/O2 port selection bit
SRDY2 output enable bit
Direction
register
Direction
register
Port latch
Data bus
Port latch
Data bus
Serial I/O2 ready output
Serial I/O2 clock output
Serial I/O2 external clock input
(6) Port P20
(5) Port P1
Pull-up control bit
Pull-up control bit
Port XC switch bit
Direction
register
Direction
register
Port latch
Data bus
Port latch
Data bus
Oscillator
Port P21
(7) Port P21
Port XC switch bit
Pull-up control bit
Port XC switch bit
(8) Ports P22,P23
Direction
register
Direction
register
Data bus
Port latch
Port latch
Data bus
Sub-clock generating circuit input
Fig. 16 Port block diagram (1) (spec. A)
Rev.3.01 2003.06.20 page 22 of 98
3850 Group (Spec.A)
(9) Port P2
4
(10) Port P2
5
Pull-up control bit
Pull-up control bit
Serial I/O1 enable bit
Receive enable bit
P-channel output disable bit
Serial I/O1 enable bit
Transmit enable bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Serial I/O1 input
Pull-up control bit
Serial I/O1 output
(12) Port P2
7
(11) Port P2
6
Pull-up control bit
Pulse output mode
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Serial I/O1 synchronous
clock selection bit
Serial I/O1 enable bit
S
RDY1 output enable bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Direction
Direction
register
register
Data bus
Port latch
Port latch
Data bus
Pulse output mode
Serial ready output
Timer output
Serial I/O1 clock output
External clock input
CNTR
0
interrupt
input
(13) Ports P0
4
-P0
7
, P3
0
-P3
4
(14) Port P40
Pull-up control bit
Pull-up control bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Pulse output mode
Timer output
A-D converter input
CNTR
1
interrupt
input
Analog input pin selection bit
Analog input port selection switch bit
(15) Ports P41,P42
(16) Port P4
3
Pull-up control bit
Serial I/O2 I/O
Pull-up control bit
comparison signal control bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
Serial I/O2 I/O
comparison signal output
Interrupt input
Interrupt input
Fig. 17 Port block diagram (2) (spec. A)
Rev.3.01 2003.06.20 page 23 of 98
3850 Group (Spec.A)
(17) Port P4
4
Pull-up control bit
PWM output enable bit
Direction
register
Data bus
Port latch
PWM output
Interrupt input
Fig. 18 Port block diagram (3) (spec. A)
Rev.3.01 2003.06.20 page 24 of 98
3850 Group (Spec.A)
b7
b0
Port P0, P1, P2 pull-up control register
(PULL012: address 001216
)
P0 pull-up control bit
0: No pull-up
1: Pull-up
P1 pull-up control bit
0: No pull-up
1: Pull-up
P2 pull-up control bit
0: No pull-up
Note: Pull-up control is valid when the corresponding bit
of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be set
to the port of which pull-up is selected.
1: Pull-up
Not used (return “0” when read)
b7
b0
Port P3 pull-up control register
(PULL3: address 001316
)
P30 pull-up control bit
0: No pull-up
1: Pull-up
P31 pull-up control bit
0: No pull-up
1: Pull-up
P32 pull-up control bit
0: No pull-up
1: Pull-up
Note: Pull-up control is valid when the corresponding bit
of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be set
to the port of which pull-up is selected.
P33 pull-up control bit
0: No pull-up
1: Pull-up
P34 pull-up control bit
0: No pull-up
1: Pull-up
Fix these bits to “0”.
Fig. 19 Structure of port registers (1) (spec. A)
Rev.3.01 2003.06.20 page 25 of 98
3850 Group (Spec.A)
b7
b0
Port P4 pull-up control register
(PULL4: address 001416
)
P40 pull-up control bit
0: No pull-up
1: Pull-up
P41 pull-up control bit
0: No pull-up
1: Pull-up
P42 pull-up control bit
0: No pull-up
1: Pull-up
Note: Pull-up control is valid when the corresponding bit
of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be set
to the port of which pull-up is selected.
P43 pull-up control bit
0: No pull-up
1: Pull-up
P44 pull-up control bit
0: No pull-up
1: Pull-up
Fix these bits to “0”.
Fig. 20 Structure of port registers (2) (spec. A)
Rev.3.01 2003.06.20 page 26 of 98
3850 Group (Spec.H/A)
INTERRUPTS
Interrupts occur by 15 sources among 15 sources: six external,
■Notes
When setting the followings, the interrupt request bit may be set to
eight internal, and one software.
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
Timer XY mode register (address 2316)
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the in-
terrupt disable flag is “0”.
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: Interrupt edge selection register (address 3A16)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
(1) Set the corresponding interrupt enable bit to “0” (disabled).
(2) Set the interrupt edge select bit or the interrupt source select
bit to “1”.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK in-
struction interrupt.
(3) Set the corresponding interrupt request bit to “0” after 1 or
more instructions have been executed.
When several interrupts occur at the same time, the interrupts are
received according to priority.
(4) Set the corresponding interrupt enable bit to “1” (enabled).
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
Rev.3.01 2003.06.20 page 27 of 97
3850 Group (Spec.H/A)
Table 10 Interrupt vector addresses and priority
Vector Addresses (Note 1)
Interrupt Request
Generating Conditions
Remarks
Non-maskable
Interrupt Source
Reset (Note 2)
INT0
Priority
1
High
Low
FFFD16
FFFC16
At reset
At detection of either rising or
falling edge of INT0 input
External interrupt
(active edge selectable)
2
3
4
FFFB16
FFF916
FFF716
FFFA16
FFF816
FFF616
Reserved
Reserved
INT1
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT1 input
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT2 input
5
6
FFF516
FFF316
FFF416
FFF216
INT2
At detection of either rising or External interrupt
falling edge of INT3 input/ At (active edge selectable)
completion of serial I/O2 data Switch by Serial I/O2/INT3
INT3/ Serial I/O2
reception/transmission
interrupt source bit
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFF016
FFEE16
FFEC16
FFEA16
FFE816
7
8
Reserved
Timer X
Timer Y
Timer 1
Timer 2
Reserved
At timer X underflow
At timer Y underflow
At timer 1 underflow
9
STP release timer underflow
10
11
At timer 2 underflow
At completion of serial I/O1 data
reception
Serial I/O1
reception
12
13
FFE716
FFE516
FFE616
FFE416
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
At completion of serial I/O1
transfer shift or when transmis-
sion buffer is empty
Serial I/O1
transmission
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of CNTR0 input
CNTR0
CNTR1
14
15
FFE216
FFE016
FFE316
FFE116
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of CNTR1 input
16
17
FFDF16
FFDD16
FFDE16
FFDC16
A-D converter
At completion of A-D conversion
At BRK instruction execution
BRK instruction
Non-maskable software interrupt
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Rev.3.01 2003.06.20 page 28 of 97
3850 Group (Spec.H/A)
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
Fig. 21 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16
)
INT
INT
INT
INT
0
active edge selection bit
1
2
3
active edge selection bit
active edge selection bit
active edge selection bit
0 : Falling edge active
1 : Rising edge active
Serial I/O2 / INT3 interrupt source bit
0 : INT interrupt selected
3
1 : Serial I/O2 interrupt selected
Not used (returns “0” when read)
b7
b0
b7
b0
Interrupt request register 2
Interrupt request register 1
(IREQ2 : address 003D16
)
(IREQ1 : address 003C16
)
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Serial I/O1 reception interrupt request bit
Serial I/O1 transmit interrupt request bit
INT
Reserved
INT
INT
INT
Reserved
Timer X interrupt request bit
Timer Y interrupt request bit
0 interrupt request bit
1
2
3
interrupt request bit
interrupt request bit
/ Serial I/O2 interrupt request bit
CNTR
CNTR
0
interrupt request bit
interrupt request bit
1
AD converter interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b7
b0
Interrupt control register 2
Interrupt control register 1
(ICON2 : address 003F16
)
(ICON1 : address 003E16
)
INT interrupt enable bit
0
Timer 1 interrupt enable bit
Reserved(Do not write “1” to this bit.)
Timer 2 interrupt enable bit
INT
INT
INT
1
2
3
interrupt enable bit
interrupt enable bit
/ Serial I/O2 interrupt enable bit
Serial I/O1 reception interrupt enable bit
Serial I/O1 transmit interrupt enable bit
CNTR
CNTR
0
interrupt enable bit
interrupt enable bit
Reserved(Do not write “1” to this bit.)
Timer X interrupt enable bit
Timer Y interrupt enable bit
1
AD converter interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
0 : Interrupts disabled
1 : Interrupts enabled
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 22 Structure of interrupt-related registers
Rev.3.01 2003.06.20 page 29 of 97
3850 Group (Spec.H/A)
TIMERS
Timer X and Timer Y
Timer X and Timer Y can each select in one of four operating
The 3850 group (spec. H/A) has four timers: timer X, timer Y, timer
1, and timer 2.
modes by setting the timer XY mode register.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are count down. When the timer reaches “0016”, an un-
derflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
(1) Timer Mode
The timer counts the count source selected by Timer count source
selection bit.
(2) Pulse Output Mode
The timer counts the count source selected by Timer count source
selection bit. Whenever the contents of the timer reach “0016”, the
signal output from the CNTR0 (or CNTR1) pin is inverted. If the
CNTR0 (or CNTR1) active edge selection bit is “0”, output begins
at “ H”.
b0
b7
Timer XY mode register
(TM : address 002316
)
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P27 ( or port P40) direction register to out-
put mode.
Timer X operating mode bit
b1b0
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR0 active edge selection bit
(3) Event Counter Mode
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Operation in event counter mode is the same as in timer mode,
except that the timer counts signals input through the CNTR0 or
CNTR1 pin.
When the CNTR0 (or CNTR1) active edge selection bit is “0”, the
rising edge of the CNTR0 (or CNTR1) pin is counted.
When the CNTR0 (or CNTR1) active edge selection bit is “1”, the
falling edge of the CNTR0 (or CNTR1) pin is counted.
Timer X count stop bit
0: Count start
1: Count stop
Timer Y operating mode bits
b5b4
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
(4) Pulse Width Measurement Mode
If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer
counts the selected signals by the count source selection bit while
the CNTR0 (or CNTR1) pin is at “H”. If the CNTR0 (or CNTR1) ac-
tive edge selection bit is “1”, the timer counts it while the CNTR0
(or CNTR1) pin is at “L”.
CNTR1 active edge selection bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Timer Y count stop bit
0: Count start
1: Count stop
The count can be stopped by setting “1” to the timer X (or timer Y)
count stop bit in any mode. The corresponding interrupt request
bit is set each time a timer underflows.
Fig. 23 Structure of timer XY mode register
b0
b7
ꢀNote
Timer count source selection register
(TCSS : address 002816
)
When switching the count source by the timer 12, X and Y count
source bits, the value of timer count is altered in unconsiderable
amount owing to generating of a thin pulses in the count input
signals.
Timer X count source selection bit
0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)
1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Timer Y count source selection bit
0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)
1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Timer 12 count source selection bit
Therefore, select the timer count source before set the value to
the prescaler and the timer.
0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)
1 : f(XCIN
)
Not used (returns “0” when read)
When timer X/timer Y underflow while executing the instruction
which sets “1” to the timer X/timer Y count stop bits, the timer X/
timer Y interrupt request bits are set to “1”. Timer X/Timer Y in-
terrupts are received if these interrupts are enabled at this time.
The timing which interrupt is accepted has a case after the in-
struction which sets “1” to the count stop bit, and a case after
the next instruction according to the timing of the timer under-
flow. When this interrupt is unnecessary, set “0” (disabled) to the
interrupt enable bit and then set “1” to the count stop bit.
Fig. 24 Structure of timer count source selection register
Timer 1 and Timer 2
The count source of prescaler 12 is the oscillation frequency
which is selected by timer 12 count source selection bit. The out-
put of prescaler 12 is counted by timer 1 and timer 2, and a timer
underflow sets the interrupt request bit.
Rev.3.01 2003.06.20 page 30 of 97
3850 Group (Spec.H/A)
Data bus
f(XIN)/16
(f(XCIN)/16 at low-speed mode)
Prescaler X latch (8)
Timer X latch (8)
Timer X (8)
f(XIN)/2
Pulse width
measurement
mode
(f(XCIN)/2 at low-speed mode)
Timer mode
Pulse output mode
Timer X count source selection bit
To timer X interrupt
request bit
Prescaler X (8)
Timer X count stop bit
CNTR0 active edge
Event
counter
mode
selection bit
P27/CNTR0
“0”
To CNTR
0 interrupt
request bit
“1”
CNTR0 active
“1”
“0”
edge selection
bit
Q
Q
T
Toggle flip-flop
R
Timer X latch write pulse
Pulse output mode
Port P2
latch
7
Port P2
direction register
7
Pulse output mode
Data bus
f(XIN)/16
Prescaler Y latch (8)
Timer Y latch (8)
Timer Y (8)
(f(XCIN)/16 at low-speed mode)
f(XIN)/2
Pulse width
measure-
(f(XCIN)/2 at low-speed mode)
Timer mode
ment mode Pulse output mode
Timer Y count source selection bit
To timer Y interrupt
request bit
Prescaler Y (8)
CNTR1 active edge
selection bit
Event
counter
mode
Timer Y count stop bit
P40/CNTR1
“0”
To CNTR
1 interrupt
request bit
“1”
CNTR1 active
“1”
“0”
edge selection
bit
Q
Q
T
Toggle flip-flop
R
Port P4
latch
0
Timer Y latch write pulse
Pulse output mode
Port P4
0
direction register
Pulse output mode
Data bus
Prescaler 12 latch (8)
Prescaler 12 (8)
Timer 1 latch (8)
Timer 1 (8)
Timer 2 latch (8)
Timer 2 (8)
f(XIN)/16
(f(XCIN)/16 at low-speed mode)
To timer 2 interrupt
request bit
f(XCIN
)
Timer 12 count source selection bit
To timer 1 interrupt
request bit
Fig. 25 Block diagram of timer X, timer Y, timer 1, and timer 2
Rev.3.01 2003.06.20 page 31 of 97
3850 Group (Spec.H/A)
SERIAL I/O
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
serial I/O1 mode selection bit of the serial I/O1 control register (bit
6 of address 001A16) to “1”.
ꢀSERIAL I/O1
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Data bus
Serial I/O1 control register
Address 001A16
Address 001816
Receive buffer register
Receive buffer full flag (RBF)
Receive shift register
Receive interrupt request (RI)
P24/RXD
Shift clock
Clock control circuit
P26/SCLK1
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
X
IN
Baud rate generator
Address 001C16
1/4
Clock control circuit
Falling-edge detector
P27/SRDY1
F/F
Shift clock
Transmit shift register
Transmit buffer register
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
P25/TXD
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Serial I/O1 status register
Address 001916
Address 001816
Data bus
Fig. 26 Block diagram of clock synchronous serial I/O1
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
Serial input RxD
D
0
0
D
1
1
D
2
2
D
3
3
D
4
4
D
5
5
D
6
6
D
7
7
D
D
D
D
D
D
D
D
Receive enable signal SRDY1
Write pulse to receive/transmit
buffer register (address 001816
)
RBF = 1
TSC = 1
Overrun error (OE)
detection
TBE = 0
TBE = 1
TSC = 0
Notes 1: As the transmit interrupt (TI), either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has
ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 27 Operation of clock synchronous serial I/O1 function
Rev.3.01 2003.06.20 page 32 of 97
3850 Group (Spec.H/A)
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit (b6) of the serial I/O1
control register to “0”.
two buffers have the same address in memory. Since the shift reg-
ister cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Data bus
Address 001816
Serial I/O1 control register Address 001A16
OE
Character length selection bit
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive buffer register
P24
/R
XD
ST detector
7 bits
8 bits
Receive shift register
1/16
UART control register
PE FE
SP detector
Address 001B16
Clock control circuit
Serial I/O1 synchronous clock selection bit
P26/SCLK1
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
XIN
Baud rate generator
Address 001C16
ST/SP/PA generator
1/16
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
P25/TXD
Transmit shift register
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer register
Address 001816
Transmit buffer empty flag (TBE)
Address 001916
Serial I/O1 status register
Data bus
Fig. 28 Block diagram of UART serial I/O1
Rev.3.01 2003.06.20 page 33 of 97
3850 Group (Spec.H/A)
Transmit or receive clock
Transmit buffer write
signal
TBE=0
TBE=0
TSC=0
TBE=1
TBE=1
TSC=1
Serial output TXD
ST
SP
D0
D1
ST
D0
D1
SP
1 start bit
Generated at 2nd bit in 2-stop-bit mode
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read
signal
RBF=0
RBF=1
SP
RBF=1
SP
ST
Serial input R
XD
D0
D1
ST
D0
D1
Notes
1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1”, can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1”.
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 29 Operation of UART serial I/O1 function
[Serial I/O1 Control Register (SIOCON)] 001A16
The serial I/O1 control register consists of eight control bits for the
serial I/O1 function.
[Transmit Buffer Register/Receive Buffer
Register (TB/RB)] 001816
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer and one bit (bit 4) which is al-
ways valid and sets the output structure of the P25/TXD pin.
[Serial I/O1 Status Register (SIOSTS)] 001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O1
function and various errors.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial trans-
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE
(bit 7 of the serial I/O1 control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at
reset, but if the transmit enable bit (bit 4) of the serial I/O1 control
register has been set to “1”, the transmit shift completion flag (bit
2) and the transmit buffer empty flag (bit 0) become “1”.
Rev.3.01 2003.06.20 page 34 of 97
3850 Group (Spec.H/A)
b7
b0
b0
b7
Serial I/O1 status register
(SIOSTS : address 001916)
Serial I/O1 control register
(SIOCON : address 001A16)
BRG count source selection bit (CSS)
0: f(XIN)
1: f(XIN)/4
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O1 is selected, BRG output divided by 16
when UART is selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
1: External clock input when clock synchronous serial
I/O1 is selected, external clock input divided by 16
when UART is selected.
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
SRDY1 output enable bit (SRDY)
0: P27 pin operates as ordinary I/O pin
1: P27 pin operates as SRDY1 output pin
Overrun error flag (OE)
0: No error
1: Overrun error
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Not used (returns “1” when read)
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
(pins P24 to P27 operate as ordinary I/O pins)
1: Serial I/O1 enabled
b7
b0
UART control register
(UARTCON : address 001B16)
(pins P24 to P27 operate as serial I/O1 pins)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P25/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
Fig. 30 Structure of serial I/O1 control registers
■Notes on serial I/O
When setting the transmit enable bit of serial I/O1 to “1”, the serial
I/O1 transmit interrupt request bit is automatically set to “1”. When
not requiring the interrupt occurrence synchronized with the trans-
mission enalbed, take the following sequence.
(1) Set the serial I/O1 transmit interrupt enable bit to “0” (disabled).
(2) Set the transmit enable bit to “1”.
(3) Set the serial I/O1 transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
(4) Set the serial I/O1 transmit interrupt enable bit to “1” (enabled).
Rev.3.01 2003.06.20 page 35 of 97
3850 Group (Spec.H/A)
ꢀSERIAL I/O2
The serial I/O2 can be operated only as the clock synchronous type.
b7
b0
As a synchronous clock for serial transfer, either internal clock or
external clock can be selected by the serial I/O2 synchronous clock
selection bit (b6) of serial I/O2 control register 1.
Serial I/O2 control register 1
(SIO2CON1 : address 001516
)
Internal synchronous clock selection bits
b2 b1 b0
The internal clock incorporates a dedicated divider and permits se-
lecting 6 types of clock by the internal synchronous clock selection
bits (b2, b1, b0) of serial I/O2 control register 1.
0
0
0
0
1
1
0
0
1
1
1
1
0: f(XIN)/8 (f(XCIN)/8 in low-speed mode)
1: f(XIN)/16 (f(XCIN)/16 in low-speed mode)
0: f(XIN)/32 (f(XCIN)/32 in low-speed mode)
1: f(XIN)/64 (f(XCIN)/64 in low-speed mode)
0: f(XIN)/128 f(XCIN)/128 in low-speed mode)
1: f(XIN)/256 (f(XCIN)/256 in low-speed mode)
Regarding SOUT2 and SCLK2 being output pins, either CMOS output
format or N-channel open-drain output format can be selected by the
P01/SOUT2, P02/SCLK2 P-channel output disable bit (b7) of
serial I/O2 control register 1.
Serial I/O2 port selection bit
0: I/O port
1: SOUT2,SCLK2 output pin
When the internal clock has been selected, a transfer starts by a
write signal to the serial I/O2 register (address 001716). After comple-
tion of data transfer, the level of the SOUT2 pin goes to high imped-
ance automatically but bit 7 of the serial I/O2 control register 2 is not
set to “1” automatically.
SRDY2 output enable bit
0: P0
3
pin is normal I/O pin
1: P0
3
pin is SRDY2 output pin
Transfer direction selection bit
0: LSB first
1: MSB first
When the external clock has been selected, the contents of the serial
I/O2 register is continuously sifted while transfer clocks are input.
Accordingly, control the clock externally. Note that the SOUT2 pin does
not go to high impedance after completion of data transfer.
To cause the SOUT2 pin to go to high impedance in the case where
the external clock is selected, set bit 7 of the serial I/O2 control reg-
ister 2 to “1” when SCLK2 is “H” after completion of data transfer. After
the next data transfer is started (the transfer clock falls), bit 7 of the
serial I/O2 control register 2 is set to “0” and the SOUT2 pin is put into
the active state.
Serial I/O2 synchronous clock selection bit
0: External clock
1: Internal clock
P01/SOUT2 ,P02/SCLK2 P-channel output disable bit
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode )
b7
b0
Serial I/O2 control register 2
(SIO2CON2 : address 001616
)
Regardless of the internal clock to external clock, the interrupt re-
quest bit is set after the number of bits (1 to 8 bits) selected by the
optional transfer bit is transferred. In case of a fractional number of
bits less than 8 bits as the last data, the received data to be stored in
the serial I/O2 register becomes a fractional number of bits close to
MSB if the transfer direction selection bit of serial I/O2 control regis-
ter 1 is LSB first, or a fractional number of bits close to LSB if the
transfer direction selection bit is MSB first. For the remaining bits, the
previously received data is shifted.
Optional transfer bits
b2 b1 b0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0: 1 bit
1: 2 bit
0: 3 bit
1: 4 bit
0: 5 bit
1: 6 bit
0: 7 bit
1: 8 bit
Not used ( returns "0" when read)
At transmit operation using the clock synchronous serial I/O, the SCMP2
signal can be output by comparing the state of the transmit pin SOUT2
with the state of the receive pin SIN2 in synchronization with a rise of
the transfer clock. If the output level of the SOUT2 pin is equal to the
input level to the SIN2 pin, “L” is output from the SCMP2 pin. If not, “H”
is output. At this time, an INT2 interrupt request can also be gener-
ated. Select a valid edge by bit 2 of the interrupt edge selection reg-
ister (address 003A16).
Serial I/O2 I/O comparison signal control bit
0: P43 I/O
1: SCMP2 output
S
OUT2 pin control bit (P0
0: Output active
1: Output high-impedance
1)
Fig. 31 Structure of Serial I/O2 control registers 1, 2
[Serial I/O2 Control Registers 1, 2 (SIO2CON1 /
SIO2CON2)] 001516, 001616
The serial I/O2 control registers 1 and 2 are containing various se-
lection bits for serial I/O2 control as shown in Figure 31.
Rev.3.01 2003.06.20 page 36 of 97
3850 Group (Spec.H/A)
Internal synchronous
clock selection bits
1/8
X
CIN
1/16
1/32
Data bus
“10”
Main clock division ratio
selection bits (Note)
1/64
“00”
“01”
1/128
1/256
X
IN
P0
3
latch
Serial I/O2 synchronous
clock selection bit
“0”
“1”
P03/SRDY2
S
RDY2
Synchronous circuit
“1”
S
RDY2 output enable bit
“0”
External clock
P02 latch
“0”
Optional transfer bits (3)
Serial I/O counter 2 (3)
P02
/SCLK2
Serial I/O2
“1”
interrupt request
Serial I/O2 port selection bit
P01 latch
“0”
P0
1
/SOUT2
/SIN2
“1”
Serial I/O2 port selection bit
Serial I/O2 register (8)
P00
P43 latch
“0”
D
P43
/SCMP2/INT2
Q
“1”
Serial I/O2 I/O comparison
signal control bit
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register.
Fig. 32 Block diagram of Serial I/O2
Transfer clock (Note 1)
Write-in signal to
serial I/O2 register
(Note 2)
.
Serial I/O2 output
SOUT2
D0
D1
D2
D3
D4
D5
D6
D7
Serial I/O2 input SIN2
Receive enable signal SRDY2
Serial I/O2 interrupt request bit set
Notes
1: When the internal clock is selected as a transfer clock, the f(XIN) clock division (f(XCIN) in low-speed mode) can be selected
by setting bits 0 to 2 of serial I/O2 control register 1.
2: When the internal clock is selected as a transfer clock, the SOUT2 pin has high impedance after transfer completion.
Fig. 33 Timing chart of Serial I/O2
Rev.3.01 2003.06.20 page 37 of 97
3850 Group (Spec.H/A)
SCMP2
SCLK2
SOUT2
SIN2
Judgement of I/O data comparison
Fig. 34 SCMP2 output operation
Rev.3.01 2003.06.20 page 38 of 97
3850 Group (Spec.H/A)
PULSE WIDTH MODULATION (PWM)
The 3850 group (spec. H/A) has a PWM function with an 8-bit
resolution, based on a signal that is the clock input XIN or that
clock input divided by 2.
PWM Operation
When bit 0 (PWM enable bit) of the PWM control register is set to
“1”, operation starts by initializing the PWM output circuit, and
pulses are output starting at an “H”.
If the PWM register or PWM prescaler is updated during PWM
output, the pulses will change in the cycle after the one in which
the change was made.
Data Setting
The PWM output pin also functions as port P44. Set the PWM
period by the PWM prescaler, and set the “H” term of output pulse
by the PWM register.
31.875 ꢀ m ꢀ (n+1)
If the value in the PWM prescaler is n and the value in the PWM
register is m (where n = 0 to 255 and m = 0 to 255) :
PWM period = 255 ꢀ (n+1) / f(XIN)
µs
255
= 31.875 ꢀ (n+1) µs
PWM output
(when f(XIN) = 8 MHz,count source selection bit = “0”)
Output pulse “H” term = PWM period ꢀ m / 255
= 0.125 ꢀ (n+1) ꢀ m µs
T = [31.875 ꢀ (n+1)] µs
(when f(XIN) = 8 MHz,count source selection bit = “0”)
m: Contents of PWM register
n : Contents of PWM prescaler
T : PWM period (when f(XIN) = 8 MHz,count source
selection bit = “0”)
Fig. 35 Timing of PWM period
Data bus
PWM
prescaler pre-latch
PWM
register pre-latch
Transfer control circuit
PWM
prescaler latch
PWM
register latch
Count source
selection bit
Port P4
4
“0”
X
IN
PWM prescaler
PWM register
(XCIN at low-speed mode)
“1”
1/2
Port P44 latch
PWM enable bit
Fig. 36 Block diagram of PWM function
Rev.3.01 2003.06.20 page 39 of 97
3850 Group (Spec.H/A)
b7
b0
PWM control register
(PWMCON : address 001D16
)
PWM function enable bit
0: PWM disabled
1: PWM enabled
Count source selection bit
0: f(XIN) (f(XCIN) at low-speed mode)
1: f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Not used (return “0” when read)
Fig. 37 Structure of PWM control register
B
T
C
T2
=
A
B
C
PWM output
T
T
T2
PWM register
write signal
(Changes “H” term from “A” to “B”.)
PWM prescaler
write signal
(Changes PWM period from “T” to “T2”.)
When the contents of the PWM register or PWM prescaler have changed, the PWM
output will change from the next period after the change.
Fig. 38 PWM output timing when PWM register or PWM prescaler is changed
ꢀNote
The PWM starts after the PWM function enable bit is set to enable and “L” level is output from the PWM pin.
The length of this “L” level output is as follows:
n+1
sec
sec
(Count source selection bit = 0, where n is the value set in the prescaler)
(Count source selection bit = 1, where n is the value set in the prescaler)
2 • f(XIN)
n+1
f(XIN)
Rev.3.01 2003.06.20 page 40 of 97
3850 Group (Spec.H)
A-D CONVERTER
[A-D Conversion Registers (ADL, ADH)]
003516, 003616
b7
b0
A-D control register
(ADCON : address 003416)
The A-D conversion registers are read-only registers that store the
result of an A-D conversion. Do not read these registers during an
A-D conversion.
Analog input pin selection bits
b2 b1 b0
0 0 0: P30/AN0
0 0 1: P31/AN1
0 1 0: P32/AN2
0 1 1: P33/AN3
1 0 0: P34/AN4
[A-D Control Register (ADCON)] 003416
The AD control register controls the A-D conversion process. Bits
0 to 2 select a specific analog input pin. Bit 4 indicates the
completion of an A-D conversion. The value of this bit remains at
“0” during an A-D conversion and changes to “1” when an A-D
conversion ends. Writing “0” to this bit starts the A-D conversion.
Not used (returns “0” when read)
A-D conversion completion bit
0: Conversion in progress
1: Conversion completed
Not used (returns “0” when read)
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
Fig. 39 Structure of A-D control register (spec. H)
AVSS and VREF into 1024 and outputs the divided voltages.
Channel Selector
10-bit reading
(Read address 003616 before 003516
The channel selector selects one of ports P30/AN0 to P34/AN4 and
)
inputs the voltage to the comparator.
b0
b7
(Address 003616
(Address 003516
)
b9 b8
Comparator and Control Circuit
b7
b0
The comparator and control circuit compare an analog input volt-
age with the comparison voltage, and the result is stored in the
A-D conversion registers. When an A-D conversion is completed,
the control circuit sets the A-D conversion completion bit and the
A-D interrupt request bit to “1”.
)
b7 b6 b5 b4 b3 b2 b1 b0
Note : The high-order 6 bits of address 003616 become “0”
at reading.
Note that because the comparator consists of a capacitor cou-
pling, set f(XIN) to 500 kHz or more during an A-D conversion.
When the A-D converter is operated at low-speed mode, f(XIN)
and f(XCIN) do not have the lower limit of frequency, because of
the A-D converter has a built-in self-oscillation circuit.
8-bit reading (Read only address 003516
)
b0
b7
(Address 003516
)
b9 b8 b7 b6 b5 b4 b3 b2
Fig. 40 Structure of A-D conversion registers (spec. H)
Data bus
b7
3
b0
A-D control register
(Address 003416
)
A-D interrupt request
A-D control circuit
P30/AN0
P3
P3
P3
1
2
3
/AN
/AN
/AN
1
2
3
A-D conversion high-order register (Address 003616
)
)
Comparator
(Address 003516
A-D conversion low-order register
10
P34/AN4
Resistor ladder
V
REF AVSS
Fig. 41 Block diagram of A-D converter (spec. H)
Rev.3.01 2003.06.20 page 41 of 97
3850 Group (Spec.A)
b7
b0
A-D CONVERTER
A-D control register
(ADCON : address 003416
[A-D Conversion Registers (ADL, ADH)]
003516, 003616
The A-D conversion registers are read-only registers that store the
result of an A-D conversion. Do not read these registers during an
A-D conversion.
)
Analog input pin selection bits
Note 1
Note 2
b2 b1 b0
or
or
or
or
0 0 0: P3
0 0 1: P3
0 1 0: P3
0 1 1: P3
1 0 0: P3
0
1
2
3
4
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
P0
P0
P0
P0
4
5
6
7
/AN
/AN
/AN
/AN
5
6
7
8
––––––
[A-D Control Register (ADCON)] 003416
The A-D control register controls the A-D conversion process. Bits
0 to 2 select a specific analog input pin. By setting a value to these
bits, when bit 0 of the A-D input selection register (address
003716) is “0”, P30/AN0-P34/AN4 can be selected, and when bit 0
of the A-D input selection register is “1”, P04/AN5-P07/AN8 can be
selected.
Not used (returns “0” when read)
A-D conversion completion bit
0: Conversion in progress
1: Conversion completed
Not used (returns “0” when read)
Notes 1: This is selected when bit 0 of the A-D input selection register
(address 003716) is “0”.
2: This is selected when bit 0 of the A-D input selection register
(address 003716) is “1”.
Bit 4 indicates the completion of an A-D conversion. The value of
this bit remains at “0” during an A-D conversion and changes to “1”
when an A-D conversion ends. Writing “0” to this bit starts the A-D
conversion.
Fig. 42 Structure of A-D control register (spec. A)
b7
b0
A-D input selection register
(ADSEL: address 003716
[A-D Input Selection Register (ADSEL)]
003716
)
The analog input port selection switch bit is assigned to bit 0 of the
A-D input selection register. When “0” is set to the analog input
port selection switch bit, P30/AN0-P34/AN4 can be selected by the
analog input pin selection bits (b2, b1, b0) of the A-D control reg-
ister (address 003416). When “1” is set to the analog input port
selection switch bit, P04/AN5-P07/AN8 can be selected by the ana-
log input pin selection bits (b2, b1, b0) of the A-D control register
(address 003416).
Analog input port selection switch bit
0: P3 /AN toP3 /AN4 is selected as
analog input pin.
1: P04/AN5 to P07/AN8 is selected as
0
0
4
analog input pin.
Not used (returns “0” when read)
Fix this bit to “0”.
Not used (returns “0” when read)
Fix this bit to “0”.
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
Fig. 43 Structure of A-D input selection register (spec. A)
AVSS and VREF into 1024 and outputs the divided voltages.
Channel Selector
The channel selector selects one of ports P30/AN0 to P34/AN4,
10-bit reading
(Read address 003616 before 003516
)
P04/AN5 to P07/AN8 and inputs the voltage to the comparator.
b0
b7
(Address 003616
(Address 003516
)
b9 b8
Comparator and Control Circuit
The comparator and control circuit compare an analog input volt-
age with the comparison voltage, and the result is stored in the
A-D conversion registers. When an A-D conversion is completed,
the control circuit sets the A-D conversion completion bit and the
A-D interrupt request bit to “1”.
b7
b0
)
b7 b6 b5 b4 b3 b2 b1 b0
Note : The high-order 6 bits of address 003616 become “0”
at reading.
Note that because the comparator consists of a capacitor cou-
pling, set f(XIN) to 500 kHz or more during an A-D conversion.
When the A-D converter is operated at low-speed mode, f(XIN)
and f(XCIN) do not have the lower limit of frequency, because of
the A-D converter has a built-in self-oscillation circuit.
8-bit reading (Read only address 003516
)
b0
b7
(Address 003516
)
b9 b8 b7 b6 b5 b4 b3 b2
Fig. 44 Structure of A-D conversion registers (spec. A)
Rev.3.01 2003.06.20 page 42 of 97
3850 Group (Spec.A)
Data bus
b7
3
b0
b7
b0
A-D control register
(Address 003416
)
A-D input selection register
(Address 003716
)
A-D interrupt request
A-D control circuit
P30/AN0
P3
P3
P3
1
2
3
/AN
/AN
/AN
1
2
3
A-D conversion high-order register (Address 003616
A-D conversion low-order register (Address 003516
)
)
Comparator
P34/AN4
10
P0
P0
4
5
/AN
/AN
5
6
Resistor ladder
P0
P0
6
/AN
7
7
/AN
8
V
REF AVSS
Fig. 45 Block diagram of A-D converter (spec. A)
Rev.3.01 2003.06.20 page 43 of 97
3850 Group (Spec.H/A)
WATCHDOG TIMER
ꢀWatchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 003916) per-
mits selecting a watchdog timer H count source. When this bit is
set to “0”, the count source becomes the underflow signal of
watchdog timer L. The detection time is set to 131.072 ms at f(XIN)
= 8 MHz frequency and 32.768 s at f(XCIN) = 32 kHz frequency.
When this bit is set to “1”, the count source becomes the signal
divided by 16 for f(XIN) (or f(XCIN)). The detection time in this case
is set to 512 µs at f(XIN) = 8 MHz frequency and 128 ms at f(XCIN)
= 32 kHz frequency. This bit is cleared to “0” after reset.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Standard Operation of Watchdog Timer
When any data is not written into the watchdog timer control reg-
ister (address 003916) after reset, the watchdog timer is in the
stop state. The watchdog timer starts to count down by writing an
optional value into the watchdog timer control register (address
003916) and an internal reset occurs at an underflow of the watch-
dog timer H.
ꢀOperation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 003916) per-
mits disabling the STP instruction when the watchdog timer is in
operation.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 003916) may be
started before an underflow. When the watchdog timer control reg-
ister (address 003916) is read, the values of the high-order 6 bits
of the watchdog timer H, STP instruction disable bit, and watch-
dog timer H count source selection bit are read.
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled, once the STP
instruction is executed, an internal reset occurs. When this bit is
set to “1”, it cannot be rewritten to “0” by program. This bit is
cleared to “0” after reset.
ꢀInitial value of watchdog timer
At reset or writing to the watchdog timer control register (address
003916), each watchdog timer H and L are set to “FF16”.
“FF16” is set when
watchdog timer
Data bus
“FF16” is set when
watchdog timer
control register is
X
CIN
control register is
written to.
“0”
“10”
written to.
Watchdog timer L (8)
Main clock division
ratio selection bits
(Note)
Watchdog timer H (8)
1/16
“1”
“00”
“01”
Watchdog timer H count
source selection bit
X
IN
STP instruction disable bit
STP instruction
Reset
circuit
Internal reset
RESET
Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
Fig. 46 Block diagram of Watchdog timer
b0
b7
Watchdog timer control register
(WDTCON : address 003916
)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/16 or f(XCIN)/16
Fig. 47 Structure of Watchdog timer control register
Rev.3.01 2003.06.20 page 44 of 97
3850 Group (Spec.H/A)
RESET CIRCUIT
To reset the microcomputer, RESET pin must be held at an “L”
level for 20 cycles or more of XIN. Then the RESET pin is returned
to an “H” level (the power source voltage must be between 2.7 V
and 5.5 V, and the oscillation must be stable), reset is released.
After the reset is completed, the program starts from the address
contained in address FFFD16 (high-order byte) and address
FFFC16 (low-order byte). Make sure that the reset input voltage is
less than 0.54 V for VCC of 2.7 V.
Poweron
(Note)
Power source
voltage
0V
RESET
VCC
Reset input
voltage
0V
0.2VCC
Note : Reset release voltage; Vcc = 2.7 V
RESET
V
CC
Power source
voltage detection
circuit
Fig. 48 Reset circuit example
X
IN
φ
RESET
RESETOUT
Address
AD
H,L
?
?
?
?
FFFC
FFFD
Reset address from the vector table.
AD
H
Data
?
?
?
AD
L
?
SYNC
X
IN: 8 to 13 clock cycles
Notes1: The frequency relation of f(XIN) and f(φ) is f(XIN) = 2 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
3: All signals except XIN and RESET are internals.
Fig. 49 Reset sequence
Rev.3.01 2003.06.20 page 45 of 98
3850 Group (Spec.H)
Address
Register contents
Address Register contents
(1)
Port P0 (P0)
(34)MISRG
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
001516
001616
001716
0016
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
(PS)
0016
0 0 1 1 1 1 1 1
0016
(2)
Port P0 direction register (P0D)
Port P1 (P1)
(35)Watchdog timer control register (WDTCON)
(36)Interrupt edge selection register (INTEDGE)
(37)CPU mode register (CPUM)
(38)Interrupt request register 1 (IREQ1)
(39)Interrupt request register 2 (IREQ2)
(40)Interrupt control register 1 (ICON1)
(41)Interrupt control register 2 (ICON2)
(42)Processor status register
(43)Program counter
0016
(3)
0016
(4)
Port P1 direction register (P1D)
Port P2 (P2)
0016
0 1 0 0 1 0 0 0
0016
(5)
0016
(6)
Port P2 direction register (P2D)
Port P3 (P3)
0016
0016
0016
(7)
0016
(8)
Port P3 direction register (P3D)
Port P4 (P4)
0016
0016
0016
(9)
X X X X X 1 X X
FFFD16 contents
FFFC16 contents
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
Port P4 direction register (P4D)
Serial I/O2 control register 1 (SIO2CON1)
Serial I/O2 control register 2 (SIO2CON2)
Serial I/O2 register (SIO2)
Transmit/Receive buffer register (TB/RB)
Serial I/O1 status register (SIOSTS)
Serial I/O1 control register (SIOCON)
UART control register (UARTCON)
Baud rate generator (BRG)
PWM control register (PWMCON)
PWM prescaler (PREPWM)
PWM register (PWM)
0016
(PCH)
0016
(PCL)
0 0 0 0 0 1 1 1
X X X X X X X X
001816 X X X X X X X X
1 0 0 0 0 0 0 0
001916
001A16
001B16
0016
1 1 1 0 0 0 0 0
001C16 X X X X X X X X
001D16
001E16
0016
X X X X X X X X
001F16 X X X X X X X X
Prescaler 12 (PRE12)
002016
002116
002216
002316
002416
002516
002616
002716
002816
003416
FF16
Timer 1 (T1)
0116
Timer 2 (T2)
0016
Timer XY mode register (TM)
Prescaler X (PREX)
0016
FF16
Timer X (TX)
FF16
FF16
Prescaler Y (PREY)
Timer Y (TY)
FF16
Timer count source selection register (TCSS)
A-D control register (ADCON)
A-D conversion low-order register (ADL)
A-D conversion high-order register (ADH)
0016
0 0 0 1 0 0 0 0
003516 X X X X X X X X
003616
0 0 0 0 0 0 X X
Note : X : Not fixed
Since the initial values for other than above mentioned registers and
RAM contents are indefinite at reset, they must be set.
Fig. 50 Internal status at reset (spec. H)
Rev.3.01 2003.06.20 page 46 of 98
3850 Group (Spec.A)
Address Register contents
Register contents
Address
(1)
Port P0 (P0)
0 0 0 1 0 0 0 0
X X X X X X X X
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
(34) A-D control register (ADCON)
(35) A-D conversion low-order register (ADL)
(36) A-D conversion high-order register (ADH)
(37) A-D input selection register (ADSEL)
(38) MISRG
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
(PS)
(2)
Port P0 direction register (P0D)
Port P1 (P1)
(3)
0 0 0 0 0 0 X X
0016
(4)
Port P1 direction register (P1D)
Port P2 (P2)
0016
(5)
Watchdog timer control register (WDTCON)
(39)
(6)
0 0 1 1 1 1 1 1
0016
Port P2 direction register (P2D)
Port P3 (P3)
(7)
(40) Interrupt edge selection register (INTEDGE)
(41) CPU mode register (CPUM)
(8)
Port P3 direction register (P3D)
Port P4 (P4)
0 1 0 0 1 0 0 0
0016
Interrupt request register 1 (IREQ1)
(42)
(9)
Interrupt request register 2 (IREQ2)
(43)
0016
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
Port P4 direction register (P4D)
PortP0,P1,P2pull-upcontrolregister(PULL012)
Port P3 pull-up control register (PULL3)
Port P4 pull-up control register (PULL4)
Serial I/O2 control register 1 (SIO2CON1)
Serial I/O2 control register 2 (SIO2CON2)
Serial I/O2 register (SIO2)
Transmit/Receive buffer register (TB/RB)
Serial I/O1 status register (SIOSTS)
Serial I/O1 control register (SIOCON)
UART control register (UARTCON)
Baud rate generator (BRG)
PWM control register (PWMCON)
PWM prescaler (PREPWM)
PWM register (PWM)
Interrupt control register 1 (ICON1)
(44)
0016
Interrupt control register 2 (ICON2)
(45)
0016
X X X X X 1 X X
FFFD16 contents
FFFC16 contents
(46) Processor status register
(47) Program counter
(PCH)
(PC
L
)
0 0 0 0 0 1 1 1
X X X X X X X X
X X X X X X X X
1 0 0 0 0 0 0 0
0016
1 1 1 0 0 0 0 0
X X X X X X X X
0016
X X X X X X X X
X X X X X X X X
Prescaler 12 (PRE12)
FF16
0116
0016
0016
FF16
FF16
FF16
FF16
0016
Timer 1 (T1)
Timer 2 (T2)
Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Prescaler Y (PREY)
Timer Y (TY)
Timer count source selection register (TCSS)
Note : X : Not fixed
Since the initial values for other than above mentioned registers and
RAM contents are indefinite at reset, they must be set.
Fig. 51 Internal status at reset (spec. A)
Rev.3.01 2003.06.20 page 47 of 98
3850 Group (Spec.H/A)
(2) Wait mode
CLOCK GENERATING CIRCUIT
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock φ re-
starts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after
the clock is restarted.
The 3850 group (spec. H/A) has two built-in oscillation circuits. An
oscillation circuit can be formed by connecting a resonator be-
tween XIN and XOUT (XCIN and XCOUT). Use the circuit constants
in accordance with the resonator manufacturer’s recommended
values. No external resistor is needed between XIN and XOUT
since a feed-back resistor exists on-chip. However, an external
feed-back resistor is needed between XCIN and XCOUT.
To ensure that the interrupts will be received to release the STP or
WIT state, their interrupt enable bits must be set to “1” before ex-
ecuting of the STP or WIT instruction.
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
When releasing the STP state, the prescaler 12 and timer 1 will
start counting the clock XIN divided by 16. Accordingly, set the
timer 1 interrupt enable bit to “0” before executing the STP instruc-
tion.
Frequency Control
(1) Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8. After re-
set is released, this mode is selected.
ꢀNote
(2) High-speed mode
The internal clock φ is half the frequency of XIN.
When using the oscillation stabilizing time set after STP instruction
released bit set to “1”, evaluate time to stabilize oscillation of the
used oscillator and set the value to the timer 1 and prescaler 12.
(3) Low-speed mode
The internal clock φ is half the frequency of XCIN.
ꢀNote
If you switch the mode between middle/high-speed and low-
speed, stabilize both XIN and XCIN oscillations. The sufficient time
is required for the sub-clock to stabilize, especially immediately af-
ter power on and at returning from the stop mode. When switching
the mode between middle/high-speed and low-speed, set the fre-
quency on condition that f(XIN) > 3•f(XCIN).
XCIN XCOUT
XIN
XOUT
Rf
Rd
(4) Low power dissipation mode
COUT
CCIN
CCOUT
CIN
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set
bit 5 of the CPU mode register to “1”. When the main clock XIN is
restarted (by setting the main clock stop bit to “0”), set sufficient
time for oscillation to stabilize.
Fig. 52 Ceramic resonator circuit
The sub-clock XCIN-XCOUT oscillating circuit can not directly input
clocks that are generated externally. Accordingly, make sure to
cause an external resonator to oscillate.
Oscillation Control
X
CIN
X
COUT
X
IN
XOUT
(1) Stop mode
Open
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillation stops. When the oscillation
stabilizing time set after STP instruction released bit is “0”, the
prescaler 12 is set to “FF16” and timer 1 is set to “0116”. When the
oscillation stabilizing time set after STP instruction released bit is
“1”, set the sufficient time for oscillation of used oscillator to stabi-
lize since nothing is set to the prescaler 12 and timer 1.
Either XIN or XCIN divided by 16 is input to the prescaler 12 as
count source. Oscillator restarts when an external interrupt is re-
ceived, but the internal clock φ is not supplied to the CPU (remains
at “H”) until timer 1 underflows. The internal clock φ is supplied for
the first time, when timer 1 underflows. This ensures time for the
clock oscillation using the ceramic resonators to be stabilized.
When the oscillator is restarted by reset, apply “L” level to the
RESET pin until the oscillation is stable since a wait time will not
be generated.
Rf
Rd
External oscillation
circuit
C
CIN
CCOUT
Vcc
Vss
Fig. 53 External clock input circuit
Rev.3.01 2003.06.20 page 48 of 98
3850 Group (Spec.H/A)
[MISRG (MISRG)] 003816
b7
b0
MISRG
(MISRG : address 003816)
MISRG consists of three control bits (bits 1 to 3) for middle-speed
mode automatic switch and one control bit (bit 0) for oscillation
stabilizing time set after STP instruction released.
Oscillation stabilizing time set after STP instruction
released bit
0: Automatically set “0116” to Timer 1,
“FF16” to Prescaler 12
By setting the middle-speed mode automatic switch start bit to “1”
while operating in the low-speed mode and setting the middle-
speed mode automatic switch set bit to “1”, XIN oscillation
automatically starts and the mode is automatically switched to the
middle-speed mode.
1: Automatically set nothing
Middle-speed mode automatic switch set bit
0: Not set automatically
1: Automatic switching enable
Middle-speed mode automatic switch wait time set bit
0: 4.5 to 5.5 machine cycles
1: 6.5 to 7.5 machine cycles
Middle-speed mode automatic switch start bit
(Depending on program)
0: Invalid
1: Automatic switch start
Not used (return “0” when read)
Note: When the mode is automatically switched from the low-speed mode to
the middle-speed mode, the value of CPU mode register (address 003B16)
changes.
Fig. 54 Structure of MISRG
X
COUT
XCIN
“0”
“1”
Port X
C
switch bit
X
OUT
X
IN
Main clock division ratio
selection bits (Note 1)
Low-speed mode
1/2
High-speed or
middle-speed
mode
Prescaler 12
(Note 3)
Timer 1
1/4
1/2
Reset or
STP instruction
(Note 2)
Main clock division ratio
selection bits (Note 1)
Middle-speed mode
Timing φ (internal clock)
High-speed or
low-speed mode
Main clock stop bit
Reset
Q
S
R
S
R
Q
Q
S
R
STP instruction
STP instruction
WIT instruction
Reset
Interrupt disable flag l
Interrupt request
Notes 1: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
When low-speed mode is selected, set port Xc switch bit (b4) to “1”.
2: f(XIN)/16 is supplied as the count source to the prescaler 12 at reset, the count source
before executing the STP instruction is supplied as the count source at executing STP instruction.
3: When bit 0 of MISRG = “0”, the prescaler 12 is set to "FF16" and timer 1 is set to "0116".
When bit 0 of MISRG = “1”, set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to
the prescaler 12 and timer 1.
Fig. 55 System clock generating circuit block diagram (Single-chip mode)
Rev.3.01 2003.06.20 page 49 of 98
3850 Group (Spec.H/A)
Reset
High-speed mode
(f(φ) = 4 MHz)
Middle-speed mode
(f(φ) = 1 MHz)
CM6
CM7 = 0
CM6 = 0
CM7 = 0
CM6 = 1
“1” ←→ “0”
CM5 = 0 (8 MHz oscillating)
CM4 = 0 (32 kHz stopped)
CM5 = 0 (8 MHz oscillating)
CM4 = 0 (32 kHz stopped)
Middle-speed mode
(f(φ) = 1 MHz)
High-speed mode
(f(φ) = 4 MHz)
CM6
CM7 = 0
CM6 = 1
CM5 = 0 (8 MHz oscillating)
CM4 = 1 (32 kHz oscillating)
“1” ←→ “0”
CM7 = 0
CM6 = 0
CM5 = 0 (8 MHz oscillating)
CM4 = 1 (32 kHz oscillating)
Middle-speed mode
automatic switch set bit
"1"
Low-speed mode
(f(φ)=16 kHz)
CM7 = 1
CM6 = 0
CM5 = 0 (8 MHz oscillating)
CM4 = 1 (32 kHz oscillating)
Middle-speed mode
automatic switch start bit
"1"
b7
b4
CPU mode register
(CPUM : address 003B16)
CM
CM
CM
4
5
7
: Port Xc switch bit
0 : I/O port function (stop oscillating)
1 : XCIN-XCOUT oscillating function
: Main clock (XIN- XOUT) stop bit
0 : Operating
1 : Stopped
, CM
6: Main clock division ratio selection bit
Low-speed mode
(f(φ)=16 kHz)
b7 b6
CM7 = 1
CM6 = 0
CM5 = 1 (8 MHz stopped)
CM4 = 1 (32 kHz oscillating)
0
0
1
1
0 : φ = f(XIN)/2 ( High-speed mode)
1 : φ = f(XIN)/8 (Middle-speed mode)
0 : φ = f(XCIN)/2 (Low-speed mode)
1 : Not available
1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)
2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is
ended.
Notes
3 : Timer operates in the wait mode.
4 : When bit 0 of MISRG is “0” and the stop mode is ended, a delay of approximately 1 ms occurs by connecting timer 1 in middle/high-speed
mode.
5 : When bit 0 of MISRG is “0” and the stop mode is ended, the following is performed.
(1) After the clock is restarted, a delay of approximately 256 ms occurs in low-speed mode if Timer 12 count source selection bit is “0”.
(2) After the clock is restarted, a delay of approximately 16 ms occurs in low-speed mode if Timer 12 count source selection bit is “1”.
6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed
mode.
7 : When the mode is switched to the middle-speed mode by the middle-speed mode automatic switch set bit of MISRG, the waiting time set
by the middle-speed mode automatic switch wait time set bit is automatically generated, and then the mode is switched to the middle-
speed mode.
8 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
Fig. 56 State transitions of system clock
Rev.3.01 2003.06.20 page 50 of 98
3850 Group (Spec.H/A)
FLASH MEMORY MODE
Summary
The M38507F8 (flash memory version) has an internal new
DINOR (DIvided bit line NOR) flash memory that can be rewritten
with a single power source when VCC is 5 V, and 2 power sources
when VPP is 5 V and VCC is 3.0-5.5 V in the CPU rewrite and stan-
dard serial I/O modes.
Table 11 lists the summary of the M38507F8 (flash memory ver-
sion).
The flash memory of the M38507F8 is divided into User ROM area
and Boot ROM area as shown in Figure 57.
In addition to the ordinary User ROM area to store the MCU op-
eration control program, the flash memory has a Boot ROM area
that is used to store a program to control rewriting in CPU rewrite
and standard serial I/O modes. This Boot ROM area has had a
standard serial I/O mode control program stored in it when
shipped from the factory. However, the user can write a rewrite
control program in this area that suits the user’s application sys-
tem. This Boot ROM area can be rewritten in only parallel I/O
mode.
For this flash memory, three flash memory modes are available in
which to read, program, and erase: the parallel I/O and standard
serial I/O modes in which the flash memory can be manipulated
using a programmer and the CPU rewrite mode in which the flash
memory can be manipulated by the Central Processing Unit
(CPU).
Table 11 Summary of M38507F8 (flash memory version)
Item
Specifications
Vcc = 2.7– 5.5 V (Note 1)
Vcc = 2.7–3.6 V (Note 2)
Power source voltage
4.5-5.5 V
VPP voltage (For Program/Erase)
Flash memory mode
3 modes (Parallel I/O mode, Standard serial I/O mode, CPU rewrite mode)
1 block (32 Kbytes)
Erase block division
User ROM area
Boot ROM area
1 block (4 Kbytes) (Note 3)
Byte program
Program method
Erase method
Batch erasing
Program/Erase control by software command
Program/Erase control method
Number of commands
6 commands
100 times
Number of program/Erase times
ROM code protection
Available in parallel I/O mode and standard serial I/O mode
Notes 1: The power source voltage must be Vcc = 4.5–5.5 V at program and erase operation.
2: The power source voltage can be Vcc = 3.0–3.6 V also at program and erase operation.
3: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. This Boot ROM area can be
rewritten in only parallel I/O mode.
Rev.3.01 2003.06.20 page 51 of 98
3850 Group (Spec.H/A)
(1) CPU Rewrite Mode
Microcomputer Mode and Boot Mode
In CPU rewrite mode, the internal flash memory can be operated
on (read, program, or erase) under control of the Central Process-
ing Unit (CPU).
The control program for CPU rewrite mode must be written into
the User ROM or Boot ROM area in parallel I/O mode beforehand.
(If the control program is written into the Boot ROM area, the stan-
dard serial I/O mode becomes unusable.)
In CPU rewrite mode, only the User ROM area shown in Figure 57
can be rewritten; the Boot ROM area cannot be rewritten. Make
sure the program and block erase commands are issued for only
the User ROM area and each block area.
See Figure 57 for details about the Boot ROM area.
Normal microcomputer mode is entered when the microcomputer
is reset with pulling CNVSS pin low. In this case, the CPU starts
operating using the control program in the User ROM area.
When the microcomputer is reset by pulling the P41/INT0 pin high,
the CNVss pin high, the CPU starts operating using the control
program in the Boot ROM area (program start address is FFFC16,
FFFD16 fixation). This mode is called the “Boot” mode.
The control program for CPU rewrite mode can be stored in either
User ROM or Boot ROM area. In the CPU rewrite mode, because
the flash memory cannot be read from the CPU, the rewrite con-
trol program must be transferred to internal RAM area to be
executed before it can be executed.
Block Address
Block addresses refer to the maximum address of each block.
These addresses are used in the block erase command. In case
of the M38507F8, it has only one block.
Parallel I/O mode
800016
F00016
4 kbyte
FFFF16
Block 1 : 32 kbyte
FFFF16
User ROM area
Boot ROM area
BSEL = 0
BSEL = 1
CPU rewrite mode, standard serial I/O mode
800016
F00016
4 kbyte
FFFF16
Block 1 : 32 kbyte
Flash memory
start address
Product name
FFFF16
User ROM area
Boot ROM area
M38507F8
800016
User area / Boot area selection bit = 0
User area / Boot area selection bit = 1
Notes 1: The Boot ROM area can be rewritten in only parallel
input/output mode. (Access to any other areas is inhibited.)
2: To specify a block, use the maximum address in the block.
Fig. 57 Block diagram of built-in flash memory
Rev.3.01 2003.06.20 page 52 of 98
3850 Group (Spec.H/A)
Outline Performance (CPU Rewrite Mode)
CPU rewrite mode is usable in the single-chip or Boot mode. The
only User ROM area can be rewritten in CPU rewrite mode.
In CPU rewrite mode, the CPU erases, programs and reads the in-
ternal flash memory by executing software commands. This
rewrite control program must be transferred to the RAM before it
can be executed.
Therefore, use the control program in the RAM for write to bit 1. To
set this bit to “1”, it is necessary to write “0” and then write “1” in
succession. The bit can be set to “0” by only writing “0”.
Bit 2 is the CPU Rewrite Mode Entry Flag. This flag indicates “1” in
CPU rewrite mode, so that reading this flag can check whether
CPU rewrite mode has been entered or not.
Bit 3 is the flash memory reset bit used to reset the control circuit
of internal flash memory. This bit is used when exiting CPU rewrite
mode and when flash memory access has failed. When the CPU
Rewrite Mode Select Bit is “1”, setting “1” for this bit resets the
control circuit. To set this bit to “1”, it is necessary to write “0” and
then write “1” in succession. To release the reset, it is necessary
to set this bit to “0”.
The MCU enters CPU rewrite mode by applying 5 V ± 0.5 V to the
CNVSS pin and setting “1” to the CPU Rewrite Mode Select Bit (bit
1 of address 0FFE16). Software commands are accepted once the
mode is entered.
Use software commands to control program and erase operations.
Whether a program or erase operation has terminated normally or
in error can be verified by reading the status register.
Bit 4 is the User Area/Boot Area Select Bit. When this bit is set to
“1”, Boot ROM area is accessed, and CPU rewrite mode in Boot
ROM area is available. In Boot mode, this bit is set to “1” auto-
matically. Reprogramming of this bit must be in the RAM.
Figure 59 shows a flowchart for setting/releasing CPU rewrite
mode.
Figure 58 shows the flash memory control register.
Bit 0 is the RY/BY status flag used exclusively to read the operat-
ing status of the flash memory. During programming and erase
operations, it is “0” (busy). Otherwise, it is “1” (ready).
Bit 1 is the CPU Rewrite Mode Select Bit. When this bit is set to
“1”, the MCU enters CPU rewrite mode. Software commands are
accepted once the mode is entered. In CPU rewrite mode, the
CPU becomes unable to access the internal flash memory directly.
b7
b0
Flash memory control register (address 0FFE16) (Note 1)
FMCR
RY/BY status flag
0: Busy (being programmed or erased)
1: Ready
CPU rewrite mode select bit (Note 2)
0: Normal mode (Software commands invalid)
1: CPU rewrite mode (Software commands acceptable)
CPU rewrite mode entry flag
0: Normal mode
1: CPU rewrite mode
Flash memory reset bit (Note 3)
0: Normal operation
1: Reset
User ROM area / Boot ROM area select bit (Note 4)
0: User ROM area accessed
1: Boot ROM area accessed
Reserved bits (Indefinite at read/ “0” at write)
Notes 1: The contents of flash memory control register are “XXX00001” just after reset release. In the mask
ROM version, this address is reserved area.
2: For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession. If it is not
this procedure, this bit will not be set to “1”. Additionally, it is required to ensure that no interrupt
will be generated during that interval.
Use the control program in the area except the built-in flash memory for write to this bit.
3: This bit is valid when the CPU rewrite mode select bit is “1”. Set this bit 3 to “0” subsequently after
setting bit 3 to “1”.
4: Use the control program in the area except the built-in flash memory for write to this bit.
Fig.58 Structure of flash memory control register
Rev.3.01 2003.06.20 page 53 of 98
3850 Group (Spec.H/A)
Start
Single-chip mode or Boot mode (Note 1)
Set CPU mode register (Note 2)
Transfer CPU rewrite mode control program
to RAM
Setting
Jump to control program transferred in RAM
(Subsequent operations are executed by control
program in this RAM)
Set CPU rewrite mode select bit to “1” (by
writing “0” and then “1” in succession)
Check CPU rewrite mode entry flag
Using software command execute erase,
program, or other operation
Execute read array command or reset flash
memory by setting flash memory reset bit (by
writing “1” and then “0” in succession) (Note 3)
Released
Write “0” to CPU rewrite mode select bit
End
Notes 1: When starting the MCU in the single-chip mode, supply 4.5 V to 5.25 V to the
CNVss pin until checking the CPU rewrite mode entry flag.
2: Set bits 6, 7 (main clock division ratio selection bits) at CPU mode register (003B16).
3: Before exiting the CPU rewrite mode after completing erase or program operation,
always be sure to execute the read array command or reset the flash memory.
Fig. 59 CPU rewrite mode set/release flowchart
Rev.3.01 2003.06.20 page 54 of 98
3850 Group (Spec.H/A)
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting
the flash memory in CPU rewrite mode.
(1) Operation speed
During CPU rewrite mode, set the internal clock frequency 6.25
MHz or less using the main clock division ratio selection bits (bit
6, 7 at 003B16).
(2) Instructions inhibited against use
The instructions which refer to the internal data of the flash
memory cannot be used during CPU rewrite mode .
(3) Interrupts inhibited against use
The interrupts cannot be used during CPU rewrite mode be-
cause they refer to the internal data of the flash memory.
(4) Watchdog timer
In case of the watchdog timer has been running already, the in-
ternal reset generated by watchdog timer underflow does not
happen, because of watchdog timer is always clearing during
program or erase operation.
(5) Reset
Reset is always valid. In case of CNVSS = H when reset is re-
leased, boot mode is active. So the program starts from the ad-
dress contained in address FFFC16 and FFFD16 in boot ROM
area.
Rev.3.01 2003.06.20 page 55 of 98
3850 Group (Spec.H/A)
Software Commands (CPU Rewrite Mode)
Table 12 lists the software commands.
register mode is entered automatically and the contents of the sta-
tus register is read at the data bus (D0 to D7). The status register
bit 7 (SR7) is set to “0” at the same time the write operation starts
and is returned to “1” upon completion of the write operation. In
this case, the read status register mode remains active until the
After setting the CPU Rewrite Mode Select Bit of the flash memory
control register to “1”, execute a software command to specify an
erase or program operation.
Each software command is explained below.
next command is written.
____
The RY/BY Status Flag is “0” (busy) during write operation and “1”
(ready) when the write operation is completed as is the status reg-
ister bit 7.
ꢀRead Array Command (FF16)
The read array mode is entered by writing the command code
“FF16” in the first bus cycle. When an address to be read is input in
one of the bus cycles that follow, the contents of the specified ad-
dress are read out at the data bus (D0 to D7).
At program end, program results can be checked by reading bit 4
(SR4) of the status register.
The read array mode is retained intact until another command is
written.
Start
ꢀRead Status Register Command (7016)
Write 4016
The read status register mode is entered by writing the command
code “7016” in the first bus cycle. The contents of the status regis-
ter are read out at the data bus (D0 to D7) by a read in the second
bus cycle.
Write address
Write
Write data
The status register is explained in the next section.
Status register
read
ꢀClear Status Register Command (5016)
This command is used to clear the bits SR1, SR4, and SR5 of the
status register after they have been set. These bits indicate that
operation has ended in an error. To use this command, write the
command code “5016” in the first bus cycle.
SR7 = 1 ?
NO
or
RY/BY = 1 ?
ꢀProgram Command (4016)
YES
Program operation starts when the command code “4016” is writ-
ten in the first bus cycle. Then, if the address and data to program
are written in the 2nd bus cycle, program operation (data program-
ming and verification) will start.
NO
Program
error
SR4 = 0 ?
YES
Whether the write operation is completed can be confirmed by
_____
reading the status register or the RY/BY Status Flag of the flash
memory control register. When the program starts, the read status
Program completed
(Read array command
“FF16” write)
Fig. 60 Program flowchart
First bus cycle
Table 12 List of software commands (CPU rewrite mode)
Second bus cycle
Command
Cycle number
Data
to D7)
Data
to D7)
Mode
Address
Mode
Address
(D
0
(D0
(Note 1)
Read array
1
2
1
Write
Write
Write
X
FF16
7016
5016
(Note 2)
Read status register
Clear status register
X
X
Read
X
SRD
(Note 3)
(Note 3)
Program
2
2
2
Write
Write
Write
X
X
X
4016
2016
2016
Write
Write
Write
WA
WD
Erase all blocks
Block erase
X
2016
D016
(Note 4)
BA
Notes 1: X denotes a given address in the User ROM area .
2: SRD = Status Register Data
3: WA = Write Address, WD = Write Data
4: BA = Block Address to be erased (Input the maximum address of each block.)
Rev.3.01 2003.06.20 page 56 of 98
3850 Group (Spec.H/A)
ꢀErase All Blocks Command (2016/2016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “2016” in the second bus cycle that
follows, the operation of erase all blocks (erase and erase verify)
starts.
Start
Whether the erase all blocks command is terminated can be con-
____
Write 2016
firmed by reading the status register or the RY/BY Status Flag of
flash memory control register. When the erase all blocks operation
starts, the read status register mode is entered automatically and
the contents of the status register can be read out at the data bus
(D0 to D7). The status register bit 7 (SR7) is set to “0” at the same
time the erase operation starts and is returned to “1” upon comple-
tion of the erase operation. In this case, the read status register
2016/D016
Block address
2016:Erase all blocks command
D016:Block erase command
Write
Status register
read
mode remains active until another command is written.
____
SR7 = 1 ?
or
RY/BY = 1 ?
The RY/BY Status Flag is “0” during erase operation and “1” when
the erase operation is completed as is the status register bit 7
(SR7).
NO
NO
YES
After the erase all blocks end, erase results can be checked by
reading bit 5 (SRS) of the status register. For details, refer to the
section where the status register is detailed.
Erase error
SR5 = 0 ?
YES
ꢀBlock Erase Command (2016/D016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “D016” and the blobk address in the
second bus cycle that follows, the block erase (erase and erase
verify) operation starts for the block address of the flash memory
to be specified.
Erase completed
(Read comand “FF16
”
write)
Whether the block erase operation is completed can be confirmed
____
by reading the status register or the RY/BY Status Flag of flash
memory control register. At the same time the block erase opera-
tion starts, the read status register mode is automatically entered,
so that the contents of the status register can be read out. The
status register bit 7 (SR7) is set to “0” at the same time the block
erase operation starts and is returned to “1” upon completion of
the block erase operation. In this case, the read status register
mode remains active until the read array command (FF16) is writ-
Fig. 61 Erase flowchart
ten.
____
The RY/BY Status Flag is “0” during block erase operation and “1”
when the block erase operation is completed as is the status reg-
ister bit 7.
After the block erase ends, erase results can be checked by read-
ing bit 5 (SRS) of the status register. For details, refer to the
section where the status register is detailed.
Rev.3.01 2003.06.20 page 57 of 98
3850 Group (Spec.H/A)
Status Register (SRD)
•Erase status (SR5)
The status register shows the operating status of the flash
memory and whether erase operations and programs ended suc-
cessfully or in error. It can be read in the following ways:
(1) By reading an arbitrary address from the User ROM area after
writing the read status register command (7016)
The erase status indicates the operating status of erase operation.
If an erase error occurs, it is set to “1”. When the erase status is
cleared, it is set to “0”.
•Program status (SR4)
(2) By reading an arbitrary address from the User ROM area in the
period from when the program starts or erase operation starts
to when the read array command (FF16) is input.
The program status indicates the operating status of write opera-
tion. When a write error occurs, it is set to “1”.
The program status is set to “0” when it is cleared.
Also, the status register can be cleared by writing the clear status
register command (5016).
If “1” is written for any of the SR5 and SR4 bits, the program,
erase all blocks, and block erase commands are not accepted.
Before executing these commands, execute the clear status regis-
ter command (5016) and clear the status register.
Also, if any commands are not correct, both SR5 and SR4 are set
to “1”.
After reset, the status register is set to “8016”.
Table 13 shows the status register. Each bit in this register is ex-
plained below.
•Sequencer status (SR7)
The sequencer status indicates the operating status of the flash
memory. This bit is set to “0” (busy) during write or erase operation
and is set to “1” when these operations ends.
After power-on, the sequencer status is set to “1” (ready).
Table 13 Definition of each bit in status register (SRD)
Definition
Symbol
Status name
“1”
“0”
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Sequencer status
Reserved
Ready
Busy
-
-
Erase status
Program status
Reserved
Terminated in error
Terminated normally
Terminated in error
Terminated normally
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Rev.3.01 2003.06.20 page 58 of 98
3850 Group (Spec.H/A)
Full Status Check
By performing full status check, it is possible to know the execu-
full status check flowchart and the action to be taken when each
error occurs.
tion results of erase and program operations. Figure 62 shows a
Read status register
YES
SR4 = 1 and
SR5 = 1 ?
Command
sequence error
Execute the clear status register command (5016
to clear the status register. Try performing the
)
operation one more time after confirming that the
command is entered correctly.
NO
NO
NO
Should an erase error occur, the block in error
cannot be used.
Erase error
SR5 = 0 ?
YES
Should a program error occur, the block in error
cannot be used.
Program error
SR4 = 0 ?
YES
End (erase, program)
Note: When one of SR5 and SR4 is set to “1”, none of the read array, the program, erase
all blocks, and block erase commands is accepted. Execute the clear status register
command (5016) before executing these commands.
Fig. 62 Full status check flowchart and remedial procedure for errors
Rev.3.01 2003.06.20 page 59 of 98
3850 Group (Spec.H/A)
Functions To Inhibit Rewriting Flash Memory
Version
To prevent the contents of internal flash memory from being read
out or rewritten easily, this MCU incorporates a ROM code protect
function for use in parallel I/O mode and an ID code check func-
tion for use in standard serial I/O mode.
the ROM code protect is turned on, so that the contents of internal
flash memory are protected against readout and modification. The
ROM code protect is implemented in two levels. If level 2 is se-
lected, the flash memory is protected even against readout by a
shipment inspection LSI tester, etc. When an attempt is made to
select both level 1 and level 2, level 2 is selected by default.
If both of the two ROM Code Protect Reset Bits are set to “00”, the
ROM code protect is turned off, so that the contents of internal
flash memory can be read out or modified. Once the ROM code
protect is turned on, the contents of the ROM Code Protect Reset
Bits cannot be modified in parallel I/O mode. Use the serial I/O or
CPU rewrite mode to rewrite the contents of the ROM Code Pro-
tect Reset Bits.
ꢀROM Code Protect Function (in Parallel I/O Mode)
The ROM code protect function is the function to inhibit reading
out or modifying the contents of internal flash memory by using
the ROM code protect control (address FFDB16) in parallel I/O
mode. Figure 63 shows the ROM code protect control (address
FFDB16). (This address exists in the User ROM area.)
If one or both of the pair of ROM Code Protect Bits is set to “0”,
b7
b0
ROM code protect control register (address FFDB16) (Note 1)
ROMCP
1 1
Reserved bits (“1” at read/write)
ROM code protect level 2 set bits (ROMCP2) (Notes 2, 3)
b3b2
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
ROM code protect reset bits (Note 4)
b5b4
0 0: Protect removed
0 1: Protect set bits effective
1 0: Protect set bits effective
1 1: Protect set bits effective
ROM code protect level 1 set bits (ROMCP1) (Note 2)
b7b6
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
Notes 1: This area is on the ROM in the mask ROM version.
2: When ROM code protect is turned on, the internal flash memory is protected
against readout or modification in parallel I/O mode.
3: When ROM code protect level 2 is turned on, ROM code readout by a shipment
inspection LSI tester, etc. also is inhibited.
4: The ROM code protect reset bits can be used to turn off ROM code protect level 1
and ROM code protect level 2. However, since these bits cannot be modified in
parallel I/O mode, they need to be rewritten in standard serial I/O mode or CPU
rewrite mode.
Fig. 63 Structure of ROM code protect control
Rev.3.01 2003.06.20 page 60 of 98
3850 Group (Spec.H/A)
ID Code Check Function (in Standard serial
I/O mode)
Use this function in standard serial I/O mode. When the contents
of the flash memory are not blank, the ID code sent from the pro-
grammer is compared with the ID code written in the flash memory
to see if they match. If the ID codes do not match, the commands
sent from the programmer are not accepted. The ID code consists
of 8-bit data, and its areas are FFD416 to FFDA16. Write a pro-
gram which has had the ID code preset at these addresses to the
flash memory.
Address
FFD416
FFD516
FFD616
FFD716
FFD816
FFD916
FFDA16
FFDB16
ID1
ID2
ID3
ID4
ID5
ID6
ID7
ROM code protect control
Interrupt vector area
Fig. 64 ID code store addresses
Rev.3.01 2003.06.20 page 61 of 98
3850 Group (Spec.H/A)
(2) Parallel I/O Mode
Parallel I/O mode is the mode which parallel output and input soft-
ware command, address, and data required for the operations
(read, program, erase, etc.) to a built-in flash memory. Use the ex-
clusive external equipment flash programmer which supports the
3850 Group (flash memory version). Refer to each programmer
maker’s handling manual for the details of the usage.
User ROM and Boot ROM Areas
In parallel I/O mode, the user ROM and boot ROM areas shown in
Figure 57 can be rewritten. Both areas of flash memory can be oper-
ated on in the same way.
Program and block erase operations can be performed in the user ROM
area. The user ROM area and its block is shown in Figure 57.
The boot ROM area is 4 Kbytes in size. It is located at addresses
F00016 through FFFF16. Make sure program and block erase opera-
tions are always performed within this address range. (Access to any
location outside this address range is prohibited.)
In the Boot ROM area, an erase block operation is applied to only
one 4 Kbyte block. The boot ROM area has had a standard serial I/O
mode control program stored in it when shipped from the Mitsubishi
factory. Therefore, using the device in standard serial I/O mode, you
do not need to write to the boot ROM area.
Rev.3.01 2003.06.20 page 62 of 98
3850 Group (Spec.H/A)
(3) Standard serial I/O Mode
Outline Performance (Standard Serial I/O
Mode)
In standard serial I/O mode, software commands, addresses and
data are input and output between the MCU and peripheral units
(serial programmer, etc.) using 4-wire clock-synchronized serial
I/O (serial I/O1).
The standard serial I/O mode inputs and outputs the software
commands, addresses and data needed to operate (read, pro-
gram, erase, etc.) the internal flash memory. This I/O is clock
synchronized serial. This mode requires the exclusive external
equipment (serial programmer).
The standard serial I/O mode is different from the parallel I/O
mode in that the CPU controls flash memory rewrite (uses the
CPU rewrite mode), rewrite data input and so forth. The standard
serial I/O mode is started by connecting “H” to the P26 (SCLK1) pin
and “H” to the P41 (INT0) pin and “H” to the CNVSS pin (apply 4.5
V to 5.5 V to Vpp from an external source), and releasing the re-
set operation. (In the ordinary microcomputer mode, set CNVss
pin to “L” level.)
In reception, software commands, addresses and program data
are synchronized with the rise of the transfer clock that is input to
the SCLK1 pin, and are then input to the MCU via the RxD pin. In
transmission, the read data and status are synchronized with the
fall of the transfer clock, and output from the TxD pin.
The TxD pin is for CMOS output. Transfer is in 8-bit units with LSB
first.
When busy, such as during transmission, reception, erasing or
program execution, the SRDY1 (BUSY) pin is “H” level. Accord-
ingly, always start the next transfer after the SRDY1 (BUSY) pin is
“L” level.
This control program is written in the Boot ROM area when the
product is shipped from Mitsubishi. Accordingly, make note of the
fact that the standard serial I/O mode cannot be used if the Boot
ROM area is rewritten in parallel I/O mode. Figure 65 shows the
pin connection for the standard serial I/O mode.
Also, data and status registers in a memory can be read after in-
putting software commands. Status, such as the operating state of
the flash memory or whether a program or erase operation ended
successfully or not, can be checked by reading the status register.
Here following explains software commands, status registers, etc.
In standard serial I/O mode, serial data I/O uses the four serial I/O
pins SCLK1, RxD, TxD and SRDY1 (BUSY). The SCLK1 pin is the
transfer clock input pin through which an external transfer clock is
input. The TxD pin is for CMOS output. The SRDY1 (BUSY) pin
outputs “L” level when ready for reception and “H” level when re-
ception starts.
Serial data I/O is transferred serially in 8-bit units.
In standard serial I/O mode, only the User ROM area shown in
Figure 44 can be rewritten. The Boot ROM area cannot.
In standard serial I/O mode, a 7-byte ID code is used. When there
is data in the flash memory, commands sent from the peripheral
unit (programmer) are not accepted unless the ID code matches.
Rev.3.01 2003.06.20 page 63 of 98
3850 Group (Spec.H/A)
Table 14 Description of pin function (Standard Serial I/O Mode)
Pin
Name
Power input
I/O
Description
V
CC,VSS
Apply program/erase protection voltage to Vcc pin and 0 V to Vss pin.
Connect to VCC when VCC = 4.5 V to 5.5 V.
Connect to Vpp (=4.5 V to 5.5 V) when VCC = 2.7 V to 4.5 V.
CNVSS
RESET
CNVSS
I
I
Reset input
Reset input pin. While reset is “L” level, a 20 cycle or longer clock
must be input to XIN pin.
Connect a ceramic resonator or crystal oscillator between XIN and
X
IN
OUT
AVSS
REF
Clock input
I
XOUT pins. To input an externally generated clock, input it to XIN pin
X
Clock output
O
and open XOUT pin.
Analog power supply input
Reference voltage input
Input port P0
Connect AVSS to VSS
.
V
I
I
Enter the reference voltage for AD from this pin.
P0
0
0
to P0
to P1
7
7
Input “H” or “L” level signal or open.
P1
Input port P1
I
Input “H” or “L” level signal or open.
P2
0
to P2
3
Input port P2
RxD input
I
I
Input “H” or “L” level signal or open.
Serial data input pin
P2
P2
P2
P2
4
5
6
7
TxD output
O
I
Serial data output pin
SCLK1 input
Serial clock input pin
BUSY output
Input port P3
Input port P4
Input port P4
O
I
BUSY signal output pin
P30
to P3
4
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” level signal, when reset is released.
P40, P4
2
to P4
4
I
P41
I
Rev.3.01 2003.06.20 page 64 of 98
3850 Group (Spec.H/A)
V
CC
SS
V
P3
P3
P3
P3
P3
0
1
2
3
4
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
V
CC
1
2
3
4
42
41
40
39
38
37
36
35
34
VREF
AVSS
/PWM
/SCMP2
/INT
P4
P4
4
/INT
3
3/INT
2
5
P4
P4
2
1
0
1
P0
P0
P0
P0
P0
P0
P0
P0
P1
P1
P1
P1
P1
P1
P1
P1
0/SIN2
6
P41
1
/INT
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
/SOUT2
/SCLK2
/SRDY2
7
P4
/CNTR
P2
P2
P2
P2 /SCL
P2 /SDA
CNVSS
P2 /XCIN
P2 /XCOUT
0/CNTR
8
B
USY
P27
0
/SRDY1
9
S
CLK1
6
/SCLK1
10
11
12
13
14
15
16
17
18
19
20
21
33
5
/TxD
TxD
32
31
4
/RxD
D
RxD
3
1
30
29
28
27
26
25
24
23
22
2
1
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
/(LED
0
1
2
3
4
5
6
7
)
)
)
)
)
)
)
)
ꢀꢀ2
VPP
1
0
RESET
RESET
X
IN
OUT
SS
ꢀꢀ1
X
V
Mode setup method
Signal
CNVSS
P4
Value
4.5 to 5.5 V
Notes 1: Connect oscillator circuit
2: Connect to Vcc when Vcc = 4.5 V to 5.5 V.
V
V
CC ꢀ 3
CC ꢀ 3
1
Connect to VPP (=4.5 V to 5.5 V) when Vcc = 2.7 V to 4.5 V.
3: It is necessary to apply Vcc only when reset is released.
S
CLK1
VSS → VCC
RESET
Fig. 65 Pin connection diagram in standard serial I/O mode
Rev.3.01 2003.06.20 page 65 of 98
3850 Group (Spec.H/A)
Software Commands (Standard Serial I/O
Mode)
commands via the RxD pin. Software commands are explained
here below.
Table 15 lists software commands. In standard serial I/O mode,
erase, program and read are controlled by transferring software
Table 15 Software commands (Standard serial I/O mode)
1st byte 2nd byte
transfer
3rd byte
4th byte
5th byte
6th byte
When ID is
not verified
.....
Control command
Address
(middle)
Address
(high)
Data
Data
Data
Data
output to
259th byte
Not
acceptable
FF16
1
2
Page read
output
output
output
Data input
to 259th
byte
Data
input
Data
input
Data
input
Address
4116
Address
(high)
Not
acceptable
Page program
(middle)
Not
acceptable
D016
A716
3
4
5
6
Erase all blocks
SRD1
output
SRD
7016
Acceptable
Read status register
Clear status register
ID code check
output
Not
acceptable
5016
Address
(middle)
Address
F516
Address
(high)
ID1
To ID7
Acceptable
ID size
(low)
To
Data
input
Check-
sum
Size
(high)
Size
FA16
Not
acceptable
required
number
of times
7
8
Download function
(low)
Version
data
output
Version
data output
to 9th byte
Version
data
output
Version
data
output
Version
data
output
Version
data
output
Acceptable
Version data output function
FB16
Notes1: Shading indicates transfer from the internal flash memory microcomputer to a programmer. All other data is transferred from an external equipment
(programmer) to the internal flash memory microcomputer.
2: SRD refers to status register data. SRD1 refers to status register 1 data.
3: All commands can be accepted when the flash memory is totally blank.
4: Address high must be “0016”.
Rev.3.01 2003.06.20 page 66 of 98
3850 Group (Spec.H/A)
ꢀPage Read Command
(1) Transfer the “FF16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and
3rd bytes respectively.
This command reads the specified page (256 bytes) in the flash
memory sequentially one byte at a time. Execute the page read
command as explained here following.
(3) From the 4th byte onward, data (D0 to D7) for the page (256
bytes) specified with addresses A8 to A23 will be output se-
quentially from the smallest address first synchronized with the
fall of the clock.
S
CLK1
RxD
TxD
A
8
to
A
16 to
FF16
A
15
A23
data0
data255
S
RDY1(BUSY)
Fig. 66 Timing for page read
ꢀRead Status Register Command
This command reads status information. When the “7016” com-
mand code is transferred with the 1st byte, the contents of the
status register (SRD) with the 2nd byte and the contents of status
register 1 (SRD1) with the 3rd byte are read.
S
CLK1
RxD
TxD
7016
SRD
output
SRD1
output
S
RDY1(BUSY)
Fig. 67 Timing for reading status register
Rev.3.01 2003.06.20 page 67 of 98
3850 Group (Spec.H/A)
ꢀClear Status Register Command
This command clears the bits (SR4, SR5) which are set when the
status register operation ends in error. When the “5016” command
code is sent with the 1st byte, the aforementioned bits are
cleared. When the clear status register operation ends, the SRDY1
(BUSY) signal changes from “H” to “L” level.
S
CLK1
RxD
TxD
5016
S
RDY1(BUSY)
Fig. 68 Timing for clear status register
ꢀPage Program Command
(3) From the 4th byte onward, as write data (D0 to D7) for the
page (256 bytes) specified with addresses A8 to A23 is input
sequentially from the smallest address first, that page is auto-
matically written.
This command writes the specified page (256 bytes) in the flash
memory sequentially one byte at a time. Execute the page pro-
gram command as explained here following.
(1) Transfer the “4116” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 (“0016”) with the
2nd and 3rd bytes respectively.
When reception setup for the next 256 bytes ends, the SRDY1
(BUSY) signal changes from “H” to “L” level. The result of the
page program can be known by reading the status register. For
more information, see the section on the status register.
S
CLK1
RxD
TxD
A
8
to
A
16 to
4116
data0
data255
A
15
A23
SRDY1(BUSY)
Fig. 69 Timing for page program
Rev.3.01 2003.06.20 page 68 of 98
3850 Group (Spec.H/A)
ꢀErase All Blocks Command
When erase all blocks end, the SRDY1 (BUSY) signal changes
from “H” to “L” level. The result of the erase operation can be
known by reading the status register.
This command erases the contents of all blocks. Execute the
erase all blocks command as explained here following.
(1) Transfer the “A716” command code with the 1st byte.
(2) Transfer the verify command code “D016” with the 2nd byte.
With the verify command code, the erase operation will start
and continue for all blocks in the flash memory.
SCLK1
A716
D016
RxD
TxD
SRDY1(BUSY)
Fig. 70 Timing for erase all blocks
Rev.3.01 2003.06.20 page 69 of 98
3850 Group (Spec.H/A)
ꢀDownload Command
This command downloads a program to the RAM for execution.
Execute the download command as explained here following.
(1) Transfer the “FA16” command code with the 1st byte.
(2) Transfer the program size with the 2nd and 3rd bytes.
(3) Transfer the check sum with the 4th byte. The check sum is
added to all data sent with the 5th byte onward.
(4) The program to execute is sent with the 5th byte onward.
When all data has been transmitted, if the check sum matches,
the downloaded program is executed. The size of the program will
vary according to the internal RAM.
S
CLK1
RxD
TxD
Data size Data size
(low) (high)
Program
data
Check
sum
FA16
Program
data
S
RDY1(BUSY)
Fig. 71 Timing for download
Rev.3.01 2003.06.20 page 70 of 98
3850 Group (Spec.H/A)
(1) Transfer the “FB16” command code with the 1st byte.
(2) The version information will be output from the 2nd byte on-
ward.
ꢀVersion Information Output Command
This command outputs the version information of the control pro-
gram stored in the Boot ROM area. Execute the version
information output command as explained here following.
This data is composed of 8 ASCII code characters.
S
CLK1
RxD
TxD
FB16
‘V’
‘E’
‘R’
‘X’
S
RDY1(BUSY)
Fig. 72 Timing for version information output
Rev.3.01 2003.06.20 page 71 of 98
3850 Group (Spec.H/A)
(1) Transfer the “F516” command code with the 1st byte.
(2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 (“0016”)
of the 1st byte of the ID code with the 2nd, 3rd, and 4th bytes
respectively.
ꢀID Check
This command checks the ID code. Execute the boot ID check
command as explained here following.
(3) Transfer the number of data sets of the ID code with the 5th
byte.
(4) Transfer the ID code with the 6th byte onward, starting with the
1st byte of the code.
S
CLK1
RxD
TxD
F516
D416
FF16
0016
ID size
ID1
ID7
S
RDY1(BUSY)
Fig. 73 Timing for ID check
ꢀID Code
When the flash memory is not blank, the ID code sent from the se-
rial programmer and the ID code written in the flash memory are
compared to see if they match. If the codes do not match, the
command sent from the serial programmer is not accepted. An ID
code contains 8 bits of data. Area is, from the 1st byte, addresses
FFD416 to FFDA16. Write a program into the flash memory, which
already has the ID code set for these addresses.
Address
FFD416
ID1
FFD516
FFD616
FFD716
FFD816
FFD916
FFDA16
ID2
ID3
ID4
ID5
ID6
ID7
FFDB16
ROM code protect control
Interrupt vector area
Fig. 74 ID code storage addresses
Rev.3.01 2003.06.20 page 72 of 98
3850 Group (Spec.H/A)
ꢀStatus Register (SRD)
•Sequencer status (SR7)
The status register indicates operating status of the flash memory
and status such as whether an erase operation or a program
ended successfully or in error. It can be read by writing the read
status register command (7016). Also, the status register is
cleared by writing the clear status register command (5016).
Table 16 lists the definition of each status register bit. After releas-
ing the reset, the status register becomes “8016”.
The sequencer status indicates the operating status of the flash
memory.
After power-on and recover from deep power down mode, the se-
quencer status is set to “1” (ready).
This status bit is set to “0” (busy) during write or erase operation
and is set to “1” upon completion of these operations.
•Erase status (SR5)
The erase status indicates the operating status of erase operation.
If an erase error occurs, it is set to “1”. When the erase status is
cleared, it is set to “0”.
•Program status (SR4)
The program status indicates the operating status of write opera-
tion. If a program error occurs, it is set to “1”. When the program
status is cleared, it is set to “0”.
Table 16 Definition of each bit of status register (SRD)
Definition
SRD0 bits
Status name
“1”
“0”
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Sequencer status
Reserved
Ready
Busy
-
-
Erase status
Program status
Reserved
Terminated in error
Terminated normally
Terminated in error
Terminated normally
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Rev.3.01 2003.06.20 page 73 of 98
3850 Group (Spec.H/A)
•Boot update completed bit (SR15)
ꢀStatus Register 1 (SRD1)
This flag indicates whether the control program was downloaded
to the RAM or not, using the download function.
The status register 1 indicates the status of serial communica-
tions, results from ID checks and results from check sum
comparisons. It can be read after the status register (SRD) by writ-
ing the read status register command (7016). Also, status register
1 is cleared by writing the clear status register command (5016).
Table 17 lists the definition of each status register 1 bit. This regis-
ter becomes “0016” when power is turned on and the flag status is
maintained even after the reset.
•Check sum consistency bit (SR12)
This flag indicates whether the check sum matches or not when a
program, is downloaded for execution using the download func-
tion.
•ID check completed bits (SR11 and SR10)
These flags indicate the result of ID checks. Some commands
cannot be accepted without an ID code check.
•Data reception time out (SR9)
This flag indicates when a time out error is generated during data
reception. If this flag is attached during data reception, the re-
ceived data is discarded and the MCU returns to the command
wait state.
Table 17 Definition of each bit of status register 1 (SRD1)
Definition
SRD1 bits
Status name
“1”
“0”
SR15 (bit7)
SR14 (bit6)
SR13 (bit5)
SR12 (bit4)
SR11 (bit3)
SR10 (bit2)
Boot update completed bit
Reserved
Update completed
Not Update
-
-
-
Reserved
-
Checksum match bit
ID check completed bits
Match
00
Mismatch
Not verified
01
Verification mismatch
Reserved
10
11
Verified
SR9 (bit1)
SR8 (bit0)
Data reception time out
Reserved
Time out
-
Normal operation
-
Rev.3.01 2003.06.20 page 74 of 98
3850 Group (Spec.H/A)
Full Status Check
Results from executed erase and program operations can be
known by running a full status check. Figure 75 shows a flowchart
of the full status check and explains how to remedy errors which
occur.
Read status register
YES
SR4 = 1 and
SR5 = 1 ?
Command
sequence error
Execute the clear status register command (5016
to clear the status register. Try performing the
)
operation one more time after confirming that the
command is entered correctly.
NO
NO
NO
Should an erase error occur, the block in error
cannot be used.
Erase error
SR5 = 0 ?
YES
Should a program error occur, the block in error
cannot be used.
Program error
SR4 = 0 ?
YES
End (Erase, program)
Note: When one of SR5 to SR4 is set to “1” , none of the program, erase all blocks
commands is accepted. Execute the clear status register command (5016) before
executing these commands.
Fig. 75 Full status check flowchart and remedial procedure for errors
Rev.3.01 2003.06.20 page 75 of 98
3850 Group (Spec.H/A)
Example Circuit Application for Standard
Serial I/O Mode
Figure 76 shows a circuit application for the standard serial I/O
mode. Control pins will vary according to a programmer, therefore
see a programmer manual for more information.
P41
S
CLK1
Clock input
BUSY output
Data input
SRDY1 (BUSY)
RX
D
TXD
Data output
M38507F8
V
PP power
CNVss
source input
Notes 1: Control pins and external circuitry will vary according to peripheral unit. For more
information, see the peripheral unit manual.
2: In this example, the Vpp power supply is supplied from an external source (writer). To use
the user’s power source, connect to 4.5 V to 5.5 V.
3: It is necessary to apply Vcc to SCLK1 pin only when reset is released.
Fig. 76 Example circuit application for standard serial I/O mode
Rev.3.01 2003.06.20 page 76 of 98
3850 Group (Spec.H/A)
Flash memory Electrical characteristics
Table 18 Absolute maximum ratings
Symbol
Parameter
Power source voltage
Conditions
Ratings
Unit
V
VCC
–0.3 to 6.5
Input voltage P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44,
VREF
VI
–0.3 to VCC +0.3
V
VI
VI
VI
Input voltage P22, P23
Input voltage RESET, XIN
Input voltage CNVSS
–0.3 to 5.8
–0.3 to VCC +0.3
–0.3 to 6.5
V
V
V
All voltages are based on VSS.
Output transistors are cut off.
Output voltage P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44,
XOUT
VO
–0.3 to VCC +0.3
V
VO
Output voltage P22, P23
Power dissipation
–0.3 to 5.8
1000 (Note)
25±5
V
mW
°C
Pd
Ta = 25 °C
Topr
Tstg
Operating temperature
Storage temperature
–40 to 125
°C
Note: The rating becomes 300 mW at the 42P2R-A/E package.
Table 19 Flash memory mode Electrical characteristics
o
(Ta = 25 C, VCC = 4.5 to 5.5V unless otherwise noted)
Limits
Symbol
Parameter
Conditions
Unit
Min.
Typ.
Max.
100
60
IPP1
VPP power source current (read)
VPP power source current (program)
VPP power source current (erase)
VPP power source voltage
VPP = VCC
µA
mA
mA
V
VPP = VCC
VPP = VCC
IPP2
IPP3
VPP
VCC
30
4.5
4.5
5.5
VCC power source voltage
Microcomputer mode operation at
VCC = 2.7 to 5.5V
5.5
3.6
V
V
Microcomputer mode operation at
VCC = 2.7 to 3.6V
3.0
Rev.3.01 2003.06.20 page 77 of 98
3850 Group (Spec.H/A)
NOTES ON PROGRAMMING
A-D Converter
Processor Status Register
The comparator uses capacitive coupling amplifier whose charge
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
will be lost if the clock frequency is too low.
Therefore, make sure that f(XIN) in the middle/high-speed mode is
at least on 500 kHz during an A-D conversion.
Do not execute the STP instruction during an A-D conversion.
Instruction Execution Time
Interrupts
The instruction execution time is obtained by multiplying the fre-
quency of the internal clock φ by the number of cycles needed to
execute an instruction.
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt
request register, execute at least one instruction before perform-
ing a BBC or BBS instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The frequency of the internal clock φ is half of the XIN frequency in
high-speed mode.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction be-
fore executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
NOTES ON USAGE
Differences among 3850 group (standard),
3850 group (spec. H), and 3850 group (spec.
A)
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
(1) The absolute maximum ratings of 3850 group (spec. H/A) is
quency division ratio is 1/(n+1).
smaller than that of 3850 group (standard).
•Power source voltage Vcc = –0.3 to 6.5 V
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not af-
fect the MUL and DIV instruction.
•CNVss input voltage VI = –0.3 to Vcc +0.3 V
(2) The oscillation circuit constants of XIN-XOUT, XCIN-XCOUT may
be some differences between 3850 group (standard) and 3850
group (spec. H/A).
• The execution of these instructions does not change the con-
tents of the processor status register.
(3) Do not write any data to the reserved area and the reserved
bit. (Do not change the contents after rest.)
Ports
(4) Fix bit 3 of the CPU mode register to “1”.
(5) Be sure to perform the termination of unused pins.
The contents of the port direction registers cannot be read. The
following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis-
ter as an index
Handling of Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suit-
able for high frequencies as bypass capacitor between power
source pin (VCC pin) and GND pin (VSS pin) and between power
source pin (VCC pin) and analog power source input pin (AVSS
pin). Besides, connect the capacitor to as close as possible. For
bypass capacitor which should not be located too far from the pins
to be connected, a ceramic capacitor of 0.01 µF–0.1µF is recom-
mended.
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to
a direction register.
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
Serial I/O
EPROM Version/One Time PROM Version/
Flash Memory Version
In clock synchronous serial I/O, if the receive side is using an ex-
ternal clock and it is to output the SRDY1 signal, set the transmit
enable bit, the receive enable bit, and the SRDY1 output enable bit
to “1”.
The CNVss pin is connected to the internal memory circuit block
by a low-ohmic resistance, since it has the multiplexed function to
be a programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVss
pin and Vss pin or Vcc pin with 1 to 10 kΩ resistance.
The mask ROM version track of CNVss pin has no operational in-
terference even if it is connected to Vss pin or Vcc pin via a
resistor.
Serial I/O1 continues to output the final bit from the TXD pin after
transmission is completed.
SOUT2 pin for serial I/O2 goes to high impedance after transmis-
sion is completed.
When an external clock is used as synchronous clock in serial I/
O1 or serial I/O2, write transmission data to the transmit buffer
register or serial I/O2 register while the transfer clock is “H”.
Rev.3.01 2003.06.20 page 78 of 98
3850 Group (Spec.H/A)
Electric Characteristic Differences Among
Mask ROM, Flash Memory, and One Time
PROM Version MCUs
There are differences in electric characteristics, operation margin,
noise immunity, and noise radiation among mask ROM, flash
memory, and One Time PROM version MCUs due to the differ-
ences in the manufacturing processes.
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and buit-
in EPROM version can be read or programmed with a
general-purpose PROM programmer using a special programming
adapter. Set the address of PROM programmer in the user ROM
area.
When manufacturing an application system with the flash memory,
One Time PROM version and then switching to use of the mask
ROM version, perform sufficient evaluations for the commercial
samples of the mask ROM version.
Table 20 Programming adapter
Name of Programming Adapter
PCA4738S-42A
Package
42P4B, 42S1B
42P2R-A/E
PCA4738F-42A
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 77 is recommended to verify programming.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
✽
1. Mask ROM Order Confirmation Form
✽
2. Mark Specification Form
3. Data to be written to ROM, in EPROM form (three identical cop-
ies) or one floppy disk.
Programming with PROM
programmer
DATA REQUIRED FOR One Time PROM
PROGRAMMING ORDERS
The following are necessary when ordering a PROM programming
service:
Screening (Caution)
(150 °C for 40 hours)
✽
1. ROM Programming Confirmation Form
✽
2. Mark Specification Form (only special mark with customer’s
trade mark logo)
3. Data to be programmed to PROM, in EPROM form (three iden-
tical copies) or one floppy disk.
Verification with
PROM programmer
✽For the mask ROM confirmation and the mark specifications, re-
fer to the “Renesas Technology” Homepage Rom ordering
(http://www.renesas.com/eng/rom).
Functional check in
target device
The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Caution :
Fig. 77 Programming and testing of One Time PROM version
Rev.3.01 2003.06.20 page 79 of 98
3850 Group (Spec.H/A)
Electrical characteristics
Absolute maximum ratings
Table 21 Absolute maximum ratings
Symbol
Parameter
Conditions
Ratings
Unit
V
VCC
Power source voltage
–0.3 to 6.5
Input voltage P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44,
VREF
VI
–0.3 to VCC +0.3
V
Input voltage P22, P23
Input voltage RESET, XIN
Input voltage CNVSS
–0.3 to 5.8
VI
VI
VI
V
V
V
All voltages are based on VSS.
Output transistors are cut off.
–0.3 to VCC +0.3
–0.3 to VCC +0.3
Output voltage P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44,
XOUT
–0.3 to VCC +0.3
VO
V
Output voltage P22, P23
Power dissipation
–0.3 to 5.8
1000 (Note)
–20 to 85
VO
V
mW
°C
Pd
Ta = 25 °C
Operating temperature
Storage temperature
Topr
Tstg
–40 to 125
°C
Note : The rating becomes 300mW at the 42P2R-A/E package.
Rev.3.01 2003.06.20 page 80 of 98
3850 Group (Spec.H)
Recommended operating conditions
Table 22 Recommended operating conditions (1) (spec. H)
(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
5.0
Symbol
Parameter
Unit
V
Min.
4.0
Max.
5.5
8 MHz (high-speed mode)
Power source voltage
Power source voltage
VCC
8 MHz (middle-speed mode), 4 MHz (high-speed mode)
2.7
5.0
5.5
VSS
VREF
AVSS
VIA
0
V
V
V
V
V
V
V
V
V
A-D convert reference voltage
Analog power source voltage
Analog input voltage
2.0
VCC
0
AN0–AN4
AVSS
VCC
VCC
“H” input voltage
P00–P07, P10–P17, P20–P27, P30–P34, P40–P44
RESET, XIN, CNVSS
VIH
0.8VCC
“H” input voltage
VIH
0.8VCC
VCC
VIL
0
0
0
“L” input voltage
“L” input voltage
“L” input voltage
P00–P07, P10–P17, P20–P27, P30–P34, P40–P44
0.2VCC
0.2VCC
0.16VCC
VIL
RESET, CNVSS
XIN
VIL
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
“H” total peak output current (Note) P00–P07, P10–P17, P30–P34
“H” total peak output current (Note) P20, P21, P24–P27, P40–P44
“L” total peak output current (Note) P00–P07, P30–P34
“L” total peak output current (Note) P10–P17
–80
–80
80
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
120
80
“L” total peak output current (Note) P20–P27,P40–P44
“H” total average output current (Note)
“H” total average output current (Note)
“L” total average output current (Note)
“L” total average output current (Note)
“L” total average output current (Note)
P00–P07, P10–P17, P30–P34
–40
–40
40
P20, P21, P24–P27, P40–P44
P00–P07, P30–P34
P10–P17
60
P20–P27,P40–P44
40
Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
Rev.3.01 2003.06.20 page 81 of 98
3850 Group (Spec.A)
Recommended operating conditions
Table 23 Recommended operating conditions (1) (spec. A)
(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
5.0
Symbol
Parameter
Unit
V
Min.
4.0
Max.
5.5
12.5 MHz (high-speed mode)
Power source voltage
Power source voltage
12.5 MHz (middle-speed mode), 6 MHz (high-speed mode)
32 kHz (low-speed mode)
2.7
VCC
5.0
5.5
VSS
0
0
V
V
A-D convert reference voltage
Analog power source voltage
Analog input voltage
2.0
VREF
VCC
AVSS
V
AN0–AN8
AVSS
VIA
VCC
VCC
VCC
0.2VCC
0.2VCC
0.16VCC
–80
–80
80
V
“H” input voltage
P00–P07, P10–P17, P20–P27, P30–P34, P40–P44
RESET, XIN, CNVSS
0.8VCC
VIH
V
“H” input voltage
0.8VCC
VIH
V
0
0
0
VIL
V
“L” input voltage
“L” input voltage
“L” input voltage
P00–P07, P10–P17, P20–P27, P30–P34, P40–P44
VIL
V
RESET, CNVSS
XIN
VIL
V
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
“H” total peak output current (Note) P00–P07, P10–P17, P30–P34
“H” total peak output current (Note) P20, P21, P24–P27, P40–P44
“L” total peak output current (Note) P00–P07, P30–P34
“L” total peak output current (Note) P10–P17
120
80
“L” total peak output current(Note) P20–P27,P40–P44
–40
–40
40
“H” total average output current (Note)
“H” total average output current (Note)
“L” total average output current (Note)
“L” total average output current (Note)
“L” total average output current (Note)
P00–P07, P10–P17, P30–P34
P20, P21, P24–P27, P40–P44
P00–P07, P30–P34
P10–P17
60
40
P20–P27,P40–P44
Note : The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
Rev.3.01 2003.06.20 page 82 of 98
3850 Group (Spec.H)
Table 24 Recommended operating conditions (2) (spec. H)
(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
mA
Min.
Max.
IOH(peak)
“H” peak output current
P00–P07, P10–P17, P20, P21, P24–P27, P30–P34,
P40–P44 (Note 1)
–10
IOL(peak)
“L” peak output current (Note 1) P00–P07, P20–P27, P30–P34, P40–P44
P10–P17
10
20
mA
mA
“H” average output current
P00–P07, P10–P17, P20, P21, P24–P27, P30–P34,
P40–P44 (Note 2)
IOH(avg)
IOL(avg)
–5
mA
“L” average output current (Note 2) P00–P07, P20–P27, P30–P34, P40–P44
P10–P17
5
15
8
mA
mA
Internal clock oscillation frequency (VCC = 4.0 to 5.5V) (Note 3)
Internal clock oscillation frequency (VCC = 2.7 to 5.5V) (Note 3)
f(XIN)
f(XIN)
MHz
MHz
4
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms.
3: When the oscillation frequency has a duty cycle of 50%.
Electrical characteristics
Table 25 Electrical characteristics (1) (spec. H)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Test conditions
Min.
Max.
VOH
VOL
VOL
“H” output voltage
IOH = –10 mA
VCC–2.0
V
V
V
V
V
V
P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44
(Note)
VCC = 4.0–5.5 V
IOH = –1.0 mA
VCC = 2.7–5.5 V
IOL = 10 mA
VCC–1.0
“L” output voltage
2.0
1.0
2.0
1.0
P00–P07, P20–P27, P30–P34,
P40–P44
VCC = 4.0–5.5 V
IOL = 1.0 mA
VCC = 2.7–5.5 V
IOL = 20 mA
“L” output voltage
P10–P17
VCC = 4.0–5.5 V
IOL = 10 mA
VCC = 2.7–5.5 V
Note: P25 is measured when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
Rev.3.01 2003.06.20 page 83 of 98
3850 Group (Spec.A)
Table 26 Recommended operating conditions (2) (spec. A)
(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
mA
Min.
Max.
IOH(peak)
“H” peak output current
P00–P07, P10–P17, P20, P21, P24–P27, P30–P34,
P40–P44 (Note 1)
–10
IOL(peak)
“L” peak output current (Note 1) P00–P07, P20–P27, P30–P34, P40–P44
P10–P17
10
20
mA
mA
“H” average output current
P00–P07, P10–P17, P20, P21, P24–P27, P30–P34,
P40–P44 (Note 2)
IOH(avg)
IOL(avg)
–5
mA
“L” average output current (Note 2) P00–P07, P20–P27, P30–P34, P40–P44
P10–P17
5
mA
mA
15
Internal clock oscillation frequency (VCC = 4.0 to 5.5 V) (Note 3)
Internal clock oscillation frequency (VCC = 2.7 to 4.0 V) (Note 3)
f(XIN)
f(XIN)
12.5 MHz
MHz
5Vcc-7.5
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms.
3: When the oscillation frequency has a duty cycle of 50%.
Electrical characteristics
Table 27 Electrical characteristics (1) (spec. A)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Test conditions
Min.
Max.
VOH
VOL
VOL
“H” output voltage
VCC–2.0
IOH = –10 mA
V
V
V
V
V
V
P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44
(Note)
VCC = 4.0–5.5 V
IOH = –1.0 mA
VCC = 2.7–5.5 V
IOL = 10 mA
VCC–1.0
“L” output voltage
2.0
1.0
2.0
1.0
P00–P07, P20–P27, P30–P34,
P40–P44
VCC = 4.0–5.5 V
IOL = 1.0 mA
VCC = 2.7–5.5 V
IOL = 20 mA
“L” output voltage
P10–P17
VCC = 4.0–5.5 V
IOL = 10 mA
VCC = 2.7–5.5 V
Note: P25 is measured when the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
Rev.3.01 2003.06.20 page 84 of 98
3850 Group (Spec.H)
Table 28 Electrical characteristics (2) (spec.H)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
VT+–VT–
Parameter
Unit
V
Test conditions
Min.
Max.
Hysteresis
0.4
0.5
0.5
CNTR0, CNTR1, INT0–INT3
Hysteresis
VT+–VT–
V
RxD, SCLK1, SCLK2, SIN2
____________
VT+–VT–
IIH
Hysteresis
RESET
V
“H” input current
µA
VI = VCC
5.0
P00–P07, P10–P17, P20, P21,
P24–P27, P30–P34, P40–P44
____________
IIH
IIH
IIL
“H” input current RESET, CNVSS
“H” input current XIN
µA
µA
µA
VI = VCC
VI = VCC
VI = VSS
5.0
4
“L” input current
–5.0
P00–P07, P10–P17, P20–P27
P30–P34, P40–P44
____________
IIL
“L” input current RESET,CNVSS
µA
µA
V
VI = VSS
–5.0
5.5
IIL
“L” input current
XIN
VI = VSS
–4
VRAM
RAM hold voltage
2.0
When clock stopped
Rev.3.01 2003.06.20 page 85 of 98
3850 Group (Spec.A)
Table 29 Electrical characteristics (2) (spec.A)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
VT+–VT–
Parameter
Unit
V
Test conditions
Min.
Typ.
0.4
Max.
Hysteresis
CNTR0, CNTR1, INT0–INT3
Hysteresis
VT+–VT–
0.5
0.5
V
RxD, SCLK1, SCLK2, SIN2
____________
VT+–VT–
IIH
Hysteresis
RESET
V
“H” input current
VI = VCC
5.0
µA
P00–P07, P10–P17, P20, P21,
Pin floating, Pull-up
Transistor "off"
VI = VCC
P24–P27, P30–P34, P40–P44
____________
IIH
IIH
IIL
“H” input current RESET, CNVSS
“H” input current XIN
5.0
µA
µA
µA
VI = VCC
4
“L” input current
VI = VSS
–5.0
P00–P07, P10–P17, P20–P27
Pin floating, Pull-up
Transistor "off"
VI = VSS
P30–P34, P40–P44
____________
IIL
IIL
IIL
“L” input current RESET,CNVSS
–5.0
–120
–40
µA
µA
µA
“L” input current
XIN
VI = VSS
–4
“L” input current (at Pull-up)
P00–P07, P10–P17, P20–P27
P30–P34, P40–P44
VI = VSS
–25
–8
–65
VCC = 5.0 V
VI = VSS
–22
µA
VI = 3.0 V
VRAM
RAM hold voltage
When clock stopped
2.0
5.5
V
Rev.3.01 2003.06.20 page 86 of 98
3850 Group (Spec.H)
Table 30 Electrical characteristics (3) (spec. H)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Test conditions
Symbol
ICC
Parameter
Unit
mA
Max.
13
Min.
High-speed mode
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
Power source current
6.8
1.6
High-speed mode
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
mA
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
Except
M38507F8FP/SP
60
200
µA
µA
µA
250
M38507F8FP/SP
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
Except
M38507F8FP/SP
40
55
20
M38507F8FP/SP
µA
µA
70
20
Except
M38507F8FP/SP
Low-speed mode (VCC = 3 V)
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
150
M38507F8FP/SP
µA
µA
µA
Except
M38507F8FP/SP
Low-speed mode (VCC = 3 V)
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
5.0
20
10.0
7.0
M38507F8FP/SP
Middle-speed mode
f(XIN) = 8 MHz
f(XCIN) = stopped
Output transistors “off”
mA
mA
4.0
1.5
Middle-speed mode
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = stopped
Output transistors “off”
Increment when A-D conversion is executed
f(XIN) = 8 MHz
µA
µA
µA
800
0.1
All oscillation stopped
(in STP state)
Ta = 25 °C
1.0
10
Output transistors “off”
Ta = 85 °C
Rev.3.01 2003.06.20 page 87 of 98
3850 Group (Spec.A)
Table 31 Electrical characteristics (3) (spec. A)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Test conditions
Symbol
ICC
Parameter
Unit
mA
Max.
13.0
Min.
Except
M38507F8FP/SP
High-speed mode
f(XIN) = 12.5 MHz
Power source current
6.5
f(XCIN) = 32.768 kHz
Output transistors “off”
M38507F8FP/SP
7.5
5.0
15.0
10
mA
mA
High-speed mode
f(XIN) = 8 MHz
Except
M38507F8FP/SP
f(XCIN) = 32.768 kHz
Output transistors “off”
M38507F8FP/SP
6.8
1.6
13
mA
mA
High-speed mode
f(XIN) = 12.5 MHz (in WIT state)
f(XCIN) = 32.768 kHz
4.5
Output transistors “off”
High-speed mode
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
1.6
4.2
mA
Middle-speed mode
f(XIN) = 12.5 MHz
f(XCIN) = stopped
Except
M38507F8FP/SP
4.0
4.0
3.0
3.0
7.0
8.5
6.5
7.0
mA
mA
mA
mA
M38507F8FP/SP
Output transistors “off”
Middle-speed mode
f(XIN) = 8 MHz
f(XCIN) = stopped
Output transistors “off”
Except
M38507F8FP/SP
M38507F8FP/SP
Middle-speed mode
f(XIN) = 12.5 MHz (in WIT state)
f(XCIN) = stopped
1.5
4.2
mA
Output transistors “off”
Middle-speed mode
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = stopped
Output transistors “off”
1.5
60
4.0
mA
Except
M38507F8FP/SP
Low-speed mode
f(XIN) = stopped
200
µA
f(XCIN) = 32.768 kHz
Output transistors “off”
M38507F8FP/SP
250
40
70
20
150
5
500
70
µA
µA
µA
µA
µA
µA
Except
M38507F8FP/SP
Low-speed mode
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
M38507F8FP/SP
150
55
Except
M38507F8FP/SP
Low-speed mode (VCC = 3 V)
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “off”
M38507F8FP/SP
300
10
Except
M38507F8FP/SP
Low-speed mode (VCC = 3 V)
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
M38507F8FP/SP
20
800
0.1
40
µA
µA
µA
Increment when A-D conversion is executed
f(XIN) = 8 MHz
All oscillation stopped
(in STP state)
Output transistors “off”
1.0
10
Ta = 25 °C
Ta = 85 °C
µA
Rev.3.01 2003.06.20 page 88 of 98
3850 Group (Spec.H)
A-D converter characteristics
Table 32 A-D converter characteristics (spec. H)
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 8 MHz, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
Max.
10
–
–
Resolution
bit
Absolute accuracy (excluding quantization error)
Conversion time
±4
LSB
High-speed mode,
Middle-speed mode
tCONV
61
2tc(XIN)
Low-speed mode
40
35
µs
kΩ
µA
RLADDER
IVREF
Ladder resistor
VREF = 5.0 V
VREF “on”
VREF “off”
Reference power source input current
50
150
200
5.0
5.0
II(AD)
A-D port input current
0.5
µA
Rev.3.01 2003.06.20 page 89 of 98
3850 Group (Spec.A)
A-D converter characteristics
Table 33 A-D converter characteristics (spec. A)
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 12.5 MHz, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
Max.
10
–
–
Resolution
bit
Absolute accuracy (excluding quantization error)
Conversion time
±4
LSB
High-speed mode,
Middle-speed mode
tCONV
61
2tc(XIN)
Low-speed mode
40
35
µs
kΩ
µA
RLADDER
IVREF
Ladder resistor
VREF = 5.0 V
VREF “on”
VREF “off”
Reference power source input current
50
150
200
5.0
5.0
II(AD)
A-D port input current
0.5
µA
Rev.3.01 2003.06.20 page 90 of 98
3850 Group (Spec.H)
Timing requirements
Table 34 Timing requirements (1) (spec. H)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
20
Max.
Reset input “L” pulse width
XIN cycle
ns
tW(RESET)
tC(XIN)
External clock input cycle time
125
50
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input setup time
ns
tWH(XIN)
50
ns
tWL(XIN)
200
80
ns
tC(CNTR)
ns
tWH(CNTR)
tWL(CNTR)
tWH(INT)
80
ns
80
ns
80
ns
tWL(INT)
800
370
370
220
100
1000
400
400
200
200
ns
tC(SCLK1)
ns
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
ns
ns
ns
Serial I/O1 input hold time
ns
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 clock input setup time
Serial I/O2 clock input hold time
ns
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
ns
ns
ns
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Table 35 Timing requirements (2) (spec. H)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
20
Max.
XIN cycle
ns
tW(RESET)
tC(XIN)
Reset input “L” pulse width
External clock input cycle time
250
100
100
500
230
230
230
230
2000
950
950
400
200
2000
950
950
400
300
ns
tWH(XIN)
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input setup time
ns
tWL(XIN)
ns
tC(CNTR)
ns
tWH(CNTR)
tWL(CNTR)
tWH(INT)
ns
ns
ns
tWL(INT)
ns
tC(SCLK1)
ns
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
ns
ns
ns
Serial I/O1 input hold time
ns
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 clock input setup time
Serial I/O2 clock input hold time
ns
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
ns
ns
ns
Note : When f(XIN) = 4 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 4 MHz and bit 6 of address 001A16 is “0” (UART).
Rev.3.01 2003.06.20 page 91 of 98
3850 Group (Spec.A)
Timing requirements
Table 36 Timing requirements (1) (spec. A)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
20
Max.
Reset input “L” pulse width
XIN cycle
ns
tW(RESET)
tC(XIN)
External clock input cycle time
80
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input setup time
32
ns
tWH(XIN)
32
ns
tWL(XIN)
200
80
ns
tC(CNTR)
ns
tWH(CNTR)
tWL(CNTR)
tWH(INT)
80
ns
80
ns
80
ns
tWL(INT)
800
370
370
220
100
1000
400
400
200
200
ns
tC(SCLK1)
ns
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
ns
ns
ns
Serial I/O1 input hold time
ns
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 clock input setup time
Serial I/O2 clock input hold time
ns
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
ns
ns
ns
Note : When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART).
Table 37 Timing requirements (2) (spec. A)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
20
Max.
XIN cycle
ns
tW(RESET)
tC(XIN)
Reset input “L” pulse width
External clock input cycle time
166
66
ns
tWH(XIN)
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input setup time
ns
tWL(XIN)
66
ns
tC(CNTR)
500
230
230
230
230
2000
950
950
400
200
2000
950
950
400
300
ns
tWH(CNTR)
tWL(CNTR)
tWH(INT)
ns
ns
ns
tWL(INT)
ns
tC(SCLK1)
ns
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD-SCLK1)
th(SCLK1-RxD)
tC(SCLK2)
ns
ns
ns
Serial I/O1 input hold time
ns
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 clock input setup time
Serial I/O2 clock input hold time
ns
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
ns
ns
ns
Note : When f(XIN) = 4 MHz and bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when f(XIN) = 4 MHz and bit 6 of address 001A16 is “0” (UART).
Rev.3.01 2003.06.20 page 92 of 98
3850 Group (Spec.H/A)
Switching characteristics
Table 38 Switching characteristics (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
140
tWH (SCLK1)
tWL (SCLK1)
td (SCLK1-TXD)
tv (SCLK1-TXD)
tr (SCLK1)
tC(SCLK1)/2–30
tC(SCLK1)/2–30
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time (Note 2)
Serial I/O2 output valid time (Note 2)
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Fig. 78
–30
30
30
tf (SCLK1)
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tv (SCLK2-SOUT2)
tf (SCLK2)
tC(SCLK2)/2–160
tC(SCLK2)/2–160
200
0
30
30
30
tr (CMOS)
10
10
tf (CMOS)
Notes 1: When the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is “0”.
3: The XOUT pin is excluded.
Table 39 Switching characteristics (2)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Unit
Parameter
Test conditions
Min.
Typ.
Max.
350
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time (Note 2)
Serial I/O2 output valid time (Note 2)
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
tC(SCLK1)/2–50
tC(SCLK1)/2–50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWH (SCLK1)
tWL (SCLK1)
td (SCLK1-TXD)
tv (SCLK1-TXD)
tr (SCLK1)
Fig. 78
–30
50
50
tf (SCLK1)
tC(SCLK2)/2–240
tC(SCLK2)/2–240
tWH (SCLK2)
tWL (SCLK2)
td (SCLK2-SOUT2)
tv (SCLK2-SOUT2)
tf (SCLK2)
400
0
50
50
50
20
20
tr (CMOS)
tf (CMOS)
Notes 1: When the P25/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: When the P01/SOUT2 and P02/SCLK2 P-channel output disable bit of the Serial I/O2 control register 1 (bit 7 of address 001516) is “0”.
3: The XOUT pin is excluded.
Rev.3.01 2003.06.20 page 93 of 98
3850 Group (Spec.H/A)
Measurement output pin
100 pF
CMOS output
Fig. 78 Circuit for measuring output switching characteristics
Rev.3.01 2003.06.20 page 94 of 98
3850 Group (Spec.H/A)
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
CNTR0
CNTR1
0.8VCC
0.2VCC
0.2VCC
tWL(INT)
tWH(INT)
0.8VCC
INT0 to INT3
RESET
tW(RESET)
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN
)
0.8VCC
XIN
0.2VCC
tC(SCLK1), tC(SCLK2)
tWL(SCLK1), tWL(SCLK2)
tWH(SCLK1), tWH(SCLK2)
tr
tf
SCLK1
SCLK2
0.8VCC
0.2VCC
th(SCLK1
th(SCLK2
-
-
R
x
D),
tsu(R
tsu(SIN2
x
D
-
SCLK1),
SCLK2)
SIN2)
-
RXD
SIN2
0.8VCC
0.2VCC
td(SCLK1-TXD),
td(SCLK2-SOUT2)
tv(SCLK1-TXD),
tv(SCLK2-SOUT2)
TXD
SOUT2
Fig. 79 Timing diagram
Rev.3.01 2003.06.20 page 95 of 98
3850 Group (Spec.H/A)
PACKAGE OUTLINE
MMP
42P4B
Plastic 42pin 600mil SDIP
EIAJ Package Code
JEDEC Code
–
Weight(g)
4.1
Lead Material
Alloy 42/Cu Alloy
SDIP42-P-600-1.78
42
22
1
21
Dimension in Millimeters
Symbol
A
Min
–
0.51
–
Nom
–
–
Max
5.5
–
D
A
A
1
2
3.8
–
b
0.35
0.9
0.63
0.22
36.5
12.85
–
–
3.0
0°
0.45
1.0
0.55
1.3
1.03
0.34
36.9
13.15
–
–
–
15°
b1
b2
0.73
0.27
36.7
13.0
1.778
15.24
–
c
D
E
e
e
b1
b
b2
e1
L
SEATING PLANE
–
42P2R-A/E
Plastic 42pin 450mil SSOP
EIAJ Package Code
SSOP42-P-450-0.80
JEDEC Code
Weight(g)
0.63
Lead Material
Alloy 42
e
b2
–
42
22
Recommended Mount Pad
Dimension in Millimeters
F
Symbol
Min
–
0.05
–
0.25
0.13
17.3
8.2
–
11.63
0.3
–
–
–
–
0°
–
–
1.27
Nom
–
–
Max
2.4
–
A
A
A
b
c
D
E
e
H
L
1
21
1
2
A
2.0
0.3
0.15
17.5
8.4
0.8
11.93
0.5
1.765
0.75
–
–
D
G
0.4
0.2
17.7
8.6
–
12.23
0.7
–
A2
A1
e
b
E
y
L1
z
Z
y
–
1
0.9
0.15
10°
–
–
–
–
–
c
z
b2
0.5
11.43
–
Z
1
Detail G
Detail F
e1
I
2
Rev.3.01 2003.06.20 page 96 of 98
3850 Group (Spec.H/A)
42S1B-A
Metal seal 42pin 600mil DIP
EIAJ Package Code
WDIP42-C-600-1.78
JEDEC Code
–
Weight(g)
D
42
22
1
21
Dimension in Millimeters
Symbol
Min
–
1.0
–
0.38
0.7
0.17
–
–
–
–
3.05
–
Nom
–
–
Max
5.0
–
3.44
0.54
0.9
0.33
41.1
15.8
–
A
A1
A2
b
b1
c
D
E
e
e1
–
0.46
0.8
0.25
–
e
Z
b
b1
SEATING PLANE
–
1.778
15.24
–
–
–
L
Z
–
3.05
Rev.3.01 2003.06.20 page 97 of 98
3850 Group (Spec.H/A)
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer’s application; they
do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party.
2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers
contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed
herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page
(http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information
as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage,
liability or other loss resulting from the information contained herein.
5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially
at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained
herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be
imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
http://www.renesas.com
Copyright © 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan.
Rev.3.01 2003.06.20 page 98 of 98
3850 Group (Spec.H/A) Data Sheet
REVISION HISTORY
Rev.
1.0
Date
03/09/00
Description
Summary
Page
1.00 Mar. 9, 2000
1.10 Mar. 22, 2000
–
First edition issued
Font errors are revised.
2.00 Dec. 22, 2000 1
“lnterrupts” of “FEATURES” is revised.
1
6
17
23
27
33
36
Figure 1 is partly revised.
Table 3 is partly revised.
Explanations of “INTERRUPTS” are partly revised.
Figure 20 is partly revised.
Figure 24 is partly revised.
Explanations of “RESET CIRCUIT” are partly revised.
Note 1 into Figure 42 is partly revised.
38 to 71
41
72
Explanations of “FLASH MEMORY VERSION” are added.
Figure 45 is partly revised.
“EPROM Version/One Time PROM Version/Flash Memory Version” of “NOTES
ON USAGE” is added.
73
73
73
77
79
79
“DATA REQUIRED FOR MASK ORDERS” is added.
“DATA REQUIRED FOR One Time PROM PROGRAMMING ORDERS” is added.
“ROM PROGRAMMING METHOD” is added.
Table 32 is partly revised.
Limit of tw(RESET) into Table 34 is revised.
Limit of tw(RESET) into Table 35 is revised.
●Explanations of “Spec. A” are added.
3.00 May. 29, 2002
P2, P4, P6, P16, P18, P22-P26, P42,P43, P47, P82, P84, P87, P89, P91
●Power dissipation is partly revised.
Figure 5 is partly revised.
Figure 6 is partly revised.
Table 3 3850 group (standard) and 3850 group (spec. H) corresponding products
of Rev.2.0 is eliminated.
1
7
8
9
Table 4 is added.
Table 5 is partly added.
Clause name and explanations of “Notes on differences among 3850 group
(standard), 3850 group (spec. H), and 3850 group (spec. A)” are partly added.
Explanations of “CENTRAL PROCESSING UNIT (CPU)” are partly added.
Figure 9 is partly revised.
Figure 11 is partly revised.
●Notes is revised.
●Notes is partly added.
●Notes on serial I/O is added.
Figure 55 is partly revised.
Explanations of “FLASH MEMORY MODE” is partly revised.
Table 11 is partly revised.
Clause name of “Microcomputer Mode and Boot Mode” is revised.
Explanations of “Outline Performance (CPU Rewrite Mode)” are partly revised.
Figure 58 is partly revised.
9
9
9
10
13
15
27
30
35
49
51
51
52
53
53
54
55
56
56
56
56
Figure 59 is partly revised.
Explanations of “(1) Operation speed” are partly revised.
Explanations of “Software Commands (CPU Rewrite Mode)” are partly revised.
Explanations of “●Read Array Command (FF16)” are partly eliminated.
Explanations of “●Read Status Register Command (7016)” are partly revised.
Explanations of “●Program Command (4016)” are partly revised.
(1/3)
3850 Group (Spec.H/A) Data Sheet
REVISION HISTORY
Rev.
Date
Description
Summary
Page
3.00 May. 29, 2002 57
Explanations of “●Erase All Blocks Command (2016/2016)” are partly revised.
Explanations of “●Block Erase Command (2016/D016)” are partly revised.
Explanations of “Status Register (SRD)” are partly revised.
Figure 62 is partly revised.
Explanations of “●ROM Code Protect Function (in Parallel I/O Mode)” is partly
revised.
57
58
59
60
60
62
Figure 63 is partly revised.
Contents of “(2) Parallel I/O Mode” are revised.
(Explanations, figures, and tables of Pages 61–67 in Rev. 2.0 except “Parallel
I/O Mode” and “User ROM and Boot ROM Areas” are eliminated.)
Explanations of “(3) Standard serial I/O Mode” are partly revised.
Figure 65 is partly revised.
Limits of VI (CNVss) into Table 18 are revised.
Item of VIL, VIH into Table 19 are eliminated.
Figures and tables of Pages 79–84 in Rev. 2.0 are eliminated.
Explanations of “A-D converter” are partly eliminated.
Clause name and explanations of “Differences among 3850 group (standard),
3850 group (spec. H), and 3850 group (spec. A)” are partly revised.
“Electric Characteristic Differences Among Mask ROM, Flash Memory, and One
Time PROM Version MCUs” is added.
63
65
77
77
77
78
78
79
86
Test conditions of Low-speed mode of Icc are partly added.
3.01 Jun. 20, 2003
2
SCLK → SCLK1
Power dissipation is partly revised.
In high-speed mode .... 34mW
→ In high-speed mode
Except M38507F8FP/SP ... 32.5mW
M38507F8/SP.... 37.5mW
8
8
Mitsubishi → Renesas Technology
Delete the following : Products under development or planning: the development
schedule and specification may be revised without notice. The development of
planning products may be stopped.
49
50
79
Fig.55 System clock generating circuit block diagram (Single-chip mode)
Note is partly added.
Fig.56 State transition of system clock
Note is partly added.
the “Mitsubishi MCU Technical information ” Homepage
(http://www.infomicom.maec.co.jp/indexe.html)
→the “Renesas Technology” Homepage Rom ordering
(http://www.renesas.com/eng/rom)
85
Table 28 Electrical characteristics (2)
Separate spec.H and spec.A
85,86
86
VT+–VT- RXD, SCLK → RXD, SCLK1, SCLK2, SIN2
Table 29 Electrical characteristics (2)
Limit of “L” input current (at Pull-up) is added
Table 31 Electrical characteristics (3)
88
Limit of power source current is partly revised.
Limit of M38507F8FP/SP is added
Limit of the high-speed mode [f(XIN)=8MHZ] is added.
Limit of the high-speed mode [f(XIN)=8MHZ(in WIT state)] is added.
Limit of the middle-speed mode [f(XIN)=12.5MHZ] is added.
Limit of the middle-speed mode [f(XIN)=12.5MHZ(in WIT state)] is added.
(2/3)
3850 Group (Spec.H/A) Data Sheet
REVISION HISTORY
Rev.
Date
Description
Summary
Page
3.01 Jun. 20, 2003 88
Limit of the high-speed mode [f(XIN)=12.5MHZ(in WIT state)] is partly added.
Limit of the high-speed mode [f(XIN)=12.5MHZ, Except M38507F8FP/SP] is revised.
Typ. : 7.5 mA → 6.5 mA,
Limit of the middle-speed mode [f(XIN)=8MHZ, Except M38507F8FP/SP] is revised.
Typ. : 4.0 mA → 3.0 mA, Max. : 7.0 mA → 6.5 mA
Max. : 15 mA → 13 mA
(3/3)
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