RTD2120L [REALTEK]
8051 Embedded Micro-Controller for Monitor;型号: | RTD2120L |
厂家: | Realtek Semiconductor Corp. |
描述: | 8051 Embedded Micro-Controller for Monitor |
文件: | 总37页 (文件大小:525K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Realtek
RTD2120-series
RTD2120-series
8051 Embedded Micro-Controller for Monitor
Fully Technology
Revision
Version 1.06
Last updated: 2007/4/3
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Realtek
RTD2120-series
Revision History
Rev.
Description
Date
1.02
1. CLKO2( XFR FF01[1] ) default value 1 à 0
2. PLL_TEST(XFR FF10[7] ) à PLL_STA
3. revise the “Reset table”
2006/2/9
1.03
1.
2.
3.
4.
revise the SFR table à delete address 93 , B3
add PWM description
2006/8/1
add power supply current
add description “All NC pin must be left unconnected or be connected
to GND.”
1.04
1. added RTD2120K, QFP44 pin config.
2. added RTD2120K, QFP44 pin description.
1. added reset pulse minimum length is 16 MCU clk cycle (page-10)
1. modified WDT block diagram
2007/1/16
1.05
1.06
2007/2/9
2007/4/3
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Realtek
RTD2120-series
Overview
This chip is the micro-processor of LCD monitor. It uses the Designware DW8051 of Synopsys
as the 8051 core of this chip and is compatible with other industry 8051 series. Also, 96Kbyte
FLASH with 8 bit bus is embedded in this chip which is licensed from TSMC 0.18um e-FLASH
process. Here we use the package of PLCC44/LQFP48/QFP44 if we would like to have a discrete
MCU controller or we make a multi-chip package with our LCD monitor controller to form one
chip package to save the cost of package and PCB material.
Features
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Operating voltage range : 3.0V to 3.6V
8051 core, CPU operating frequency up to 50MHz
4 clocks per machine cycle
256-byte internal RAM
512-byte external data RAM, including 256-byte DDC RAM(128-byte x 2) and 256-byte
general purpose RAM
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96K-byte flash memory, 64k for program and 32k for saving parameter
Two DDC ports compliant with VESA DDC1/2B/2Bi/CI
Three channels of PWM DAC with programmable frequency from 100K to 100Hz
Watchdog timer with programmable interval
Three 16-bit counters/timers (T0, T1, and T2)
One PLL to provide programmable operating frequency and clock output, 2 clock output
ports
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One full-duplex serial port
Six interrupt sources with 2 external interrupts
Four channels of 6-bit ADC
Hardware In System Programming(ISP) capability, no boot code required
Built-in Low voltage reset circuit
Embedded 1.8V regulator
Code protection
Available in 44-pin PLCC, 44-pin QFP or 48-pin LQFP package
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Realtek
RTD2120-series
Pin Configurations
P5.5/PWM5
DSCL/P5.6
DSDA/P5.7
RST
7
8
39
38
P1.4
P1.5
P1.6
9
37
36
35
34
10
11
12
P1.7
NC
ASCL/P3.0/RXD
RTD2120S
44-PIN
NC
NC
NC
PLCC
ASDA/P3.1/TXD
13
14
15
16
33
32
31
30
P3.2/INT0
P3.3/INT1
VSYNC
P6.7
P3.4/T0
P3.5/T1
P6.6/CLKO1
P6.5
17
29
P5.5/PWM5
DSCL/P5.6
DSDA/P5.7
RST
36
35
34
33
32
31
30
29
28
27
26
25
P1.4
P1.5
P1.6
1
2
3
4
5
6
P1.7
NC
ASCL/P3.0/RXD
RTD2120L
48-PIN
NC
NC
NC
NC
NC
7
8
LQFP
ASDA/P3.1/TXD
9
P3.2/INT0
P3.3/INT1
VSYNC
P6.7
10
P3.4/T0
P3.5/T1
11
12
P6.6/CLKO1
P6.5
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Realtek
RTD2120-series
P5.5/PWM5
DSCL/P5.6
DSDA/P5.7
RST
1
2
33
32
P1.4
P1.5
P1.6
3
4
31
30
P1.7
NC
ASCL/P3.0/RXD
5
6
29
28
RTD2120K
44-PIN
QFP
NC
NC
NC
ASDA/P3.1/TXD
7
8
27
26
25
24
P3.2/INT0
P3.3/INT1
VSYNC
P6.7
9
10
P3.4/T0
P3.5/T1
P6.6/CLKO1
P6.5
11
23
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RTD2120-series
Block Diagram
DDC_RAM1 DDC_RAM2
128 byte 128 byte
TSMC FLASH
96K byte
Internal RAM
256 byt`e
F900-F97F
F980-F9FF
00-FF
Routing
Box
FLASH/ISP
interface
IRAM_bus
Watch dog
timer
I2C slave 1
I2C slave 2
Timer 2
Timer 0
Interrupt
Controller
MEM_bus
PWM
XFR
register
generator
Serial
port 0
Timer 1
External RAM
FF00
Interface
-FFFF
6 bit ADC
DW8051_core
External RAM
256 byte
PLL
(clock gen.)
XTAL
GPIO
F800-F8FF
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RTD2120-series
Pin Description
Pin No.
Name
I/O
Internal Default Pin Type
Description
Pull
output
PLCC LQFP QFP
Up/Down value
44
48
44
2
44
40
P5.0/PWM0
P5.1/PWM1
P5.2/PWM2
P5.3/PWM3
P5.4/PWM4
P5.5/PWM5
P5.6/DSCL
P5.7/DSDA
RST
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
--
--
1(P5.0)
1(P5.1)
1(P5.2)
1(P5.3)
1(P5.4)
1(P5.5)
1(P5.6)
1(P5.7)
0
Open General purpose I/O /
Drain
Open General purpose I/O /
Drain PWM1 output
Open General purpose I/O /
Drain PWM2 output
Open General purpose I/O /
Drain PWM3 output
Open General purpose I/O /
Drain PWM4 output
Open General purpose I/O /
Drain PWM5 output
Open General purpose I/O /
Drain DVI DDC SCL
Open General purpose I/O /
PWM0 output
3
4
45
46
47
48
1
41
42
43
44
1
--
5
--
6
--
7
--
8
2
2
--
9
3
3
--
Drain
DVI DDC SDA
10
11
4
4
Down
--
Input
High active RESET
5
5
ASCL/P3.0/RXD I/O
ASDA/P3.1/TXD I/O
1(ASCL)
Open
ADC DDC SCL /
Drain General purpose I/O /
RXD
13
8
7
--
1(ASDA) Open
ADC DDC SDA /
Drain General purpose I/O /
TXD
14
15
16
17
18
19
20
21
22
9
8
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P7.6/CLKO2
P7.7
I/O
I/O
I/O
I/O
I/O
I/O
O
--
--
1(P3.2) Standard General purpose I/O /
8051
1(P3.3) Standard General purpose I/O /
8051 External interrupt 1
1(P3.4) Standard General purpose I/O /
8051 Timer 0
1(P3.5) Standard General purpose I/O /
8051 Timer 1
External interrupt 0
10
11
12
13
14
15
16
17
9
10
11
12
13
14
15
16
--
--
Up
Up
--
1
Push-Pull General purpose I/O /
Clock out 2
1
Push-Pull General purpose I/O
XO
--
--
--
--
--
--
Crystal out
Crystal in
Ground
XI
I
--
VSS
--
--
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Realtek
RTD2120-series
Pin No.
PLCC LQFP QFP
Name
I/O
Internal Default Pin Type
Description
Pull
output
Up/Down value
24
25
26
27
28
29
30
31
32
36
20
21
22
23
24
25
26
27
28
33
18
19
20
21
22
23
24
25
26
30
P6.0/ADC0
P6.1/ADC1
P6.2/ADC2
P6.3/ADC3
P6.4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Up
Up
1(P6.0) Push-Pull General purpose I/O /
ADC 0 input
1(P6.1) Push-Pull General purpose I/O /
ADC 1 input
1(P6.2) Push-Pull General purpose I/O /
ADC 2 input
1(P6.3) Push-Pull General purpose I/O /
ADC 3 input
Up
Up
Up
1
Push-Pull General purpose I/O
P6.5
Up
1
Push-Pull General purpose I/O
P6.6/CLKO1
P6.7
Up
1(P6.6) Push-Pull General purpose I/O /
Clock out 1
Up
1
0
1
Push-Pull General purpose I/O
VSYNC
P1.7
Down
--
Input VSYNC input
I/O
Standard General purpose I/O
8051/
Push-Pull
37
38
39
40
41
42
43
44
34
35
36
37
38
39
40
41
31
32
33
34
35
36
37
38
P1.6
P1.5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
--
--
--
--
--
--
--
--
--
1
1
1
1
1
1
Standard General purpose I/O
8051/
Push-Pull
Standard General purpose I/O
8051/
Push-Pull
Standard General purpose I/O
8051/
Push-Pull
Standard General purpose I/O
8051/
Push-Pull
Standard General purpose I/O
8051/
Push-Pull
Standard General purpose I/O
P1.4
P1.3
P1.2
P1.1
8051/
Push-Pull
P1.0/ET2
VCC
1(P1.0) Standard General purpose I/O /
8051/
Push-Pull
--
External Timer 2
--
Power
Note: All NC pin must be left unconnected or be connected to GND.
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Realtek
RTD2120-series
DW8051 micro-processor
The DW8051 contained in RTD2120 is compatible with industry standard 803x/805x and
provides the following design features and enhancements to the standard 8051 microcontroller:
1. High speed architecture
Compared to standard 8051, the DW8051 processor core provides increased performance by
executing instructions in a 4-clock bus cycle, as opposed to the 12-clock bus cycle in the standard
8051. The shortened bus timing improves the instruction execution rate for most instructions by a
factor of three over the standard 8051 architectures. The average speed improvement for the entire
instruction set is approximately 2.5X.
2. Stretch Memory Cycles
The stretch memory cycle feature enables application software to adjust the speed of data
memory access. The DW8051 can execute the MOVX instruction in as little as 2 instruction cycles.
However, it is sometimes desirable to stretch this value; for example, to access slow memory or slow
memory-mapped peripherals such as UARTs or LCDs.
The three LSBs of the Clock Control Register (at SFR location 8Eh) control the stretch value.
You can use stretch values between zero and seven. A stretch value of zero adds zero instruction
cycles, resulting in MOVX instructions executing in two instruction cycles. A stretch value of seven
adds seven instruction cycles, resulting in MOVX instructions executing in nine instruction cycles.
The stretch value can be changed dynamically under program control.
By default, the stretch value resets to one (three cycle MOVX). For full-speed data memory
access, the software must set the stretch value to zero. The stretch value affects only data memory
access. The only way to reduce the speed of program memory (ROM) access is to use a slower clock.
3. Dual Data Pointers
The DW8051 employs dual data pointers to accelerate data memory block moves. The standard
8051 data pointer (DPTR) is a 16-bit value used to address external data RAM or peripherals. The
DW8051 maintains the standard data pointer as DPTR0 at SFR locations 82h and 83h. It is not
necessary to modify code to use DPTR0.
The DW8051 adds a second data pointer (DPTR1) at SFR locations 84h and 85h. The SEL bit in
the DPTR Select register, DPS (SFR 86h), selects the active pointer. When SEL = 0, instructions that
use the DPTR will use DPL0 and DPH0. When SEL = 1, instructions that use the DPTR will use
DPL1 and DPH1. SEL is the bit 0 of SFR location 86h. No other bits of SFR location 86h are used.
All DPTR-related instructions use the currently selected data pointer. To switch the active
pointer, toggle the SEL bit. The fastest way to do so is to use the increment instruction (INC DPS).
This requires only one instruction to switch from a source address to a destination address, saving
application code from having to save source and destination addresses when doing a block move.
Using dual data pointers provides significantly increased efficiency when moving large blocks of
data.
4. Timer Rate Control
One important difference exists between the RTD2120 and 80C32 regarding timers. The original
80C32 used a 12 clock per cycle scheme for timers and consequently for some serial baud
rates(depending on the mode). The RTD2120 architecture normally runs using 4 clocks per cycle.
However, in the area of timers, it will default to a 12 clock per cycle scheme on a reset. This allows
existing code with real–time dependencies such as baud rates to operate properly. If an application
needs higher speed timers or serial baud rates, the timers can be set to run at the 4 clock rate.
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RTD2120-series
The Clock Control register (CKCON – 8Eh) determines these timer speeds. When the relevant
CKCON bit is a logic 1, the device uses 4 clocks per cycle to generate timer speeds. When the control
bit is set to a zero, the device uses 12 clocks for timer speeds. The reset condition is a 0. CKCON.5
selects the speed of Timer 2. CKCON.4 selects Timer 1 and CKCON.3 selects Timer zero. Note that
unless a user desires very fast timing, it is unnecessary to alter these bits. Note that the timer controls
are independent.
Memory Organization
Internal Data memory
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256 bytes of internal RAM
128 bytes of Special Function Register (SFR)
External Data memory
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128 bytes of External Special Function Register (XFR)
256 bytes of DDCRAM(128-bytex2)
256 bytes of general purpose RAM
32k bytes of flash for EDID data and other parameters
External Program memory
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64k bytes of flash for program memory
The program content can not be read out unless user mass erase the flash first.
External Data Memory
External Program Memory
Internal Data Memory
FFFF
FF
FFFF
FF00
XFR
Internal RAM
SFR
Indirect addressing
Direct addressing
80
7F
Unused
Internal RAM
Direct/Indirect
addressing
F9FF
DDC_RAM1&2
F900
F8FF
00
flash 0~64K
General Purpose RAM
F800
Unused
7FFF
0000
flash 64~96K
0000
Reset
There are five reset sources in RTD2120, as described below:
RST pin
The external reset is high active and its pulse width must be larger than 16 mcu clock cycles. The
RST pin can reset the whole chip of RTD2120.
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Low voltage reset(LVR) and power on reset(POR)
The LVR and POR monitor the power status of RTD2120. The same as external reset, the LVR
and POR will reset the whole chip of RTD2120 when triggered.
Software reset
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RTD2120-series
To activate software reset, set FF39[1](SOF_RST). When software reset is triggered, it will reset
all modules except debug mode.
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Watchdog timer(WDT)
The watchdog timer generates reset when it is overflowed. The watchdog timer resets almost the
same modules as software reset except itself(watchdog timer module).
In System Programing(ISP) reset
ISP reset will generate when entering ISP mode. Compared to Watchdog timer reset, ISP mode
resets almost the same modules as Watchdog timer except itself(ISP module).
Debug mode
Watchdog timer
CPU
ISP module and
module
module
other modules
RST pin
O
O
x
x
x
O
O
O
x
O
O
O
O
O
O
O
O
x
LVR & POR
Software reset
WDT reset
ISP reset
x
x
Note: O = Reset , x = No effect
Interrupt
Six interrupts are provided in RTD2120. Four of these are generated automatically by internal
operation: timer 0, timer 1, timer 2 and the serial port interrupt. The other two interrupts are triggered
by external pins: INT0 and INT1. Moreover, the DDC and IIC interrupts are connected to DW8051
INT1 source as the following figure.
PIN_INT1_EN
pin INT1
AWRI_EN
DWRI_EN
VSI_EN
A_WR_I
D_WR_I
128VS_I
STOP_I
D_OUT_I
D_IN_I
SUB_I
to DW8051
INT1
STOPI_EN
DOLI_EN
DILI_EN
SUBI_EN
SLVI_EN
SLV_I
Timer/Counter
RTD2120 has three timers/counters: T0, T1 andT2. T0 and T1 are fully compatible to
timer/counter in standard 8051’s. Like timer2 in 8052, T2 of RTD2120 has three operating modes: 16-
bit timer/counter with capture, 16-bit auto-reload timer/counter and Baud rate generator. However, T2
of RTD2120 does not support “Timer2 output enable(T2OE)” and “downcount enable(DCEN)”. The
SFRs associated with Timer2 are listed below.
Register Bit 7
T2CON TF2
RCAP2L
Bit 6
EXF2
Bit 5
RCLK TCLK
Bit 4
Bit 3
EXEN2 TR2
Bit 2
Bit 1
C/T2
Bit 0
CP/RL2 C8h
CAh
Addr
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RTD2120-series
RCAP2H
TL2
TH2
CBh
CCh
CDh
1. 16-bit timer/counter with capture
The Timer 2 capture mode is the same as the 16-bit timer/counter with the addition of the capture
registers and control signals. If EXEN2 = 0, Timer2 is a 16-bit timer/counter . The C/T2 bit determines
whether the 16-bit counter counts osc cycles (divided by 4 or 12), or high-to-low transitions on the
P1.0 pin. The TR2 bit enables the counter. When the count increments from FFFFh, the TF2 flag is set.
The CP/RL2 bit in the T2CON SFR enables the capture feature. When CP/RL2 = 1, a high-to-low
transition on P1.1 when EXEN2 = 1 causes the Timer 2 value to be loaded into the capture registers
(RCAP2L and RCAP2H).
2. 16-bit timer/counter with auto-reload
When CP/RL2 = 0, Timer 2 is configured for the auto-reload mode. Control of counter input is the
same as for the other 16-bit counter modes. When the count increments from FFFFh, Timer 2 sets the
TF2 flag and the starting value is reloaded into TL2 and TH2. The software must preload the starting
value into the RCAP2L and RCAP2H registers. When Timer 2 is in auto-reload mode, a reload can be
forced by a high-to-low transition on the P1.1 pin, if enabled by EXEN2 = 1.
3. Baud rate generator
Setting either RCLK or TCLK to 1 configures Timer 2 to generate baud rates for Serial Port 0 in
serial mode 1 or 3. In baud rate generator mode, Timer 2 functions in auto-reload mode. However,
instead of setting the TF2 flag, the counter overflow generates a shift clock for the serial port function.
As in normal auto-reload mode, the overflow also causes the preloaded start value in the RCAP2L and
RCAP2H registers to be reloaded into the TL2 and TH2 registers. When either TCLK = 1 or RCLK =
1, Timer 2 is forced into auto-reload operation, regardless of the state of the CP/RL2 bit. When
operating as a baud rate generator, Timer 2 does not set the TF2 bit. In this mode, a Timer 2 interrupt
can only be generated by a high-to-low transition on the P1.1 pin setting the EXF2 bit, and only if
enabled by EXEN2 = 1.
The counter time base in baud rate generator mode is osc/2. To use an external clock source,
set C/T2 to 1 and apply the desired clock source to the P1.0 pin.
Special Function Registers(SFR)
Reset Addr
Register
SP
DPL0
DPH0
DPL1
DPH1
DPS
PCON
TCON
TMOD
TL0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 Value (Hex)
(Hex)
07
00
00
00
00
00
30
00
00
00
81
82
83
84
85
86
87
88
89
8A
0
0
0
1
0
1
0
0
0
SEL
SMOD0
TF1
GATE C/T
GF1
IE1
GATE C/T
GF0
IT1
STOP IDLE
IE0
M1
TR1
TF0
M1
TR0
M0
IT0
M0
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RTD2120-series
Reset Addr
Bit 0 Value (Hex)
(Hex)
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
TL1
TH0
TH1
CKCON
SPC_FNC 0
00
00
00
01
00
FF
00
FF
00
00
00
00
FF
FF
80
8B
8C
8D
8E
8F
90
92
93
98
99
A0
A8
B0
B3
B8
C8
CA
CB
CC
CD
D0
E0
F0
T2M
0
P1.5
T1M
0
P1.4
T0M
0
P1.3
MD2
0
P1.2
MD1
0
P1.1
MD0
WRS
P1.0
0
P1.6
P1
P1.7
MPAGE
P1_R
SCON0
SBUF0
P2
P1.7
SM0
P1.6
SM1
P1.5
SM2
P1.4
REN
P1.3
TB8
P1.2
RB8
P1.1
TI
P1.0
RI
P2.7
EA
P3.7
P3.7
1
P2.6
0
P3.6
P3.6
0
P2.5
ET2
P3.5
P3.5
PT2
P2.4
ES0
P3.4
P3.4
PS0
P2.3
ET1
P3.3
P3.3
PT1
P2.2
EX1
P3.2
P3.2
PX1
P2.1
ET0
P3.1
P3.1
PT0
C/T2
P2.0
EX0
P3.0
P3.0
PX0
IE
P3
P3_R
IP
T2CON
RCAP2L
RCAP2H
TL2
TF2
EXF2 RCLK TCLK EXEN2 TR2
CP/RL2 00
00
00
00
00
00
00
00
TH2
PSW
ACC
B
CY
AC
F0
RS1
RS0
OV
F1
P
External Special Function Registers(XFR)
Pin Share
Register::Pin_share0
0xFF00
Name
Bits
Read/Write
Reset State Comments
Reserved
IIC2E
7
6
--
R/W
0
1
Reserved
0: Pin “P5.6/DSCL“ is P5.6, Pin
“P5.7/DSDA“ is P5.7
1: Pin “P5.6/DSCL“ is DSCL, Pin
“P5.7/DSDA“ is DSDA
PWM5E
PWM4E
PWM3E
PWM2E
5
4
3
2
R/W
R/W
R/W
R/W
0
0
0
0
0: Pin “P5.5/PWM5“ is P5.5
1: Pin “P5.5/PWM5“ is PWM5
0: Pin “P5.4/PWM4“ is P5.4
1: Pin “P5.4/PWM4“ is PWM4
0: Pin “P5.3/PWM3“ is P5.3
1: Pin “P5.3/PWM3“ is PWM3
0: Pin “P5.2/PWM2“ is P5.2
1: Pin “P5.2/PWM2“ is PWM2
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RTD2120-series
PWM1E
PWM0E
1
0
R/W
R/W
0
0
0: Pin “P5.1/PWM1“ is P5.1
1: Pin “P5.1/PWM1“ is PWM1
0: Pin “P5.0/PWM0“ is P5.0
1: Pin “P5.0/PWM0“ is PWM0
Register::Pin_share1
Bits
0xFF01
Name
Read/Write
Reset State Comments
A_DDC_PIN_
SEL
7
6
R/W
0
1
0: ADC DDC ports are connected to
ASDA/ASCL
1: ADC DDC ports are connected to
DSDA/DSCL
0: DVI DDC ports are connected to
ASDA/ASCL
D_DDC_PIN_
SEL
R/W
1: DVI DDC ports are connected to
DSDA/DSCL
Reserved
PIN_INT1_E
N
5:3
2
--
R/W
0
1
Reserved
Pin “P3.3/INT1” connect to 8051 INT1
enable
0: disable
1: enable
when Pin “P3.3/INT1” is used as GPIO, this
bit must be 0.
CLKO2E
IIC1E
1
0
R/W
R/W
0
1
0: Pin “P7.6/CLKO2“ is P7.6
1: Pin “P7.6/CLKO2“ is CLKO2
0: Pin “ASCL/P3.0/Rxd“ is P3.0/RXD, Pin
“ASDA/P3.1/Txd“ is P3.1/TXD
1: Pin “ASCL/P3.0/Rxd“ is ASCL, Pin
“ASDA/P3.1/Txd“ is ASDA
Register::Pin_share2
Bits
0xFF02
Name
Read/Write
Reset State Comments
Reserved
CLKO1E
7:5
4
--
R/W
0
0
Reserved
0: Pin “P6.6/CLKO1“ is P6.6
1: Pin “P6.6/CLKO1“ is CLKO1
0: Pin “P6.3/ADC3“ is P6.3
1: Pin “P6.3/ADC3“ is ADC3
0: Pin “P6.2/ADC2“ is P6.2
1: Pin “P6.2/ADC2“ is ADC2
0: Pin “P6.1/ADC1“ is P6.1
1: Pin “P6.1/ADC1“ is ADC1
0: Pin “P6.0/ADC0“ is P6.0
1: Pin “P6.0/ADC0“ is ADC0
ADC3E
ADC2E
ADC1E
ADC0E
3
2
1
0
R/W
R/W
R/W
R/W
0
0
0
0
I/O port
l
Each I/O pin of RTD2120 can drive/sink 4mA and the internal pull up/down circuit can
drive/sink 10uA.
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Realtek
RTD2120-series
l
All pins have 5V tolerance except four ADC pins: “P6.0/ADC0”, “P6.1/ADC1”, “P6.2/ADC2”
and ”P6.3/ADC3”.
Register::Port5_output_enable
Bits Read/Write
0xFF03
Reset State Comments
Name
P57OE
P56OE
P55OE
P54OE
P53OE
P52OE
P51OE
P50OE
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0: P5.7 is input pin
1: P5.7 is output pin
0: P5.6 is input pin
1: P5.6 is output pin
0: P5.5 is input pin
1: P5.5 is output pin
0: P5.4 is input pin
1: P5.4 is output pin
0: P5.3 is input pin
1: P5.3 is output pin
0: P5.2 is input pin
1: P5.2 is output pin
0: P5.1 is input pin
1: P5.1 is output pin
0: P5.0 is input pin
1: P5.0 is output pin
Register::Port6_output_enable
Bits Read/Write
0xFF04
Name
Reset State Comments
P67OE
P66OE
P65OE
P64OE
P63OE
P62OE
P61OE
P60OE
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0: P6.7 is input pin
1: P6.7 is output pin
0: P6.6 is input pin
1: P6.6 is output pin
0: P6.5 is input pin
1: P6.5 is output pin
0: P6.4 is input pin
1: P6.4 is output pin
0: P6.3 is input pin
1: P6.3 is output pin
0: P6.2 is input pin
1: P6.2 is output pin
0: P6.1 is input pin
1: P6.1 is output pin
0: P6.0 is input pin
1: P6.0 is output pin
Register::Port7_output_enable
Bits Read/Write
R/W
0xFF05
Name
Reset State Comments
P77OE
7
0
0: P7.7 is input pin
1: P7.7 is output pin
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Realtek
RTD2120-series
P76OE
6
R/W
--
0
0
0: P7.6 is input pin
1: P7.6 is output pin
Reserved
Reserved
5:0
Register::Port1_pad_type
0xFF09
Name
Bits
Read/Write
Reset State Comments
P17_PPO
P16_PPO
P15_PPO
P14_PPO
P13_PPO
P12_PPO
P11_PPO
P10_PPO
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0:P1.7 is standar 8051 I/O
1:P1.7 is Push-Pull output
0:P1.6 is standar 8051 I/O
1:P1.6 is Push-Pull output
0:P1.5 is standar 8051 I/O
1:P1.5 is Push-Pull output
0:P1.4 is standar 8051 I/O
1:P1.4 is Push-Pull output
0:P1.3 is standar 8051 I/O
1:P1.3 is Push-Pull output
0:P1.2 is standar 8051 I/O
1:P1.2 is Push-Pull output
0:P1.1 is standar 8051 I/O
1:P1.1 is Push-Pull output
0:P1.0 is standar 8051 I/O
1:P1.0 is Push-Pull output
Register::Port50_pin_reg
Bits Read/Write
7:1
0xFF50
0xFF51
0xFF52
Name
Reset State Comments
Reserved
P50
--
0
1
Reserved
Input/output value of P5.0
0
R/W
Register::Port51_pin_reg
Name
Bits
7:1
Read/Write
Reset State Comments
Reserved
P51
--
R/W
0
1
Reserved
Input/output value of P5.1
0
Register::Port52_pin_reg
Bits Read/Write
7:1
Name
Reset State Comments
Reserved
P52
--
R/W
0
1
Reserved
Input/output value of P5.2
0
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Realtek
RTD2120-series
Register::Port53_pin_reg
0xFF53
0xFF54
0xFF55
0xFF56
0xFF57
0xFF58
Name
Bits
7:1
Read/Write
Reset State Comments
Reserved
P53
--
R/W
0
1
Reserved
Input/output value of P5.3
0
Register::Port54_pin_reg
Bits Read/Write
7:1
Name
Reset State Comments
Reserved
P54
--
R/W
0
1
Reserved
Input/output value of P5.4
0
Register::Port55_pin_reg
Name
Bits
7:1
Read/Write
Reset State Comments
Reserved
P55
--
R/W
0
1
Reserved
Input/output value of P5.5
0
Register::Port56_pin_reg
Bits Read/Write
7:1
Name
Reset State Comments
Reserved
P56
--
R/W
0
1
Reserved
Input/output value of P5.6
0
Register::Port57_pin_reg
Name
Bits
7:1
Read/Write
Reset State Comments
Reserved
P57
--
R/W
0
1
Reserved
Input/output value of P5.7
0
Register::Port60_pin_reg
Bits Read/Write
7:1
Name
Reset State Comments
Reserved
P60
--
R/W
0
1
Reserved
Input/output value of P6.0
0
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Realtek
RTD2120-series
Register::Port61_pin_reg
0xFF59
0xFF5A
0xFF5B
0xFF5C
0xFF5D
0xFF5E
Name
Bits
7:1
Read/Write
Reset State Comments
Reserved
P61
--
R/W
0
1
Reserved
Input/output value of P6.1
0
Register::Port62_pin_reg
Bits Read/Write
7:1
Name
Reset State Comments
Reserved
P62
--
R/W
0
1
Reserved
Input/output value of P6.2
0
Register::Port63_pin_reg
Name
Bits
7:1
Read/Write
Reset State Comments
Reserved
P63
--
R/W
0
1
Reserved
Input/output value of P6.3
0
Register::Port64_pin_reg
Bits Read/Write
7:1
Name
Reset State Comments
Reserved
P64
--
R/W
0
1
Reserved
Input/output value of P6.4
0
Register::Port65_pin_reg
Name
Bits
7:1
Read/Write
Reset State Comments
Reserved
P65
--
R/W
0
1
Reserved
Input/output value of P6.5
0
Register::Port66_pin_reg
Bits Read/Write
7:1
Name
Reset State Comments
Reserved
P66
--
R/W
0
1
Reserved
Input/output value of P6.6
0
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Realtek
RTD2120-series
Register::Port67_pin_reg
0xFF5F
0xFF60
0xFF61
Name
Bits
7:1
Read/Write
Reset State Comments
Reserved
P67
--
R/W
0
1
Reserved
Input/output value of P6.7
0
Register::Port76_pin_reg
Bits Read/Write
7:1
Name
Reset State Comments
Reserved
P76
--
R/W
0
1
Reserved
Input/output value of P7.6
0
Register::Port77_pin_reg
Name
Bits
7:1
Read/Write
Reset State Comments
Reserved
P77
--
R/W
0
1
Reserved
Input/output value of P7.7
0
Low Voltage Reset & Power on Reset
When the voltage level of power supply is below VLT, the low voltage reset(LVR) generates a chip
reset signal. After the power supply is above VUT(2.6V), LVR remain in reset state for 65536 X’tal
cycle(tPOR) to guarantee the chip exit reset condition.
VCC
VUT
VLT
VSS
tPOR
INTERNAL RESET
Register::LVR_control
Bits Read/Write
0xFF0A
Name
Reset State Comments
confidential
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Realtek
RTD2120-series
VLT
7:6
5:0
R/W
--
0
low_threshold_voltage
00:1.8V
01:2.0V
10:2.2V
11:2.4V
reserved
00
reserved
A/D Converter
RTD2120 has embedded 4 channels of analog-to-digital converter. The ADCs convert analog
input voltage on the four A/D input pins to four 6-bit digital data stored in XFRs (FF0C~FF0F)
sequentially.
The ADC conversion range is from GND to VDD and the conversion is linear and monotonic with no
missing codes. To start A/D conversion, set STRT_ADC(FF0B[7]) = 1 and the conversion will be
complete in less than 12 us for 4 channels.
Register::ADC_control
Bits Read/Write
0xFF0B
Name
Reset State Comments
STRT_ADC
7
R/W
0
Write 1 to start the A/D conversion. Auto
clear when A/D Conversion has been
completed.
0:A/D Conversion has been completed
1:A/D Conversion is not completed yet
ADC_TEST
6
R/W
0
0: Normal operation
1: ADC test mode
reserved
BIAS_ADJ
5:3
2:1
R/W
R/W
0
1
Reserved
ADC bias current adjust
00: 15u
01: 20u
10: 25u
11: 30u
CK_SEL
0
R/W
0
Inverse ADC input clock pos/neg
0: pos
1: neg
Register::ADC0_convert_result
0xFF0C
Name
Bits
7:2
1:0
Read/Write
Reset State Comments
ADC0_CONV
_DATA
reserved
R
--
3F
00
Converted data of ADC0
Register::ADC1_convert_result
0xFF0D
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Realtek
RTD2120-series
Name
Bits
7:2
1:0
Read/Write
Reset State Comments
ADC1_CONV
_DATA
reserved
R
--
3F
00
Converted data of ADC1
Register::ADC2_convert_result
0xFF0E
Name
Bits
7:2
1:0
Read/Write
Reset State Comments
ADC2_CONV
_DATA
reserved
R
--
3F
00
Converted data of ADC2
Register::ADC3_convert_result
0xFF0F
Name
Bits
7:2
1:0
Read/Write
Reset State Comments
ADC3_CONV
_DATA
reserved
R
--
3F
00
Converted data of ADC3
PLL
RTD2120 contains a PLL to make the whole chip operate at higher or lower speed for different
demands. After reset, RTD2120 uses crystal frequency as the system clock. User can program the PLL
to operate at the desired frequency and select system clock to PLL output by setting MCU_CLK_SEL.
RTD2120 will switch system clock to PLL output only when PLL is stable. Moreover, the divider is
glitch free so user can modify its value at any time.For normal operation, user must choose the crystal
whose frequency is between 11M and 27MHz . Besides, VCO frequency must be programmed
between 40M and 80MHz.
Note: Fvco = Xtal *(M/N) , where M=M_code+1, N=N_code+1.
MCU_CLK_SEL
DIV
MCU_CLK
Crystal
11M~27MHz
PFD
PUMP
M
VCO
N
40M~80MHz
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Realtek
RTD2120-series
Register::PLL_control
0xFF10
Name
Bits
Read/Write
Reset State Comments
PLL_STA
7
R
1
2
PLL status
0: normal operation
1: PLL abnormal or PLL power down
Test mode vctrl set
11(0.8v)
DVSET
6:5
R/W
10(1.0v)
01(1.2v)
00(1.4v)
reserved
WD_RST
4:3
2
--
R/W
0
0
0: No effect
1: Watchdog reset
WD_SET
1
0
R/W
R/W
0
1
0: No effect
1: Watchdog set
0: normal operation
1: power down PLL
PWDN_PLL
Register::PLL_filter_control
Bits Read/Write
7:4
0xFF11
Name
Reset State Comments
reserved
VR
--
0
3:2
R/W
0
Loop filter resister
00: 16.32k
01: 19.12k
10: 21.92k
11: 24.72k
PLL_IP
1:0
R/W
2
Charge Pump current
Ich=5u+bit[1]*10u+ bit[0]*5u
Register::PLL_M_N_DIV
0xFF12
Name
Bits
7:4
Read/Write
Reset State Comments
M_CODE
N_CODE
DIV
R/W
R/W
R/W
1
0
0
Actual M = M_CODE+1
Actual N = N_CODE+1
Divider value
00:1
3:2
1:0
01:1/2
10:1/4
11:1/8
3.3V to 1.8V Regulator
max
typ
min
2
Input voltage(V)
Output current(mA)
80
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Realtek
RTD2120-series
Register::regulator_control
0xFF13
Name
Bits
7:5
Read/Write
Reset State Comments
reserved
VBG
--
R/W
0
1
4:3
bandgap voltage select
00: 1.14v
01: 1.20v
10: 1.27v
11: 1.34v
Regulator 1.8v voltage select
000: 2.22
V_SEL
2:0
R/W
4
001: 2.12
010: 2.0
011: 1.9
100: 1.8
101: 1.7
110: 1.6
111: 1.5
DDC
RTD2120 has two DDC ports for both D-sub and DVI interface. The external master can access
DDC_RAM1(F900~F97F) through pin ASDL and ASDA by ADC DDC channel or DDC_RAM2
(F980~F9FF) through pin DSDL and DSDA by DVI DDC channel. Besides, the DDC_RAM1 and
DDC_RAM2 can be combined together to form a 256-bytes DDC_RAM for just ADC/DVI DDC
slave by setting DDCRAM_SIZ (FF26[1:0]).
The DDC of RTD2120 is compliant with VESA DDC standard. Both DDC slaves are in DDC1
mode after reset. When a high to low transition is detected on ASCL/DSCL pin, the DDC slave will
enter DDC2 transition mode. The DDC slave can revert to DDC1 mode if the SCL signal keeps
unchanged for 128 VSYNC periods in DDC2 transition mode and RVT_A_DDC1_EN /
RVT_D_DDC1_EN = 1. In DDC2 transition mode, the DDC slave will lock in DDC2 mode if a valid
control byte is received. Furthermore, user can force the DDC slave to operate DDC2 mode by setting
A_DDC2 / D_DDC2 = 1.
(Refers to the VESA “Display Data Channel Standard” for detailed)
Register::ADC_DDC_enable
Bits Read/Write
7:5
0xFF20
Name
Reset State Comments
A_DDC_ADD
R
R/W
0
ADC DDC Channel Address Least
Significant 3 Bits
(The default DDC channel address MSB 4
Bits is “A”)
reserved
A_DDC_W_S
TA
4
3
--
R/W
0
0
Reserved
ADC DDC Write Status (for external DDC
access only)
It is cleared after write.
A_DDCRAM
_W_EN
2
R/W
0
ADC DDC SRAM Write Enable (for
external DDC access only)
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Realtek
RTD2120-series
0: Disable
1: Enable
A_DBN_EN
A_DDC_EN
1
0
R/W
R/W
1
0
ADC DDC De-bounce Enable
0: Disable
1: Enable (with crystal/4)
ADC DDC Channel Enable Bit
0: MCU access Enable
1: DDC channel Enable
Register::ADC_DDC_control
Bits Read/Write
7:6
0xFF21
Name
Reset State Comments
A_DBN_CLK
_SEL
R/W
0
0
De-bounce clock divider
00: 1/1 reference clock
01: 1/2 reference clock
1X: 1/4 reference clock
De-bounce sda stage
0X: latch one stage
10: latch two stage
11: latch three stage
De-bounce reference clock
0: crystal clock
A_STOP_DB
N_SEL
5:4
R/W
A_SYS_CK_S
EL
3
2
1
0
R/W
R/W
R/W
R/W
0
0
0
0
1: PLL clock
A_DDC2
Force to ADC DDC to DDC2 mode
0: Normal operation
1: DDC2 is active
Reset ADC DDC circuit
0: Normal operation
1: reset (auto cleared)
ADC DDC revert to DDC1 enable(SCL idle
for 128 VSYNC)
RST_A_DDC
RVT_A_DDC
1_EN
0: Disable
1: Enable
Register::DVI_DDC_enable
Bits Read/Write
7:5
0xFF23
Name
Reset State Comments
D_DDC_ADD
R
R/W
0
DVI DDC Channel Address Least
Significant 3 Bits
(The default DDC channel address MSB 4
Bits is “A”)
reserved
D_DDC_W_S
TA
4
3
--
R/W
0
0
Reserved
DVI DDC External Write Status (for external
DDC access only)
It is cleared after write.
DVI DDC External Write Enable (for
external DDC access only)
0: Disable
1: Enable
DVI DDC Debounce Enable
0: Disable
D_DDCRAM
_W_EN
2
1
R/W
R/W
0
1
D_DBN_EN
1: Enable (with crystal/4)
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Realtek
RTD2120-series
D_DDC_EN
0
R/W
0
DVI DDC Channel Enable Switch
0: MCU access Enable
1: External DDC access Enable
Register::DVI_DDC_control
Bits Read/Write
7:6
0xFF24
Name
Reset State Comments
D_DBN_CLK
_SEL
R/W
0
0
De-bounce clock divider
00: 1/1 reference clock
01: 1/2 reference clock
1X: 1/4 reference clock
De-bounce sda stage
0X: latch one stage
10: latch two stage
D_STOP_DB
N_SEL
5:4
R/W
11: latch three stage
De-bounce reference clock
0: crystal clock
D_SYS_CK_S
EL
3
2
1
0
R/W
R/W
R/W
R/W
0
0
0
0
1: PLL clock
D_DDC2
Force to DVI DDC to DDC2 mode
0: Normal operation
1: DDC2 is active
Reset DVI DDC circuit
0: Normal operation
1: reset (auto cleared)
DVI DDC revert to DDC1 enable(SCL idle
for 128 VSYNC)
RST_D_DDC
RVT_D_DDC
1_EN
0: Disable
1: Enable
Register::DDCRAM_partition
Bits Read/Write
7:3
0xFF26
Name
Reset State Comments
reserved
--
00
0
Reserved
VS_CON
2
R/W
0: VSYNC signal is connected to ADC DDC
1: VSYNC signal is connected to DVI DDC
0x:ADC DDCRAM=128 byte, DVI
DDCRAM=128 byte
DDCRAM_SI
Z
1:0
R/W
0
10:ADC DDCRAM=0 byte, DVI
DDCRAM=256 byte
11:ADC DDCRAM=256 byte, DVI
DDCRAM=0 byte
IIC Interface
Register::IIC_set_slave
0xFF27
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RTD2120-series
Name
Bits
7:1
Read/Write
Reset State Comments
IIC_ADDR
CH_SEL
R/W
R/W
37
0
IIC Slave Address to decode
Channel Select
0
0: from ADC DDC
1: from DVI DDC
Register::IIC_sub_in
Bits
0xFF28
Name
Read/Write
Reset State Comments
IIC_SUB_AD
DR
7:0
R
00
IIC Sub-Address Received
Register::IIC_data_in
Bits
0xFF29
Name
IIC_D_IN
Read/Write
Reset State Comments
7:0
R
00
IIC data received
Register::IIC_data_out
Bits Read/Write
7:0
0xFF2A
Name
Reset State Comments
IIC_D_OUT
W
00
IIC data to be transmitted
Register::IIC_status
Bits
0xFF2B
Name
Read/Write
Reset State Comments
A_WR_I
D_WR_I
7
6
R/W
0
0
If ADC DDC detects a STOP condition in
write mode, this bit is set to “1” . Write 0 to
clear.
If DVI DDC detects a STOP condition in
write mode, this bit is set to “1” . Write 0 to
clear.
R/W
128VS_I
STOP_I
5
4
R/W
R/W
0
0
In DDC2 Transition mode, SCL idle for 128
VSYNC. Write 0 to clear.
If IIC detects a STOP condition(slave
address must match), this bit is set to “1” .
Write 0 to clear.
D_OUT_I
3
R
0
If IIC_DATA_OUT loaded to serial-out-
byte, this bit is set to “1”. Write IIC_data_out
(FF2A) to clear.
D_IN_I
SUB_I
2
1
R
0
0
If IIC_DATA_IN latched, this bit is set to
“1” . Read IIC_data_in (FF29) to clear.
If IIC_SUB latched, this bit is set to “1”
Write 0 to clear.
R/W
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RTD2120-series
SLV_I
0
R/W
0
If IIC_SLAVE latched, this bit is set to “1”
Write 0 to clear.
Register::IIC_IRQ_control
Bits Read/Write
0xFF2C
Name
Reset State Comments
0: Disable the A_WR_I signal as an
AWI_EN
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
interrupt source
1: Enable the A_WR_I signal as an interrupt
source
0: Disable the D_WR_I signal as an interrupt
source
1: Enable the D_WR_I signal as an interrupt
source
0: Disable the 128VS_I signal as an interrupt
source
1: Enable the 128VS_I signal as an interrupt
source
0: Disable the STOP_I signal as an interrupt
source
1: Enable the STOP_I signal as an interrupt
source
0: Disable the D_OUT_I signal as an
interrupt source
1: Enable the D_OUT_I signal as an
interrupt source
0: Disable the D_IN_I signal as an interrupt
source
1: Enable the D_IN_I signal as an interrupt
source
0: Disable the SUB_I signal as an interrupt
source
1: Enable the SUB_I signal as an interrupt
source
DWI_EN
128VSI_EN
STOPI_EN
DOI_EN
DII_EN
SUBI_EN
SLVI_EN
0: Disable the SLV_I signal as an interrupt
source
1: Enable the SLV_I signal as an interrupt
source
PWM
RTD2120 supports 3 channels of PWM DAC. The resolution of each PWM is 8-bit. PWM0,
PWM1and PWM2 are connected to DA0, DA1and DA2 respectively. Meanwhile, they can also be
connected to DA3, DA4 and DA5 which are programed via PWM_source_select register. The figure
below represent the PWM clock generator. Based on the clock, we make up the PWM waveform
which frequency is 1/256 of the PWM clock.
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Realtek
RTD2120-series
PWM clock generator
first stage
output
OSC
PLL
second stage
output
1/2M
1/(N+1)
Register::PWM_clock_control
Bits Read/Write
0xFF30
Name
Reset State Comments
PWM_EN
PWM0_CK
PWM1_CK
PWM2_CK
7
6
5
4
3
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0: Disable PWM output
1: Enable PWM output
0: Select first stage output
1: Select second stage output
0: Select first stage output
1: Select second stage output
0: Select first stage output
1: Select second stage output
PWM clock generator input source
0: Crystal
PWM_CK_SE
L
1: PLL output
reserved
PWM_M
2
1:0
--
R/W
0
0
Reserved
PWM clock first stage divider
Register::PWM_divider_N
Bits Read/Write
7:0 R/W
0xFF31
Name
Reset State Comments
PWM_N
0
PWM clock Second stage divider
Register::PWM0_duty_width
Bits Read/Write
7:0 R/W
0xFF32
Name
Reset State Comments
PWM0_DUT
0
PWM0 duty width
Register::PWM1_duty_width
Bits Read/Write
7:0 R/W
0xFF33
Name
Reset State Comments
PWM1_ DUT
0
PWM1 duty width
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Realtek
RTD2120-series
Register::PWM2_duty_width
0xFF34
Name
Bits
7:0
Read/Write
Reset State Comments
PWM2 duty width
PWM2_ DUT
R/W
0
Register::PWM_source_select
Bits Read/Write
7:6
0xFF35
Name
Reset State Comments
reserved
--
0
2
Reserved
PWM5_SEL
5:4
3:2
1:0
R/W
00: PWM5 is the same as PWM0
01: PWM5 is the same as PWM1
1x: PWM5 is the same as PWM2
00: PWM4 is the same as PWM0
01: PWM4 is the same as PWM1
1x: PWM4 is the same as PWM2
00: PWM3 is the same as PWM0
01: PWM3 is the same as PWM1
1x: PWM3 is the same as PWM2
PWM4_SEL
PWM3_SEL
R/W
R/W
1
0
Watchdog Timer
The Watchdog Timer automatically generates a device reset when it is overflowed. The interval of
overflow is about 0.25 sec to 2 sec(assume crystal is 12MHz) and can be programmed via register
CNT1.
EN_WDT
OSC
1
0
WDT reset
CNT1
N
CNT3
3*210
CNT2
210
0
1
BY_CNT3
BY_CNT2
Register::WATCHDOG_timer
Bits Read/Write
0xFF36
Name
Reset State Comments
WDT_EN
CLR_WDT
BY_CNT2
7
6
5
R/W
W
0
0
0
0: Disable watchdog timer
1: Enable watchdog timer
0: No effect
1: Clear all counters of watchdog
Signal bypass counter2*
0: signal pass through counter2
1: bypass
R/W
BY_CNT3
4
R/W
0
Signal bypass counter3*
0: signal pass through counter3
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Realtek
RTD2120-series
1: bypass
reserved
CNT1
3
2:0
--
R/W
0
0
Reserved
The number N of counter1
000~111: 1~8
l
When ISP mode is enabled, watchdog will be disabled by hardware.
*When BY_CNT2 and BY_CNT3 are all assigned one (bypass), watchdog will be counted by CNT2
In System Programming
User can program the embedded 96K flash of RTD2120 by internal hardware without removing
RTD2120 from the system. RTD2120 utilizes DDC channel (ADC/DVI DDC) to communicate with
IIC host for ISP function. The ISP protocol is mainly compatible with DDC protocol. However, one
significant difference is that the LSB of 7-bit ISP address is the address auto increase bit. Thus, we can
improve the flash program speed.
Register::ISP_slave_address
Bits Read/Write
7:2
0xFF37
Name
Reset State Comments
ISP_ADDR
ISP_ADDR_I
NC_A
R/W
R
25
1
ISP slave address
1
Received LSB of ISP slave address of ADC
DDC channel
0: address is nonincrease
1: address is auto-increase
Received LSB of ISP slave address of DVI
DDC channel
ISP_ADDR_I
NC_D
0
R
1
0: address is nonincrease
1: address is auto-increase
Register::option
Bits
0xFF38
Name
Read/Write
Reset State Comments
PORT_PIN_R
EG
7
R/W
1
port_pin_reg_n enable
0: port_pin_reg_n signal is disabled
1: port_pin_reg_n signal is enabled
Reserved
reserved
MCU_CLK_S
EL
6:2
1
--
R/W
0
0
CPU clock source select
0: CPU clock is from Crystal divided by DIV
1: CPU clock is from PLL divided by DIV
CLKO1 & CLKO2 select
CKOUT_SEL
0
R/W
0
0: Select Crystal output
1: Select PLL output
Register::flash_page_erase_control
Bits Read/Write
0xFF39
Name
Reset State Comments
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Realtek
RTD2120-series
PAGE_ADDR
reserved
7:3
2
R/W
--
00
0
Flash page address from 64K to 96K
Reserved
1
R/W
0
Software reset for debug mode
0: No effect
SOF_RST
1: reset RTD2120
STR_P_ERS
0
R/W
0
Start page erase
0: page erase complete
1: write 1 to start page erase
Register::RAM_test
Bits
0xFF3A
Name
Read/Write
Reset State Comments
reserved
EXT_RAM_B
IST
7:4
3
--
R/W
0
0
Reserved
Start BIST function for MCU external RAM
(512 bytes)
0: finished and clear
1: start
EXT_RAM_S
TA
2
1
R
0
0
Test result about MCU external RAM
0: fail
1: ok
Start BIST function for MCU internal RAM
(256 bytes)
INT_RAM_BI
ST
R/W
0: finished and clear
1: start
INT_RAM_S
TA
0
R
0
Test result about MCU internal RAM
0: fail
1: ok
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Realtek
RTD2120-series
Memory map of XFR
Register name Addr
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin_share0
Pin_share1
Pin_share2
FF00
FF01
FF02
FF03
FF04
FF05
IIC2E
PWM5E PWM4E PWM3E PWM2E PWM1E PWM0E
PIN_INT1
A_DDC_P D_DDC_P
IN_SEL IN_SEL
CLKO2E
ADC1E
P51OE
IIC1E
ADC0E
P50OE
P60OE
_EN
CLKO1E ADC3E
ADC2E
Port5_output_enabl
P57OE
P67OE
P77OE
P56OE
P66OE
P76OE
P55OE
P65OE
P54OE
P64OE
P53OE
P63OE
P52OE
P62OE
e
Port6_output_enabl
P61OE
e
Port7_output_enabl
e
Port1_pad_type
LVR_control
ADC_control
FF09 P17_PPO P16_PPO P15_PPO P14_PPO P13_PPO P12_PPO P11_PPO P10_PPO
FF0A
FF0B
FF0C
FF0D
FF0E
FF0F
VLT
STRT_AD ADC_TES
BIAS_ADJ
CK_SEL
C
T
ADC0_convert_res
ADC0_CONV_DATA
ADC1_CONV_DATA
ADC2_CONV_DATA
ADC3_CONV_DATA
ult
ADC1_convert_res
ult
ADC2_convert_res
ult
ADC3_convert_res
ult
PWDN_P
LL
PLL_control
FF10 PLL_STA
DVSET
WD_RST WD_SET
PLL_filter_control FF11
PLL_M_N_DIV FF12
VR
N_CODE
PLL_IP
DIV
V_SEL
A_DBN_E A_DDC_E
M_CODE
Regulator_control FF13
VBG
A_DDCR
AM_W_E
N
A_DDC_
W_STA
ADC_DDC_enable FF20
ADC_DDC_contro
A_DDC_ADDR
N
N
A_SYS_C
K_SEL
RST_A_D RVT_A_D
FF21 A_DBN_CLK_SEL A_STOP_DBN_SEL
A_DDC2
l
DC
DC1_EN
D_DDCR
AM_W_E
N
D_DDC_
W_STA
D_DBN_E D_DDC_E
DVI_DDC_enable FF23
D_DDC_ADDR
N
N
D_SYS_C
K_SEL
RST_D_D RVT_D_D
DVI_DDC_control FF24 D_DBN_CLK_SEL D_STOP_DBN_SEL
D_DDC2
VS_CON
DC
DC1_EN
DDCRAM_partitio
FF26
n
DDCRAM_SIZ
IIC_set_slave
IIC_sub_in
FF27
FF28
FF29
FF2A
IIC_ADDR
CH_SEL
IIC_SUB_ADDR
IIC_D_IN
IIC_data_in
IIC_data_out
IIC_D_OUT
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Realtek
RTD2120-series
Register name Addr
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
IIC_status
FF2B A_WR_I D_WR_I 128VS_I STOP_I D_OUT_I D_IN_I
128VSI_E STOPI_E
SUB_I
SLV_I
IIC_IRQ_control FF2C AWI_EN DWI_EN
DOI_EN DII_EN SUBI_EN SLVI_EN
N
N
PWM_clock_contr
ol
PWM0_C PWM1_C PWM2_C PWM_CK
FF30 PWM_EN
PWM_M
K
K
K
_SEL
PWM_divider_N FF31
PWM0_duty_width FF32
PWM1_duty_width FF33
PWM2_duty_width FF34
PWM_N
PWM0_DUT
PWM1_DUT
PWM2_DUT
PWM_source_sele
FF35
ct
PWM5_SEL
BY_CNT2 BY_CNT3
ISP_ADDR
PWM4_SEL
PWM3_SEL
WATCHDOG_tim
CLR_WD
T
FF36 WDT_EN
CNT1
er
ISP_ADD ISP_ADD
R_INC_A R_INC_D
MCU_CL CKOUT_
ISP_slave_address FF37
PORT_PI
N_REG
option
FF38
FF39
FF3A
K_SEL
SEL
STR_P_E
RS
Flash_page_erase_
control
PAGE_ADDR
SOF_RST
EXT_RA EXT_RA INT_RAM INT_RAM
M_BIST M_STA _BIST _STA
RAM_test
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Realtek
RTD2120-series
Electric Specification
DC Characteristics
Table 1 Absolute Maximum Ratings
PARAMETER
Voltage on VDD
Voltage on Input (5V tolerant)
Voltage on Output or I/O or NC
Electrostatic Discharge
Latch-Up
Ambient Operating Temperature
Storage temperature (plastic)
SYMBOL
VVDD
VIN1
MIN
-1
-1
TYP
MAX
4.6
5.5
UNITS
V
V
V
kV
mA
ºC
VIO
VESD
ILA
TA
TSTG
-1
4.6
±3.5
±100
70
0
-55
125
ºC
Table 2 DC Characteristics/Operating Condition
(0℃<TA<70℃; VDD = 3.3V ± 0.3V)
PARAMETER
SYMBOL
MIN
3.0
TYP
3.3
MAX
3.6
UNITS
V
mA
mA
V
V
V
V
Ω
Ω
μA
μA
Supply Voltage
Supply Current
VDD
IVDD
IVDD
VOH
VOL
VIH
VIL
RPU
RPD
ILI
22(1)
31(2)
Supply Current(Power Saving)
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
2.4
GND
2.0
VDD
0.5
0.8
300
150
+10
+20
I/O Pull-up resistance
100
50
-10
-20
I/O Pull-down resistance
Input Leakage Current(VI=VCC or GND)
Output Leakage Current(VO=VCC or GND)
ILO
(1) MCU operate at 24M Hz without any clock output.
(2) MCU operate at 48M Hz with PLL active and two clock outputs.
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Realtek
RTD2120-series
Mechanical Specification
48 Pin LQFP
L
L1
TITLE: LQFP-48 (7.0x7.0x1.6mm)
PACKAGE OUTLINE DRAWING, FOOTPRINT 2.0mm
SYMBOL
MILLIMETER
INCH
MIN. TYPICAL
MAX.
1.60
0.15
1.45
0.20
MIN. TYPICAL
MAX
A
A1
A2
c
0.063
0.006
0.057
0.008
0.05
0.002
LEADFRAME MATERIAL
1.35
0.09
1.40
0.053
0.004
0.055
APPROVE
CHECK
DOC. NO.
VERSION
DWG NO
DATE
02
D
9.00 BSC
7.00 BSC
5.50
0.354 BSC
0.276 BSC
0.217
PKGC-065
D1
D2
E
REALTEK SEMICONDUCTOR CORP.
9.00 BSC
7.00BSC
5.50
0.354 BSC
0.276 BSC
0.217
E1
E2
b
0.17
0.20
0.27
0.007
0.008
0.011
e
0.50 BSC
3.5o
0.0196 BSC
3.5o
TH
L
0o
7o
0o
7o
0.45
0.60
0.75
0.018
0.0236
0.030
L1
1.00
0.0393
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Realtek
RTD2120-series
44 Pin PLCC
Symbol
Dimension in inch
Dimension in mm
Min
-
Typ
-
Max
0.185
-
Min
Typ
-
Max
4.70
Note:
A
A1
A2
b1
b
-
1.Dimension D & E do not include interlead
flash.
0.020
-
0.51
-
-
0.140 0.150 0.160
0.020 0.028 0.036
0.014 0.018 0.022
0.006 0.010 0.014
0.646 0.653 0.660
0.646 0.653 0.660
0.05 BSC
3.56
0.51
0.36
0.15
3.81
4.06
0.91
0.56
0.36
2.Dimension b1 does not include dambar
protrusion/intrusion.
0.71
0.46
0.25
3.Controlling dimension: Inch
4.General appearance spec. should be based
on final visual inspection spec.
TITLE : 44L PLCC (0.653" X 0.653")
PACKAGE OUTLINE DRAWING
LEADFRAME MATERIAL:
c
D
16.41 16.59 16.74
16.41 16.59 16.74
1.27 BSC
E
e
GD
GE
HD
HE
L
0.590 0.610 0.630
0.590 0.610 0.630
0.675 0.690 0.715
0.675 0.690 0.715
0.085 0.100 0.115
14.98 15.49 16.00
14.98 15.49 16.00
17.15 17.53 18.16
17.15 17.53 18.16
APPROVE
DOC. NO.
510-ASS-P004
1
VERSION
PAGE
17 OF 22
L044 - 1
2.16
2.54
2.92
0.10
10°
CHECK
Albert Chang
DWG NO.
DATE
y
-
-
-
0.004
-
-
MAR. 08.2005
θ
0°
10°
0°
-
REALTEK SEMI-CONDUCTOR CO., LTD
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Realtek
RTD2120-series
Ordering Information:
The available RTD2120 related products are listed below:
Part No.
Flash Size
Package Type
RTD2120K
RTD2120L
RTD2120S
RTD2120L-LF
RTD2120S-LF
96K byte
96K byte
96K byte
96K byte
96K byte
44 QFP
48 LQFP
44 PLCC
48 LQFP (lead free)
44 PLCC (lead free)
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相关型号:
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