FM16W08 [RAMTRON]
64Kb Wide Voltage Bytewide F-RAM; 64Kb的宽电压字节宽度的F- RAM
| 型号： | FM16W08 |
| 厂家： | 
RAMTRON INTERNATIONAL CORPORATION |
| 描述： | 64Kb Wide Voltage Bytewide F-RAM |
| 文件： | 总11页 (文件大小：96K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
FM16W08
64Kb Wide Voltage Bytewide F-RAM
Features
SRAM & EEPROM Compatible
64Kbit Ferroelectric Nonvolatile RAM
•
•
•
JEDEC 8Kx8 SRAM & EEPROM pinout
70 ns Access Time
130 ns Cycle Time
•
•
•
•
•
Organized as 8,192 x 8 bits
High Endurance 100 Trillion (1014) Read/Writes
38 year Data Retention (
NoDelay™ Writes
Advanced High-Reliability Ferroelectric Process
@ +75C)
Low Power Operation
•
•
•
Wide Voltage Operation 2.7V to 5.5V
12 mA Active Current
20 µA (typ.) Standby Current
Superior to BBSRAM Modules
•
•
•
•
•
No Battery Concerns
Monolithic Reliability
True Surface Mount Solution, No Rework Steps
Superior for Moisture, Shock, and Vibration
Resistant to Negative Voltage Undershoots
Industry Standard Configuration
•
•
Industrial Temperature -40° C to +85° C
28-pin “Green”/RoHS SOIC Package
Description
Pin Configuration
The FM16W08 is a 64-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or F-RAM is
nonvolatile but operates in other respects as a RAM.
It provides data retention for 38 years while
eliminating the reliability concerns, functional
disadvantages and system design complexities of
battery-backed SRAM (BBSRAM). Fast write timing
and high write endurance make F-RAM superior to
other types of nonvolatile memory.
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
VDD
WE
NC
2
A12
3
A7
4
A6
A8
5
A5
A9
6
A4
A11
OE
7
A3
8
A2
A10
CE
In-system operation of the FM16W08 is very similar
to other RAM devices. Minimum read- and write-
cycle times are equal. The F-RAM memory, however,
is nonvolatile due to its unique ferroelectric memory
process. Unlike BBSRAM, the FM16W08 is a truly
monolithic nonvolatile memory. It provides the same
functional benefits of a fast write without the
disadvantages associated with modules and batteries
or hybrid memory solutions.
9
A1
10
A0
DQ7
DQ6
DQ5
DQ4
DQ3
11
DQ0
12
DQ1
13
DQ2
14
VSS
Ordering Information
These capabilities make the FM16W08 ideal for
nonvolatile memory applications requiring frequent
or rapid writes in a bytewide environment. The
availability of a true surface-mount package improves
the manufacturability of new designs. Device
specifications are guaranteed over an industrial
temperature range of -40°C to +85°C.
FM16W08-SG
28-pin “Green” SOIC
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Rev. 1.2
Mar. 2011
Page 1 of 11
FM16W08
Address
Latch &
Decoder
A0-A12
A0-A12
8,192 x 8 FRAM Array
CE
Control
Logic
WE
OE
I/O Latch
Bus Driver
DQ0-7
Figure 1. Block Diagram
Pin Description
Pin Name
Type
Description
A(12:0)
Input
Address: The 13 address lines select one of 8,192 bytes in the F-RAM array. The
address value is latched on the falling edge of /CE.
DQ(7:0)
/CE
I/O
Input
Data: 8-bit bi-directional data bus for accessing the F-RAM array.
Chip Enable: /CE selects the device when low. Asserting /CE low causes the
address to be latched internally. Address changes that occur after /CE goes low
will be ignored until the next falling edge occurs.
/OE
Input
Input
Output Enable: Asserting /OE low causes the FM16W08 to drive the data bus
when valid data is available. Deasserting /OE high causes the DQ pins to be tri-
stated.
Write Enable: Asserting /WE low causes the FM16W08 to write the contents of
the data bus to the address location latched by the falling edge of /CE.
Supply Voltage
/WE
VDD
VSS
Supply
Supply
Ground
Functional Truth Table
/CE
H
↓
L
L
/WE
Function
Standby/Precharge
Latch Address (and Begin Write if /WE=low)
Read
X
X
H
↓
Write
Note: The /OE pin controls only the DQ output buffers.
Rev. 1.2
Mar. 2011
Page 2 of 11
FM16W08
/CE goes inactive. Data becomes available on the bus
after the access time has been satisfied.
Overview
The FM16W08 is a bytewide F-RAM memory. The
memory array is logically organized as 8,192 x 8 and
is accessed using an industry standard parallel
interface. All data written to the part is immediately
nonvolatile with no delay. Functional operation of the
F-RAM memory is the same as SRAM type devices,
except the FM16W08 requires a falling edge of /CE
to start each memory cycle.
After the address has been latched, the address value
may be changed upon satisfying the hold time
parameter. Unlike an SRAM, changing address values
will have no effect on the memory operation after the
address is latched.
The FM16W08 will drive the data bus when /OE is
asserted low. If /OE is asserted after the memory
access time has been satisfied, the data bus will be
driven with valid data. If /OE is asserted prior to
completion of the memory access, the data bus will
not be driven until valid data is available. This feature
minimizes supply current in the system by eliminating
transients caused by invalid data being driven onto
the bus. When /OE is inactive the data bus will
remain tri-stated.
Memory Architecture
Users access 8,192 memory locations each with 8
data bits through a parallel interface. The complete
13-bit address specifies each of the 8,192 bytes
uniquely. Internally, the memory array is organized
into 1024 rows of 8-bytes each. This row
segmentation has no effect on operation, however the
user may wish to group data into blocks by its
endurance characteristics as explained on page 4.
Write Operation
Writes occur in the FM16W08 in the same time
interval as reads. The FM16W08 supports both /CE-
and /WE-controlled write cycles. In all cases, the
address is latched on the falling edge of /CE.
The cycle time is the same for read and write memory
operations. This simplifies memory controller logic
and timing circuits. Likewise the access time is the
same for read and write memory operations. When
/CE is deasserted high, a precharge operation begins,
and is required of every memory cycle. Thus unlike
SRAM, the access and cycle times are not equal.
Writes occur immediately at the end of the access
with no delay. Unlike an EEPROM, it is not
necessary to poll the device for a ready condition
since writes occur at bus speed.
In a /CE controlled write, the /WE signal is asserted
prior to beginning the memory cycle. That is, /WE is
low when /CE falls. In this case, the part begins the
memory cycle as a write. The FM16W08 will not
drive the data bus regardless of the state of /OE.
In a /WE controlled write, the memory cycle begins
on the falling edge of /CE. The /WE signal falls after
the falling edge of /CE. Therefore, the memory cycle
begins as a read. The data bus will be driven
according to the state of /OE until /WE falls. The
timing of both /CE- and /WE-controlled write cycles
is shown in the electrical specifications.
It is the user’s responsibility to ensure that VDD
remains within datasheet tolerances to prevent
incorrect operation. Also proper voltage level and
timing relationships between VDD and /CE must be
maintained during power-up and power-down events.
See Power Cycle Timing diagram on page 9.
Write access to the array begins asynchronously after
the memory cycle is initiated. The write access
terminates on the rising edge of /WE or /CE,
whichever is first. Data set-up time, as shown in the
electrical specifications, indicates the interval during
which data cannot change prior to the end of the write
access.
Memory Operation
The FM16W08 is designed to operate in a manner
similar to other bytewide memory products. For users
familiar with BBSRAM, the performance is
comparable but the bytewide interface operates in a
slightly different manner as described below. For
users familiar with EEPROM, the obvious differences
result from the higher write performance of F-RAM
technology including NoDelay writes and much
higher write endurance.
Unlike other truly nonvolatile memory technologies,
there is no write delay with F-RAM. Since the read
and write access times of the underlying memory are
the same, the user experiences no delay through the
bus. The entire memory operation occurs in a single
bus cycle. Therefore, any operation including read or
write can occur immediately following a write. Data
Read Operation
A read operation begins on the falling edge of /CE.
At this time, the address bits are latched and a
memory cycle is initiated. Once started, a full
memory cycle must be completed internally even if
polling,
a technique used with EEPROMs to
determine if a write is complete, is unnecessary.
Rev. 1.2
Mar. 2011
Page 3 of 11
FM16W08
Precharge Operation
150,000 accesses per second to the same row for over
20 years.
The precharge operation is an internal condition that
prepares the memory for a new access. All memory
cycles consist of a memory access and a precharge.
The precharge is initiated by deasserting the /CE pin
high. It must remain high for at least the minimum
precharge time tPC.
F-RAM Design Considerations
When designing with F-RAM for the first time, users
of SRAM will recognize a few minor differences.
First, bytewide F-RAM memories latch each address
on the falling edge of chip enable. This allows the
address bus to change after starting the memory
access. Since every access latches the memory
address on the falling edge of /CE, users cannot
ground it as they might with SRAM.
The user determines the beginning of this operation
since a precharge will not begin until /CE rises.
However, the device has a maximum /CE low time
specification that must be satisfied.
Endurance
Users who are modifying existing designs to use F-
RAM should examine the memory controller for
timing compatibility of address and control pins.
Each memory access must be qualified with a low
transition of /CE. In many cases, this is the only
change required. An example of the signal
relationships is shown in Figure 2 below. Also shown
is a common SRAM signal relationship that will not
work for the FM16W08.
Internally, a F-RAM operates with a read and restore
mechanism. Therefore, each read and write cycle
involves a change of state. The memory architecture
is based on an array of rows and columns. Each read
or write access causes an endurance cycle for an
entire row. In the FM16W08, a row is 64 bits wide.
Every 8-byte boundary marks the beginning of a new
row. Endurance can be optimized by ensuring
frequently accessed data is located in different rows.
Regardless, F-RAM offers substantially higher write
endurance than other nonvolatile memories. The
rated endurance limit of 1014 cycles will allow
The reason for /CE to strobe for each address is two-
fold: it latches the new address and creates the
necessary precharge period while /CE is high.
Valid Strobing of /CE
CE
FRAM
Signaling
A1
A2
Address
D1
D2
Data
Invalid Strobing of /CE
CE
SRAM
Signaling
A1
A2
Address
D1
D2
Data
Figure 2. Chip Enable and Memory Address Relationships
Rev. 1.2
Mar. 2011
Page 4 of 11
FM16W08
A second design consideration relates to the level of
VDD during operation. Battery-backed SRAMs are
forced to monitor VDD in order to switch to battery
backup. They typically block user access below a
certain VDD level in order to prevent loading the
battery with current demand from an active SRAM.
The user can be abruptly cut off from access to the
nonvolatile memory in a power down situation with
no warning or indication.
below VDD min. (2.7V). Figure 3 shows a pullup
resistor on /CE which will keep the pin high during
power cycles assuming the MCU/MPU pin tri-states
during the reset condition. The pullup resistor value
should be chosen to ensure the /CE pin tracks VDD yet
a high enough value that the current drawn when /CE
is low is not an issue.
VDD
F-RAM memories do not need this system overhead.
The memory will not block access at any VDD level
that complies with the specified operating range. The
user should take measures to prevent the processor
from accessing memory when VDD is out-of-
tolerance. The common design practice of holding a
processor in reset during powerdown may be
sufficient. It is recommended that Chip Enable is
pulled high and allowed to track VDD during powerup
and powerdown cycles. It is the user’s responsibility
to ensure that chip enable is high to prevent accesses
FM16W08
R
CE
MCU/
MPU
WE
OE
A(12:0)
DQ
Figure 3. Use of Pullup Resistor on /CE
Rev. 1.2
Mar. 2011
Page 5 of 11
FM16W08
Electrical Specifications
Absolute Maximum Ratings
Symbol
Description
Ratings
-1.0V to +7.0V
-1.0V to +7.0V
and VIN < VDD+1.0V
-55°C to + 125°C
260° C
VDD
VIN
Power Supply Voltage with respect to VSS
Voltage on any pin with respect to VSS
TSTG
TLEAD
VESD
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
Electrostatic Discharge Voltage
- Human Body Model (AEC-Q100-002 Rev. E)
- Charged Device Model (AEC-Q100-011 Rev. B)
- Machine Model (AEC-Q100-003 Rev. E)
Package Moisture Sensitivity Level
4kV
1.25kV
300V
MSL-2
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this
specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
DC Operating Conditions (TA = -40° C to + 85° C, VDD = 2.7V to 5.5V unless otherwise specified)
Symbol Parameter
Min
2.7
Typ
3.3
-
Max
5.5
12
Units
V
Notes
VDD
IDD
Power Supply
VDD Supply Current
mA
µA
µA
µA
V
1
2
3
3
ISB
Standby Current
20
50
ILI
Input Leakage Current
-
-
±1
±1
VDD+0.3
0.3*VDD
ILO
Output Leakage Current
VIH
VIL
Input High Voltage
Input Low Voltage
0.7*VDD
-0.3
V
VOH1
VOH2
VOL1
VOL2
Output High Voltage (IOH = -1 mA, VDD=2.7V)
Output High Voltage (IOH = -100 µA)
Output Low Voltage (IOL = 2 mA, VDD=2.7V)
Output Low Voltage (IOL = 150 µA)
2.4
VDD-0.2
V
V
V
V
0.4
0.2
Notes
1. VDD = 5.5V, /CE cycling at minimum cycle time. All inputs at CMOS levels, all outputs unloaded.
2. /CE at VIH, All other pins at CMOS levels (0.2V or VDD-0.2V).
3. VIN, VOUT between VDD and VSS.
Rev. 1.2
Mar. 2011
Page 6 of 11
FM16W08
Read Cycle AC Parameters (TA = -40°C to + 85°C, CL = 30 pF, unless otherwise specified)
VDD 2.7 to 3.0V VDD 3.0 to 5.5V
Symbol
tCE
tCA
tRC
tPC
tAS
tAH
tOE
tHZ
Parameter
Min
Max
80
Min
Max Units Notes
Chip Enable Access Time (to data valid)
Chip Enable Active Time
Read Cycle Time
Precharge Time
Address Setup Time
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
80
145
65
0
70
130
60
0
Address Hold Time
15
15
Output Enable Access Time
Chip Enable to Output High-Z
Output Enable to Output High-Z
15
15
15
12
15
15
1
1
tOHZ
Write Cycle AC Parameters (TA = -40°C to + 85°C, unless otherwise specified)
VDD 2.7 to 3.0V VDD 3.0 to 5.5V
Symbol
tCA
tCW
tWC
tPC
tAS
tAH
tWP
tDS
tDH
Parameter
Min
80
80
145
65
0
15
50
40
0
Max
Min
70
70
130
60
0
15
40
30
0
Max Units Notes
Chip Enable Active Time
Chip Enable to Write High
Write Cycle Time
Precharge Time
Address Setup Time
Address Hold Time
Write Enable Pulse Width
Data Setup
Data Hold
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWZ
tWX
tHZ
tWS
tWH
Notes
Write Enable Low to Output High Z
Write Enable High to Output Driven
Chip Enable to Output High-Z
Write Enable Setup
15
15
15
15
ns
ns
ns
ns
ns
1
1
1
2
2
10
10
0
0
0
0
Write Enable Hold
1
2
This parameter is periodically sampled and not 100% tested.
The relationship between /CE and /WE determines if a /CE- or /WE-controlled write occurs. There is no timing
specification associated with this relationship.
Data Retention
Symbol
TDR
Parameter
Min
10
19
Max
Units
Years
Years
Years
Notes
@
@
@
+85ºC
+80ºC
+75ºC
-
-
-
38
Rev. 1.2
Mar. 2011
Page 7 of 11
FM16W08
Capacitance (TA = 25° C, f=1.0 MHz, VDD = 5V)
Symbol
CI/O
CIN
Parameter
Input/Output Capacitance (DQ)
Input Capacitance
Min
-
-
Max
8
6
Units
pF
pF
Notes
AC Test Conditions
Input Pulse Levels
Equivalent AC Load Circuit
10% and 90% of VDD
Input rise and fall times
Input and output timing levels
5 ns
0.5 VDD
Read Cycle Timing
tRC
tCA
tPC
CE
tAH
tAS
A0-14
OE
tOE
tOHZ
DQ0-7
tCE
tHZ
Write Cycle Timing - /CE Controlled Timing
tWC
tCA
tPC
CE
tAH
tAS
A0-14
tWS
tWH
WE
OE
tDS
tDH
DQ0-7
Rev. 1.2
Mar. 2011
Page 8 of 11
FM16W08
Write Cycle Timing - /WE Controlled Timing
tWC
tCA
tPC
tC W
CE
tAH
tAS
A0-14
tWH
tWS
tWP
WE
OE
tWZ
tWX
DQ0-7
out
tDH
tDS
DQ0-7
in
Power Cycle Timing
VDD (min)
VDD (min)
tPU
VDD
tPD
tPC
V
V
IH (min)
IH (min)
CE
V
IL (max)
Power Cycle Timing (TA = -40° C to + 85° C, VDD = 2.7V to 5.5V unless otherwise specified)
Symbol
tPU
tPD
tVR
tVF
Parameter
Min
10
0
30
100
Max
Units
ms
µs
µs/V
µs/V
Notes
VDD(min) to First Access Start
Last Access Complete to VDD(min)
VDD Rise Time
-
-
-
-
1
1
VDD Fall Time
Notes
1. Slope measured at any point on VDD waveform.
Rev. 1.2
Mar. 2011
Page 9 of 11
FM16W08
28-pin SOIC (JEDEC MS-013 variation AE)
All dimensions in millimeters
7.50 ±0.10 10.30 ±0.30
0.25
0.75
Pin 1
17.90 ±0.20
2.35
2.65
0.23
0.32
°
45
0?- 8?
0.10
1.27 typ
0.10
0.30
0.40
1.27
0.33
0.51
SOIC Package Marking Scheme
Legend:
XXXXXX= part number, P= package type (-SG)
R=rev code, YY=year, WW=work week, LLLLLL= lot code
RAMTRON
XXXXXXX-P
RYYWWLLLLLL
Example: FM16W08, 70ns speed, “Green”/RoHS SOIC package,
A die rev., Year 2010, Work Week 37, Lot code 00002G
RAMTRON
FM16W08-SG
A103700002G
Rev. 1.2
Mar. 2011
Page 10 of 11
FM16W08
Revision History
Revision
Date
Summary
1.0
1.1
1.2
11/22/2010
12/20/2010
3/10/2011
Initial Release
Updated MSL rating.
Changed tPU and tVF spec limits.
Rev. 1.2
Mar. 2011
Page 11 of 11
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