QT60645 [QUANTUM]
32, 48, 64 KEY QMatrix KEYPANEL SENSOR ICS; 32 , 48 , 64 KEY QMatrix KEYPANEL传感器IC型号: | QT60645 |
厂家: | QUANTUM RESEARCH GROUP |
描述: | 32, 48, 64 KEY QMatrix KEYPANEL SENSOR ICS |
文件: | 总42页 (文件大小:810K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LQ
QT60325, QT60485, QT60645
ENSOR IC
S
PRELIMINARY
32, 48, 64 KEY QMatrix™ KEYPANEL
S
ꢀ Advanced second generation QMatrix controllers
ꢀ Up to 32, 48 or 64 touch keys through any dielectric
ꢀ Panel thicknesses to 5 cm or more
34
44 43 42 41 40 39 38 37 36 35
MOSI
MISO
SCLK
RST
Vdd
1
2
3
4
5
6
7
8
9
33
CZ2
YS0
YS1
YS2
Aref
AGnd
AVdd
YC7
YC6
YC5
YC4
ꢀ 100% autocal for life - no adjustments required
ꢀ Keys individually adjustable for sensitivity, response time,
and many other critical parameters
32
31
30
29
28
27
26
25
24
23
QT60325
QT60485
QT60645
ꢀ Mix and match key sizes & shapes in one panel
ꢀ Passive matrix - no components at the keys
ꢀ Moisture suppression capable
Vss
XTO
XTI
TQFP-44
X0
ꢀ AKS™ - Adjacent Key Suppression feature
ꢀ Synchronous noise suppression
ꢀ Sleep mode with wake pin
X1
10
11
X2WS
13 14 15 16 17 18 19 20 21 22
12
ꢀ SPI Slave or Master/Slave interface to a host controller
ꢀ Low overhead communications protocol
ꢀ 44-pin TQFP package
APPLICATIONS
ꢀ Security keypanels
ꢀ Industrial keyboards
ꢀ Appliance controls
ꢀ Outdoor keypads
ꢀ ATM machines
ꢀ Touch-screens
ꢀ Automotive panels
ꢀ Machine tools
The QT60325, QT60485, and QT60645 digital charge-transfer (“QT”) QMatrix™ ICs are designed to detect human touch on up to
32, 48, or 64 keys respectively using a scanned, passive X-Y matrix. It will project the keys through almost any dielectric, e.g.
glass, plastic, stone, ceramic, and even wood, up to thicknesses of 5 cm or more. The touch areas are defined as simple 2-part
interdigitated electrodes of conductive material, like copper or screened silver or carbon deposited on the rear of a control panel.
Key sizes, shapes and placement are almost entirely arbitrary; sizes and shapes of keys can be mixed within a single panel of
keys and can vary by a factor of 20:1 in surface area. The sensitivity of each key can be set individually via simple functions over
the SPI port, for example via Quantum’s QmBtn program. Key setups are stored in an onboard eeprom and do not need to be
reloaded with each power-up.
These ICs are designed specifically for appliances, electronic kiosks, security panels, portable instruments, machine tools, or
similar products that are subject to environmental influences or even vandalism. They permit the construction of 100% sealed,
watertight control panels that are immune to humidity, temperature, dirt accumulation, or the physical deterioration of the panel
surface from abrasion, chemicals, or abuse. To this end the devices contain Quantum-pioneered adaptive self-calibration, drift
compensation, and digital filtering algorithms that make the sensing function robust and survivable. The devices use short dwell
times and Quantum’s patent-pending AKS™ feature to permit operation in wet environments.
The parts use a passive key matrix, dramatically reducing cost over older technologies that require an ASIC for every key. The
key-matrix can be made of standard flex material (e.g. Silver on PET plastic) or ordinary PCB material to save cost.
External circuitry consists of an opamp, R2R ladder-DAC network, a common PLD, a FET switch, and a small number of resistors
and capacitors which can fit into a footprint of roughly 8 sq. cm (1.5 sq. in). Control and data transfer is via a SPI port which can
be configured in either a Slave or Master/Slave mode.
QT60xx5 ICs make use of an important new variant of charge-transfer sensing, transverse charge-transfer, in a matrix format that
minimizes the number of required scan lines to provide a high economy of scale.
AVAILABLE OPTIONS
TA
TQFP
00C to +700C
00C to +700C
00C to +700C
-400C to +1050C
-400C to +1050C
-400C to +1050C
QT60325-S
QT60485-S
QT60645-S
QT60325-AS
QT60485-AS
QT60645-AS
lQ
Copyright © 2001 Quantum Research Group Ltd
Pat Pend. R1.05/0802
© Quantum Research Group Ltd.
Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
3
4
5
6
7
0x32 - Reference Value
0x33 - R2R Offset
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4
4
4
5
5
5
5
6
6
6
6
7
7
7
8
8
8
8
9
9
9
9
9
9
1.1 Field Flows
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x34 - Cz State
1.2 Circuit Model
0x35 - Detection Integrator Counts
1.3 Matrix Configuration
. . . . . . . . . . . . . . . . . . . . . . 22
. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
. . . . . . . . . . . . . . . . . . . . . . . . . 22
. . . . . . . . . . . . . . . . . . . . . . . 22
. . . . . . . . . . . . . . . . . . . . . . . . . 22
. . . . . . . . . . . . . . . . . . . . . . 22
. . . . . . . . . . . . . . . . . . . . . . . . . . 22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x36 - Eeprom Checksum
1.4 Communications
0x37 - General Device Status
2 Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Negative Threshold
<sp> 0x20 - Signal Levels for Group
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
!
0x21 - Delta Signals for Group
2.2 Positive Threshold
"
0x22 - Reference Levels for Group
2.3 Hysteresis
#
$
%
e
k
K
0x23 - R2R Offset for Group
2.4 Drift Compensation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x24 - Charge Cancellation for Group
2.5 Detection Recalibration Delay
. . . . . . . . . . . . . . . . . . . . 22
. . . . . . . . . . . . . . . . . 22
. . . . . . . . . . . . . . . . . . . . . 23
. . . . . . . . . . . . . . . . . . . . 23
. . . . . . . . . . . . . . . . . . . 24
. . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0x25 - Detect Integrator Counts for Group
2.6 Detect Integrator (‘DI’)
0x65 - Error Code for Selected Key
0x6B - Reporting of First Touched Key
0x4B - Key Touch Reporting for Group
2.7 Positive Recalibration Delay
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 Reference Guardbanding
2.9 Adjacent Key Suppression (AKS™)
. . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 Setup Commands
^A 0x01 - Negative Detect Threshold
2.10 Full Recalibration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
. . . . . . . . . . . . . . . . . . . . . . . 24
. . . . . . . . . . . . . . . . . . . . . . . 24
2.11 Boundary Error Reporting
2.12 Device Status & Reporting
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Circuit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
^B 0x02 - Positive Detect Threshold
^C 0x03 - Negative Threshold Hysteresis
^D 0x04 - Positive Threshold Hysteresis
^E 0x05 - Dwell Time in Machine Cycles
^G 0x07 - Burst Spacing
. . . . . . . . . . . . . . . . . . . . 25
. . . . . . . . . . . . . . . . . . . . . 25
. . . . . . . . . . . . . . . . . . . . . 25
3.1 Part Differences
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Matrix Scan Sequence
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3 Signal Path
^H 0x08 - Negative Drift Compensation Rate
. . . . . . . . . . . . . . . . . . 26
. . . . . . . . . . . . . . . . . . . 26
. . . . . . . . . . . . . . . . . . . . . . . . . 26
. . . . . . . . . . . . . . . . . . . . . 26
. . . . . . . . . . . . . . . . . . . . . 26
. . . . . . . . . . . . . . . . . . . . . . . 27
3.4 'X' Electrode Drives
3.4.1 RFI From X Lines
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
^I 0x09 - Positive Drift Compensation Rate
^J 0x0A - Detect Integrator Limit
3.4.2 Noise Coupling Into X lines
. . . . . . . . . . . . . . . . . . . . . . . . . . 12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
^K 0x0B - Positive Recalibration Delay
3.5 'Y' Gate Drives
3.5.1 RFI From Y Lines
^L 0x0C - Negative Recalibration Delay
^M 0x0D - Intra-Burst Pulse Spacing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5.2 Noise Coupling Into Y Lines
3.6 Burst Length & Sensitivity
3.7 Intra-Burst Spacing
. . . . . . . . . . . . . . . . . . . . . . . . . . 12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
^N 0x0E - Positive Reference Error Band
^O 0x0F - Negative Reference Error Band
^P 0x10 - Adjacent Key Suppression (‘AKS’)
5.5 Supervisory / System Functions
. . . . . . . . . . . . . . . . . . . . 27
. . . . . . . . . . . . . . . . . . . 27
. . . . . . . . . . . . . . . . . . 27
3.8 Burst Spacing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
. . . . . . . . . . . . . . . . . . . . . . . . 28
. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.9 PLD Circuit and Charge Sampler
3.10 Opamps
. . . . . . . . . . . . . . . . . . . . . . . 13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
D
L
b
l
0x36 - Eeprom Checksum
0x44 - DAC Test
3.11 Sample Capacitors
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
0x4C - Lock Reference Levels
. . . . . . . . . . . . . . . . . . . . . . . . . 28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.12 R2R Resistor Ladder
0x62 - Recalibrate Keys
3.13 Water Film Suppression
3.14 Reset Input
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
0x6C - Return Last Command Character
. . . . . . . . . . . . . . . . . . . 28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
r
0x72 - Reset Device
3.15 Oscillator
V
W
Z
0x56 - Return Part Version
. . . . . . . . . . . . . . . . . . . . . . . . . . . 29
. . . . . . . . . . . . . . . . . . . . . . . . . 29
3.16 Startup / Calibration Times
3.17 Sleep_Wake / Noise Sync
3.18 LED / Alert Output
. . . . . . . . . . . . . . . . . . . . . . . . . . 14
. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
0x57 - Return Part Signature
0x5A - Enter Sleep
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
^Q 0x11 - Data Rate Selection
^R 0x12 - Oscilloscope Sync
^S 0x13 - Cs Clamp Polarity
. . . . . . . . . . . . . . . . . . . . . . . . . . 29
. . . . . . . . . . . . . . . . . . . . . . . . . . . 29
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.19 CSR Drive Polarity
3.20 Oscilloscope Sync
3.21 Power Supply and PCB Layout
. . . . . . . . . . . . . . . . . . . . . . . . 15
. . . . . . . . . . . . . . . . . . . . . . . . . . 16
4 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
^T 0x14 - Boundary Eqn Constant C1, MSB
^U 0x15 - Boundary Eqn Constant C1, LSB
^V 0x16 - Boundary Equation Constant C2
^W 0x17 - Noise Sync
. . . . . . . . . . . . . . . . . . 30
. . . . . . . . . . . . . . . . . . 30
. . . . . . . . . . . . . . . . . . . 30
3.22 ESD / Noise Considerations
4.1 Serial Port specifications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2 Protocol Overview
5.6 Function Summary Table
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6 PLD Source Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.3 SPI Slave-Only Mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.7 Timing Limitations
4.4 SPI Master-Slave Mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5 Sensor Echo and Data Response
. . . . . . . . . . . . . . . . . . . . . . . 19
4.6 Eeprom Corruption
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5 Commands & Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1 Direction Commands
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
g
0x67 - Get Command
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
. . . . . . . . . . . . . . . . . . . . . . . . . . 21
p
0x70 - Put Command
5.2 Scope Commands
s
S
x
0x73 - Specific Key Scope
0x53 - All Keys Scope
0x78 - Row Keys Scope
y
0x79 - Column Keys Scope
5.3 Status Commands
0
0x30 - Signal for Single Key
1
0x31 - Delta Signal for Single Key
. . . . . . . . . . . . . . . . . . . . . . . 21
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www.qprox.com QT60xx5 / R1.05
©Quantum Research Group Ltd.
Table 1.1 Device Pin List
Pin
Name
Type Description
Master-Out / Slave In SPI line. In Master/Slave SPI mode is used for both communication directions.
In Slave SPI mode is the data input (in only).
Master-In / Slave Out SPI line. Not used in Master/Slave SPI mode.
In Slave mode outputs data to host (out only).
SPI Clock. In Master mode is an output; in Slave mode is an input
Reset input, active low reset
1
MOSI
I/O PP
2
MISO
I/O PP
3
4
5
6
SCK
RST
Vdd
Vss
I/O PP
I
Pwr
Pwr
+5 supply
Ground
Oscillator drive output. Connect to resonator or crystal. Can drive a charge pump circuit for Vee
supply
7
XTO
O
8
XTI
X0
I
O
Oscillator drive input. Connect to resonator or crystal, or external clock source.
X0 Drive matrix scan / R2R DAC Ladder drive
X1 Drive matrix scan / R2R DAC Ladder drive
X2 Drive matrix scan / R2R DAC Ladder drive / Wake from Sleep / Sync to noise source
X3 Drive matrix scan / R2R DAC Ladder drive
X4 Drive matrix scan / R2R DAC Ladder drive
X5 Drive matrix scan / R2R DAC Ladder drive
X6 Drive matrix scan / R2R DAC Ladder drive
X summation / R2R DAC Ladder drive
+5 supply
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
X1
O
X2WS
X3
X4
O
O
O
X5
X6
O
O
XS
O
Vdd
Vss
YC0
YC1
YC2
YC3
YC4
YC5
YC6
YC7
AVdd
AGnd
Aref
YS2
YS1
YS0
CZ2
CZ1
CSR
Ain
Pwr
Pwr
O
Ground
Y 0 Line clamp control
O
Y 1 Line clamp control
Y 2 Line clamp control
O
O
Y 3 Line clamp control
Y 4 Line clamp control
O
O
Y 5 Line clamp control
Y 6 Line clamp control
O
O
Y 7 Line clamp control
+5 supply for analog sections
Pwr
Pwr
Pwr
O
Analog ground
Analog reference, connect to Vcc
Transfer switch control bit 2
Transfer switch control bit 1
Transfer switch control bit 0
O
O
O
Charge cancellation drive for CZ2 capacitor
Charge cancellation drive for CZ1 capacitor
Charge integrator reset line. Active high or active low (select polarity via Setups)
Analog input from amplifier
O
O
I
MS
I/O OD
Pwr
Pwr
O
SPI Mode / Sync out. Connect via 10k resistor to Vcc or Gnd for mode. Scope sync yields Pulse.
+5 supply
Ground
Vdd
Vss
LED
DRDY
X7
Active low LED status drive / Activity indicator
Data ready output for Slave SPI mode; active low
X7 Drive matrix scan
O OD
O
YG
SS
O
IO OD
Y gate control to drive Y dwell timing circuit
Slave select for SPI direction control; active low
I/O: I = Input
O = Output
Pwr = Power pin
I/O = Bi-directional line
PP = Push Pull output drive
OD = Open drain output drive
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www.qprox.com QT60xx5 / R1.05
© Quantum Research Group Ltd.
Figure 1-2 Sample Electrode Geometries
1 Overview
QMatrix devices are digital burst mode charge-transfer (QT)
sensors designed specifically for matrix geometry touch
controls; they include all signal processing functions
necessary to provide stable sensing under a wide variety of
changing conditions. Only a few external parts are required
for operation. The entire circuit can be built within 8 square
centimeters of PCB area.
PARALLEL LINES
SERPENTINE
SPIRAL
Figure 1-1 Field flow between X and Y elements
edge transitions of the X drive pulse. The charge emitted by
the X electrode is partly received onto the corresponding Y
electrode which is then processed. The parts use 8 'X'
edge-driven rows and 8 'Y' sense columns to permit up to 64
keys. Keys are typically formed from interleaved conductive
traces on a substrate like a flex circuit or PCB (Figure 1-2).
overlying panel
X
Y
The charge flows are absorbed by the touch of a human
finger (Figure 1-3) resulting in a decrease in coupling from X
to Y. Thus, received signals decrease or go negative with
respect to the reference level during a touch.
element
element
Water films cause the coupled fields to increase slightly,
making water films easy to distinguish from touch.
QMatrix devices include charge cancellation methods which
allow for a wide range of key sizes and shapes to be mixed
together in a single touch panel. These features permit the
construction of entirely new classes of keypads never before
contemplated, such as touch-sliders, back-illuminated keys,
and complex warped panel shapes, all at very low cost.
1.2 Circuit Model
An electrical circuit model is shown in Figure 1-5. The
coupling capacitance between X and Y electrodes is
represented by Cx. While the reset switch is open, a sample
switch is gated so that it transfers charge flows only from the
rising edge of X into a charge integrator. On the falling edge
of X, the switch connects the Y line to ground to allow the
charge across Cx to neutralize to zero. The voltage change
on the output of the charge integrator after each X edge is
quite small, on the order of a few tens of millivolts. Changes
due to touch are typically under 0.1% of total integrator
voltage. The X pulse can be
The devices use an SPI interface running at up to 1.5MHz to
allow key data to be extracted and to permit individual key
parameter setup. The interface protocol uses simple single
byte commands and responds with single byte responses in
most cases. The command structure is designed to minimize
the amount of data traffic while maximizing the amount of
information conveyed.
repeated in a burst of up to 64
pulses to increase the change in
integrator output voltage due to
touch during an acquire (Section
3.6) to increase gain.
Figure 1-3 Field Flows When Touched
In addition to normal operating
and setup functions the device
can also report back actual
signal strengths and error codes.
QmBtn software for the PC can
be used to program the IC as
well as read back key status and
signal levels in real time.
The charge detector is an opamp
configured as an integrator with a
reset switch; this creates a virtual
ground input, making the Y lines
appear low impedance when the
sample switch is closed. This
configuration effectively
eliminates cross-coupling among
Y lines while greatly lowering
QMatrix parts employ transverse
charge-transfer ('QT') sensing, a
new technology that senses
changes in the charge forced
across an electrode by a digital
edge.
overlying panel
X
Y
element
element
susceptibility to EMI. The circuit
is also highly immune to
The parts are electrically
identical with the exception of the
number of keys which may be
sensed.
capacitive loading on the Y lines,
since stray C from Y to ground
appears merely as a small
parallel capacitance across a
Figure 1-4 Fields With a Conductive Film
virtual ground.
1.1 Field Flows
The circuit uses an 8-bit ADC,
with a subranging structure to
effectively deliver a 14-bit total
conversion 'space' (see Figure
1-6 and Section 3.3). In this way
the circuit can tolerate very large
Figure 1-1 shows how charge is
transferred across an electrode
set to permeate the overlying
panel material; this charge flow
exhibits a high dQ/dt during the
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Short sample gate dwell times after the X
edges will limit the effect of moisture
spreading from key to key by taking
advantage of the RC filter-like nature of
continuous films; a short dwell time will limit
the time that the charge has to travel
through the impedance of the film (Section
3.13). This effect is independent of the
frequency of burst repetition, intra-burst
pulse spacing, or X drive pulse width.
Figure 1-5 QT60xx5 Basic Circuit Model
Sample
switch (1 of 8)
X drive
(1 of 8)
Y line
(1 of 8)
0
Cx
Cancellation
Xn
switches
1
X
Y
Reset switch
electrode
electrode
0
Cz1
1
Burst mode operation permits reduced
power consumption and reduces RF
emissions, while permitting excellent
response time.
Cs
Cz2
Ca
Cha rge
In te grator
Xn
To 60xxx ADC
Amp
Reset
switch
1.3 Matrix Configuration
S
a
m
p
le
The matrix scanning configuration is shown
in Figure 1-5. The ‘X’ drives are sequentially
pulsed in groupings of bursts; an 8:1 analog
mux acts as the sample switch for all ‘Y’
lines. At the intersection of each ‘X’ and ‘Y’
line in the matrix itself, where a key is
s
w
i
tc
h
From60xxx
8-bit
Offset DAC
Offset Control
Amp
out
V
ou t
0
absolute signals yet still respond to very small signal
changes. Subranging is provided by two offset mechanisms
which can be thought of as 'coarse' and 'fine' offsets.
desired, should be an interdigitated electrode set similar to
those shown in Figure 1-2. The outermost electrode or the
key border should always be connected to an ‘X’ drive;
flooding the area around keys with X fill to a width of up to
10mm can help in suppressing moisture films further.
The 'coarse' method uses one or two switched Cz capacitors
to subtract charge from the charge integrator to create up to
two step offsets, to bring the analog signal back to a more
reasonable level. This action occurs during the course of the
burst.
Although it is referred to as a ‘matrix’, there is no restriction
on where individual keys can be located. The term ‘matrix’
refers to the electrical configuration of keys, not the physical
arrangement. Consult Quantum for application assistance on
key design.
The 'fine' method of offset uses an 8-bit R2R ladder DAC
driven by the X drive lines to create an offset in the amplifier
stage. The DAC is driven after the burst has ceased and the
charge accumulated, so there is no conflict in this dual-use of
the X lines.
1.4 Communications
The device uses two variants of SPI communications,
Slave-only and Master-Slave. Over this interface is a
command and data transfer structure
Figure 1-6 Circuit Block Diagram (8x8 Matrix Shown)
designed for high levels of flexibility using
minimal numbers of bytes. For more
information see Sections 4 and 5.
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X0
X1
X2
X3
X4
X5
X6
X7
X0
X1
X2
X3
X4
X5
X6
X7
Device variations: Refer to Section 3.1 for
differences between the parts covered by
this datasheet.
SPI
to
Host
2 Signal Processing
✟
X{1..7}
X7
XS
The devices calibrate and process all
signals using a number of algorithms
specifically designed to provide for high
survivability in the face of adverse
environmental challenges. They provide a
large number of processing options which
can be user-selected to implement very
flexible, robust keypanel solutions.
Timing &
Charge
YC0 .
.
YC1
YC2 .
YC3
YC4 .
YC5
YC6 .
YC7
Neutralizing
Control
(PLD)
.
.
Transfer Strobe
Transfer Select
.
YS0..YS2
X0 .
.
X2 .
.
X4 .
.
X6 .
.
Transfer
M ux
X1
Signal Offset
Charge
R2R
DAC
X3
X5
XS
QT60xx5
AIN
Integrator
+
-
2.1 Negative Threshold
See also command ^A, page 24
Gain
✟
✟
“
Amp
The negative threshold value is established
relative to a key’s signal reference value.
The threshold is used to determine key
touch when crossed by a negative-going
signal swing after having been filtered by
Integrator Reset
CSR
Charge Cancellation 1
Charge Cancellation 2
CZ1
Cz1
Cz2
CZ2
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the detection integrator (Section 2.6). Larger absolute values when the signal in question has not crossed the negative
of threshold desensitize keys since the signal must travel
farther in order to cross the threshold level. Conversely, lower
thresholds make keys more sensitive.
threshold level (Section 2.1).
The drift compensation mechanism can be made asymmetric
if desired; the drift-compensation can be made to occur in
one direction faster than it does in the other simply by setting
^H and ^I to different settings.
As Cx and Cs drift, the reference point drift-compensates for
these changes at a user-settable rate (Section 2.4); the
threshold level is recomputed whenever the reference point
moves, and thus it also is drift compensated.
Specifically, drift compensation should be set to compensate
faster for increasing signals than for decreasing signals.
Decreasing signals should not be compensated quickly, since
an approaching finger could be compensated for partially or
entirely before even touching the touch pad. However, an
obstruction over the sense pad, for which the sensor has
already made full allowance for, could suddenly be removed
leaving the sensor with an artificially suppressed reference
level and thus become insensitive to touch. In this latter case,
the sensor should compensate for the object's removal by
raising the reference level relatively quickly.
The negative threshold is programmed on a per-key basis
using the setup process described in Section 5.
2.2 Positive Threshold
See also command ^B, page 24
The positive threshold is used to provide a mechanism for
recalibration of the reference point when a key's signal moves
abruptly to the positive. These transitions are described more
fully in Section 2.7.
The drift compensation rate can be set for each key
individually, and can also be disabled completely if desired on
a per-key basis.
Positive threshold levels are programmed in using the setup
process described in Section 5 on a per-key basis.
Drift compensation and the detection time-outs (Section 2.5)
work together to provide for robust, adaptive sensing. The
time-outs provide abrupt changes in reference calibration
depending on the duration of the signal 'event'.
2.3 Hysteresis
See also command ^C and ^D, page 25
Refer to Figure 2-1. QT60xx5 ICs employ programmable
hysteresis levels of 12.5%, 25%, or 50% of the delta between
the reference and threshold levels. There are different
hysteresis settings for positive and negative thresholds which
can be set by the user. The hysteresis is a percentage of the
distance from the threshold level back towards the reference,
and defines the point at which the detection will drop out. A
percentage of 12.5% is less hysteresis than 25%, and the
12.5% hysteresis point is closer to the threshold level than to
the reference level.
Drift compensation can result in reference levels that are at
the boundaries of the 8-bit signal window. When this occurs,
saturation is reached and the drift compensation process
stops. One of two error flags is set when the signal
approaches either end of the signal window; it is up to the
host to read these flags and induce a full recalibration via a
recalibration command at that time (Section 2.10 and
command ‘b’, page 28) for the key in question.
2.5 Detection Recalibration Delay
See also command ^L, page 26
The hysteresis levels are set for all keys only; it is not
possible to set the hysteresis differently from key to key on
either the positive or negative hysteresis levels.
If a foreign object contacts a key the key's signal may change
enough in the negative direction, the same as a normal
touch, to create an unintended detection. When this happens
it is usually desirable to cause the key to be recalibrated in
order to restore its function after a time delay of some
seconds.
2.4 Drift Compensation
See also commands ^H, ^I, page 26
Signals can drift because of changes in Cx and Cs over time
and temperature. It is crucial that such drift be compensated,
else false detections and sensitivity shifts can occur. The
QT60xx5 compensates for drift using setups, ^H and ^I.
The Negative Recal Delay timer monitors this detection
duration; if a detection event exceeds the timer's setting, the
key will be fast-recalibrated within its current 8-bit window.
This form of recalibration is simply one of setting Reference =
Signal, and does not affect Offset or Cz state; as a result this
form of recalibration requires only one burst spacing interval
t
Drift compensation (Figure 2-1) is performed by making the
reference level track the raw signal at a slow rate, but only
while there is no detection in effect. The rate of adjustment
must be performed slowly, otherwise legitimate
detections could be ignored. The devices drift
compensate using a slew-rate limited change to
the reference level; the threshold and hysteresis
values are slaved to this reference.
Figure 2-1 Thresholds and Drift Compensation
When a finger is sensed, the signal falls since the
human body acts to absorb charge from the
Reference
Hysteresis
Threshold
cross-coupling between X and Y lines. An isolated,
untouched foreign object (a coin, or a water film)
will cause the signal to rise very slightly due to an
enhancement of coupling. This is contrary to the
way most capacitive sensors operate.
Signal
Once a finger is sensed, the drift compensation
mechanism ceases since the signal is legitimately
detecting an object. Drift compensation only works
Output
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o accomplish. Only a full recalibration via a reset or a
2.8 Reference Guardbanding
See also commands ^N, ^O, page 27; L, page 28
recalibration command will perform a complete recalibration
involving both the R2R Offset and Cz capacitors (Section
2.10).
QT60xx5 devices provide for a method of self-checking that
allows the host device to ascertain whether one or more key
reference levels are 'out of spec'. This feature can be used to
determine if an X or Y line has broken, the matrix panel has
delaminated from the control panel, or there is a circuit fault.
After a fast recalibration has taken place, the affected key will
once again function normally even if it is still being contacted
by the foreign object. This feature is set on a per-key basis
using setup ^L. It can be disabled if desired by setting this
parameter to zero, so that it will not recalibrate automatically.
Guardbanding alerts the host controller when the reference
level of a key falls outside of acceptable absolute levels. The
guardband is expressed in percent of absolute reference from
the reference level of each individual key. The normal
reference levels can be locked into internal eeprom via the
Lock command 'L' during production; deviations in references
that fall outside the guardbands centered on these reference
levels are then reported as errors.
2.6 Detect Integrator (‘DI’)
See also command ^J, page 26
To suppress false detections caused by spurious events like
electrical noise, the QT60xx5 incorporates a 'detection
integrator' or DI counter that increments with each sample
where the signal passes below the negative threshold, until a
user-defined DI limit is reached, at which point the detection
is confirmed and the corresponding detect bit is set.
The calculations required for guardbanding are performed
after the device has recalibrated or been reset after the ‘L’
command.
If before the DI limit is reached, the signal rises to a point
between the hysteresis and threshold levels, the DI counter is
decremented with each such sample to a limit of zero.
Positive excursion guarding is treated separately from
negative excursion guarding. The possible negative settings
are from 1% to 99% of absolute signal reference in steps of
1% as set by command ^O. Positive excursions can run from
10% to 1,000% in steps of 10% as set by command ^N. A
setting of 0 disables the corresponding guardband direction.
If before the DI limit is reached, the signal rises above the
hysteresis level, the DI counter is immediately cleared.
When an active key is released, the DI must count down to
zero before the key state is cleared. Clearing a key’s DI limit
disables that key although the bursts for that key continue.
Since the circuit uses a segmented ADC approach with a
'coarse' (based on Cz states) and 'fine' (based on R2R ladder
drive) offsets, the determination of percentage reference
deviation from 'normal' presents a problem. The contributions
of the Cz caps and the R2R ladder must be factored into the
determination in order to make an accurate assessment of
the error band. There are three commands which set
coefficients used to convert the Cz and DAC offset values to
'absolute signal' values, according to the following equation,
for each key:
The DI is extremely effective at reducing false detections at
the expense of slower reaction times. In some applications a
slow reaction time is desirable; the DI can be used to
intentionally slow down touch response in order to require the
user to touch longer to operate the key.
There are 16 possible values for the DI limit.
2.7 Positive Recalibration Delay
See also command ^K, page 26
TotalRef(k) = (C1 x nCz) + (C2 x Offset) + SigRef
Where -
TotalRef(k) is the equivalent absolute reference for key ‘k’;
C1 is a global constant set by commands ^T and ^U;
C2 is a global constant set by command ^V;
nCz is the number of Cz caps switched in for key ‘k’;
Offset is the noted value of the R2R DAC for key ‘k’;
SigRef is the noted current 'window reference' for key ‘k’.
A recalibration can occur automatically if the signal swings
more positive than the positive threshold level. This condition
can occur if there is positive drift but insufficient positive drift
compensation, or if the reference moved negative due to a
recalibration, and thereafter the signal returned to normal.
As an example of the latter, if a foreign object or a finger
contacts a key for period longer than the Negative Recal
Delay, the key is by recalibrated to a new lower reference
level. Then, when the condition causing the negative swing
ceases to exist (e.g. the object is removed) the signal can
suddenly swing back positive to near its normal reference.
The percent deviations are computed in relation to
TotalRef(k) on a per-key basis at the time the 'L' command is
executed. Once the L command has recorded all values of
relating to TotalRef into eeprom, the part will compare the
actual running reference level of each key to its
corresponding computed TotalRef value to see if it falls
outside the guardbands specified by global parameters ^N
and ^O.
It is almost always desirable in these cases to cause the key
to recalibrate to the new signal level so as to restore normal
touch operation. The device accomplishes this by simply
setting Reference = Signal.
Values which correspond to the reference circuit of Figure 3-1
are:
The time required to detect this condition before recalibrating
is governed by the Positive Recalibration Delay command. In
order for this feature to operate, the signal must rise through
the positive threshold level (Section 2.2) for the proscribed
user-set interval determined by ^K.
C1 = 1513; ^T value = 0x05, ^U value = 0xE9
C2 = 8; ^V value = 0x08
Guardbanding tests should not be confused with Reference
Boundary errors (Section 2.11). Guardbanding can report
errors that occur even if the signal is properly centered in the
ADC window, while Reference Boundary error reporting
cannot. Guardband tests do however require that the key
After the Positive Recal Delay interval has expired and the
fast-recalibration has taken place, the affected key will once
again function normally. This interval can be set on a per-key
basis; it can also be disabled by setting ^K to zero.
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being checked be first fully recalibrated in order to allow the
Cz and DAC offset values to alter.
Individual keys or groups of keys can be recalibrated with a
single command depending on the current command scope.
The time required to recalibrate many keys is not
multiplicative; the cal process for multiple keys runs in
parallel.
If a key is outside of a limit, either of bits 2 and 3 of command
'e' will be set for that key. The error will also appear as an
error in a bitfield reported with command 'E'.
There is no mechanism by which keys will automatically
recalibrate if the reference drifts past a guardband boundary.
2.11 Boundary Error Reporting
See also commands ‘e’, page 23; ^N, page 27
Unlike guardband error reporting, boundary error reporting
only works within the active ADC signal window segment in
which the key's signal resides. Complex factoring of Cz and
Offset are not required for these tests, and the tests do not
require that the key be recalibrated to see the error condition.
2.9 Adjacent Key Suppression (AKS™)
See also command ^P, page 27
QT60xx5 devices incorporate adjacent key suppression
(‘AKS’ - patent pending) that can be selected on a per-key
basis. AKS permits the suppression of multiple key presses
based on relative signal strength. This feature assists in
solving the problem of surface moisture which can bridge a
key touch to an adjacent key, causing multiple key presses.
This feature is also useful for panels with tightly spaced keys,
where a fingertip might inadvertently activate an adjacent key.
Drift compensation can cause a key's reference level to move
near to the border of the ADC's 8-bit signal window; this may
make a key inoperable if the reference pegs near zero,
depriving the signal of the ability to move further negative
when a key is touched. Normally the reference level should
be reasonably centered within the ADC's current range, i.e. at
a level of about 128 decimal / 0x80 hex.
AKS works for keys that are AKS-enabled anywhere in the
matrix and is not restricted to physically adjacent keys; the
device has no knowledge of which keys are actually
physically adjacent. When enabled for a key, adjacent key
suppression causes detections on that key to be suppressed
if any other AKS-enabled key in the panel has a more
negative signal deviation from its reference.
The truth logic for reference level drift error reporting is:
e/b2 = Reference > 191
e/b3 = Reference < 64
where e/b2 is command 'e' bit 2, and e/b3 is command 'e' bit
3. If either bit is set, the key should be recalibrated using
command 'b'. Note that guardbanding errors (Section 2.8)
also use these same bits for error reporting, but
guardbanding does not usually affect these bits until after a
recalibration.
This feature does not account for varying key gains (burst
length) but ignores the actual negative detection threshold
setting for the key. If AKS-enabled keys in a panel have
different sizes, it may be necessary to reduce the gains of
larger keys relative to smaller ones to equalize the effects of
AKS. The signal threshold of the larger keys can be altered to
compensate for this without causing problems with key
suppression.
Each Reference Boundary error will also appear as an error
in a bitfield reported from command 'E'.
There is no mechanism by which keys can be made to
automatically recalibrate if the reference drifts past a window
boundary.
Adjacent key suppression works to augment the natural
moisture suppression of narrow gated transfer switches
(Section 3.13), creating a more robust sensing method.
2.12 Device Status & Reporting
See also commands ‘7’, page 22; ‘e’, page 23; ‘E’, page 23;
‘k’, page 23, ‘K’, page 24
2.10 Full Recalibration
See also command ‘b’, page 28
The device can report on the general device status or specific
key states including touches and error conditions, depending
on the command used.
The devices fully recalibrate on powerup, after a hard reset, a
soft reset or after a recalibrate ‘b’ command using an
algorithm that seeks out the optimal level of R2R offset and
Cz cancellation on a per-key basis. After powerup or a reset
the matrix is scanned key by key and appropriate calibrations device status using command ‘7’ first, as the response to this
Usually it is most efficient to periodically request the general
are set for each in accordance with user-defined setup
information. Since the circuit can tolerate a very wide signal
command is a single byte which reports back on behalf of all
keys. ‘7’ indicates if there are any keys detecting, calibrating,
range, it is capable of adapting to a wide mix of key sizes and or in error.
shapes having widely varying Cx coupling capacitances.
If command ‘7’ reports a condition requiring further
If a false calibration occurs due to a key touch or foreign
object on the keys during powerup, the affected key will
recalibrate again when the object is removed depending on
the settings of Positive Threshold and Positive Recal Delay
(Sections 2.2 and 2.7).
investigation, the host device can then use commands ‘e’, ‘E’,
‘k’ or ‘K’ to provide further details of the event(s) in progress.
This hierarchical approach provides for a concise information
flow using minimal data transfers and low host software
overhead.
Full recalibration is distinct from fast-recalibration, wherein Bit 4 of command 7 reports if there is a discrepancy between
only the Reference level is quickly adjusted. Full recalibration the eeprom and the Flash ROM backup of the eeprom in
requires 26 burst cycles to complete whereas fast
recalibration requires only one cycle (Section 2.5). The time
required for recalibration is dependent on the burst spacing
setting ^G (Section 3.8).
case of data corruption; it is also set whenever a Setup
parameter has changed but was not yet been copied into
Flash. See Section 4.6. Resetting the device will force the
eeprom changes to be copied to Flash if legitimate, or it will
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force an update of eeprom from Flash memory if not
legitimate.
operation. To accomplish this, the PLD always clamps all Y
lines to ground except during the rise of X for the key being
scanned.
Charge integrator. The first opamp is configured as an
integrator with a reset switch; capacitor Cs (C14 in Figure
3-1, and C7 in Figure 3-2) performs the charge integration
function. Capacitor Ca (C11 in Figure 3-1 only) acts to absorb
charge momentarily before the Figure 3-1 opamp can react to
absorb the charge across Cs; the value of Ca is not critical. A
P-channel jfet resets Cs between bursts (n-channel mosfet in
the case of Figure 3-2). The output of the opamp of Figure
3-1 swings negative, and as a consequence a negative power
supply is required for that circuit; the circuit of Figure 3-2 is
unipolar and requires only a positive supply.
3 Circuit Operation
Two reference circuits are shown in Figures 3-1 and 3-2.
Figure 3-1 shows a circuit having slightly greater precision
and sensitivity than that of Figure 3-2, however both will
perform well in most situations. Note that the Figure 3-2
circuit must have the Cs clamp control (command ^S) polarity
set to 0x01 to operate properly.
3.1 Part Differences
QT60xx5 parts use identical circuits and operate in identical
manner in all respects, except that only the QT60645 can
acquire 64 keys.
Charge cancellation. Two Cz capacitors are used to cancel
charge across Cs in stepwise fashion in order to increase
signal range. These capacitors can switch during the course
of a burst to reduce the final output of the amplifier chain,
preventing early signal saturation due to large keys (high Cx)
and/or long burst lengths. The Cz's are normally driven to
+5V when not in use; switching them to ground causes a step
subtraction of charge from the integrator.
The QT60325 and QT60485 only acquire 32 and 48 keys
respectively, but both still use an 8x8 matrix; any 32 or 48
keys in the matrix can be used. Unused keys must be
disabled by setting their burst length to zero (command ^F).
These devices have their upper keys disabled (keys 32 and
48 and up respectively). Upper keys can be enabled by first
disabling undesired lower keys so that the maximum number
of keys is never exceeded during the setup process.
Signal amplification; offset. At the end of the burst, the
charge integrator result is amplified, and an offset from an
R2R ladder DAC driven off the X drive lines is applied. This
offset repositions the final analog signal as close as possible
to the center of the ADC span, or at about 2.5V. The amount
of offset applied is determined during the calibration process.
3.2 Matrix Scan Sequence
The circuit operates by scanning each key sequentially, key
by key. Key scanning begins with location X=0 / Y=0. X axis
keys are known as rows while Y axis keys are referred to as
columns. Keys are scanned sequentially by row, for example
the sequence Y0X0 Y0X1 .... Y0X3, Y1X0 Y1X1... etc.
Burst / R2R timing. Figure 3-3 relates to a particular key
being addressed by an X row line and gate control lines YSn.
At the end of the burst, the X pins drive the R2R ladder
network to generate a correction offset to the amplifier chain.
The amplifier must stabilize to within ½ LSB (10mV) 8µs after
the application of the R2R value so that the signal can be
accurately sampled by the QT60xx5 on pin Ain.
Each key is sampled from 1 to 64 times in a burst whose
length is determined by command ^F. A burst is completed
entirely before the next key is sampled; at the end of each
burst the resulting analog signal is converted to digital by the
part’s ADC. The burst length directly impacts key gain; each
key can have a unique burst length in order to allow tailoring
of key sensitivity on a key by key basis.
Signal gain. Gain is directly controlled by burst length,
amplifier gain, and the value of Cs. Burst length can be
adjusted on a key by key basis whereas Av and Cs are fixed
for all keys. See Section 3.6. The detection threshold setting
also factors directly into key sensitivity.
3.3 Signal Path
Refer to Figures 1-4, 3-1, 3-2, and 3-3. Further descriptions
can be found in Section 1.20.
3.4 'X' Electrode Drives
The 'X' lines are directly connected to the matrix without
buffering. The positive edges of these signals are used to
create the transient field flows used to scan the keys. Only
one X line is actively driving the matrix for scanning purposes
at a time, and it will pulse for a ‘burst length’ for each key as
determined by the 'Burst Length' Setups parameter (see
command ^F, page 25 and Section 3.6).
Charge gate. Only one X row is pulsed during a burst.
Charge is coupled across a key's Cx capacitance from the X
row to all Y columns. A particular key is chosen by gating the
charge from a single Y column into a charge integrator. The
gate is an 8:1 analog mux whose path is selected by lines
YS0, YS1, and YS2; the gate is enabled by a pulse from the
PLD. The charge integrator is described below.
3.4.1 RFI FROM X LINES
Dwell time. The gate must be switched closed just prior to
the rising edge of X and must be reopened just after X has
finished rising, in order to capture the charge driven across
key capacitance Cx. The delay time from the rise of X to the
opening of the gate is known as the Y-sample dwell time.
Dwell time duration has a dramatic effect on the suppression
of signals due to moisture films as described in Section 3.13.
Dwell time is fixed in these devices to 167ns but this can be
shortened using an external circuit (Section 3.9).
X drive lines will radiate a small amount of RFI. This can be
attenuated if required by using series resistor in-line with
each X trace; the resistor should be placed near to the
QT60xx5. Typical values can range from 47 to 470 ohms.
Excessive amounts of R will cause a counterproductive drop
in signal strength. RC networks can also be used as shown in
Figure 4-4.
Inserted resistors in the X lines also have the positive effect
of limiting ESD transient currents (Section 3.22).
Charge neutralization. When X falls again, the charge
across Cx must be neutralized. Without neutralization, Cx
charge would be sampled one time only and not again during
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3.5.2 NOISE
C
OUPLING
INTO Y LINES
Figure 3-3 Relationship of X and Y signals
External noise, sometimes caused by ground bounce due to
injected line noise, can couple into the Y lines and cause
signal interference in extreme cases. Such noise can be
readily suppressed by adding a 100pF capacitor from each Y
line to a ground plane near the QT60xx5.
'n' pulses / burst
R2R Value
Xa
Yb
3.6 Burst Length & Sensitivity
See also Command ^F, page 25
Amp out
The signal gain in volts / pF of Cx for each key is controlled
by circuit parameters as well as the burst length.
The burst length is simply the number of times the
charge-transfer (‘QT’) process is performed on a given key.
Each QT process is simply the pulsing of an X line once, with
a corresponding Y line enabled to capture the resulting
charge passed through the key’s capacitance Cx.
Xa
Yb
Yb'
Yb
QT60xx5 devices use a finite number of QT cycles which are
executed in a short burst. There can be from 1 to 64 cycles in
a burst, in accordance with the list of permitted values shown
for command ^F, page 25. If burst length is set to zero, the
burst is disabled but its time slot in the scanning sequence of
all keys is preserved so as to maintain uniform timing.
3.4.2 NOISE
C
OUPLING
I
NTO
X
LINES
External noise, sometimes caused by ground bounce due to
injected line noise, can couple into the X lines and cause
signal interference in extreme cases. Such noise can be
readily suppressed by the use of series resistors as
described above. Adding a small capacitor to the matrix line
on the QT60xx5 side of the R, for example 100pF to ground
near the QT60xx5, will greatly help to reduce such effects.
Increasing burst length directly affects key sensitivity. This
occurs because the accumulation of charge in the charge
integrator is directly linked to the burst length. The burst
length of each key can be set individually, allowing for direct
digital control over the signal gains of each key individually.
Apparent touch sensitivity is also controlled by Negative
Threshold (Section 2.1). Burst length and negative threshold
interact; normally burst lengths should be kept as short as
possible to limit RF emissions, but the threshold setting
should be kept above a setting of 6 to limit false detections.
The detection integrator can also prevent false detections at
the expense of slower reaction time (Section 2.6).
3.5 'Y' Gate Drives
There are 8 'Y' gate drives (YC0..YC7) which are active-high;
only one of these lines is used during a burst for a particular
key. These lines are used to control the PLD to ground all
unselected ‘Y’ lines, making them low impedance. The
selected ‘Y’ line in the matrix remains unclamped by the PLD
during the rising edge of the ‘X’ drive line, during the time that
the coupled charge from a single key is fed to the charge
integrator via the 8:1 analog mux.
3.7 Intra-Burst Spacing
See also Command ^M, page 27
The time between X drive pulses during a burst is the
intra-burst pulse spacing. This timing has no noticeable effect
on performance of the circuit, but can have an impact on the
nature of RF spectral emissions from the matrix panel. The
setting of this function can be from 2µs through 10µs, loosely
corresponding to fundamental emission frequencies from
500kHz and 100kHz respectively.
There are also 3 Y-encoded lines YS0..YS2 which select the
correct switch to actuate in the analog mux for the desired ‘Y’
line. Line ‘YG’ from the controller acts to trigger the PLD’s
pulse generation circuit, whose pulse width following the rise
of an ‘X’ line is dependent on an RC time constant. This
pulse, ‘YE’, drives the enable pin of the QS3251 mux low
(switch on) just before a positive-going ‘X’ drive pulse, and
high again (switch off) just after the ‘X’ drive pulse. The time
from the rising edge of an ‘X’ signal to the rising edge of ‘YE’
is referred to as the dwell time, and this parameter has a
direct effect on the ability of the circuit to suppress moisture
films (see Sections 3.9 and 3.13).
Longer spacings require more time to execute and can limit
the operational settings of burst length and/or burst spacing
(Section 5.7).
The intra-burst QT spacing has no effect on sensitivity or
water film suppression and is not particularly important to the
sensing function other than described above.
After the ‘YE’ pulse has ceased, the controller and circuit act
to ground all ‘Y’ lines via the PLD just before the ‘X’ drive
signal goes low; this restores the charge across the matrix
keys to a null state, making them ready for another sample.
3.8 Burst Spacing
See also Command ^G, page 25
The interval of time from the start of one burst to the start of
the next is known as the burst spacing. This is an alterable
parameter which affects all keys.
3.5.1 RFI FROM Y LINES
Y lines are 'virtual grounds' and do not radiate a significant
amount of RFI; in fact, they act as ‘sinks’ for RFI emitted by
the X lines since they are virtual grounds. Series-R in the Y
lines is not required for RFI suppression, and in fact series-R
can introduce cross-talk among keys.
Shorter spacings result in faster response time, but due to
increasing timing restrictions at shorter spacings burst
lengths are restricted, limiting the amount of gain that can be
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obtained; see Section 5.7. Conversely longer spacings permit TLC2272 type opamp is a good example of the type of device
which should be employed.
higher burst lengths but slow down response time.
Spacings from 250µs to 2ms are available.
Figure 3-1 Circuit: The first opamp is a charge integrator
whose output ranges between 0V to -2.5V. A JFET is used as
a reset switch for the integration capacitor C14. Since most
opamps are not fast enough to integrate the nanosecond
duration transient charge pulses coming from the Y lines and
the switched Cz capacitors, a large, non-critical capacitor C11
is used to temporarily store transient charge until the opamp
can assimilate it over the following microseconds.
3.9 PLD Circuit and Charge Sampler
The PLD should be a CMOS 22V10 type having no internal
pullup or bus-keeper resistors in order to limit leakage
current. ICT’s PEEL22CV10AZ is a good example device,
and code for this part can be found in Section 6.
The PLD performs two functions: Y line clamping and transfer
switch gating.
The second stage opamp must invert the first opamp output
in order to provide a positive-going signal to Ain of the
QT60xx5. This stage is also used to facilitate the introduction
of offset from the R2R network (Section 3.12).
The PLD clamps Y-lines to ground whenever key charge is
not being collected. The charge integrator should only receive
charge starting just before an X line goes high, to a point just
after the transition (the X-Y ‘dwell time’). It is an essential
function of the PLD to neutralize charge keys during the
negative transition of X lines; without this, charge-transfer
would cease to function after a single X pulse, and multiple
pulse bursts would be impossible.
The second stage must be clamped with a low-C diode as
shown (BAV-99 preferred) so that negative excursions of the
amplifier do not under-drive the Ain pin of the device. An
output resistor further limits possible Ain+ currents. Without
clamping there can be high currents taken from Ain which can
lead to device latchup, requiring power to be cycled to restore
operation.
The PLD also acts to generate a pulse that sets the dwell
time for the QS3251 8:1 charge sampler switch. A simple
PLD-based RC network controls the QS3251 gate pin ‘E’
starting from when line YG becomes active to a time after X7
or XS transition high. XS is the logical-OR of X0..X6; X8 and
XS are OR’d together in the PLD so that any single X line can
trigger the timing network.
Figure 3-2 Circuit: The first opamp is a positive-gain high
impedance configuration which amplifies the small voltage on
Cs (C7). The reset transistor is a small-signal N-fet. C7 also
receives charge cancellation capacitances C8 and C9. The
R2R DAC offset is injected into the summing junction of this
amplifier.
X-Y dwell time can be measured with an oscilloscope by
timing the interval from XS or X8 to 22V10 output F9. Dwell
times of 70ns - 90ns work very well to suppress the effects of
surface moisture films. Longer times are acceptable if such
moisture is not anticipated.
The second stage amplifier has a positive gain that provides
final amplification.
This design is simpler to implement but has lower gain than
the circuit of Figure 3-1.
R2 and/or C5 in Figure 3-1 should be adjusted to provide a
timing dwell delay from the rise of an X line to the rising edge
of Y-enable (QS3251) of around 75ns +/-20%. Shorter dwell
times will begin to cause the suppression of human touch
signals as well. If resistors and capacitors are used in line
with the X and Y matrix lines for EMC and ESD suppression
(Section 3.22), excessively short dwell times can seriously
deteriorate signal gain. The circuit should be evaluated for the
amount of signal loss by comparing delta signals due to touch
both with and without the EMC circuits.
3.11 Sample Capacitors
Charge sampler capacitor Cs (C14 in Figure 3-1, C7 in Figure
3-2) should be the values shown. They should be either NP0
or C0G ceramic or PPS film for thermal stability reasons. The
two Cz capacitors should be NP0 or C0G types only. The
transient charge absorber C11 can be a 10% X7R type.
More information on how the Cs and Cz capacitors function is
described in Section 1.2.
The values of capacitance should not be altered from the
reference schematics; value changes can cause acquisition
gaps to occur which can result in keys that cannot calibrate.
R2 and C5 can be eliminated to provide the full 167ns of
dwell time output by the QT60xx5. C5 should be replaced by
a connection to ground, and R2 should be open-circuited.
Source code for one type of recommended 22V10 can be
found in Section 6. The 22V10 should have conventional
CMOS I/O structures without ‘bus-keepers’ or pullup resistors
in order to work optimally.
3.12 R2R Resistor Ladder
The R2R ladder network (RN1 in Figure 3-1) should have a
value of 100K ohms and a precision of 7 or 8 bits. The R2R
connects to the summing junction of the first or second
opamp depending on the circuit; it is used to offset the analog
signal down with increasing binary input value. The R2R
value is determined for each key during calibration by an
algorithm that seeks to put the signal Ain+ at 2.5 volts. This
binary value only changes when a key is recalibrated or after
powerup during the normal startup calibration cycle; drift
compensation does not change R2R drive.
While the QS3251 is gated by the signal on its ‘E’ pin from
the PLD, the actual switch being controlled is determined by
the YS0, YS1, YS2 lines from the QT60xx5.
3.10 Opamps
The amplifier chain should be configured as shown in Figures
3-1 or 3-2. The opamps should have a GBW product of at
least 2MHz, have rail-rail CMOS outputs, and be able to
operate from split-rail supplies (split-rail capable only in the
case of Figure 3-1). To eliminate leakage current issues the
amplifier should be a JFET or CMOS input type only. TI’s
The R2R is driven by the matrix X lines; this is possible since
Ain+ is only read after the completion of each burst, therefore
this dual-use of X drive lines does not pose a conflict so long
as these lines are not heavily loaded.
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The rated resistance of an R2R ladder is also its Thevenin frequency source can also be connected to XTI; XTO should
be left unconnected.
equivalent resistance which affects the scaling of the offset
injected into the amplifier, in terms of mV/bit. The scaling of
offset injection also affects the crossover points for the
switching of each Cz capacitor. If during the calibration cycle
the R2R network is found to not provide enough offset to
bring the signal to the midpoint of the ADC's range, a Cz
capacitor is switched in to create an additional offset.
The frequency of oscillation should be 6MHz +/-2%.
3.16 Startup / Calibration Times
The QT60xx5 requires initialization times as follows:
1. From very first powerup to ability to communicate:
2,000ms (One time event to initialize all of eeprom)
If the R2R drive value and Cz values are not properly
matched, the circuit may not be able to converge on all
calibration points, i.e. there will be acquisition ‘holes’. This will
happen if the Cz cancellation voltage step is too large with
respect to the amount of full-scale influence of the R2R
ladder on the analog offset. It is recommended that the
reference circuits shown in Figures 3-1 and 3-2 should not be
altered to avoid problems.
2. Normal cold start to ability to communicate:
70ms (Normal initialization from any reset)
3. Calibration time per key vs. burst spacings:
spacing = 250µs: 425ms
spacing = 300µs: 510ms
spacing = 400µs: 680ms
spacing = 500µs: 850ms
spacing = 1ms: 1,700ms
spacing = 2ms: 3,400ms
3.13 Water Film Suppression
Water films on the user surface can cause problems with
false detection under certain conditions. Water films on their
own will not normally cause false detections. The most
common problem occurs when surface water bridges over 2
or more keys, and a user touches one of the keys and the
water film causing an adjacent key to also trigger. Essentially,
the water film transports the touch contact to adjacent keys.
To the above, add 2,000ms or 70ms from (1) or (2) for
the total elapsed time from reset to ability to report key
detections.
Keys that cannot calibrate for some reason require 5 cal
cycles before they report as errors. However, the device can
report back during this interval that the key(s) affected are still
in calibration via status function bits.
The recommended circuit suppresses water coupling by
means of a short sample dwell time: a short dwell time
reduces the signal from resistive films by limiting the amount
of time during which charge is collected. Charge from distant
regions of the film take longer to return, and so a short dwell
time will prevent such charge from being sensed. This effect
has nothing to do with the frequency of the burst itself, it is
purely a time-domain phenomenon; changing the burst or
pulse spacings (i.e. sample frequency) will have no effect on
water film suppression.
3.17 Sleep_Wake / Noise Sync
The Sleep_wake and Noise Sync features depend on the use
of pin X2WS as an input. To prevent interference with scan
line X2 during acquisitions, a resistor equal to the rating of
the R2R ladder (i.e. 100K) must be used in series. The Sleep
and Sync features can be used simultaneously; the part can
be put into Sleep mode, but awakened by a noise sync signal
which is gated in at the time desired.
Sleep mode: See also command ‘Z’, page 29.
To create short dwell times, a CMOS PLD is configured with a
simple timing circuit to control the ‘Y’ gate (Section 3.9).
The device can be put into an ultra low-power sleep mode
using the ‘Z’ command. When this command is received, the
Sleep line must be placed immediately thereafter into a
logic-high state. The part will complete an ongoing burst
before entering Sleep. The part can be awakened by a low
transition on the X2WS pin lasting at least 5µs. One
convenient way to wake the part is to connect pin X2WS to
MOSI via the 100K resistor, and have the host send a null
command to the device. The part will wake and the null
command will not be processed. The MOSI line in turn
requires a pullup resistor to prevent the line from floating low
and causing an unintentional wake from sleep.
Mechanical means can also be used to suppress cross-
coupling due to moisture films, for example raised plastic
barriers between keys, or placing keys in shallow wells or on
raised areas to lengthen the electrical path from key to key.
AKS - Adjacent Key Suppression - is included in these
devices to enhance moisture performance (Section 2.9).
3.14 Reset Input
The RST’ pin can be used to reset the device to simulate a
power down cycle, in order to bring the part up into a known
state should communications with the part be lost. The pin is
active low, and a low pulse lasting at least 10µs must be
applied to this pin to cause a reset.
During Sleep the oscillator is shut down, and the part
hibernates with microamp levels of current drain. When the
part wakes, the part resumes normal functionality from the
point where it left off. It will not recalibrate keys or engage in
other unwarranted behavior.
To provide for proper operation during power transitions the
devices have an internal brown-out detector set to 4 volts.
Before going to sleep the part will respond with a 'Z'. In
slave-only SPI mode (see Section 4.3), the SS line must be
floated high by the host as soon as it receives this response;
if SS does not float high, sleep will fail and the device will
instead completely reset after about 2 seconds. Upon waking
the part will issue another 'Z' byte back to the host.
A reset command, ‘r’, is also provided which generates an
equivalent hardware reset (page 28).
3.15 Oscillator
The oscillator can use either a quartz crystal or a ceramic
resonator. In either case, the XTI and XTO must both be
loaded with 22pF capacitors to ground. 3-terminal resonators
having onboard ceramic capacitors are commonly available
and are recommended. An external TTL-compatible
Noise sync: See also command ^W, page 30.
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External fields can cause interference leading to false
Cs when the drive signal is low, so ^S should be set to ‘0’.
Figure 3-2 requires that ^S be set to ‘1’.
detections or sensitivity shifts. Most fields come from AC
power sources. RFI noise sources are heavily suppressed by
the low impedance nature of the QT circuitry itself.
This feature allows for operation with the two basic circuit
topologies which require different Cs reset control polarities.
External noise becomes a problem if the noise is uncorrelated
with signal sampling; uncorrelated noise can cause aliasing
effects in the key signals. To suppress this problem the
devices feature a noise sync input which allows bursts to
synchronize to the noise source. This same input can also be
used to wake the part from a low-power Sleep state.
3.20 Oscilloscope Sync
See also Command ^R, page 29
‘MS’ pin 37 can output a positive pulse oscilloscope sync that
brackets the burst of a selected key. This feature is controlled
by the ^R command. More than one burst can output a sync
pulse, for example if the scope of the command when set is
a row or column, or is all keys. The ^R command is volatile
and does not survive reset or power down.
The device’s bursts can be synchronized to an external
source of repetitive electrical signal, such as 50Hz or 60Hz,
or possibly a video display vertical sync line, using the
Sleep_wake / Noise sync line. The noise sync operating
mode is set by command ^W. This feature allows dominant
external noise signals to be heavily suppressed, since the
system and the noise become synchronized and no longer
beat or alias with respect to each other. The sync occurs
only at the burst for key 0 (X0Y0); the device waits for the
sync signal for up to 100ms after the end of a preceding full
matrix scan (after key #63), then when a negative sync edge
is received, the matrix is scanned in its entirety again.
This feature is invaluable for diagnostics; without it, observing
signals clearly on an oscilloscope for a particular burst is
nearly impossible.
This pin is also used as a SPI mode select pin. In order to
prevent a shorted output when the oscilloscope sync is
enabled, the MS pin should only be connected to ground or
Vdd via a m10K resistor.
This function is supported in QmBtn PC software via a
checkbox.
The sync signal drive should be a buffered logic signal, or
perhaps a diode-clamped signal, but never a raw AC signal
from the mains.
3.21 Power Supply and PCB Layout
Since Noise sync is highly effective yet simple and
Vdd should be 5.0 volts +/- 5%. This can be provided by a
common 78L05 3-terminal regulator. LDO type regulators are
usually fine but can suffer from poor transient load response
which may cause erratic signal behavior.
inexpensive to implement, it is strongly advised to take
advantage of it anywhere there is a possibility of encountering
electric fields. Quantum’s QmBtn software can show signal
noise caused by nearby AC electric fields and will hence
assist in determining the need to make use of this feature.
If the power supply is shared with another electronic system,
care should be taken to assure that the supply is free of
digital spikes, sags, and surges which can adversely affect
the circuit. The devices can track slow changes in Vcc
depending on the settings of drift compensation, but signals
can be adversely affected by rapid voltage steps and impulse
noise on the supply rail.
If the sync feature is enabled but no sync signal exists, the
sensor will continue to operate but with a delay of 100ms
from the end of one scan to the start of the next, and hence
will have a slow response time.
3.18 LED / Alert Output
0.1µF bypass caps from power to ground should be used
near every supply pin of every active component in the circuit.
Pin 40 is designed to drive a low-current LED, 5mA
maximum, active-low. The LED will glow brightly (i.e. pin 40
will be solid low) during calibration of one or more keys, for
example at startup. When a key is detected, pin 40 will be low
for the duration of each burst for which a key is sensed, i.e.
with a very low duty cycle. Each additional key being detected
will also create a low pulse for that key’s burst. During all
other times, the LED pin will be inactive (high).
Vee is a negative supply used by the circuit of Figure 3-1; it
can range from -3V to -5V. It does not need to be regulated
but should be well filtered and free from external fluctuations.
Figure 3-1 shows a simple, inexpensive charge-pump which
is driven from resonator pin XTO to generate Vee.
Current requirements of the circuit are approximately
20mA / Vdd, 4mA / Vee when running.
This pin can be used to alert the host that there is key activity,
in order to limit the amount of communication between the
device and the host. The LED / Alert line should ideally be
connected to an interrupt pin on the host that can detect a
negative edge, following which the host can proceed to poll
the device for key activations.
PCB layout: The PCB layout should incorporate a ground
plane under the entire circuit; this is possible even with
2-layer boards. The ground plane should be broken up as
little as possible. Internal nodes of the circuit can be quite
sensitive to external noise and the circuit should be kept
away from stray magnetic and electric fields, for example
those emanating from mains power components such as
transformers and power capacitors. If proximity to such
components is unavoidable, an electrostatic shield should be
considered. The Sync feature (Section 3.17) can also be
invaluable in reducing these types of noise sources.
This pin also pulls low if there is a key error of any kind.
Note that in sleep mode if the LED was on just prior to sleep,
it will remain on during sleep.
3.19 CSR Drive Polarity
See also Command ^S, page 29
Sample layout artwork is available from Quantum on request.
The polarity of the Cs integrator capacitor reset drive can be
set for active high or active low operation using command ^S.
In the reference circuit show in Figure 3-1, the JFET will reset
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Bypass capacitors and series resistors can be used to
prevent these effects as shown in Figures 4-4 and 4-5.
3.22 ESD / Noise Considerations
In general the QT60xx5 will be well protected from static
discharge during use by the overlying panel. However, even
with a dielectric panel transients currents can still flow into
scan lines via induction or in extreme cases, dielectric
breakdown. Porous or cracked materials may allow a spark to
tunnel through the panel. In all cases, testing is required to
reveal any potential problems. The devices have diode
protected pins which can absorb and protect the device from
most induced discharges, up to 5mA.
4 Serial Interface
QT60xx5 devices use an SPI serial interface to a host MCU.
This port uses a protocol described in Section 5.
4.1 Serial Port specifications
QT60xx5's use an SPI synchronous serial interface with the
following specifications at 6MHz oscillator frequency:
The X lines are not usually at risk during operation, since they
are low-resistance output drives. The YCn lines are not
directly connected to the matrix and so are not at risk.
However the PLD and the QS3251 are connected to the Y
lines and may require additional ESD protection.
Max clock rate, Fck
Data length
Host command space, Tcm
Response delay to host, Tdr1
Drdy delay from response, Tdr2
Multi-byte return spacing, Tdr3
1.5MHz
8 bits
m 50µs
Table 4-1, also, Sec. 7
1µs to 1ms
15µs to 2ms
Diode clamps can be used on the X and Y matrix lines. The
diodes should be high speed / high current types such as
BAV99 dual diodes, connected from Vdd to Vss with the
diode junction connected to the matrix pin.
The host can clock the SPI at any rate up to and including the
maximum clock rate Fck. The maximum clock rate of the part
in Master mode is determined by Setup ^Q.
Capacitors placed on the X and Y matrix lines can also help
to a limited degree by absorbing ESD transients and lowering
induced voltages. Values up to 100pF can be used without
causing circuit problems.
The part can operate in either master-slave mode or
slave-only mode, and is thus compatible with virtually all
SPI-capable microcontrollers.
The circuit can be further protected by inserting series
resistors into the X and/or Y lines to limit peak transient
current. Values up to 500 ohms can be used in most cases,
but if the dwell time is short this resistance can cause a
reduction in signal gain. RC networks as shown in Figures
4-4 and 4-5 can provide enhanced protection against ESD
while also limiting the effects of external fields.
The SPI interface should not be used over long distances due
to problems with signal ringing and introduced noise etc.
unless suitably buffered or filtered with RC networks as
shown in Figures 4-4 and 4-5. Slower data rates with longer
RC timeconstants will provide enhanced resistance to noise
and ringing problems.
Conversion to asynchronous UART format can be
accomplished by using a microcontroller with conversion
firmware. Using such a conversion device the part can
communicate with Quantum's QmBtn PC software. Consult
Quantum for details.
External field interference can occur in some cases; these
problems are highly dependent on the interfering frequency
and the manner of coupling into the circuit. PCB layout
(Section 3.21) and external wiring should be carefully
designed to reduce the probability of these effects occurring.
Of particular note is the length of the connection from the
circuit to the key panel. This connection will act as an
antenna that will resonate at various radio frequencies to
cause interference, and thus should be very short. If RFI
pickup is a problem, the connections should be damped
using ferrite beads or low-value (22 - 100 ohm) series
resistors in all lines including any ground and power lines
running in parallel to the panel.
4.2 Protocol Overview
The SPI protocol is based entirely on polled data
transmission, that is, the part will not send data to the host of
its own volition but will do so only in response to specific
commands from the host.
Run-time data responses, such as key detection or error
information, requires simple single-byte functions to evoke a
response from the part.
SPI data noise: In some applications the host MCU can be
some distance from the sensor, with the interface coupled via
ribbon cable. The SPI link is particularly vulnerable to noise
injection on these lines; corrupted or false commands can be
induced from transients on the power supply or ground wiring.
Setup mode interactions mostly use 2-byte functions from the
host to cause the part to alter its behavior; these functions
also cause writes to the internal eeprom.
The concept of 'scope' is used to allow functions to operate
on individual keys or groupings of keys. The scope of
subsequent functions can be altered by short initial scope
instructions.
Figure 4-1 SPI Connections
Slave-Only
Master-Slave
See Section 5 for protocol details.
Host MCU
QT60xx5
Host MCU
QT60xx5
4.3 SPI Slave-Only Mode
DRDY
SS
P_IN
P_OUT
SCK
DRDY
SS
Refer to Figures 4-1 and 4-2. Select Slave-only by
floating Pin 37 (MS) or tying high via a m10K resistor. Pin
37 also functions as an oscilloscope sync output (Section
3.20) and should never be tied directly to a supply rail. In
Slave mode the host must always be in Master mode, as
it controls all SPI activity including clocking of the
SS
SCK
SCK
MISO
MOSI
MS
SCK
MISO
MOSI
MS
MISO
MOSI
SS
MISO
MOSI
Vdd
10K
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Figure 4-2 SPI Slave-Only Mode Timing
T
dr3
T
cm
T
T
dr2
dr1
DRDY
{from sensor}
SS
{from host}
SCK
{from host}
MOSI
{from host}
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Optional Byte 2
Host Command Byte 1
Null Dummy Data
7 6 5 4 3 2 1 0
Null Dummy Data
7 6 5 4 3 2 1 0
MISO
{from sensor}
7 6 5 4 3 2 1 0
Invalid Data
7 6 5 4 3 2 1 0
Invalid Data
Response Data or Echo
Nth Response Data
{N = command dependent}
Figure 4-3 SPI Master/Slave Mode Timing
T
T
T
cm
dr1
dr3
SS
SCK
MOSI
7 6 5 4 3 2 1 0
Command Byte 1
from Host to sensor
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
Optional Byte 2
from host to sensor
Response Byte or Echo
from sensor to host
Nth Byte from sensor
{N = command dependent}
SS, SCK, MOSI originate from Host
Floating
SS, SCK, MOSI originate from sensor
interface in both directions. Unlike hardware SPI slaves,
QT60xx5's need processing time to respond to functions.
DRDY’ is used to let the host know when data is ready for
collection; it indicates to the host when data is ready in
response to a command so that the host can clock over the
data.
SS’ transitions either up or down, or the transmission will
fail; between bytes SCK should always idle low. SCK
should never float.
SS’ - Slave select - input only; acts as a framing signal to the
sensor from the host. SS’ must be low before and during
reception of data from the host. It must not go high again
until SCK line has returned low; during data or echo
response it must not go high until after the host has
sensed that DRDY’ has gone high from the device. SS’
must idle high. SS’ has an internal pullup resistor.
This mode requires 5 signals to operate:
MOSI - Master out / Slave in data pin; used as an input for
data from the host at all times. This pin should be
connected to the MOSI pin of the host device.
DRDY’ - Data Ready - active-low - indicates to the host that
the part is ready to send data back subsequent to a
command from the host. This pin idles high. The DRDY’
pin has an internal pullup resistor inside.
MISO - Master in / Slave out data pin; used as an output for
data to the host at all times. This pin should be connected
to the MISO pin of the host device.
SCK - SPI clock - input only clock pin from host. The host
must shift out data on the falling edge of SCK; the
QT60xx5 clocks data in on the rising edge of SCK.
Important note: SCK must idle low just before and after
Internal pullup resistors note: The internal pullup resistors
can range from 35k to 120k ohms. If RC filtering is used on
the SPI lines per Figure 4-4, this resistance may not be low
Table 4-1 Typical DRDY (Tdr1) Response Delays (Burst Length = 12)
Burst Spacing
Function Type
Setup - Put (affect 1 key)
250µs
10ms
40ms
300ms
800ms
3ms
300µs
10ms
40ms
300ms
800ms
2.7ms
1ms
400µs
500µs
10ms
1ms
10ms
40ms
300ms
800ms
2ms
2ms
10ms
40ms
300ms
800ms
2ms
10ms
40ms
40ms
Setup - Put (affect 8 keys)
Setup - Put (affect 64 keys)
Lock Reference Levels ('L') command
Calibrate command (all keys)
Get key errors (E), Get keys pushed (K)
All other commands
300ms
800ms
2.5ms
800us
300us
300ms
800ms
2.5ms
800us
300us
1ms
800us
300us
800us
300us
400us
300us
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3) When the sensor has the command echo or requested
data ready to send back to the host, it loads it into its SPI
Figure 4-4 Filtering SPI Slave-Only Connections
register and pulls DRDY’ low.
+5
+5
QT60xx5 Circuit
10K 10K
Host MCU
P_IN
4) The host detects that the sensor has pulled DRDY’ low
and in turn the host pulls SS’ low.
X drives
(1 of 8
shown)
DRDY
SS
Xn
Ra
Ca
220
5) The host obtains the byte from the sensor by transmitting
a dummy byte (0x00) to the sensor.
P_OUT1
SCK
47pF
Ra
Ra
Ra
Ra
Ca
Ca
SCK
MISO
6) The sensor releases DRDY’ to float high.
MISO
7) After the host detects that DRDY' has floated high the
host must allow SS’ to also float high.
Ca
Y Lines
(1 of 8
shown)
Yn
MOSI
MOSI
100
22pF
8) For multi-byte responses, steps (3) through (7) are
repeated until the return data is completely sent.
Ca
P_OUT2
RESET
1K
(MS not
shown)
1nF
The host must release the SS’ line in step (7) even between
multiple byte responses because the QT60xx5 waits for the
SS’ line to return high before signalling that the next byte is
ready for collection.
Figure 4-5 Filtering SPI Master-Slave Connections
+5
The host should check the DRDY’ line and wait for it to go
high before transmitting another byte. Until the DRDY’ line is
released the sensor is still processing a data return, even if
the complete response data has been fully transferred; the
sensor may still be busy when the host finishes the byte
transfer and may not be able to digest a new command
immediately.
QT60xx5 Circuit
10K
Host MCU
SS
X drives
(1 of 8
shown)
DRDY
SS
Xn
220
47pF
Ra
Ra
Ca
Ca
Ca
SCK
SCK
Ca
MISO
MISO
See Section 3.18, page 15, for a description of the Alert pin
which can be used to reduce communication traffic.
Y Lines
(1 of 8
shown)
Yn
MOSI
MOSI
100
22pF
Ra
1K
Ca
Ca
P_OUT
RESET
4.4 SPI Master-Slave Mode
(MS not
shown)
1nF
Refer to Figures 4-1 and 4-3. In Master-Slave mode the host
and sensor take turns being Master; the host always initiates
in Master mode during an exchange. The current Master
always controls all 3 signals. The sensor takes a variable
amount of time to respond to the host, depending on the
function and current and pending tasks. SPI Master/Slave
mode is selected by tying Pin 37 (MS) low via a 10K resistor.
Pin 37 is also an oscilloscope sync output (see Section
3.20 and command ^R, page 29) and should never be tied
directly to either supply rail. The host, like the sensor, must
idle in slave mode when not sending a command.
Recommended Values of Ra & Ca for Figures 4-4 and 4-5
SPI Clock Rate
1.5MHz
375kHz
Ra
680
Ca
100pF
270pF
470pF
1nF
1,000
2,200
2,200
93.75kHz
46.875kHz
enough to ensure adequate signal risetime and may need to
be augmented with external 10k pullups.
Master/Slave requires 3 signals to operate:
The host must wait until DRDY’ goes low before an SPI
transfer to retrieve data. For multi-byte responses, the host
must observe DRDY' to see when it goes high again after
each data byte, then low again, before executing another
transfer to get the next data byte. The host should send null
bytes (0x00) to retrieve data.
MOSI - Master out / Slave in data pin - bidirectional - an input
pin while the host is transmitting data; an output when the
sensor is transmitting data. The MOSI of the host and
slave should be tied together. The MISO lines are not used
on either part and should be left open.
If the DRDY’ line does not go low after a command, the
command was not properly received or it was inappropriate.
The delay to DRDY’ low depends on how many bytes of data
are being loaded into eeprom; Table 4-1. Absolute worst case
delays are found in Section 7; these timings occur only rarely,
for example if the device happens to be busy with adjacent
key suppression calculations, which occurs only at the
moment when a key is first detected.
SCK - SPI clock - bidirectional - an input pin when receiving
data; an output pin when sending. The host must shift out
data on the falling edge of SCK; the QT60xx5 clocks data
in on the rising edge of SCK. Important note: SCK from
the host must be low before asserting SS’ low or high at
either end of a byte or the transmission will fail. SCK
should idle low; if in doubt, a 10K pulldown resistor should
be used. When the sensor returns data it becomes the
Master; data is shifted out by it on the falling edge of SCK
and should be clocked in by the host on the rising edge.
A typical Slave-only function sequence is as follows:
1) The host pulls SS’ low, then transfers a command to the
sensor. The host then releases SS’ to float high. DRDY’ is
unaffected in this step.
SS’ - Slave select - bidirectional framing control. When the
sensor is in slave mode, this pin accepts the SS’ control
signal from the host. In either data direction, SS' must go
low before and any during data transfer; it should not go
high again until SCK has returned low at the end of a byte.
2) For 2-byte functions, (1) is repeated with a m50µs delay.
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In Master mode the sensor asserts control over this line, to Commands that return data do not send back a command
make the host a slave and to frame the data. This line
must idle high; the part includes an internal pullup resistor
and should be floated during idle times.
echo. If desired, the command can be verified via the 'l'
(lowercase L) echo function; see page 28.
The host should not transmit a new command until the
Internal pullup resistor note: The internal pullup resistor on last command has been processed and responded to
SS’ can range from 35k to 120k ohms. If RC filtering is used
on the SPI lines per Figure 4-5, this pullup resistance may not
be low enough to ensure adequate signal risetime and may
need to be augmented with external 10k pullups.
completion, plus 1ms.
Commands that are not recognized are ignored, and the host
should monitor for timeouts to detect these conditions. If this
occurs a new command should not be sent until the specified
timeout duration has expired.
A command may consist of one or two bytes with a m50µs
delay between bytes. At the end of a full command, the host
must go into Slave mode to await a response.
The maximum timings shown in Table 4-1 and Section 7-5
are guaranteed provided that the part is operating within the
timing limitations of Section 5.7. If burst timing is in violation,
the response time to a command may be longer.
The sensor may take some time to process the command
and respond. When it does, it asserts SS’ low and begins
clocking data out. For multi-byte responses, bytes will be sent
at intervals which may be irregular depending on the request
and the processing load of the sensor. The host must be
prepared to accept the sensor data as it comes or there can
be a data overrun in the host. If the data returns too quickly
for the host to accept it, lower the SPI clock rate.
4.6 Eeprom Corruption
The device stores its Setup data in an internal eeprom which
can be readily altered via Put mode commands. Sometimes
noise on Vdd, the SPI lines or Reset pin can cause eeprom
corruption which can be difficult or inconvenient to correct.
A typical Master-Slave function sequence is as follows:
The device should always be left in Get mode to prevent
spurious commands from corrupting the eeprom. The Get
command should ideally be repeated every second or so to
ensure that if noise on the SPI lines causes a false Put mode
command that it does not last long. Preferably, the ‘l’
command (lowercase ‘L’) should be used to verify that the Put
command has succeeded.
1) Host enters Master mode. The sensor is already in Slave
mode.
2) The host pulls SS’ low, then transfers one byte of
command to the sensor via MOSI, then releases SS’ to
float high again.
3) For 2-byte functions, (2) is repeated with m50µs spacings
between bytes.
Flash backup: The part backs up the entire eeprom array
into onboard Flash rom after one or more Setup write
4) The host immediately places its SPI port into Slave mode, commands have been issued and the part is then reset.
floating SCK and MOSI’; SS’ stays floating.
During normal operation the part constantly compares the
Flash area with the eeprom array to ensure the two sections
match. If an eeprom error is detected, the device sets an
error flag (bit 4) in the general device status byte (Command
‘7’, page 22) which can be read by the host device. The LED
output also becomes active. If the bit 4 error flag is set, the
host should immediately induce a device reset.
5) When the sensor has a command echo or data to send
back, it puts its SPI register in Master mode, taking control
over MOSI and SCK. SS' remains floating.
6) The sensor pulls SS’ low, then clocks out its response
byte to the host, then floats SS’ high again.
7) The sensor repeats (6) as necessary for multiple byte
responses.
Bit 4 is also set if an intentional write has been made to
eeprom, but not yet copied into Flash via the reset process. It
is perfectly acceptable to continue altering any number of
Setup parameters prior to doing the reset, ignoring this bit.
8) The sensor returns to slave mode.
After the transmission sequence, the SPI lines float high or
are left to float in an indeterminate state (MOSI) until the next
transmission sequence is initiated by the host. The host
should wait for m1ms after a sequence before initiating
another transmission sequence.
During power up or after a reset, the device compares the
Flash area with eeprom, and if there is a discrepancy the
eeprom is refreshed from Flash, unless an intentional write
was detected in which case the Flash is updated from the
eeprom. As intentional writes in Put mode should only occur
during manufacture, it is normally safe to assume that
eeprom changes during normal run mode are errors.
See Section 3.18, page 15, for a description of the Alert pin
which can be used to reduce communication traffic.
The host can also periodically test the checksum of the
eeprom as a backup mechanism to the bit 4 error flag.
4.5 Sensor Echo and Data Response
The devices respond to each and every valid command from
the host with at least one return byte. In the case of functions
that do not send data back to the host, the part returns the
command itself as an echo, but only after the function has
been completed; this also holds for 2-byte functions where
the second byte is an operand: in these cases the return byte
is an echo of the command, not the operand.
The uppercase ‘L’ command, Lock Reference Levels, also
writes data to eeprom, and this data also has the potential to
become corrupted. This data is also backed up in Flash so
that it can be recovered, and an error in this data will also set
bit 4 and also alter the checksum. Also, the ‘L’ command only
operates if the device is in Put mode as a further protection.
Flash rom has a limit of 1,000 write cycles, so copy-to-Flash
should not be used routinely.
Exception: The recalibration command ‘b’ returns an
acknowledgement immediately rather than just before the
actual recalibration.
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5.1 Direction Commands
5 Commands & Functions
Setup commands can be used to either send control
information to the part for programming into its internal
eeprom, or to extract the current setting of this information.
The same Setup function can do either. To accomplish this
the device relies on direction control via the Get and Put
commands. In Get mode, a Setup command will return
information. In Put mode, the behavior of the device is
altered, and often a second operand byte must be sent.
The command structure is designed to minimize control and
data traffic. All repetitive data and status commands from the
host are single-byte, and most commands result in single-
byte device responses. Behavioral setup commands involve
multiple bytes but these are infrequently used.
Special 'scope' commands exist to restrict subsequent
commands to a specific key or range of keys. This control
structure permits most matrix keys, which are usually
identical in shape and size, to be programmed 'in bulk' using
a 'global' scope command, followed by a scope restriction to
specific key(s), followed by more key programming, to
prevent the need for tedious key-by-key programming across
an entire matrix.
The powerup or reset default mode is Get. The current
Get/Put mode persists until countermanded by a different
Get/Put command or until the device is reset or powered off.
It is advisable to use Put mode only when actually writing
Setups to the device, which will happen infrequently; the part
should normally be left in Get mode. Get mode acts as a lock
to prevent accidental changes to the internal eeprom.
There are four types of commands:
Direction - Determine whether subsequent commands are
used to get data from or put data to the part;
Multiple direction commands of the same type (g, g, g, g ...)
are harmless and can be used to insure that the part does not
accidentally enter Put mode for a prolonged period, for
example due to noise glitches on the SPI lines. The 'g'
command can be repeated every few seconds.
Scope - Restrict the range of effect of subsequent
commands to a specific set of keys;
Status - Cause the part to respond with key information,
such as detections, signals, error codes, and the like;
g
0
X
67 - GET
Scope
n/a
C
OMMAND
Setup - Modify functionality such as burst length, threshold
levels, drift compensation characteristics, etc.
Bytes / Cmd 2nd Byte Range
Returns
0x67
n/a
Put
Get
1
n/a
n/a
n/a
Supervisory - Special functions such as diagnostics,
calibration, etc. which affect the part as a whole.
n/a
Lowercase 'G'. The 'g' command causes the device to treat all
subsequent Setup commands as 'Gets'; after, when a Setup
command is received from the host the part will respond by
sending back the current status of that Setup parameter.
All command types can be intermixed. Even during normal
device operation it is possible to use Setup and Supervisory
functions to alter key behavior on the fly. There is no special
'setup mode'.
The 'g' command is always single-byte and echoes back
itself.
Get/Put, Scope, and many Supervisory functions are volatile
and do not persist after a power down or reset cycle. Some
Supervisory commands require that the part be reset in order
for the new settings to take effect.
p
0
X
70 - PUT
Scope
n/a
C
OMMAND
Bytes / Cmd 2nd Byte Range
Returns
0x70
n/a
Note that the Setup functions write to eeprom and require
extra time for a response back to the host. Also note that as
with all eeprom memories there is a recommended lifetime
limit to the number of writes; this limit is 100,000 cycles.
Put
Get
1
n/a
n/a
n/a
n/a
Lower case 'p'. The 'p' command causes the device to treat
all subsequent Setup commands as 'Puts'; after, when a
2-byte Setup command is received from the host the part will
respond by programming in the desired parameter for the
key(s) which are affected.
Command functions are summarized in Section 5-6
It is highly advised to test the device checksum
(command ‘6’) or individual key settings or the general
device status (‘7’) once Setups have been programmed
into the part, each time the part is powered up and
periodically while running.
The 'p' command is always single-byte and echoes back
itself.
The part backs up all eeprom locations into Flash
memory, from which data is restored automatically
following a reset if eeprom corruption is detected. The
part should also be reset after any Put command(s) in
order to force the copy of eeprom data into Flash. See
Section 4.6.
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5.2 Scope Commands
5.3 Status Commands
Status commands cause the sensor to report back
information related to keys and their signals.
The host should always set the scope parameter when
initializing the part during normal operation as well as during
setup. Scope commands are persistent and apply to all
subsequent functions that are affected by scope, until a
different scope command is issued. On powerup or after reset
the device defaults to scope = 'all keys'.
It is not necessary to set the part to Get mode with these
commands, although it is advised to leave the part in Get
mode as a normal precaution (see Section 5.1)
Many functions only address one key regardless of the
current scope; in these cases the key being addressed is
always the key last set by the 's' or 'x' and 'y' commands. If
the 's' command was last set to key #9 (x=1, y=1), then even
though the 'S' command was issued afterwards the one-key
scope will remain key '9'. If 'x' were subsequently set to 2 then
one-key scope will be key x=2, y=1 (key #10). If 'y' were
subsequently set to 3, then one-key scope will be key x=2 /
y=3 (key #26). This rule operates for commands in either Put
or Get modes.
0
0
X
30 - SIGNAL FOR
S
Bytes / Cmd # Bytes Rtnd
INGLE
K
EY
Scope
n/a
Returns
n/a
0x00..0xFF
Put
Get
n/a
1
n/a
1
1
Numeric '0'. Returns the signal level in 8-bit unsigned binary
for one key whose location is determined by scope. Note that
the signal level is inverted: decreasing values correspond to
more touch due to the physics of key detection described in
Section 1.1.
Key numbering convention: The numbering of keys goes by
row then column. For example, the key in row X=3, column
Y=1 (X3Y1) is key 11. The formula for conversion of an X-Y
location to a key number is:
1
0
X
31 - DELTA
S
IGNAL FOR
S
Bytes / Cmd # Bytes Rtnd
INGLE
K
EY
Scope
n/a
Returns
n/a
0x00..0xFF
Put
Get
n/a
1
n/a
1
1
key_number = X_row + (Y_column x 8)
Row and column numbers are per Fig. 1-6. Keys are acquired
in this same burst sequence, i.e. X0Y0, X1Y0, X2Y0 etc.
Numeric '1'. Returns the value {Reference - Signal} in
unsigned 8-bit binary for one key whose location is
determined by scope. If Signal > Reference, the result is
truncated to zero.
s
0
X
73 - SPECIFIC
K
Bytes / Cmd 2nd Byte Range
EY
S
COPE
Scope
n/a
n/a
Returns
0x73
n/a
Increasing amounts of this value correspond to increasing
amounts of touch as the sign of signal is inverted (see 0x30
above).
Put
Get
2
n/a
0x00..0x3F
n/a
Lowercase 'S'. Targets a specific individual key for all further
functions that are affected by scope. The second byte must
contain a binary key number from 0..63 decimal.
2
0
X
32 - REFERENCE
V
Bytes / Cmd # Bytes Rtnd
ALUE
Scope
n/a
Returns
n/a
0x00..0xFF
Put
Get
n/a
1
n/a
1
1
S
0
X
53 - ALL
Scope
n/a
K
EYS
S
Bytes / Cmd 2nd Byte Range
COPE
Returns
0x53
n/a
Numeric '2'. Returns the Reference value in unsigned 8-bit
binary for one key whose location is determined by scope.
Put
Get
1
n/a
n/a
n/a
n/a
3
0
X
33 - R2R OFFSET
Uppercase 'S'. Addresses all keys in the matrix for all further
functions that can target a group of keys.
Scope
n/a
Bytes / Cmd # Bytes Rtnd
Returns
n/a
0x00..0xFF
Put
Get
n/a
1
n/a
1
1
x
0
X
78 - ROW
Scope
n/a
K
EYS
S
Bytes / Cmd 2nd Byte Range
COPE
Returns
0x78
n/a
Section 1.2, p. 4
Put
Get
2
n/a
0x00..0x07
n/a
Numeric '3'. Returns the R2R offset value in unsigned 8-bit
binary for one key whose location is determined by scope.
This function is useful primarily for circuit diagnostics or for an
independent determination of proper circuit operation.
n/a
Lowercase 'X'. Targets keys in a specific row for functions
that can address key groups. The second byte must contain a
row number from 0..7. This command also affects scope for
single-key commands.
4
0
X34 - C
Z
S
TATE
Scope
n/a
Bytes / Cmd # Bytes Rtnd
Returns
n/a
0x00..0x02
y
0
X
79 - COLUMN
K
Bytes / Cmd 2nd Byte Range
EYS
S
COPE
Put
Get
n/a
1
n/a
1
Scope
n/a
n/a
Returns
0x79
n/a
1
Put
Get
2
n/a
0x00..0x07
n/a
Section 1.2, p. 4
Numeric '4'. Returns the Cz state for one key whose location
is determined by scope. This function is useful primarily for
circuit diagnostics or for an independent determination of
circuit operation after calibration. A higher value indicates
more Cz cancellation is being applied to compensate for Cx;
a value of 2 indicates both Cz caps are being switched in.
Lowercase 'Y'. Targets keys in a specific column for functions
that can address key groups. The second byte is a binary
column number from 0..7. This command also affects scope
for single-key commands.
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5
0
X
35 - DETECTION
I
NTEGRATOR
C
Bytes / Cmd # Bytes Rtnd
OUNTS
<
SP> 0
X
20 - SIGNAL
L
EVELS FOR
G
Bytes / Cmd # Bytes Rtnd
ROUP
Scope
n/a
Returns
n/a
0x00..0xFF
Scope
n/a
8, 64
Returns
n/a
0x00..0xFF
Put
Get
n/a
1
n/a
1
Put
Get
n/a
1
n/a
8 or 64
1
Numeric '5'. Returns the Detection Integrator counter value
for one key whose location is determined by scope. This
function is useful primarily for circuit diagnostics.
Space character. Same function as 0x30 above except
returns a group response of 8 bytes (if Scope = row or
column selected) or 64 bytes (if Scope = entire matrix
selected). If no group scope has been selected, returns data
for all keys (64 bytes).
6
0
X
36 - EEPROM
CHECKSUM
Bytes / Cmd # Bytes Rtnd
Scope
n/a
n/a
Returns
n/a
0x00..0xFF
!
0
X
21 - DELTA
Scope
n/a
S
IGNALS FOR
G
Bytes / Cmd # Bytes Rtnd
ROUP
Put
Get
n/a
1
n/a
1
Returns
n/a
0x00..0xFF
Put
Get
n/a
1
n/a
8 or 64
8, 64
Numeric '6'. Returns the entire eeprom checksum. This
function is useful primarily for diagnostics and should
periodically be used to check for valid eeprom contents.
Exclamation character. Same function as 0x31 above except
returns a group response for 8 or 64 keys depending on
current scope. If no group scope has been selected, returns
data for all keys (64 bytes).
The checksum should be computed when the entire device's
settings, including the locked reference levels ('L' command)
are set. The host can then periodically test the checksum to
validate eeprom integrity. If needed, the eeprom can then be
reprogrammed by the host or the device can be reset to allow
the eeprom to be updated from Flash ROM (see Section 4.6).
"
0
X
22 - REFERENCE
L
Bytes / Cmd # Bytes Rtnd
EVELS FOR
G
ROUP
Scope
n/a
8, 64
Returns
n/a
0x00..0xFF
Put
Get
n/a
1
n/a
8 or 64
The checksum is a simple 8-bit carry fold-back type. Changes
to multiple Setups can generate identical checksums.
Changes to one location only will always produce a different
checksum. An identical change to 2, 4, 8, 16, 32 or 64 keys is
more prone to generating an identical checksum. A unique
checksum can be obtained again by altering any Setup for
another key (i.e. an unused key) to be different.
Double quote character. Same function as 0x32 above except
returns a group response of 8 or 64 bytes depending on
current scope. If no group scope has been selected, returns
64 bytes.
#
0
X
23 - R2R OFFSET FOR
G
Bytes / Cmd # Bytes Rtnd
ROUP
After any Setups change, the checksum will not be valid until
after the device has been reset.
Scope
n/a
8, 64
Returns
n/a
0x00..0xFF
Put
Get
n/a
1
n/a
8 or 64
Note that the general status byte returned by the ‘7’
command contains a bit that is set if there is an error in
eeprom data; this feature operates independently of the
checksum command.
Hash character. Same function as 0x33 above except returns
a group response of 8 bytes (Scope = row or column
selected) or 64 bytes (Scope = entire matrix selected)
depending on the current group scope setting. If no group
scope has been selected, returns 64 bytes.
There is no put version of the command.
7
0
X
37 - GENERAL
D
Bytes / Cmd # Bytes Rtnd
EVICE
S
TATUS
Scope
n/a
n/a
Returns
n/a
0x00..0x1F
$
0
X
24 - CHARGE
C
Bytes / Cmd # Bytes Rtnd
ANCELLATION FOR
G
ROUP
Put
Get
n/a
1
n/a
1
Scope
n/a
8, 64
Returns
n/a
0x00..0x03
Put
Get
n/a
1
n/a
8 or 64
Section 2.12, p. 8
Dollar character. Same function as 0x34 above except returns
a group response of 8 bytes (Scope = row or column
selected) or 64 bytes (Scope = entire matrix selected)
depending on the current group scope setting. If no group
scope has been selected, returns 64 bytes.
Numeric '7'. Returns the part's general status byte which is a
5-bit pattern as follows:
b7
u
b6
u
b5
u
b4
EF
b3
SF
b2
KE
b1
KR
b0
KD
KD: 1= one or more keys are in detection
KR: 1= one or more keys are recalibrating
KE: 1= one or more keys are reporting errors
SF: 1= sync fail; the part is not synchronized to an
external source (if in that mode; see Section 3.17).
EF: 1 = Eeprom / Flash discrepancy (Section 4.6)
%
0
X
25 - DETECT
I
NTEGRATOR
C
Bytes / Cmd # Bytes Rtnd
OUNTS FOR
G
ROUP
Scope
n/a
8, 64
Returns
n/a
0x00..0xFF
Put
Get
n/a
1
n/a
8 or 64
Percent character. Same function as 0x35 above except
returns a group response of 8 bytes (Scope = row or column)
or 64 bytes (Scope = entire matrix) depending on the current
group scope setting. If no group scope has been selected,
returns 64 bytes.
Higher bits (‘u’) report as 0's and are not used.
This command can be used as a general 1-byte status
response; if one or more bits are set, the host can take
interrogate further to narrow down specifics, such as which
key is being touched or in error, via other commands.
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The bitfields for a global response are:
b7 b6 b5 b4 b3
e
0
X
65 - ERROR
C
ODE FOR
S
Bytes / Cmd # Bytes Rtnd
ELECTED
K
EY
Scope
n/a
Returns
n/a
0x00..0x0F
b2
b1
b0
X7Y0 X6Y0 X5Y0 X4Y0 X3Y0 X2Y0 X1Y0 X0Y0
Put
Get
n/a
1
n/a
1
byte1
byte2
byte3
byte4
byte5
byte6
byte7
byte8
1
7
6
5
4
3
2
1
0
X7Y1 X6Y1 X5Y1 X4Y1 X3Y1 X2Y1 X1Y1 X0Y1
15 14 13 12 11 10
X7Y2 X6Y2 X5Y2 X4Y2 X3Y2 X2Y2 X1Y2 X0Y2
23 22 21 20 19 18 17 16
X7Y3 X6Y3 X5Y3 X4Y3 X3Y3 X2Y3 X1Y3 X0Y3
31 30 29 28 27 26 25 24
X7Y4 X6Y4 X5Y4 X4Y4 X3Y4 X2Y4 X1Y4 X0Y4
39 38 37 36 35 34 33 32
X7Y5 X6Y5 X5Y5 X4Y5 X3Y5 X2Y5 X1Y5 X0Y5
47 46 45 44 43 42 41 40
X7Y6 X6Y6 X5Y6 X4Y6 X3Y6 X2Y6 X1Y6 X0Y6
55 54 53 52 51 50 49 48
X7Y7 X6Y7 X5Y7 X4Y7 X3Y7 X2Y7 X1Y7 X0Y7
63 62 61 60 59 58 57 56
Section 2.12, p. 8
9
8
Lowercase 'E'. Returns the error byte for a selected key
defined by the 's' command. A 4-bit pattern is returned:
b7
u
b6
u
b5
u
b4
u
b3
L
b2
H
b1
R
b0
F
F: 1= failed last full recalibration attempt
R: 1= key is in process of full recalibration
H: 1= key reference is high (above normal bounds)
L: 1= key reference is low (below normal bounds)
u: undefined
Refer also to Section 2.10.
Byte 1 is the first returned byte in the sequence.
F, Bit 0 is set if it failed to calibrate properly during a forced
recalibration. The sensor will automatically make 5 sequential
attempts at recalibration before setting this flag.
In all the above examples a '1' in a bit position indicates that
there is some type of error associated with the key. The use
of the 'e' command (or 'E' with scope set to a specific key) will
specify the nature of the error.
R, Bit 1 is set if the key is in the process of a full
recalibration. When set, bits 2 and 3 are immediately cleared.
k
0
X
6B - REPORTING OF
F
Bytes / Cmd
IRST
T
OUCHED
K
#Bytes Rtnd
EY
H, Bit 2 when set indicates either:
Scope
n/a
n/a
Returns
n/a
0x00..0xFF
- the reference has drifted above decimal 191, or,
- the total absolute reference level has become higher than
the upper window boundary described in Section 2.11
and as defined by Command ^N after a forced
recalibration.
Put
Get
n/a
1
n/a
1
Section 2.12, p. 8
Lowercase 'K'. Returns a byte that indicates which if any key
has been touched. The byte is structured as follows:
L, Bit 3 when set indicates either:
- the reference has drifted below decimal 64, or,
- the total absolute reference level has become lower than
the lower boundary described in Section 2.11, as defined
by Command ^O after a forced recalibration.
b7
m
b6
-
b5
k5
b4
k4
b3
k3
b2
k2
b1
k1
b0
k0
Bits are used as follows:
m - if '1', indicates that yet another key is active
Bits 2 and 3, if set via drift compensation, would indicate that
the key should be recalibrated by the host. If H and L bits
appear immediately after a full recalibration, it means that the
key is probably defective.
k0..k5 - indicates the key number of a first detected key,
in the range 0..63 (0x00..0x3F).
If a reported key drops out while other keys are active, 'k' will
report one of the other active keys, but there is no rule for
which of the next keys gets reported in k0..k5.
E
0x45 - Error Codes for Group
Scope
n/a
1, 8, 64
Bytes / Cmd # Bytes Rtnd
Returns
n/a
0x00..0xFF
If the byte returned has a value of 255 (0xFF), then no key
has been detected.
Put
Get
n/a
1
n/a
1 or 8
Section 2.12, p. 8
Uppercase 'E'. Returns general error codes for a range of
keys defined by scope. Returns either 1 or 8 bytes depending
on whether a single key, row, column, or entire matrix are
selected.
The bitfields for a single key are the same as for 'e' above.
The bitfields for a single row (X) are:
b7
Y7
b6
Y6
b5
Y5
b4
Y4
b3
Y3
b2
Y2
b1
Y1
b0
Y0
The bitfields for a single column (Y) are:
b7
X7
b6
X6
b5
X5
b4
X4
b3
X3
b2
X2
b1
X1
b0
X0
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K
0
X
4B - KEY
Scope
n/a
T
OUCH
R
Bytes / Cmd # Bytes Rtnd
EPORTING FOR
G
ROUP
5.4 Setup Commands
Returns
n/a
0x00..0xFF
Setup functions are those that alter the behavior a key or a
group of keys. The setups are programmed into eeprom
locations in the part and ordinarily do not need to be
reprogrammed once set. However it is possible to change a
setup while the device is in normal operation without
interrupting the sensing function of the part.
Put
Get
n/a
1
n/a
1 or 8
1, 8, 64
Section 2.12, p. 8
Uppercase 'K'. Returns 1 or 8 bytes depending on the current
scope. The byte(s) returned contain a bit pattern which
indicates touched keys. A scope of a single key, row or
column will return one byte. A scope of all keys will return 8
bytes. If scope is one key, only the LSB is used to report.
Setup functions alter the internal eeprom, and this requires a
much longer time to complete than other commands; see
Table 4-1.
Setup 'put' commands become effective immediately after the
echo response of the command byte unless otherwise noted;
some setups require that the key(s) being altered be
The bitfields for a single key are:
b7
-
b6
-
b5
-
b4
-
b3
-
b2
-
b1
-
b0
key
recalibrated with the 'b' command before they take effect.
The bitfields for a single row (scope is X) are:
^A 0
X
01 - NEGATIVE
D
ETECT
T
Bytes / Cmd Byte 2 Range
HRESHOLD
b7
Y7
b6
Y6
b5
Y5
b4
Y4
b3
Y3
b2
Y2
b1
Y1
b0
Y0
Scope
1, 8, 64
1
Returns
0x01
0x04..0x40
Put
Get
2
1
0x04..0x40
n/a
The bitfields for a single column (scope is Y) are:
Section 2.1, p. 5
b7
X7
b6
X6
b5
X5
b4
X4
b3
X3
b2
X2
b1
X1
b0
X0
Ctrl-A. In Put mode, the command followed by a setting is
programmed into eeprom for the key(s) affected by scope.
The bitfields for a global report are:
1, 8, or 64 keys may be affected. Valid decimal values are:
b7 b6 b5 b4
b3
b2
b1
X7Y0 X6Y0 X5Y0 X4Y0 X3Y0 X2Y0 X1Y0 X0Y0
b0
byte1
byte2
byte3
byte4
byte5
byte6
byte7
byte8
4
5
6
7
17 20 25 30 35 45 55 64
8
10 12 15
7
6
5
4
3
2
1
0
X7Y1 X6Y1 X5Y1 X4Y1 X3Y1 X2Y1 X1Y1 X0Y1
15 14 13 12 11 10
X7Y2 X6Y2 X5Y2 X4Y2 X3Y2 X2Y2 X1Y2 X0Y2
23 22 21 20 19 18 17 16
X7Y3 X6Y3 X5Y3 X4Y3 X3Y3 X2Y3 X1Y3 X0Y3
31 30 29 28 27 26 25 24
X7Y4 X6Y4 X5Y4 X4Y4 X3Y4 X2Y4 X1Y4 X0Y4
39 38 37 36 35 34 33 32
X7Y5 X6Y5 X5Y5 X4Y5 X3Y5 X2Y5 X1Y5 X0Y5
47 46 45 44 43 42 41 40
X7Y6 X6Y6 X5Y6 X4Y6 X3Y6 X2Y6 X1Y6 X0Y6
55 54 53 52 51 50 49 48
X7Y7 X6Y7 X5Y7 X4Y7 X3Y7 X2Y7 X1Y7 X0Y7
63 62 61 60 59 58 57 56
Values other than the above will be rounded down.
9
8
In Get mode, the command will return a single byte according
to the rules of Section 5.2, page 21.
This setup controls key sensitivity by setting the counts of
signal delta needed to cause a detect. Higher = less
sensitive. Numbers should be 6 or greater under most
conditions to reduce the probability of noise detection.
Numbers greater than 20 indicate that the burst length is
probably too high. This setup interacts with Burst Length (^F).
^B 0
X
02 - POSITIVE
D
ETECT
T
Bytes / Cmd Byte 2 Range
HRESHOLD
Scope
1, 8, 64
1
Returns
0x02
0x04..0x40
Byte 1 is the first returned byte in the sequence.
Put
Get
2
1
0x04..0x40
n/a
In all the above examples a '1' in a bit position indicates that
the key is touched; a '0' indicates no touch.
Section 2.2, p. 6
Ctrl-B. In Put mode, the command followed by a setting is
programmed into eeprom for the key(s) affected by scope. 1,
8, or 64 keys may be affected. Valid decimal values are:
4
5
6
7
17 20 25 30 35 45 55 64
8
10 12 15
Values other than the above will be rounded down.
In Get mode, the command will return a single byte according
to the rules of Section 5.2, page 21.
This setup controls the ability of a key to recalibrate quickly
should the signal transition positive quickly, as when a touch
is prolonged enough to cause a recalibration, and when the
key is then 'untouched'. This condition can also be caused by
a foreign object being removed from a key. The value should
normally be set between 6 and 10 counts. If the value is very
high, the key will still recover by means of the drift
compensation process, albeit more slowly.
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^C 0
X
03 - NEGATIVE
T
HRESHOLD
H
Bytes / Cmd Byte 2 Range
YSTERESIS
^F
0
X
06 - BURST
Scope
1, 8, 64
1
L
ENGTH
Scope
64
64
Returns
0x03
0x01..0x03
Bytes / Cmd Byte 2 Range
Returns
0x06
0x00..0x40
Put
Get
2
1
0x01..0x03
n/a
Put
Get
2
1
0x00..0x40
n/a
Section 2.3, p. 6
Section 3.6, p. 12
Ctrl-C. In Put mode, the command followed by a setting is
programmed into eeprom for all keys only. The value should
be from 0 to 3, representing hysteresis as follows:
Ctrl-F. In Put mode the command sets the burst length of one
or more keys, according to the current scope. Valid decimal
values are:
0: 50%
1: 25%
0
1
2
3
4
5
12 15 20 25 30 40 50 64
7
10
2: 12.5%
3: 0% (no hysteresis)
Values other than the above will be rounded down.
In Get mode, the command will return a single byte according
to the rules of Section 5.2, page 21.
Values other than the above will be rounded down.
The percentage is the distance from the threshold level to the
reference level. The hysteresis level is always closer to the
threshold point than to the reference point. 25% is a
reasonable value under most conditions.
^F sets the length of the acquisition burst on a key by key
basis. This setting is directly proportional to signal gain. This
setup interacts with Negative and Positive Threshold (^A and
^B). Increasing ^F can allow for higher threshold levels and
more robust signals, at the expense of increased radiated
emissions and reduced Cx load capacity.
As this parameter is common to all keys, Put and Get
operations send or return only one byte.
Special condition: If the value for ^F for a key is set to zero
the burst disabled and the key will not function; the key will
report back with an error code. The timing for the 'phantom
burst' will be preserved so that overall key scan timing will
remain unchanged.
^D 0
X
04 - POSITIVE
T
HRESHOLD
H
Bytes / Cmd Byte 2 Range
YSTERESIS
Scope
64
64
Returns
0x04
0x01..0x03
Put
Get
2
1
0x01..0x03
n/a
Section 2.3, p. 6
^G 0
X
07 - BURST
SPACING
Bytes / Cmd Byte 2 Range
Ctrl-D. Identical in operation to ^C above except this applies
to positive 'detections' used to recalibrate the sensor (see ^B
above for details). Uses same hysteresis values as ^C above.
Scope
64
64
Returns
0x07
0x00..0x05
Put
Get
2
1
0x00..0x05
n/a
Section 3.8, p. 12
^E 0
X
05 - DWELL
T
IME IN
M
Bytes / Cmd Byte 2 Range
ACHINE
C
YCLES
Scope
64
64
Returns
0x05
0x01
Ctrl-G. In Put mode, sets the spacing between successive
acquire bursts for the entire matrix.
Put
Get
2
1
0x01
n/a
The second byte indicates the spacing to be set according to
the following values:
Sections 1.2, 3.3, 3.9, 3.13
0: 250µs
1: 300µs
2: 400µs
3: 500µs
4: 1000µs
5: 2000µs
Ctrl-E. Governs the delay from the rise of an X drive to the
termination of Y transfer gating ('dwell time').
This command is included for compatibility with future
versions. The device defaults to 1 (one) machine cycle of
dwell or 167ns with a 6MHz oscillator. Although the command
will be accepted, this setting cannot be changed.
Values higher than the above will be truncated to 2000µs.
The dwell time can be shortened below 167ns by an external
circuit as described in Section 3.9.
Longer delay times equate to slower acquisitions. At lower
delay times (faster rep rates) there can be conflicts with long
burst lengths which will prevent proper operation; see Section
5.7.
As this parameter is common to all keys, Put and Get
operations send or return only one byte, 0x01.
The time required to scan the entire keymatrix once is the
above delay multiplied by 64 regardless of the number of
keys actually used or the part model number.
Burst spacing also affects recalibration time; see Section 2.10
The scope for this function is always 'all keys'.
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The unit of measure is a burst, i.e. a setting of 5 means that a
^H 0
X
08 - NEGATIVE
D
RIFT
C
Bytes / Cmd Byte 2 Range
OMPENSATION
R
ATE
detection must be sensed 5 bursts in sequence. A burst for a
key occurs once every complete matrix scan. Thus, if the
burst spacing is 500us, the response time will be:
Scope
1, 8, 64
1
Returns
0x08
0x01..0x64
Put
Get
2
1
0x01..0x64
n/a
5 x 500us x 64 = 160ms
Section 2.4, p. 6
The second byte must be one of the following values (shown
in decimal):
Ctrl-H. In Put mode, sets the rate of drift compensation used
in the negative signal direction.
0
1
2
3
5
20 32 45 60 90 123 175 255
7
10 15
The second byte must be one of the following valid values
(shown in decimal):
Values other than the above will be rounded down.
1
15
2
20
3
25
4
33
6
45
8
60
10 12
75 100
In Get mode, the command will return a single byte according
to the rules of Section 5.2, page 21.
Values other than the above will be rounded down.
This setup can be used as a noise filter, or as a mechanism
to intentionally slow down key reaction time in order to require
a long user touch.
These numbers correspond to the amount of drift
compensation applied, in 100ms/count of reference change,
for signals which are negative with respect to the reference
level, i.e. in the same direction as legitimate detections.
Higher numbers equate to slower drift compensation.
Overcompensation (too fast) can result in the suppression of
legitimate detections. Under-compensation can result in
inadequate compensation for rapid environmental changes.
Values of 15 to 45 (1.5 to 4.5 secs/count) are considered
normal under most conditions.
Special condition: If the value for ^J is set to zero the key is
disabled, but the burst for the key is still generated.
^K 0x0B - POSITIVE
R
ECALIBRATION
D
Bytes / Cmd Byte 2 Range
ELAY
Scope
1, 8, 64
1
Returns
0x0B
0x00..0xFF
Put
Get
2
1
0x00..0xFF
n/a
Drift compensation does not occur while the signal has
passed below the ^A threshold level or subsequently
remained below the negative hysteresis level.
Section 2.7, p. 7
Ctrl-K. In Put mode, sets the delay until recalibration, timed
from when the signal first crosses the positive threshold.
In Get mode, the command will return a single byte according
to the rules of Section 5.2, page 21.
The second byte controls the delay in 100ms increments, and
must be one of the following valid values:
Put mode scope can be one key, a row or column, or all keys.
0
1
2
3
5
20 32 45 60 90 123 175 255
7
10 15
^I 0
X
09 - POSITIVE
D
RIFT
C
Bytes / Cmd Byte 2 Range
OMPENSATION
R
ATE
Values other than the above will be rounded down. As an
example, a value of 85 will cause a 6-second delay.
Scope
1, 8, 64
1
Returns
0x09
0x01..0x64
Put
Get
2
1
0x01..0x64
n/a
In Get mode, the command will return a single byte according
to the rules of Section 5.2, page 21.
Section 2.4, p. 6
Special condition: If ^K is set to zero this feature is disabled
and the key will never auto-recalibrate on positive transitions;
however drift compensation will still operate.
Ctrl-I. Same as ^H above in all respects, except operates
only when the signal is positive with respect to the reference
level, i.e. in an abnormal direction. It is usually desirable to
set this rate much faster than for ^H, i.e. to a lower number.
Valid decimal values are:
^L 0x0C - NEGATIVE
R
ECALIBRATION
D
Bytes / Cmd Byte 2 Range
ELAY
Scope
1, 8, 64
1
Returns
0x0C
0x00..0xFF
1
15
2
20
3
25
4
33
6
45
8
60
10 12
75 100
Put
Get
2
1
0x00..0xFF
n/a
Values other than the above will be rounded down.
Section 2.5, p. 6
Values of 4 to 10 (0.4 to 1.0 secs/count) are considered
suitable for most systems.
Ctrl-L. In Put mode, sets the delay until recalibration, timed
from when the signal first crosses below the negative
threshold as defined by ^A.
Positive drift compensation continues to operate even if the
signal has exceeded the positive threshold.
The second byte represents the delay in 1s increments, and
must be one of the following valid values:
^J 0x0A - DETECT
I
NTEGRATOR
L
Bytes / Cmd Byte 2 Range
IMIT
0
1
2
3
5
20 32 45 60 90 123 175 255
7
10 15
Scope
1, 8, 64
1
Returns
0x0A
0x00..0xFF
Put
Get
2
1
0x00..0xFF
n/a
Values other than the above will be rounded down. As an
example, a setting of 85 will cause delays of 60 seconds.
Section 2.6, p. 7
In Get mode, the command will return a single byte according
to the rules of Section 5.2, page 21.
Ctrl-J. In Put mode, sets the detect integrator limit for one or
more keys according to scope.
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Special condition: If the value for ^L is set to zero this Special condition: If the value is set to zero, this feature is
feature is disabled and the key will never auto-recalibrate
after a prolonged touch.
disabled.
^O 0x0F - NEGATIVE
R
EFERENCE
E
RROR
B
Bytes / Cmd Byte 2 Range
AND
^M 0x0D - INTRA-BURST
P
ULSE
S
Bytes / Cmd Byte 2 Range
PACING
Scope
64
64
Returns
0x0F
0x00..0x63
Scope
64
64
Returns
0x0D
0x02..0x0A
Put
Get
2
1
0x00..0x63
n/a
Put
Get
2
1
0x02..0x0A
n/a
Section 2.8, p. 7
Section 3.7, p. 12
Ctrl-O. In Put mode, sets the amount of tolerable negative
deviation in the reference level for all keys, in percent with
regard to the 'locked' reference value for each key. The setup
is global in nature and affects all keys equally.
Ctrl-M. In Put mode, sets the amount of time between
individual pulses in a burst.
The second byte must be in the range of 2 to 10 decimal;
other values will be ignored. The setting applies to all keys.
Valid values are from 0 to 99 decimal; higher values will be
truncated to 99. The percentage applied is equal to the
decimal value; a value of 99 equates to 99% of the signal
level (i.e. a 1% decrease w.r.t. the locked reference level).
The value corresponds to the timing between pulses within a
burst, in microseconds. For example, a setting of 5 will set the
pulse spacing to 5 microseconds.
In Get mode the function returns the current setting of ^M.
In Get mode the function returns the current value of ^M.
This setup is identical in nature to ^N except that: (1) it
governs negative reference deviations, and (2) values are
expressed in percent instead of 10's of percent.
Intra-burst pulse spacing controls the fundamental frequency
of the burst and can have a strong effect on radiated
emissions from the matrix control panel. It can also have an
effect on susceptibility to external EMI if the external fields are Special condition: If the value is set to 0, this feature is
close in periodicity to the burst spacing.
^N 0x0E - POSITIVE
disabled.
R
EFERENCE
E
RROR
B
Bytes / Cmd Byte 2 Range
AND
^P 0x10 - ADJACENT
K
EY
SUPPRESSION (‘AKS’)
Bytes / Cmd Byte 2 Range
Scope
64
64
Returns
0x0E
0x00..0x64
Scope
1, 8, 64
1
Returns
0x10
0x00, 0x01
Put
Get
2
1
0x00..0x64
n/a
Put
Get
2
1
0x00, 0x01
n/a
Section 2.8, p. 7
Section 2.9, p. 8
Ctrl-N. In Put mode, sets the amount of tolerable positive
deviation in the reference level for all keys, in percent, with
regard to the 'locked' reference value for each key. The setup
is global in nature and affects all keys equally.
Ctrl-P. In Put mode, instructs logic for the keys specified by
the current scope whether or not to enable the AKS feature.
Valid 2nd byte values for this function are:
0: AKS off {default}
1: AKS on
Valid values are from 0 to 100 decimal; higher values will be
truncated to 100. The percentage applied is 10x the decimal
value, thus, a value of 100 equates to a 1,000% change (i.e.
10x the locked reference level).
In Get mode, the command will return a single byte according
to the rules of Section 5.2, page 21.
In Get mode the function returns the current setting of ^N.
AKS functions to suppress detections from water films which
can 'spread' a touch signal from the touched key to adjacent
keys. It is also useful for panels with tightly spaced keys,
where a fingertip can partially overlap an adjacent key. This
feature will act to suppress the signals from the unintended
keys.
This setup is used to define the limit of possible positive
reference deviation with respect to a factory setting, which is
used in turn to set an error flag for key(s) whose reference
level rises above the designated error band. If for example
this setting is set to 50, and the device is calibrated and
reference levels are locked (see command 'L', Lock
Reference Levels) into the part by the OEM, then in the future
if the reference level of a key should rise 500% over its
Locked reference level then the key will report back an error
flag via commands 'e' or 'E'.
AKS only operates across keys that have been AKS-enabled;
signal strength comparisons are not made with non-
AKS-enabled keys.
Unused keys with burst lengths of zero are also ignored for
purposes of AKS.
To obtain the error flag for a boundary condition, the key must
be first recalibrated using the 'b' command.
The host device should periodically check the reference
levels for keys to make sure they do not rise above 191 or fall
below 64 (see Section 2.11); if this should happen the host
should recalibrate the affected key(s). Failure to do so will
prevent the error band limits from operating.
The error band can be used to detect circuit faults as well as
extremes of temperature or moisture on the circuitry. Typical
values are from 2 to 4 (20% to 40%).
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Due to the large number of bytes written to eeprom by this
5.5 Supervisory / System Functions
Supervisory functions report or control miscellaneous
functions that affect overall chip control, testing, or
diagnostics. All supervisory functions ignore scope except
where noted.
command, there is a significant delay from the second byte
until the return echo is sent back to the host.
This command should be used only during production. There
is no get version of the command.
For commands requiring Put mode to operate, the device
should be set back to Get mode immediately thereafter where
possible, to help prevent unintended writes to eeprom.
b
0x62 - RECALIBRATE
K
Bytes / Cmd 2nd Byte Range
EYS
Scope
1, 8, 64
n/a
Returns
0x62
n/a
Put
Get
1
n/a
n/a
n/a
6
0
X
36 - EEPROM
CHECKSUM
Bytes / Cmd # Bytes Rtnd
Scope
n/a
n/a
Returns
n/a
0x00..0xFF
Section 2.10, p. 8; Section 3.16
Put
Get
n/a
1
n/a
1
Lowercase 'B'. This is a put-only command that causes the
keys selected by scope to recalibrate. The part must be in Put
mode for this command to work.
See page 22.
44 - DAC TEST
The return byte is sent before the keys have calibrated. While
keys are in recalibration, status of the keys can be
determined using the 'e' or 'E' commands.
D
0
X
Scope
n/a
n/a
Bytes / Cmd 2nd Byte Range
0x00..0xFF
n/a
Returns
0x44
n/a
Put
Get
2
n/a
If 'b' is sent while key(s) are already in the middle of
recalibration, the affected key(s) will abandon the old
calibration cycle and start a new one.
Uppercase 'D'. Enables the DAC test mode function. The
second byte contains the value to be sent to the DAC, which
must be sent within 100ms to the part otherwise the
command is automatically cancelled. The part must be in Put
mode for this command to work.
There is no get version of the command.
l
0x6C - RETURN
Scope
L
AST
C
Bytes / Cmd
OMMAND
C
# Bytes Rtnd
HARACTER
Returns
n/a
0x00..0xFF
Put
Get
n/a
n/a
n/a
1
n/a
1
This function can be used to test the external R2R DAC for
proper operation during board production or in development.
Once in this mode the part ceases to operate as a sensor,
and must be reset via power-down or the reset pin to restore
normal operation. This function does not persist past reset or
power-down.
Lowercase 'L'. This get-only command reports back with the
value of the prior command received by the part. The
command also reports back any erroneous commands,
allowing the host device to verify that a command was
correctly received.
Before the DAC value is set in hardware, the burst length on
all keys is set to 0 to disable keys and prevent further
scanning. All keys will then report errors until all burst lengths
are again set by the host after the part has been reset.
If this command is repeated, the second and subsequent
instances of 'l' will report back with 0x6C.
There is no put version of the command.
A series of 'D' commands can be sent to cause the DAC to
generate a ramp or other test pattern which can be easily
diagnosed on an oscilloscope.
r
0x72 - RESET
Scope
D
EVICE
Bytes / Cmd 2nd Byte Range
Returns
0x72
n/a
There is no get version of the command.
Put
Get
n/a
n/a
2
n/a
0x00
n/a
L
0x4C - LOCK
Scope
R
EFERENCE
L
Bytes / Cmd 2nd Byte Range
EVELS
Section 3.14, p. 14
Returns
0x4C
n/a
Put
Get
64
n/a
2
n/a
0x00
n/a
Lowercase 'R'. This put-only command hard-resets the part.
The command 0x72 must be followed by a null (0x00) within
100ms or the command will fail. The part must be in Put
mode for this command to work.
Section 2.8, p. 7
Uppercase 'L'. This is a put-only command that locks the
reference levels of the device into eeprom for all keys, for
boundary checking purposes over the product's life.
After the null byte is received, the device will echo back the ‘r’
character; about 16ms after the echo the part will reset.
Upon waking up again, the part will resume communication
and sensing in accordance with the timing shown in Section
3.16.
The whole command – 'L' followed by a null (0x00) - must be
received within 100ms without any intervening byte, or the
command will fail. The part must be in Put mode for this
command to work.
If for some reason the device is unable to echo back the ‘r’
character, for example due to the host not releasing the SS
line, the part will completely reset anyway after about 2
seconds.
The scope of this command is always 'all keys'.
This function records to eeprom the Cz values, DAC offset,
and signal reference. The locked reference levels are used to
compute boundary checks; these are performed after the next
device recalibration or reset.
There is no get version of the command.
lQ
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Note that when the part is in Slave mode, the host can clock
V
0x56 - RETURN
P
ART
V
Bytes / Cmd
ERSION
data to the device at rates up to 1.5MHz even if the setting of
^Q is slower.
Scope
# Bytes Rtnd
Returns
n/a
0x00..0xFF
Put
Get
n/a
n/a
n/a
1
n/a
1
New settings do not become effective until the device has
been powered off and back on again or after the reset (‘r’)
command.
Uppercase 'V'. This get-only command returns the part
version number.
Refer to Sections 4.3 and 4.4 for specific timing details.
There is no put version of the command.
^R
0
X
12 - OSCILLOSCOPE
S
Bytes / Cmd 2nd Byte Range
YNC
W
0x57 - RETURN
P
ART
S
Scope Bytes / Cmd # Bytes Rtnd
IGNATURE
Scope
1, 8, 64
1, 8, 64
Returns
0x12
0x00, 0x01
Returns
n/a
0x20, 0x30, 0x40
Put
Get
2
1
0x00, 0x01
n/a
Put
Get
n/a
n/a
n/a
1
n/a
1
Section 3.20, p. 15
Section 3.1, p. 9
Ctrl-R. In Put mode, controls the oscilloscope sync function
of Pin 37. The settings of this function are:
Uppercase 'W'. This get-only command returns the part
signature as follows:
0: off {factory default}
1: on
0x20
0x30
0x40
(32 decimal) - for QT60325
(48 decimal) - for QT60485
(64 decimal) - for QT60645
When on, Pin 37 outputs a pulse that brackets the acquire
burst(s) for the keys targeted by scope. Without this it is
virtually impossible to view signals corresponding to a specific
key.
There is no put version of this command.
Z
0x5A - ENTER
Scope
SLEEP
Bytes / Cmd 2nd Byte Range
Pin 37 idles low and pulses high during a sync pulse. Pin 37
is also used for SPI mode selection by connecting to +5 or
Ground, and as a result if ^R is used, Pin 37 should never
be clamped to a supply rail but rather connected via a 10K
resistor to prevent a short circuit. See Section 3.20.
Returns
*0x5A, 0x5A
n/a
Put
Get
n/a
n/a
2
n/a
0x00
n/a
Section 3.17, p. 14
Uppercase 'Z'. This put-only command forces the device to
enter sleep mode. The command 0x5A must be followed only
by a null (0x00) within 100ms or the command will fail.
^R is volatile, that is, it does not persist after a power down.
^S 0x13 - C
S
C
LAMP
P
Bytes / Cmd 2nd Byte Range
OLARITY
Scope
Returns
0x13
0x00, 0x01
The command returns 0x5A immediately before going to
sleep, and a second 0x5A upon waking up. The part must be
in Put mode for this command to work.
Put
Get
-
-
2
1
0x00, 0x01
n/a
If for some reason the device is unable to echo back the first
‘Z’ character, for example due to the host not releasing the
SS line, the part will completely reset after about 2 seconds.
Section 3.19, p. 15
Ctrl-S. Controls the polarity of the Cs Clamp line, CSR, pin
35, using the 2nd byte as follows:
The part will reawaken after a logic low is detected for >10µs
on pin 11 (X2WS pin, see Section 3.17, p. 14). The device
then sends the second ‘Z’ back to the host, and resumes
from its prior state before it went to sleep without the need for
recalibration.
0: active-low
1: active-high
The part must be in Put mode for this command to work.
This pin controls the polarity of the reset signal applied to the
charge integrator reset switch. In systems using an n-channel
switch (active-high required to reset the Cs capacitor), this
option should be set to ‘1’; for a p-channel mosfet switch in
bipolar supply systems requiring an active-low to reset the Cs
capacitor, ^S should be set to ‘0’. For the reference circuit of
Figure 3-1 this should be set to ‘0’ (the default); for the circuit
of Figure 3-2 this should be set to ‘1’..
The device always reawakens in Get mode.
There is no get version of the ‘Z’ command.
^Q 0x11 - DATA
Scope
R
ATE
S
Bytes / Cmd 2nd Byte Range
ELECTION
Returns
0x11
0x00..0x03
Put
Get
n/a
n/a
2
1
0x00..0x03
n/a
The setting of ^S does not become effective until the device
has been powered off and back on again or after the reset
(‘r’) command has been issued.
Section 4, p. 16
Ctrl-Q. This command sets the communications clock rate of
the SPI interface in Master mode. The acceptable values of
the 2nd byte are:
0: 46.875 kHz {factory default}
1: 93.75 kHz
2: 375 kHz
3: 1.5 MHz
The part must be in Put mode for this command to work.
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^T 0x14 - BOUNDARY
E
Bytes / Cmd Byte 2 Range
QN
C
ONSTANT C1, MSB
^W 0x17 - NOISE
Scope
SYNC
Bytes / Cmd Byte 2 Range
Scope
64
64
Returns
0x14
0x00..0x7F
Returns
0x17
0x00, 0x01
Put
Get
2
1
0x00..0x7F
n/a
Put
Get
-
-
2
1
0x00, 0x01
n/a
Section 2.8, p. 7
Section 3.17, p. 14
Ctrl-T. In Put mode, sets the MSB of equation constant C1
for boundary checking purposes. The part must be in Put
mode for this command to work.
Ctrl-W. In Put mode, sets whether the noise sync feature is
enabled or disabled. The part must be in Put mode for this
command to work.
The function has global scope. The default value is 5, which
corresponds to the reference circuit on page 10. A change in
this parameter only has effect after a reset or recalibration of
all keys.
The settings are:
0: off {factory default}
1: on
This function has global scope. The default value is 0 (off).
Valid values are from 0 to 127 decimal. Each count of the
MSB has a value 256x that of the LSB.
This feature can be used to synchronize the part to an
external repetitive source of e-field which might interfere with
the sensor signals, for example 50 or 60Hz fields from
adjacent power wiring. By doing so the part becomes immune
to the noise source.
In Get mode this function returns the current ^T value.
Refer to ^U (0x15) for the LSB definition.
^U 0x15 - BOUNDARY
E
QN
C
Bytes / Cmd Byte 2 Range
ONSTANT C1, LSB
In Get mode this function returns the current setting of ^W.
Scope
64
64
Returns
0x15
0x00..0xFF
The setting of ^W does not become effective until the device
has been powered off and back on again or after the reset
(‘r’) command has been issued.
Put
Get
2
1
0x00..0xFF
n/a
Section 2.8, p. 7
Ctrl-U. In Put mode, sets the LSB of equation constant C1 for
boundary checking purposes. The part must be in Put mode
for this command to work.
The function has global scope. The default value is 0xE9,
which corresponds to the reference circuit on page 10. A
change in this parameter only has effect after a reset or
recalibration of all keys.
Valid values are from 0 to 255 decimal. The value of the LSB
must be combined with the value of the MSB to form the total
value.
In Get mode this function returns the current ^U value.
Refer to ^T (0x14) for the MSB definition.
^V 0x16 - BOUNDARY
E
QUATION
CONSTANT C2
Bytes / Cmd Byte 2 Range
Scope
64
64
Returns
0x16
0x00..0xFF
Put
Get
2
1
0x00..0xFF
n/a
Section 2.8, p. 7
Ctrl-V. In Put mode, sets equation constant C2 for boundary
checking purposes. The part must be in Put mode for this
command to work.
This function has global scope. The default value is 8, which
corresponds to the reference circuit on page 10. A change in
this parameter only has effect after a reset or recalibration of
all keys.
Valid values are from 0 to 255 decimal.
In Get mode this function returns the current ^V value.
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5.6 Function Summary Table
Put Mode
Get Mode
Operand
Range
Bytes
Scope returned
Return
range
Default
setting
Char Hex
Name
Description
P/G Scope Bytes/Put
Returns
Page
Direction Commands
g
p
0x67
0x70
Get
Put
all subsequent Setups become 'Gets'
all subsequent Setups become 'Puts’
P
P
-
-
1
1
0x67
0x70
20
20
Get
Get
Scope Commands
s
S
x
0x73
0x53
0x78
Set one key scope
Set all keys scope
Set row keys scope
targets a specific key in range 0..63
targets all keys in the matrix
P
P
P
P
-
-
-
-
2
1
2
2
0x00..0x3F
0x73
0x53
0x78
0x79
21
21
21
21
undefined
undefined
undefined
undefined
targets keys in a designated row, range 0..7
targets keys in a designated column, range 0..7
0x00..0x07
0x00..0x07
y
0x79 Set column keys scope
Status Commands
0
1
0x30
0x31
0x32
0x33
0x34
signal for 1 key
delta signal for 1 key
reference for 1 key
R2R offset for 1 key
Cz state for 1 key
get signal for 1 key
get Reference-Signal for 1 key
get Reference level for 1 key
get R2R Offset for 1 key
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
1
1
0x00..0xFF
0x00..0xFF
0x00..0xFF
0x00..0xFF
0x00..0x02
0x00..0xFF
0x00..0xFF
0x00..0x1F
0x00..0xFF
0x00..0xFF
0x00..0xFF
0x00..0xFF
0x00..0x02
0x00..0xFF
0x00..0x0F
0x00..0xFF
0x00..0xFF
0x00..0xFF
21
21
21
21
21
22
22
22
22
22
22
22
22
22
23
23
23
24
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
1
2
1
1
1
3
1
1
4
get Cz value for 1 key
1
5
0x35 Det Integrator for 1 key
get detect integrator for 1 key
get eeprom checksum of entire eeprom
get device status of entire device
get signal for group
1
1
6
0x36
0x37
0x20
0x21
0x22
0x23
0x24
eeprom checksum
general device status
signals for group
-
1
7
-
1
<sp>
!
8, 64
8, 64
8, 64
8, 64
8, 64
8, 64
1
8, 64
8, 64
8, 64
8, 64
8, 64
8, 64
1
delta signals for group
references for group
R2R offset for group
Cz states for group
get Reference-Signal for group
get References levels for group
get R2R offsets for group
“
#
$
get Cz states for group
%
e
0x25 Det integrator for group
get detection integrators for group
get error code for 1 key
0x65
0x45
0x6B
error code for 1 key
error codes for group
report 1st key
E
k
get error bits for group
1, 8, 64
-
1, 8, 64
-
get indication of first touched key
get indication of all touched keys
K
0x4B report touches for group
1, 8, 64
1, 8, 64
© Quantum Research Group Ltd.
Put Mode
Get Mode
Operand
Range
Bytes
Scope returned
Return
range
Default
setting
Char Hex
Name
Description
P/G Scope Bytes/Put
Returns
Page
Setup Commands
touch sensitivity threshold; less = more
4,5,6,7,8,10,12,15,17,20,25,30,35,45,55,64 counts
^A
^B
^C
^D
^E
0x01
0x02
0x03
0x04
0x05
Negative threshold
Positive threshold
Negative hysteresis
Positive hysteresis
Dwell time
P/G 1, 8, 64
P/G 1, 8, 64
2
2
2
2
2
0x04..0x40
0x04..0x40
0x00..0x03
0x00..0x03
0x01
0x01
0x02
0x03
0x04
0x05
1
1
1
1
1
1
1
0x04..0x40
0x04..0x40
0x0C
0x08
24
24
25
25
25
sensitivity to positive signals for recalibration
4,5,6,7,8,10,12,15,17,20,25,30,35,45,55,64 counts
hysteresis for negative threshold
50%, 25%, 12.5%, 0%
P/G
P/G
P/G
64
64
64
1
0x00..0x03 0x01 (25%)
0x00..0x03 0x01 (25%)
hysteresis for positive threshold
50%, 25%, 12.5%, 0%
1
delay from the rise of an X line to end of Y-gate;
only setting is 0x01 (167ns/period @ 6MHz Xtal)
64
0x01
0x01
0x0C
set gain via number of QT cycles / burst; zero disables
burst
0,1,2,3,4,5,7,10,12,15,20,25,30,40,50,64
^F
0x06
Burst length
P/G 1, 8, 64
2
0x00..0x40
0x06
1
1
0x01..0x40
25
time from start of one burst to start of next burst
250us, 300us, 400us, 500us, 1000us, 2000us
0x01
(300us)
^G
^H
^I
0x07
0x08
0x09
Burst spacing
P/G
64
2
2
2
0x00..0x05
0x01..0x64
0x01..0x64
0x07
0x08
0x09
64
1
1
1
1
0x00..0x05
0x01..0x64
0x01..0x64
25
26
26
rate of drift compensation for negative signal swings
.1,.2,.3,.4,.6,.8,1,1.2,1.5,2,2.5,3.3,4.5,6,7.5,10 secs
Neg drift comp rate
Pos drift comp rate
P/G 1, 8, 64
P/G 1, 8, 64
0x1E (3s)
0x0A (1s)
rate of drift compensation for positive signal swings
.1,.2,.3,.4,.6,.8,1,1.2,1.5,2,2.5,3.3,4.5,6,7.5,10 secs
1
number of detections required to register a touch,
counted in bursts of detection; zero disables a key.
0,1,2,3,5,7,10,15,20,32,45,60,90,123,175,255 counts
^J
^K
^L
0x0A
0x0B
0x0C
Neg det int limit
Pos recal delay
Neg recal delay
P/G 1, 8, 64
P/G 1, 8, 64
P/G 1, 8, 64
2
2
2
0x00..0xFF
0x00..0xFF
0x00..0xFF
0x0A
0x0B
0x0C
1
1
1
1
1
1
0x00..0xFF
0x00..0xFF
0x00..0xFF
0x03
26
26
26
time req’d to trigger a recal from a positive signal
excursion in 0.1s increments; zero disables recal.
0,.1,.2,.3,.5,.7,1,1.5,2,3.2,4.5,6,9,12.3,17.5,25.5 secs
0x0A (1s)
0x64 (10s)
time req’d to trigger a recal from a detection, in 1s
increments. Zero disables recal.
0,1,2,3,5,7,10,15,20,32,45,60,90,123,175,255 secs
period of QT pulses, in microseconds
2, 3, 4, 5, 6, 7, 8, 9, 10us
^M
^N
0x0D
0x0E
Intra-burst spacing
Pos error band
P/G
P/G
P/G
64
64
64
2
2
0x02..0x0A
0x00..0x64
0x0D
0x0E
64
64
1
1
0x02..0x0A
0x00..0x64
0x02
27
27
tolerable positive reference deviation with respect to
Locked reference values, step 10%. Zero disables.
0 (off)
tolerable negative reference deviation with respect to
Locked reference values, step 1%. Zero disables.
^O
^P
0x0F
0x10
Neg error band
Key suppression
2
2
0x00..0x63
0x00, 0x01
0x0F
0x10
64
1
1
1
0x00..0x63
0x00, 0x01
0 (off)
0 (off)
27
27
adjacent key suppression feature; 1 = on
P/G 1, 8, 64
© Quantum Research Group Ltd.
Put Mode
Get Mode
Operand
Range
Bytes
Scope returned
Return
range
Default
setting
Char Hex
Name
Description
P/G Scope Bytes/Put
Returns
Page
Supervisory Commands
6
0x36
0x44
Eeprom checksum
DAC test
returns checksum of internal eeprom
G
-
1
0x00..0xFF
-
-
0
sends operand to R2R DAC; byte 2 must be sent within
100ms of command byte
D
P
-
2
2
1
0x00..0xFF
0x00
0x44
0x4C
0x62
28
locks reference levels into eeprom for future boundary
checks. ‘L’ must be followed by 0x00 (null) 100ms after
the command byte
L
0x4C
Lock references
P
64
-
28
fully recalibrate keys;
return byte is sent prior to calibration
b
l
0x62
0x6C
0x72
0x56
0x57
Recal keys
Return last command
Reset device
Version
P
G
P
1, 8, 64
-
-
-
-
-
28
28
28
29
29
send back last command byte received
-
1
0x00..0xFF
0x00..0xFF
hard reset the device. ‘r’ must be followed by a null
within 100ms.
r
-
2
0x00
0x72
V
W
returns part version number
G
G
-
-
1
1
0x20, 0x30,
0x40
Signature
returns part signature number
force device into Sleep mode. ‘Z’ must be followed by a
null within 100ms. 0x5A returned before and after
entering Sleep
Z
0x5A
0x11
Sleep
P
-
-
2
2
0x00
0x5A, 0x5A
0x11
-
29
29
sets SPI master-mode clock rate. Part must be reset via
‘r’ command or hard reset to take effect
46.875kHz, 93.75kHz, 375kHz, 1.5MHz
^Q
SPI rate
P/G
0x00..0x03
-
1
0x00..0x03
0 (46.8k)
oscilloscope sync control. 1 = on.
feature is volatile - cleared to 0 after each reset
^R
^S
0x12
0x13
Scope sync
Cs clamp
P/G 1, 8, 64
2
2
0x00, 0x01
0x00, 0x01
0x12
0x13
-
-
1
1
0x00, 0x01
0x00, 0x01
0 (off)
0
29
29
Cs clamp drive polarity; 0 = active-low; part must be
reset via ‘r’ command or hard reset to take effect
P/G
-
^T
^U
^V
0x14
0x15
0x16
Boundary C1 MSB
Boundary C1 LSB
Boundary C2
boundary equation constant, C1, MSB
boundary equation constant, C1, LSB
boundary equation constant, C2
P/G
P/G
P/G
64
64
64
2
2
2
0x00..0x7F
0x00..0xFF
0x00..0xFF
0x14
0x15
0x16
64
64
64
1
1
1
0x00..0x7F
0x00..0xFF
0x00..0xFF
0x05
0xE9
0x08
30
30
30
noise sync enable; 1 = on
device must be reset to take effect
^W
0x17
Noise sync
P/G
-
2
0x00, 0x01
0x17
-
1
0x00, 0x01
0 (off)
30
© Quantum Research Group Ltd.
processing time. When this happens, burst timing and host
communications can slow down and become erratic.
5.7 Timing Limitations
The device requires processing time between bursts, as well
as time to handle communications with the host. With short
burst spacings, long burst lengths, and long intra-burst pulse
spacings, the device can simply run out of available
Burst spacings should be verified on an oscilloscope during
development to be certain that the device timings are
preserved and are constant. If not, the burst length and/or
pulse spacing should be reduced.
Table 5-2 Permissible Burst Lengths (BL’s)
Pulse Spacing = 2µs
Pulse Spacing = 3µs
Pulse Spacing = 4µs
Pulse Spacing = 5µs
Pulse Spacing = 6µs
Burst
Max BL
Spacing
Burst
Max BL
Spacing
Burst
Max BL
Spacing
Burst
Max BL
Spacing
Burst
Max BL
Spacing
250
300
25
50
64
64
64
64
250
300
10
20
40
64
64
64
250
300
10
20
40
64
64
64
250
300
10
20
40
50
64
64
250
300
7
15
30
50
64
64
400
400
400
400
400
500
500
500
500
500
1,000
2,000
1,000
2,000
1,000
2,000
1,000
2,000
1,000
2,000
Pulse Spacing = 7µs
Pulse Spacing = 8µs
Pulse Spacing = 9µs
Pulse Spacing = 10µs
Burst
Max BL
Spacing
Burst
Max BL
Spacing
Burst
Max BL
Spacing
Burst
Max BL
Spacing
250
300
7
250
300
7
250
300
7
250
300
5
15
30
40
50
64
12
25
30
50
64
12
20
30
40
64
10
20
30
40
64
400
400
400
400
500
500
500
500
1,000
2,000
1,000
2,000
1,000
2,000
1,000
2,000
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© Quantum Research Group Ltd.
6 PLD Source Listing
Pre-programmed parts are available from Quantum in small quantities.
The object code file for this PLD is also available upon request.
TITLE 'E664SPI'
Description
Timing skew generator for E664SPI matrix board. Code is for ICT PEEL22CV10AZ epld. Not warranted to work with any other part.
Compiler and documentation from the ICT web site, www.ictpld.com.
Programmer from System General; model “All Writer”, www.systemgeneral.com.
End_Desc;
PEEL22CV10A
"I/O CONFIGURATION DECLARATION
"IOC (PIN_NO 'PIN_NAME' POLARITY OUTPUT_TYPE FEEDBACK_TYPE)
"Inputs
Y0 PIN 5 "pre-decoded Y inputs
Y1 PIN 4
Y2 PIN 3
Y3 PIN 2
Y4 PIN 8
Y5 PIN 9
Y6 PIN 10
Y7 PIN 11
XS PIN 1 "Sum of X1..X7
X7 PIN 6 "X7 input (gets OR'd with XS)
YG PIN 7 "Y gate trigger
"Outputs
"Clamping outputs
IOC ( 21 'YM0'
IOC ( 19 'YM1'
IOC ( 17 'YM2'
IOC ( 15 'YM3'
IOC ( 16 'YM4'
IOC ( 18 'YM5'
IOC ( 20 'YM6'
IOC ( 22 'YM7'
"Dly ckt drive out
IOC ( 14 'XSD'
Pos
Pos
Pos
Pos
Pos
Pos
Pos
Pos
Com
Com
Com
Com
Com
Com
Com
Com
Feed_Pin )
Feed_Pin )
Feed_Pin )
Feed_Pin )
Feed_Pin )
Feed_Pin )
Feed_Pin )
Feed_Pin )
Pos
Com
Feed_Pin )
"QS3251 neg enable
IOC ( 23 'YGG' Pos
OutCom Feed_Pin )
AR NODE 25 "Global Asynchronous Reset
SP NODE 26 "Global Synchronous Preset
DEFINE
EQUATIONS
AR = 0;
SP = 0;
" Define Y clamp outputs
YM0.COM = 0;
YM1.COM = 0;
YM2.COM = 0;
YM3.COM = 0;
YM4.COM = 0;
YM5.COM = 0;
YM6.COM = 0;
YM7.COM = 0;
"Enable control. Goes low on active Y channel (Y= active high to clamp)
YM0.OE = Y0;
YM1.OE = Y1;
YM2.OE = Y2;
YM3.OE = Y3;
YM4.OE = Y4;
YM5.OE = Y5;
YM6.OE = Y6;
YM7.OE = Y7;
XSD.COM = 0;
XSD.OE = !(XS # X7);
"clamp the delay cap when all 'x' lines are 0
YGG.COM =!(YG & !XSD); "Enable the 3251 so long as both Yg is high AND xsd is low
"As soon as xsd goes high, disable the 3251
lQ
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© Quantum Research Group Ltd.
7 Electrical Specifications
7.1 Absolute Maximum Specifications
Operating temp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . as designated by suffix
Storage temp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55OC to +125OC
V
DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +5.5V
Max continuous pin current, any control or drive pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mꢀ
Short circuit duration to ground, any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . infinite
Short circuit duration to VDD, any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . infinite
Voltage forced onto any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6V to (Vdd + 0.6) Volts
Frequency of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10MHz
Eeprom maximum writes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100,000 write cycles
Flash maximum writes (eeprom backup). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1,000 write cycles
7.2 Recommended operating conditions
VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75 to 5.25V
Supply ripple+noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mV p-p max
Cx transverse load capacitance per key from X to Y. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 20pF
Fosc oscillator frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6MHz +/-2%
7.3 DC Specifications
Vdd = 5.0V, Cs = 15nF, Freq = 6.00MHz, Ta = recommended range, unless otherwise noted
Parameter
Notes
Description
Min
Typ
Max
Units
I
DDR
DDS
BOD
Supply current, running
Supply current, sleep
Brown-out detection voltage
Low input logic level
High input logic level
Low output voltage
15
mA
µA
V
Not including external components
Not including external components
I
20
V
4
V
IL
0.8
0.6
V
V
HL
2.2
V
V
OL
V
4mA sink
V
OH
High output voltage
Input leakage current
Acquisition resolution
Pullup resistors
Vdd-0.7
V
1mA source
I
IL
1
8
µA
bits
kohms
A
R
R
P
35
120
Drdy, SS’ pins
7.4 Timing
Parameter
Notes
Description
Min
Typ
Max
Units
T
DR
DR
2
3
Tdr delay from response
Multi-byte return spacing
Host command space
SPI Clock rate
1
1,000
2,000
µS
µS
T
15
15
Tcm
Fck
µS
1.5
MHz
µS
Tradc
ADC delay from R2R setup
8.16
From R2R setup to AIN+ sample
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© Quantum Research Group Ltd.
7.5 Maximum Drdy Response Delays
... with adjacent key suppression disabled:
Burst Spacing
Function Type
Setup - put (affect 1 key)
Setup - put (affect 8 keys)
Setup - put (affect 64 keys)
Lock reference Level (L)
Calibrate command (all keys)
Get key errors (E), Get keys pushed
All other commands
250µs
300µs
10ms
400µs
500µs
10ms
1ms
10ms
40ms
300ms
800ms
4ms
2ms
10ms
40ms
300ms
800ms
4ms
10ms
40ms
10ms
40ms
40ms
40ms
300ms
800ms
4.8ms
1.8ms
800us
300ms
800ms
5.7ms
2.1ms
900us
300ms
800ms
7.6ms
2.8ms
1.2ms
300ms
800ms
9.5ms
3.5ms
1.5ms
2ms
2ms
1ms
1ms
... with adjacent key suppression enabled:
Burst Spacing
Function Type
Setup - put (affect 1 key)
Setup - put (affect 8 keys)
Setup - put (affect 64 keys)
Lock reference Level (L)
Calibrate command (all keys)
Get key errors (E), Get keys pushed
All other commands
250µs
10ms
300µs
10ms
40ms
300ms
800ms
6.6ms
3ms
400µs
10ms
40ms
300ms
800ms
8.8ms
4ms
500µs
10ms
40ms
300ms
800ms
11ms
5ms
1ms
10ms
40ms
300ms
800ms
5ms
2ms
10ms
40ms
300ms
800ms
4ms
40ms
300ms
800ms
5.5ms
2.5ms
1.5ms
2ms
2ms
1.8ms
2.4ms
3.5ms
2ms
2ms
Preliminary Data: All specifications subject to change
.
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© Quantum Research Group Ltd.
8 Mechanical
8.1 Dimensions
A
44
42
40
38
36
34
35
43
41
39
37
1
2
3
4
5
6
7
8
9
33
32
31
30
29
28
27
26
25
24
23
p
P
L
10
11
13
15
17
19
21
20 22
12
14
16
18
a
e
o
H
h
E
Package Type: 44 Pin TQFP
Millimeters
Inches
Max
SYMBOL
Min
Max
Notes
Min
Notes
a
A
e
E
h
H
L
p
P
o
9.90
10.10
12.21
0.20
0.75
0.15
1.20
0.45
0.80
8.00
7
SQ
SQ
0.386
0.458
0.003
0.018
0.002
-
0.012
0.031
0.315
0
0.394
0.478
0.008
0.030
0.006
0.047
0.018
0.031
0.315
7
SQ
SQ
11.75
0.09
0.45
0.05
-
0.30
0.80
8.00
0
BSC
BSC
BSC
BSC
8.2 Marking
TA
TQFP
Marking
00C to +700C
00C to +700C
00C to +700C
-400C to +1050C
-400C to +1050C
-400C to +1050C
QT60325-S
QT60485-S
QT60645-S
QT60325-AS
QT60485-AS
QT60645-AS
QT60325-S
QT60485-S
QT60645-S
QT60325-AS
QT60485-AS
QT60645-AS
lQ
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© Quantum Research Group Ltd.
9 Index
A
adc
H
hard reset, 8
hysteresis, 6, 25, 26, 32
subranging, 4, 5
adjacent key suppression, 8, 27
alert output, 15
application assistance, 5
I
intra-burst pulse spacing, 12, 27, 34
B
block diagram, 5
boundary equation, 30, 33
burst length, 8, 9, 12, 20, 24, 25, 28, 34
burst spacing, 6, 25, 34
burst timing, 9, 19
J
jfet, 13
K
key design, 5
key numbering convention, 21
key reporting, 23, 24
C
calibration, 8, 13, 14, 15, 20, 21, 28
charge cancellation, 4, 9, 22
charge gate, 9
L
ladder dac
R2R ladder, 5, 7, 9, 14
led, 15
lock reference levels, 7, 17, 28
charge integrator, 4, 5, 9, 12, 13, 29
charge neutralization, 9
circuit model, 4, 5
cs, 6, 9, 13, 15, 29
cs clamp polarity, 29
csr drive polarity, 15
cx, 4, 6, 8, 9, 21, 25
M
marking, 38
master mode, 16, 18, 19
master-slave mode, 16, 18
matrix configuration, 5
mechanical, 38
miso, 17, 18
mosi, 14, 17, 18, 19
multi-byte responses, 18, 19
cz, 5, 6, 7, 8, 9, 13, 14, 21, 28
D
dac test, 28
delta signals, 22
detect integrator, 22, 26
detection integrator, 6, 7, 22
device status, 22
device variations, 5
dimensions, 38
direction commands, 20
drdy’, 17, 18
N
negative detect integrator, 26
negative detect threshold, 12, 24
negative error band, 27
negative recalibration delay, 6, 26
negative threshold, 5, 6, 8, 12, 25, 26
noise, 12, 15, 16, 24, 26
noise coupling, 12
drift compensation, 6, 7, 8, 13, 15, 20, 23, 24, 26
dwell, 34
gate dwell, 5, 9, 12, 13, 14, 16, 25
E
O
echo, 18, 19, 24, 28
eeprom checksum, 22, 28
electrostatic shield, 15
emi, 4, 27
offset, 5, 6, 7, 8, 9, 13, 14, 21, 22, 28
opamp, 13
oscillator, 14, 16
oscilloscope sync, 15
error code, 23
Error byte, 23
error guardbanding, 7
esd protection, 16
P
pcb layout, 15
peel22cv10az, 13, 35
pld, 9, 12, 13, 14, 16, 35
positive detect threshold, 24
positive drift compensation, 26
positive error band, 27
positive recal delay, 7, 8
positive recalibration delay, 7, 26
positive threshold, 6, 7, 8, 25, 26
power supply, 15
F
fast-recalibration, 7, 8
field flow, 4
function summary table, 31
G
gate dwell
put command, 20
dwell, 5, 9, 12, 13, 14, 16, 25
get command, 20
ground plane, 15
Q
qmbtn, 4, 15, 16
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© Quantum Research Group Ltd.
spi interface, 4
qs3251, 12, 13, 16, 35
qt60325, 9, 29
qt60485, 9, 29
spi noise problems, 16
spi rate, 29
ss’, 17, 18, 19
startup, 13, 14, 15
status commands, 20, 21
subranging
ADC, 4, 5
supervisory functions, 20, 28
sync, 14, 15, 16, 18, 22, 29, 30
R
r2r ladder
ladder DAC, 5, 7, 9, 14
recalibrate keys (command), 28
recalibration, 6, 7, 8, 13, 23, 24, 26, 28, 30
reference level, 4, 6, 7, 8, 25, 26, 27
reference levels, 22
T
reference window boundary, 8
reset, 4, 7, 8, 9, 13, 14, 15, 20, 21, 28, 29, 30, 35
resonator, 14, 15
response delays, 17, 37
return last command, 28
return part signature, 29
return part version, 29
threshold level, 6, 7, 25, 26
timing limitations, 34
tlc2272, 13
U
uart, 16
rf emissions, 5
V
S
scan sequence
Matrix scan sequence, 9
sck, 17, 18, 19
vdd, 15, 16
vee, 15
virtual ground, 4
scope, 16, 20, 21
scope commands, 21
sensitivity, 12
W
water films, 4, 14, 27
serial interface, 16
setup commands, 20, 24
signal gain, 9, 13, 25
signal levels, 4, 22
signal processing, 4, 5
slave mode, 16, 17, 18, 19
sleep mode, 14, 29
sleep_wake, 14, 15
soft reset, 8
X
x electrode drives, 9
x2ws, 14
Y
y gate drives, 12
yc0..yc7, 12
ys0..ys2, 12
spi, 4, 15, 16, 17, 18, 19, 20, 29
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© Quantum Research Group Ltd.
Notes -
QT60xx5 / R1.05
© Quantum Research Group Ltd.
lQ
© 2002 QRG Ltd.
Patented and patents pending
Corporate Headquarters
1 Mitchell Point
Ensign Way, Hamble SO31 4RF
Great Britain
Tel: +44 (0)23 8056 5600 Fax: +44 (0)23 8045 3939
admin@qprox.com
www.qprox.com
North America
651 Holiday Drive Bldg. 5 / 300
Pittsburgh, PA 15220 USA
Tel: 412-391-7367 Fax: 412-291-1015
All specifications subject to change.
This device expressly not for use in any medical or human safety related
application without the express written consent of an officer of the company.
QT60xx5 / R1.05
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