QT1103 [QUANTUM]
QTOUCH⑩ 10-KEY SENSOR IC; QTOUCH⑩ 10键传感器IC
| 型号： | QT1103 |
| 厂家： | 
QUANTUM RESEARCH GROUP |
| 描述： | QTOUCH⑩ 10-KEY SENSOR IC |
| 文件： | 总22页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
lQ
QT1103
SENSOR IC
QTOUCH™ 10-KEY
This datasheet is applicable to all revision 3 chips
The QT1103 is designed for low cost appliance, mobile, and consumer
electronics applications.
24 23 22
20 19 18 17
21
QTouch™ technology is a type of patented charge-transfer sensing
method well known for its robust, stable, EMC-resistant characteristics.
It is the only all-digital capacitive sensing technology in the market
today. This technology has over a decade of applications experience
spanning thousands of designs.
SNS5
SNS8
SNS8K
SNS9
SNS9K
N/C
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
SNS4K
SNS4
SNS3K
SNS3
QTouch circuits are renowned for simplicity, reliability, ease of design,
and cost effectiveness.
QT1103
SNS2K
SNS2
/CHANGE
1W
QTouch™ sensors employ a single reference capacitor tied to two pins
of the chip for each sensing key; a signal trace leads from one of the
pins to the sensing electrode which forms the key. The sensing
electrode can be a simple solid shape such as a rectangle or circle. An
LED can be placed near or inside the solid circle for illumination.
RX
SNS1K
1
3
5
8
2
4
6
7
The key electrodes can be designed into a conventional Printed Circuit
Board (PCB) or Flexible Printed Circuit Board (FPCB) as a copper
pattern, or as printed conductive ink on plastic film.
AT A GLANCE
Number of keys:
1 to 10
Patented spread-spectrum charge-transfer (one-per-key mode)
Technology:
Key outline sizes:
Key spacings:
Electrode design:
Layers required:
Substrates:
5mm x 5mm or larger (panel thickness dependent); widely different sizes and shapes possible
6mm or wider, center to center (panel thickness, human factors dependent)
Single solid or ring shaped electrodes; wide variety of possible layouts
One layer substrate; electrodes and components can be on same side
FR-4, low cost CEM-1 or FR-2 PCB materials; polyamide FPCB; PET films, glass
Copper, silver, carbon, ITO, Orgacon† ink (virtually anything electrically conductive)
Plastic, glass, composites, painted surfaces (low particle density metallic paints possible)
Compatible with grounded metal immediately next to keys
Up to 50mm glass, 20mm plastic (key size dependent)
Electrode materials:
Panel materials:
Adjacent Metal:
Panel thickness:
Key sensitivity:
Outputs:
Settable via change in reference capacitor (Cs) value
RS-232 based serial output, capable of single-wire operation
Good
Moisture tolerance:
Power:
2.8V ~ 5.0V
Package:
32-pin 5 x 5mm QFN RoHS compliant
Signal processing:
Applications:
Patents:
Self-calibration, auto drift compensation, noise filtering, AKS™
Portable devices, domestic appliances and A/V gear, PC peripherals, office equipment
AKS™ (patented Adjacent Key Suppression)
QTouch™ (patented Charge-transfer method)
†Orgacon is a registered trademark of Agfa-Gevaert N.V
AVAILABLE OPTIONS
TA
32-QFN
QT1103-ISG
-400C to +850C
LQ
C
Copyright © 2006-2007 QRG Ltd
QT1103_3R0.03_0607
Contents
2.9 Simplified Mode
2.10 Unused Keys
1 Overview
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3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
5
8
8
8
8
8
8
8
8
8
9
9
9
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1.1 Differences With QT1101
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1.2 Parameters
2.11 Serial 1W Interface
1.2.1 Introduction
2.11.1 Introduction
1.2.2 Burst Operation
1.2.3 Self-calibration
1.2.4 Autorecalibration
2.11.2 Basic 1W Operation
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2.11.3 LP Mode Effects on 1W
2.11.4 2W Operation
1.2.5 Drift Compensation
3 Design Notes
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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2.6 Detection Integrator Confirmation
1.2.7 Spread-spectrum Operation
3.1 Oscillator Frequency
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3.2 Spread-spectrum Circuit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2.8 Sync Mode
3.3 Cs Sample Capacitors - Sensitivity
3.4 Rsns Resistors
. . . . . . . . . . . . . . . . . . . . . . 12
1.2.9 Low Power (LP) Mode
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1.2.10 Adjacent Key Suppression (AKS™)
1.2.11 Outputs
3.5 Power Supply
3.6 PCB Layout and Construction
. . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2.12 Simplified Mode
4 Specifications
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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3 Wiring
4.1 Absolute Maximum Specifications
4.2 Recommended Operating Conditions
4.3 AC Specifications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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2 Device Operation
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2.1 Reset and Startup Time
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2.2 Option Resistors
4.4 DC Specifications
4.5 Signal Processing
4.6 Idd Curves
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2.3 DETECT Pin
2.4 /CHANGE Pin
2.5 SYNC/LP Pin
2.5.1 Introduction
2.5.2 Sync Mode
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4.7 LP Mode Typical Response Times
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4.8 Mechanical Dimensions
4.9 Part Marking
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2.5.3 Low Power (LP) Mode
2.6 AKS™ Function Pins
2.7 MOD_0, MOD_1 Inputs
2.8 Fast Detect Mode
4.10 Moisture Sensitivity Level (MSL)
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5 Datasheet Control
5.1 Changes
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5.2 Numbering Convention
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QT1103_3R0.03_0607
1.2.5 Drift Compensation
1 Overview
1.1 Differences With QT110
The QT1103 is a general replacement device for the highly
popular QT1101. It has all of the same features as the older
device but differs in the following ways:
Drift compensation operates to correct the reference level of
each key slowly but automatically over time, to suppress
false detections caused by changes in temperature, humidity,
dirt and other environmental effects.
1
1.2.6 Detection Integrator Confirmation
Detection Integrator (DI) confirmation reduces the effects of
noise on the QT1103. The DI mechanism requires
consecutive detections over a number of measurement
bursts for a touch to be confirmed and indicated on the
outputs. In a like manner, the end of a touch (loss of signal)
has to be confirmed over a number of measurement bursts.
This process acts as a type of ‘debounce’ against noise.
•
•
•
Rs resistors on each channel eliminated
Up to 4x more sensitive for a given value of Cs
Shorter burst lengths, less power for a given value of
Cs
•
•
•
‘Burst A and B’ only mode for up to eight keys, with
less power
A per-key counter is incremented each time the key has
exceeded its threshold and stayed there for a number of
measurement bursts. When this counter reaches a preset
limit the key is finally declared to be touched.
‘Burst B’ only mode for up to four keys, with less
power than ‘Burst A and B’ mode
Requires an external reset signal
For example, if the limit value is six, then the device has to
exceed its threshold and stay there for six measurement
bursts in succession without going below the threshold level,
before the key is declared to be touched. If on any
measurement burst the signal is not seen to exceed the
threshold level, the counter is cleared and the process has to
start from the beginning.
The QT1103 should be used instead of the QT1101 for new
designs due to a simpler circuit, lower power and lower cost.
1.2 Parameters
1.2.1 Introduction
The QT1103 is an easy to use, ten touch-key sensor IC
based on Quantum’s patented charge-transfer (‘QT’)
principles for robust operation and ease of design. This
device has many advanced features which provide for
reliable, trouble-free operation over the life of the product.
In normal operation, the start of a touch must be confirmed
for six measurement bursts and the end of a touch for three.
In a special ‘Fast Detect‘ mode (available via jumper
resistors) (Tables 1.2 and 1.6), confirmation of the start of a
touch requires only three and the end of a touch requires two
measurement bursts.
1.2.2 Burst Operation
Fast detect is only available when AKS is disabled.
The device operates in ‘burst mode’. Each key is acquired
using a burst of charge-transfer sensing pulses whose count
varies depending on the value of the reference capacitor Cs
and the load capacitance Cx. In LP mode, the device sleeps
in an ultra-low current state between bursts to conserve
power. The keys signals are acquired using three successive
bursts of pulses:
1.2.7 Spread-spectrum Operation
The bursts operate over a spread of frequencies, so that
external fields will have minimal effect on key operation and
emissions are very weak. Spread spectrum operation works
with the DI mechanism to dramatically reduce the probability
of false detection due to noise.
Burst A: Keys 0, 1, 4, 5
Burst B: Keys 2, 3, 6, 7
Burst C: Keys 8, 9
1.2.8 Sync Mode
The QT1103 features a Sync mode to allow the device to
slave to an external signal source, such as a mains signal
(50/60Hz), to limit interference effects. This is performed
using the SYNC/LP pin. Sync mode operates by triggering
three sequential acquire bursts, in sequence C-A-B from the
Sync signal. Thus, each Sync pulse causes all ten keys to be
acquired (see Section 2.5.2, page 8).
Bursts always operate in C-A-B sequence.
1.2.3 Self-calibration
On power-up, all ten keys are self-calibrated within 300ms
(typical) to provide reliable operation under almost any
conditions.
1.2.4 Autorecalibration
1.2.9 Low Power (LP) Mode
The device can time out and recalibrate each key
independently after a fixed interval of continuous touch
detection, so that the keys can never become ‘stuck on’ due
to foreign objects or other sudden influences. After
recalibration the key will continue to function normally. The
delay is selectable to be either 10s, 60s, or infinite (disabled).
The device features an LP mode for microamp levels of
current drain with a slower response time, to allow use in
battery operated devices. On detection of touch, the device
automatically reverts to its normal mode and asserts the
DETECT pin active to wake up a host controller. The device
remains in normal, full acquire speed mode until another
pulse is seen on its SYNC/LP pin, upon which it goes back to
LP mode (see Optimization of LP Mode, page 9).
The device also autorecalibrates a key when its signal
reflects a sufficient decrease in capacitance. In this case the
device recalibrates after ~2 seconds so as to recover normal
operation quickly.
When eight or fewer keys are required, current drain in LP
mode can be further reduced by choosing appropriate
channels on the QT1103 (see the end of Section 2.5.3,
page 8).
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QT1103_3R0.03_0607
If AKS is disabled, all keys can operate simultaneously.
1.2.10 Adjacent Key Suppression (AKS™)
AKS™ is a Quantum-patented feature that can be enabled
via a resistor strap option. AKS works to prevent multiple
keys from responding to a single touch, a common complaint
about capacitive touch panels. This can happen with closely
spaced keys, or with control surfaces that have water films on
them.
1.2.11 Outputs
The QT1103 has a serial output using one or two wires,
RS-232 data format, and automatic baud rate detection. A
simple protocol is employed.
The QT1103 operates in slave mode, i.e. it only sends data
to the host after receiving a request from the host.
AKS operates by comparing signal strengths from keys within
a group of keys to suppress touch detections from those that
have a weaker signal change than the dominant one.
An additional /CHANGE (state changed) signal allows the
use of the serial interface to be optimised, rather than being
polled continuously.
The QT1103 has two different AKS groupings of keys,
selectable via option resistors. These groupings are:
1.2.12 Simplified Mode
•
•
AKS operates in three groups of keys
AKS operates over all ten keys
To reduce the need for option resistors, the simplified
operating mode places the part into fixed settings with only
the AKS feature being selectable. LP mode is also possible
in this configuration. Simplified mode is suitable for most
applications.
These two modes allow the designer to provide AKS while
also providing for shift or function operations.
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QT1103_3R0.03_0607
1.3 Wiring
Table 1.1 Pin Descriptions
Pin
Name
Type
Function
Notes
If Unused
1
2
3
SS
/RST
Vdd
OD
I
P
Spread spectrum
Reset input
Power
Spread spectrum drive
Active low reset
+2.8 ~ +5.0V
100kꢀ resistor to Vss
-
-
Resistor to Vdd and optional
spread spectrum RC network
Leave open
4
5
OSC
n/c
I
Oscillator
-
-
-
-
Open or
option resistor*
Open
Open or
option resistor*
Open
Open or
option resistor*
Open
Open or
option resistor*
Sense pin and
option select
Sense pin
Sense pin and
option select
Sense pin
Sense pin and
option select
Sense pin
Sense pin and
option select
Sense pin
To Cs0 and/or
option resistor
To Cs0 + Key
To Cs1 and/or
option resistor*
To Cs1 + Key
To Cs2 and/or
option resistor*
To Cs2 + Key
To Cs3 and/or
option resistor*
To Cs3 + Key
To Cs4
To Cs4 + Key
6
SNS0
SNS0K
SNS1
SNS1K
SNS2
SNS2K
SNS3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7
8
9
10
11
12
13
14
15
SNS3K
SNS4
SNS4K
I/O
I/O
I/O
Open
Open
Open
Sense pin
Sense pin
Sense pin and
option select
Sense pin
To Cs5 and/or
option resistor *
To Cs5 + Key
To Cs6 and/or
Open or
option resistor*
Open
Open or
option resistor*
16
17
18
SNS5
SNS5K
SNS6
I/O
I/O
I/O
Sense pin and
option select
Sense pin and
mode select
Sense pin and mode
or option select
Sense pin
option resistor*
To Cs6 + Key and/or
mode resistor†
To Cs7 and/or mode resistor†
or option resistor*
To Cs7 + Key
Open or
19
20
SNS6K
SNS7
I/O
I/O
mode resistor†
Open or mode resistor† or option
resistor*
21
22
23
24
25
26
27
28
29
SNS7K
Vss
I/O
P
I
O/OD
I/O
I/O
I/O
I/O
-
Open
-
Vdd or Vss**
Open
Ground
0V
SYNC/LP‡
DETECT
SNS8
Sync In or LP In
Detect Status
Sense pin
Rising edge sync or LP pulse
See Table 1.4
To Cs8
To Cs8 + Key
To Cs9
To Cs9 + Key
Open
Open
Open
Open
SNS8K
SNS9
SNS9K
n/c
Sense pin
Sense pin
Sense pin
-
-
Open
0 = a key state has changed
Requires pull-up
Requires pull-up to Vdd
Input for 2W mode
30
/CHANGE
OD
State changed
100kꢀ resistor to Vss
31
32
1W
RX
I/OD
I
1W mode serial I/O
2W Receive
-
Vdd
Pin Type
I
CMOS input only
I/O
OD
I/OD
O/OD
P
CMOS I/O
CMOS open drain output
CMOS input or open drain output
CMOS push-pull or open-drain output (option selected)
Ground or power
Notes
† Mode resistor is required only in Simplified mode (see Figure 1.2)
* Option resistor is required only in Full Options mode (see Figure 1.1)
‡ Pin is either Sync or LP depending on options selected (functions SL_0, SL_1, see Figure 1.1)
** See text
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QT1103_3R0.03_0607
Figure 1.1 Connection Diagram - Full Options (32-QFN Package)
VDD
Voltage Reg
Vunreg
*Note: One bypass capacitor to be tightly wired between
Vdd and Vss. Follow regulator manufacturer’s
recommendations for input and output capacitors.
*100nF
Keep these parts
close to the IC
MOD_1
Keep these parts
close to the IC
3
VDD
11
10
SNS2K
SNS2
KEY 2
KEY 1
KEY 0
V
DD / VSS
1M
CS2
12
R
SNS2
SNS3
MOD_0
DD / VSS
R
SNS3
C
C
S3
S4
13
1M
1M
SNS3K
V
KEY 3
KEY 4
14
15
9
8
SNS1K
SNS1
SNS4
C
S1
R
SNS4
R
SNS1
SNS4K
AKS_1
DD / VSS
V
OUT_D
V
DD / VSS
16
17
1M
7
6
SNS0K
SNS0
SNS5
C
S0
C
S5
R
SNS5
R
SNS0
SNS5K
KEY 5
AKS_0
DD / VSS
1M
V
QT1103
32-QFN
SL_0
Recommended Rb1, Rb2 Value
VDD
V
DD / VSS
1M
18
19
With Spread-Spectrum
SNS6
R
SNS6
C
C
S6
S7
Vdd Range
Rb1 Rb2
Rb1
Rb2
SNS6K
KEY 6
KEY 7
2.8 ~ 2.99V 12K 27K
3.0 ~ 3.59V 12K 22K
3.6 ~ 5V 15K 27K
4
1
SL_1
DD / VSS
OSC
SS
V
1M
20
21
SNS7
R
SNS7
Css
SNS7K
No Spread-Spectrum
Vdd Range
Rb1 Rb2
25
26
SNS8
2.8 ~ 2.99V 15K
3.0 ~ 3.59V 18K
3.6 ~ 5V 20K
dni
dni
dni
R
SNS8
C
C
S8
S9
SNS8K
KEY 8
KEY 9
27
28
SNS9
dni = do not install
100K
100K
100K
R
SNS9
32
31
30
Vdd
Vdd
Vdd
SNS9K
RX
1W
2W DATA
2
/RST
RESET IN
DATA
23
SYNC or LP
SYNC/LP
Pull-up not required for push-pull mode
/CHANGE
/CHANGE
See Detect pin mode table
29
5
100K
N.C.
N.C.
Vdd
24
VSS
DETECT
DETECT OUT
22
Table 1.2
AKS / Fast-Detect Options
AKS_1
Vss
Vss
Vdd
Vdd
AKS_0
AKS MODE
Off
Off
On, in 3 groups
On, global
FAST-DETECT
Off
Enabled
Off
Off
Vss
Vdd
Vss
Vdd
Table 1.3
Max On-Duration
MOD_1
Vss
Vss
MOD_0
Vss
Vdd
MAX ON-DURATION MODE
10 seconds to recalibrate
60 seconds to recalibrate
Infinite (disabled)
Vdd
Vss
Vdd
Vdd
(reserved)
Table 1.4
Detect Pin Drive
OUT_D
Vss
Vdd
DETECT PIN MODE
Open drain, active low
Push-pull, active high
Table 1.5
SYNC/LP Function
SL_1
Vss
SL_0
Vss
SYNC/LP PIN MODE
Sync
Vss
Vdd
Vdd
Vdd
Vss
Vdd
LP mode: 70ms response time
LP mode: 110ms response time
LP mode: 190ms response time
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QT1103_3R0.03_0607
Figure 1.2 Connection Diagram - Simplified Mode (32-QFN Package)
VDD
Voltage Reg
Vunreg
*Note: One bypass capacitor to be tightly wired between
Vdd and Vss. Follow regulator manufacturer’s
recommendations for input and output capacitors.
*100nF
Keep these parts
close to the IC
3
Keep these parts
close to the IC
R
SNS2
VDD
11
SNS2K
SNS2
KEY 2
12
C
S2
C
S3
SNS3
10
9
R
SNS3
13
R
SNS1
SNS3K
KEY 3
KEY 4
SNS1K
SNS1
KEY 1
KEY 0
C
S1
14
15
8
C
S4
SNS4
R
SNS4
R
SNS0
SNS4K
7
6
SNS0K
SNS0
C
S0
16
17
SNS5
C
S5
AKS_0
R
SNS5
1M
VDD
VDD / VSS
SNS5K
KEY 5
KEY 6
QT1103
32-QFN
18
19
Recommended Rb1, Rb2 Values
CS6
SNS6
With Spread-Spectrum
R
SNS6
SNS6K
Vdd Range
Rb1 Rb2
Rb1
2.8 ~ 2.99V 12K 27K
3.0 ~ 3.59V 12K 22K
3.6 ~ 5V 15K 27K
4
SMR
1M
OSC
Rb2
20
21
C
S7
SNS7
R
SNS7
No Spread-Spectrum
SNS7K
KEY 7
Vdd Range
Rb1 Rb2
Css
2.8 ~ 2.99V 15K
3.0 ~ 3.59V 18K
3.6 ~ 5V 20K
dni
dni
dni
25
26
1
C
S8
SNS8
SS
R
SNS8
SNS8K
KEY 8
KEY 9
dni = do not install
27
28
C
S9
SNS9
R
SNS9
SNS9K
100K
100K
100K
32
31
30
Vdd
Vdd
Vdd
RX
1W
2W DATA
DATA
2
/RST
RESET IN
LP IN
/CHANGE
/CHANGE
23
24
29
5
N.C.
N.C.
SYNC/LP
DETECT
DETECT OUT
VSS
22
Table 1.6
AKS Resistor Options
AKS_0
Vss
Vdd
AKS MODE
Off
On, global
FAST-DETECT
Enabled
Off
Table 1.7
Functions in Simplified
Mode
SYNC/LP pin
Max on-duration delay
Detect Pin
110ms LP function; sync not available
60 seconds
Push-pull, active high
Suggested regulator manufacturers:
•
•
•
Toko (XC6215 series)
Seiko (S817 series)
BCDSemi (AP2121 series)
Re Figures 1.1 and 1.2 check the following sections for the variable component values:
•
•
•
•
Section 3.3, page 12: Cs capacitors (C )
S
Section 3.4, page 12: Sample resistors (RSNS
Section 3.5, page 12: Voltage levels
Section 3.2, page 12: Css capacitor
)
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QT1103_3R0.03_0607
2.5.2 Sync Mode
2 Device Operation
Sync mode allows the designer to synchronize acquire bursts
to an external signal source, such as mains frequency
(50/60Hz), to suppress interference. It can also be used to
synchronize two QT parts which operate near each other, so
that they will not cross-interfere if two or more of the keys (or
associated wiring) of the two parts are near each other.
2.1 Reset and Startup Time
After a reset event, the device typically requires 260ms to
initialize, calibrate, and start operating normally. Keys will
work properly once all keys have been calibrated after reset.
The QT1103 does not have a brownout detector; its reset
input must be taken active (low) following power-up and when
Vdd falls below 2V.
The SYNC input is positive pulse triggered. Following each
rising edge the device will generate three acquire bursts in
C-A-B sequence.
Figure 2.1 Acquire Bursts in C-A-B Sequence
2.2 Option Resistors
The option resistors are read on power-up only. There are
two primary option mode configurations: full, and simplified.
SYNC
Full options mode: Seven 1Mꢀ option resistors are required
as shown in Figure 1.1. All seven resistors are mandatory.
Burst C
Burst A
Burst B
Simplified mode: A 1Mꢀ resistor should be connected from
SNS6K to SNS7. In simplified mode, only one additional 1Mꢀ
option resistor is required for the AKS feature (Figure 1.2).
Note that the presence and connection of option resistors will
influence the required values of Cs; this effect will be
especially noticeable if the Cs values are under 22nF. Cs
values should be adjusted for optimal sensitivity after the
option resistors are connected.
If the SYNC input does not change level for ~150ms, the
QT1103 will free-run, generating a continuous stream of
acquire bursts C-A-B-C-A-B-C-A-... . While the QT1103 is in
free-run operation, a rising edge on the SYNC input will
return the QT1103 to synchronised operation.
2.3 DETECT Pin
DETECT represents the functional logical-OR of all ten keys.
DETECT can be used to wake a battery-operated product
upon human touch.
Note that the SYNC input must remain at one level (high or
low) for >150µs to guarantee that the QT1103 will recognise
that level.
The output polarity and drive of DETECT are governed
according to Table 1.4, page 6, and Table 1.7, page 7.
2.5.3 Low Power (LP) Mode
LP mode allows the device to be switched between full speed
operation (14ms (normal mode) or 28ms (fast mode) typical
response time and normal power consumption), and Low
Power operation (low average power consumption but an
increased maximum response time) according to the needs
of the application. There are three maximum response time
settings for low power operation: 70ms, 110ms, and 190ms
nominal; the response time setting is determined by option
resistors SL_1 and SL_0 (see Table 1.5). Slower response
times result in a lower average power drain.
2.4 /CHANGE Pin
The /CHANGE pin can be used to tell the host that a change
in touch state has been detected (i.e. a key has been
touched or released), and that the host should read the new
key states over the serial interface. /CHANGE is pulled low
when a key state change has occurred.
/CHANGE is very useful to prevent transmissions with
duplicate data. If /CHANGE is not used, the host would need
to keep polling the QT1103 constantly, even if there are no
changes in touch. Upon detection of a key, /CHANGE will pull
low and stay low until the serial interface has been polled by
the host. /CHANGE will then be released and return high until
the next change of key state, either on or off, on any key
(Figures 2.6, 2.9).
Operation in low power mode is governed by the state of the
LP input and whether at least one key has a confirmed touch.
If the LP input is at a constant low level, then the QT1103 will
remain in full speed operation (14ms or 28ms typical
response time and normal power consumption), as in
Figure 2.2.
The /CHANGE pin is open-drain, and requires a ~100k
pull-up resistor to Vdd in order to function properly.
Figure 2.2 Full Speed Operation
2.5 SYNC/LP Pin
touch
2.5.1 Introduction
The SYNC / LP pin function is configured according to the
SL_0 and SL_1 resistor connections to either Vdd or Vss
(see Table 1.5).
LP pin
bursts
full speed operation
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QT1103_3R0.03_0607
If the LP input is at a constant high level, then the QT1103
will enter low power operation whenever it is not detecting a
If this is done the QT1103 automatically selects an optimized
LP operation, which gives a significantly lower power
touch. It will switch automatically to full speed operation while consumption than would be achieved if additional acquire
there is a touch, and revert to low power operation at the end
of the touch. This is shown in Figure 2.3.
bursts were used.
Optimized LP operation is identical to the standard LP
operation in all other ways; it is controlled as described
previously.
Figure 2.3 Low Power/Full Speed Operation
touch
e
2.6 AKS™ Function Pins
LP pin
bursts
The QT1103 features an adjacent key suppression (AKS™)
function with two modes. Option resistors act to set this
feature according to Tables 1.2 and 1.6. AKS can be
disabled, allowing any combination of keys to become active
at the same time. When operating, the modes are:
low power
full speed
low power
Global: The AKS function operates across all ten keys. This
means that only one key can be active at any one time.
While there is no touch, if the LP input is driven high then
low, the QT1103 will enter low power operation, as described
previously, and remain in low power operation when LP is
taken low. When there is a touch the QT1103 will switch
automatically to full speed operation. At the end of the touch
the choice of operation depends on the state of the LP input.
This is shown in Figures 2.4 and 2.5 - the first with the LP pin
being low at the end of the touch, and the second with the LP
pin being high at the end of the touch.
Groups: The AKS function operates among three groups of
keys: 0-1-4-5, 2-3-6-7, and 8-9. This means that up to three
keys can be active at any one time.
In Group mode, keys in one group have no AKS interaction
with keys in any other group.
Note that in Fast Detect mode, AKS can only be off.
2.7 MOD_0, MOD_1 Inputs
Figure 2.4 LP Pin Low at End of Touch
In full option mode, the MOD_0 and MOD_1 resistors are
used to set the 'Max On-Duration' recalibration timeouts. If a
key becomes stuck on for a lengthy duration of time, this
feature will cause an automatic recalibration event of that
specific key only once the specified on-time has been
exceeded. Settings of 10s, 60s, and infinite are available.
touch
LP pin
bursts
The Max On-Duration feature operates on a key-by-key
basis; when one key is stuck on, its recalibration has no
effect on other keys.
low power
full speed
The logic combination on the MOD option pins sets the
timeout delay; see Table 1.3.
Figure 2.5 LP Pin High at End of Touch
Simplified mode MOD timing: In simplified mode, the max
on-duration is fixed at 60s.
touch
e
2.8 Fast Detect Mode
LP pin
bursts
In many applications, it is desirable to sense touch at high
speed. Examples include scrolling ‘slider’ strips or ‘Off’
buttons. It is possible to place the device into a ‘Fast Detect’
mode that usually requires under 14ms (typical) to respond.
This is accomplished internally by setting the Detect
Integrator to only three counts, i.e. only three successive
detections are required to detect touch.
low power
full speed
low power
Note that the LP input must remain at one level (high or low)
for >150µs to guarantee that the QT1103 will recognise that
level.
In LP mode, ‘Fast’ detection will not speed up the initial delay
(which could be up to 190ms typical depending on the option
setting). However, once a key is detected the device is forced
back into normal speed mode. It will remain in this faster
mode until requested to return to LP mode.
Optimization of LP Mode
For low power consumption, when up to eight keys are
required, all keys should be connected to QT1103 channels
that are measured during acquire bursts A and B
(i.e. K0...K7).
When used in a ‘slider’ application, it is normally desirable to
run the keys without AKS.
In Fast mode the time required to process a key release is
reduced from three samples to two. Fast Detect mode can be
enabled as shown in Tables 1.2 and 1.6.
For the lowest possible power consumption, when up to four
keys are required, all keys should be connected to QT1103
channels that are measured during acquire burst B (i.e. K2,
K3, K6, K7).
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QT1103_3R0.03_0607
Depending on the timing of a 1W host transmission, the
QT1103 device may need to abort an acquisition burst, and
rerun it after the transmission is complete and a reply has
been sent. As a consequence, each host request can
potentially result in a small, unnoticeable increase in
detection delay.
2.9 Simplified Mode
A simplified operating mode which does not require the
majority of option resistors is available. This mode is set by
connecting a resistor labeled SMR between pins SNS6K and
SNS7 (see Figure 1.2).
In this mode there is only one option available - AKS enable
or disable. When AKS is disabled, Fast Detect mode is
enabled; when AKS is enabled, Fast Detect mode is off.
1W Connection: The 1W pin should be pulled high with a
resistor. When not in use it floats high, hence this causes no
increase in supply current.
During transmission from the host, the host may drive the 1W
line with either an open-drain or a push-pull driver. However,
if the host uses push-pull driving, it must release the 1W line
as soon as it is done with its stop bit so that there is no drive
conflict when the QT1103 sends its reply.
AKS in this mode is global only (i.e. operates across all
functioning keys).
The other option features are fixed as follows:
DETECT Pin: Push-pull, active high
SYNC/LP Function: LP mode, ~110ms response time
Max On-Duration: 60 seconds
If open-drain transmission is used by the host, the value of
the pull-up resistor should be optimized for the desired baud
rate: faster rates require a lower value of resistor to prevent
rise-time problems. A typical value for 19,200 baud might be
100kꢀ. An oscilloscope should be used to confirm that the
resistor is not causing excessive timing skew that might
cause bit errors.
See also Tables 1.6 and 1.7.
2.10 Unused Keys
Unused keys should be disabled by removing the
corresponding Cs and Rsns components and connecting
SNS pins as shown in the ‘Unused’ column of Table 1.1.
Unused keys are ignored and do not factor into the AKS
function (Section 2.6).
The QT1103 uses push-pull drive to transmit data out on the
1W line back to the host. When the stop bit level is
established, 1W is floated; for this reason, a pull-up resistor
should always be used on the 1W pin to prevent the signal
from drifting to an undefined state. A 100kꢀ pull-up resistor
on 1W is recommended, unless the host uses open-drain
drive to the QT1103, in which case a lower value may be
required (see prior paragraph).
2.11 Serial 1W Interface
2.11.1 Introduction
The 1W serial interface is an RS-232 based auto baud rate
serial asynchronous interface that requires only one wire
between the host MCU and the QT1103. The serial data are
extremely short and simple to interpret.
2.11.2 Basic 1W Operation
The basic sequence of 1W serial operation is shown in
Figure 2.6. The 1W line is bi-directional and must be pulled
high with a resistor to prevent a floating, undefined state (see
Section 2.11.1).
Auto baud rate detection takes place by having the host
device send a specific character to the QT1103, which allows
the QT1103 to set its baud rate to match that of the host.
One feature of this method is that the baud rate can be any
rate between 8,000 and 38,400 bits per second. Neither the
QT1103 nor the host device has to be accurate in their
transmission rates, i.e. crystal control is not required.
Oscillator Tolerance: While the auto baud rate detection
mechanism has a wide tolerance for oscillator error, the QT’s
oscillator should still not vary by more than
the recommended value. Beyond a 20 percent error,
±20 percent from
±
communications at either the lower or upper stated limits
could fail. The oscillator frequency can be checked with an
oscilloscope by probing the pulse width on the SNS lines
(see Section 3.1, page 11).
Host Request Byte: The host requests the key
state from the QT1103 by sending an ASCII "P"
character (ASCII decimal code 80, hex 0x50)
over the 1W line. The character is formatted
according to conventional RS-232:
Figure 2.6 Basic 1W Sequence
driven reply
from QT1103
request
from host
key state
change
(1 byte)
(2 bytes)*
8 data bits
no parity
1W
floating
floating
1 stop bit
baud rate: 8,000 - 38,400
floating
floating
/CHANGE
Figure 2.7 shows the bit pattern of the host
request byte (‘P’). The first bit labeled ‘S’ is the
start bit, the last ‘S’ is the stop bit. This bit pattern
should never be changed. The QT1103 will
respond at the same baud rate as the received
‘P’ character.
1 ~ 3 bit periods
*See Figure 2.8
Figure 2.7 1W UART Host Pattern
1W
(from host)
Serial bits
S 0 1 2 3 4 5 6 7 S
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QT1103_3R0.03_0607
After sending the ‘P’ character
the host must immediately
float the 1W signal to prevent
a drive conflict between the
host and the QT1103 (see
Figure 2.6). The delay from
the received stop bit to the
QT1103 driving the 1W pin is
in the range 1-3 bit periods,
so the host should float the
pin within one bit period to
prevent a drive conflict.
Figure 2.8 UART Response Pattern on 1W Pin
floating
floating
floating
1W
(from QT1103)
Serial bits
S 0 1 2 3 4 5 6 7 S
0 1 2 3 4 5
S 0 1 2 3 4 5 6 7 S
6 7 8 9 U U
Associated key #
* *
* *
(shown with keys 0, 2 and 7 detecting)
* Fixed bit values
U - Unused bits
Data Reply: Before sending a
reply, the QT1103 returns the /CHANGE signal to its inactive
(float-high) state.
•
Neither /CHANGE nor DETECT used. The host polls
the device regularly to obtain key status, with a
timeout in operation when awaiting the reply to each
‘P’ request. Not receiving a reply within the timeout
period only occurs when the part is sleeping, and
hence when no keys are active. Before triggering LP
mode the host should wait for all keys to become
inactive and then send an additional 'P' request to the
QT1103 to ensure /CHANGE is also inactive.
The QT1103 then replies by sending two eight-bit characters
to the host over the 1W line using the same baud rate as the
request. With no keys pressed, both reply bytes are ASCII
‘@’ (0x40) characters; any keys that are pressed at the time
of the reply result in their associated bits being set in the
reply. Figure 2.8 shows the reply bytes when keys 0, 2 and 7
are pressed - 0x45, 0x42, and the associations between keys
and bits in the reply.
2.11.4 2W Operation
1W operation, as described in Section 2.11.3, requires that
the host float the 1W line while awaiting a reply from the
QT1103; this is not always possible.
The QT1103 floats the 1W pin again after establishing the
level of the stop bit.
2.11.3 LP Mode Effects on 1W
To solve this problem, the QT1103 can also receive the ‘P’
character from the host on its ‘Rx’ pin separately from the 1W
pin (Figure 2.9). The host need not float the Rx line since the
QT1103 will never try to drive it.
The use of low power (LP) mode presents some additional
1W timing requirements. In LP mode (Section 2.5), the
QT1103 will only respond to a request from the host when it
is making one of its infrequent checks for a key press. Hence,
in that condition most requests from the host to the QT1103
will be ignored, since the QT1103 will be sleeping and
unresponsive. However, if either /CHANGE or DETECT are
active the QT1103 will be at full speed, and hence will always
respond to ‘P’ requests.
Following a ‘P’ on Rx, the QT1103 will send the same
response pattern (Figure 2.8) over the 1W line as in pure 1W
mode.
All other comments and timings given for 1W operation are
applicable for 2W operation. LP operation is the same for 2W
mode as for 1W.
Note that when sleeping in LP mode, there are by definition
no keys active, so there should not be a reason for the host
to send the ‘P’ query command in the first place.
If the Rx pin is not used, it must be tied to Vdd.
Three strategies are available to the host to ensure that LP
mode operates correctly:
3 Design Notes
3.1 Oscillator Frequency
The QT1103’s internal oscillator runs from an external
network connected to the OSC and SS pins as shown in
Figures 1.1 and 1.2. The charts in these figures show the
recommended values to use depending on nominal operating
voltage and spread spectrum mode.
•
/CHANGE used. The host monitors /CHANGE, and
only sends a ‘P’ request when it is low. The part is
awake by definition when /CHANGE is low. If
/CHANGE is high, key states are known to be
unchanged since the last reply received from the
QT1103, and so additional ‘P’ requests are not
needed. Before triggering LP mode the host should
wait for /CHANGE to go high after all keys have
become inactive.
If spread spectrum mode is not used, only resistor Rb1
should be used, the Css capacitor eliminated, and the SS pin
pulled to Vss with a 100k resistor.
•
DETECT used. The host
monitors DETECT, and if it is
active (i.e. the part is awake) it
polls the device regularly to
obtain key status. When
DETECT is inactive (the part
may be sleeping) no requests
Figure 2.9 2W Operation
driven reply
(from QT1103)
(2 bytes)
request
from host
(1 byte)
key state
change
are sent because it is known
RX
that no keys are active. Before
triggering LP mode the host
should wait for DETECT to
become inactive, and then
send one additional 'P' request
to ensure /CHANGE is also
made inactive.
(from host)
1W
(from QT1103)
floating
floating
floating
floating
/CHANGE
1 ~ 3 bit periods
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QT1103_3R0.03_0607
An out-of-spec oscillator can induce timing problems such as
large variations in Max On-Duration times and response
times as well as the serial port baud rate range.
•
•
More stray capacitance on an electrode or sense
trace will decrease sensitivity on the corresponding
key; Cs will have to be increased to compensate.
Effect on serial communications: The oscillator frequency
has no nominal effect on serial communications since the
baud rate is set by an auto-sensing mechanism. However, if
the oscillator is too far outside the recommended settings,
the possible range of serial communications will shrink. For
example, if the oscillator is too slow, the upper baud rate will
be reduced.
An option resistor pulling low will increase sensitivity
on the corresponding key; Cs will have to be reduced
to compensate.
The Cs capacitors can be virtually any plastic film or low to
medium-K ceramic capacitor. Acceptable capacitor types for
most uses include PPS film, polypropylene film, and NP0 and
X5R / X7R ceramics. Lower grades than X5R / X7R are not
advised.
The oscillator frequency can be verified by measuring the
burst pulses at the start of a burst.
For most applications Cs will be in the range 680pF to 50nF;
larger values of Cs require better quality capacitors to ensure
reliable sensing. In a few applications sufficient sensitivity will
be achieved with Cs less than 680pF.
•
In spread-spectrum mode, the first pulses of a burst
should ideally be 2.87µs
•
In non spread-spectrum mode, the target value is
2.67µs
If very high sensitivity is required then the 50nF value may be
exceeded hence the 100nF maximum in Section 4.2,
page 13; in this case greater care should be taken over the
QT1103 circuit layout and interactions with neighboring
electronics.
If in doubt, make the pulses on the narrower side (i.e. a faster
oscillator) when using the higher baud rates, and conversely
on the wider side when using the lowest baud rates.
As the sensitivity of the keys, and hence the required values
of Cs, are affected by the presence and connection of the
option resistors (see Section 2.2, page 9), then final selection
of Cs values should take place after the options choice has
been finalized.
3.2 Spread-spectrum Circuit
The QT1103 offers the ability to spectrally spread its
frequency of operation to heavily reduce susceptibility to
external noise sources and to limit RF emissions. The SS pin
is used to modulate an external passive RC network that
modulates the OSC pin. OSC is the main oscillator current
input. The circuits and recommended values are shown in
Figures 1.1 and 1.2.
3.4 Rsns Resistors
Series resistors RSNS (RSNS0...RSNS9) are in line with the
electrode connections and should be used to limit
electrostatic discharge (ESD) currents and to suppress radio
frequency interference (RFI). For most applications RSNS will
be in the range 4.7kꢀ to 33kꢀ each. In a few applications
with low loading on the sense keys the value may be up to
100kꢀ.
The resistors Rb1 and Rb2 should be changed depending on
Vdd. As shown in Figures 1.1 and 1.2, three sets of values
are recommended for these resistors depending on Vdd. The
power curves in Section 4.6 also show the effect of these
resistors.
The circuit can be eliminated, if it is not desired, by using a
resistor from OSC to VDD to drive the oscillator, and
connecting SS to Vss with a 100kΩ resistor (see Section 3.1).
Although these resistors may be omitted, the device may
become susceptible to external noise or RFI. For details of
how to select these resistors see the Application Note
AN-KD02, downloadable from the Quantum website
http://www.qprox.com (go to the Support tab and click
Application Notes).
The spread-spectrum RC network might need to be modified
slightly with longer burst lengths. The sawtooth waveform
observed on SS should reach a crest height as follows:
•
•
Vdd >= 3.6V: 17 percent of Vdd
Vdd < 3.6V: 20 percent of Vdd
3.5 Power Supply
The power supply can range from 2.8V to 5.0V. If this
fluctuates slowly with temperature, the device will track and
compensate for these changes automatically with only minor
changes in sensitivity. If the supply voltage drifts or shifts
quickly, the drift compensation mechanism will not be able to
keep up, causing sensitivity anomalies or false detections.
The Css capacitor connected to SS (Figures 1.1 and 1.2)
should be adjusted so that the waveform approximates the
above amplitude, ±10 percent, during normal operation in the
target circuit. Where the bursts are of differing lengths, the
adjustment should be done for the longer burst. If this is
done, the circuit will give a spectral modulation of 12-15
percent. A typical value of Css is 100nF.
The power supply should be locally regulated using a
three-terminal device, to between 2.8V and 5.0V. If the
supply is shared with another electronic system, care should
be taken to ensure that the supply is free of digital spikes,
sags, and surges which can cause adverse effects. It is not
recommended to include a series inductor in the power
supply to the QT1103.
3.3 Cs Sample Capacitors - Sensitivity
The Cs sample capacitors accumulate the charge from the
key electrodes and hence determine sensitivity. The values
of Cs can differ for each channel, permitting differences in
sensitivity from key to key or to balance unequal sensitivities.
Higher values of Cs make the corresponding key more
sensitive.
For proper operation a 0.1µF or greater bypass capacitor
must be used between Vdd and Vss. The bypass capacitor
should be routed with very short tracks to the device’s Vss
and Vdd pins.
Unequal sensitivities can occur due to key size and
placement differences, stray wiring capacitances, and option
resistor connection.
3.6 PCB Layout and Construction
Refer to Quantum application note AN-KD02 for information
related to layout and construction matters.
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4 Specifications
4.1 Absolute Maximum Specifications
Operating temperature, Ta. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40o ~ +85oC
Storage temp, Ts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50o ~ +125oC
Vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 ~ +6.0V
Max continuous pin current, any control or drive pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA
Short circuit duration to ground or Vdd, any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . infinite
Voltage forced onto any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V ~ (Vdd + 0.3) Volts
4.2 Recommended Operating Conditions
Operating temperature, Ta. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40o ~ +85oC
V
DD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.8 ~ +5.0V
Short-term supply ripple+noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5mV/s
Long-term supply stability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100mV
Cs range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [100nF
Cx range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 ~ 50pF
4.3 AC Specifications
Vdd = 5.0V, Ta = recommended, Cx = 5pF, Cs = 4.7nF; circuit of Figure 1.1
Parameter Description
Min
Typ
Max
Units
ms
Notes
Trc
Fc
Recalibration time
150
132
15
Burst center frequency
Burst modulation, percent
Sample pulse duration
kHz
%
Fm
Tpc
Total deviation
µs
Pulses appear 33 percent longer
when viewed on an oscilloscope.
2
Tsu
Tbd
Tdtf
Tdtn
Tdtl
Tdrf
Tdrn
Tres
bps
Startup time from cold start
Burst duration
ms
ms
ms
ms
ms
ms
ms
µs
260
2.5
14
All three bursts
Response time - Fast mode
Response time - Normal mode
Response time - LP mode
Release time - Fast mode
Release time - Normal mode
External reset low pulse width
Serial communications speed
28
110ms LP setting
End of touch
110
10
End of touch
14
1
8,000
38,400
baud
4.4 DC Specifications
Vdd = 5.0V, Ta = recommended, Cx = 5pF, Cs = 4.7nF, Ta = recommended range; circuit of Figure 1.1 unless noted
Parameter Description
Min
Typ
Max
Units
Notes
4.2
2.5
1.8
1.4
8
mA
@ VDD = 5.0
@ VDD = 4.0
@ VDD = 3.3
@ VDD = 2.8
Average supply current,
normal mode*
Iddn
Iddl
Average supply current,
LP mode*
22
15
@ VDD = 3.3V; 190ms LP mode
@ VDD = 2.8V; 190ms LP mode
µA
µA
Average supply current, LP
mode
48
34
@ VDD = 3.3V
@ VDD = 2.8V
Average supply current, LP
mode, keys on bursts A and B
only
36
24
@ VDD = 3.3V
@ VDD = 2.8V
µA
µA
Average supply current,
LP mode, keys on burst B only
20
14
@ VDD = 3.3V
@ VDD = 2.8V
Vdds
Vil
Average supply turn-on slope
Low input logic level
High input logic level
Low output voltage
100
V/s
V
0.7
0.5
±1
Vhl
Vol
Voh
Iil
3.5
V
V
7mA sink
High output voltage
Vdd-0.5
V
2.5mA source
Input leakage current
Acquisition resolution
µA
bits
Ar
8
*No spread spectrum circuit
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QT1103_3R0.03_0607
4.5 Signal Processing
Vdd = 5.0V, Ta = recommended, Cx = 5pF, Cs = 4.7nF, 2µs QT Pulses
Description
Value
Units
Notes
Detection threshold
10
counts
counts
counts
secs
Threshold for increase in Cx load
Detection hysteresis
2
Anti-detection threshold
6
Threshold for decrease of Cx load
Time to recalibrate if Cx load has exceeded anti-detection threshold
Must be consecutive or detection fails
Must be consecutive or detection fails
Option pin selected
Anti-detection recalibration delay
Detect Integrator filter, normal mode
Detect Integrator filter, Fast mode
Max On-Duration
2
6
3
samples
samples
secs
10, 60, inf
2,000
500
Normal drift compensation rate
Anti drift compensation rate
ms/level
ms/level
Towards increasing Cx load
Towards decreasing Cx load
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QT1103_3R0.03_0607
4.6 Idd Curves
All Idd curves are average values, under the following conditions: Cx = 5pF, Cs = 4.7nF, Ta = 20oC; no spread-spectrum
circuit. Refer to page 9 for more information about optimization of LP modes.
QT1103, average Idd (full speed operation)
5.0
4.0
Vdd=5V
3.0
Vdd=4V
Vdd=3.3V
2.0
Vdd=2.8V
1.0
0.0
0
1
2
3
4
5
6
burst length (ms)
Full speed operation
Low Power operation (optimized - only burst B in use)
QT1103, average Idd (70ms optimized LP operation)
1500.0
QT1103, average Idd (110ms optimized LP
operation)
1000.0
800.0
600.0
400.0
200.0
0.0
1250.0
Vdd=5V
Vdd=5V
1000.0
750.0
500.0
250.0
0.0
Vdd=4V
Vdd=4V
Vdd=3.3V
Vdd=2.8V
Vdd=3.3V
Vdd=2.8V
0
1
2
3
4
5
6
0
1
2
3
4
5
6
burst length (ms)
burst length (ms)
QT1103, average Idd (190ms optimized LP
operation)
500.0
400.0
300.0
200.0
100.0
0.0
Vdd=5V
Vdd=4V
Vdd=3.3V
Vdd=2.8V
0
1
2
3
4
5
6
burst length (ms)
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15
QT1103_3R0.03_0607
Low Power operation (optimized - only burst A and B in use)
QT1103, average Idd (110ms optimized LP
operation)
QT1103, average Idd (70ms optimized LP operation)
1500.0
1000.0
800.0
600.0
400.0
200.0
0.0
1250.0
Vdd=5V
Vdd=5V
1000.0
750.0
500.0
250.0
0.0
Vdd=4V
Vdd=4V
Vdd=3.3V
Vdd=2.8V
Vdd=3.3V
Vdd=2.8V
0
1
2
3
4
5
6
0
1
2
3
4
5
6
burst length (ms)
burst length (ms)
QT1103, average Idd (190ms optimized LP
operation)
500.0
400.0
300.0
200.0
100.0
0.0
Vdd=5V
Vdd=4V
Vdd=3.3V
Vdd=2.8V
0
1
2
3
4
5
6
burst length (ms)
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QT1103_3R0.03_0607
Low Power operation (non-optimized)
QT1103, average Idd (70ms LP operation)
QT1103, average Idd (110ms LP operation)
1500.0
1000.0
800.0
600.0
400.0
200.0
0.0
1250.0
1000.0
750.0
500.0
250.0
0.0
Vdd=5V
Vdd=5V
Vdd=4V
Vdd=4V
Vdd=3.3V
Vdd=2.8V
Vdd=3.3V
Vdd=2.8V
0
1
2
3
4
5
6
0
1
2
3
4
5
6
burst length (ms)
burst length (ms)
QT1103, average Idd (190ms LP operation)
500.0
400.0
300.0
200.0
100.0
0.0
Vdd=5V
Vdd=4V
Vdd=3.3V
Vdd=2.8V
0
1
2
3
4
5
6
burst length (ms)
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QT1103_3R0.03_0607
4.7 LP Mode Typical Response Times
Response Time vs Vdd - 70ms Setting
Response Time vs Vdd - 110ms Setting
90
140
130
120
110
100
90
85
80
75
70
65
60
80
2.5
3
3.5
4
4.5
5
5.5
2.50
3.00
3.50
4.00
4.50
5.00
5.50
Vdd
Vdd
Response Time vs Vdd - 190ms Setting
240
230
220
210
200
190
180
170
160
150
2.50
3.00
3.50
4.00
4.50
5.00
5.50
Vdd
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QT1103_3R0.03_0607
4.8 Mechanical Dimensions
Dimensions In Millimeters
Symbol Minimum Nominal Maximum
A
A1
b
C
D
D2
E
E2
e
L
y
0.70
0.00
0.18
-
4.90
3.05
4.90
3.05
-
-
0.02
0.25
0.20 REF
5.00
-
5.00
-
0.50
0.40
-
0.95
0.05
0.32
-
5.10
3.65
5.10
3.65
-
0.30
0.00
0.50
0.075
Note: that there is no functional requirement for the large pad on the underside of the 32-QFN
package to be soldered to the substrate. If the final application does require this area to be soldered
for mechanical reasons, the pad(s) to which it is soldered to must be isolated and contained under the
32-QFN footprint only.
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QT1103_3R0.03_0607
4.9 Part Marking
QRG Part
Number
QT1103
QRG Revision
Code
©QRG 3
YYWWG
run nr.
‘YY’ = Year of manufacture
‘WW’ = Week of manufacture
‘G’ = Green/RoHS Compliant
Pin 1
Identification
'run nr.' = 6 Digit Run Number
4.10 Moisture Sensitivity Level (MSL)
MSL Rating
Peak Body Temperature
Specifications
IPC/JEDEC J-STD-020C
MSL3
260OC
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QT1103_3R0.03_0607
5 Datasheet Control
5.1 Changes
Changes this issue (datasheet issue 03)
Front page.
5.2 Numbering Convention
Part Number
Datasheet Issue Number
QT1103_MXN.nn_mmyy
Chip Revision
Datasheet Release Date;
(Where mm = Month, yy = Year)
(Where M= Major chip revision,
N = Minor chip revision,
X = Prereleased Product
[or R = Released Product])
A minor chip revision (N) is defined as a revision change which does not affect product functionality or datasheet.
The value of N is only stated for released parts (R).
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QT1103_3R0.03_0607
LQ
Copyright © 2006-2007 QRG Ltd. All rights reserved.
Patented and patents pending
Corporate Headquarters
1 Mitchell Point
Ensign Way, Hamble SO31 4RF
Great Britain
Tel: +44 (0)23 8056 5600 Fax: +44 (0)23 8045 3939
www.qprox.com
North America
651 Holiday Drive Bldg. 5 / 300
Pittsburgh, PA 15220 USA
Tel: 412-391-7367 Fax: 412-291-1015
The specifications set out in this document are subject to change without notice. All products sold and services supplied by QRG are
subject to QRG’s Terms and Conditions of sale and services. QRG patents, trademarks and Terms and Conditions can be found online at
http://www.qprox.com/about/legal.php. Numerous further patents are pending, one or more which may apply to this device or the
applications thereof.
QRG products are not suitable for medical (including lifesaving equipment), safety or mission critical applications or other similar
purposes. Except as expressly set out in QRG's Terms and Conditions, no licenses to patents or other intellectual property of QRG
(express or implied) are granted by QRG in connection with the sale of QRG products or provision of services. QRG will not be liable for
customer product design and customers are entirely responsible for their products and applications which incorporate QRG's products.
Development Team: John Dubery, Alan Bowens, Matthew Trend
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