HYS72T64400HFD-3S-B [QIMONDA]
240-Pin Fully-Buffered DDR2 SDRAM Modules; 240针全缓冲DDR2 SDRAM模组型号: | HYS72T64400HFD-3S-B |
厂家: | QIMONDA AG |
描述: | 240-Pin Fully-Buffered DDR2 SDRAM Modules |
文件: | 总43页 (文件大小:2219K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
February 2007
Cover Page
HYS72T64[4/5]00HFD–3S–B
HYS72T128[4/5]20HFD–3S–B
HYS72T256[4/5]20HFD–3S–B
240-Pin Fully-Buffered DDR2 SDRAM Modules
DDR2 SDRAM
RoHS Compliant Products
Internet Data Sheet
Rev. 1.2
Internet Data Sheet
HYS72T[64/128/256][4/5][00/20]HFD–3S–B
Revision History
Revision History: 2007-02-09, Rev. 1.2
All
Adapted internet edition
Updated “Ordering Information (Pb-free components and assembly)” on Page 4
Page 4
Previous Revision: 2006-08-18, Rev. 1.1
Page 20
Updated “Current Spec. and Conditions” on Page 20
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09142006-Q5TN-B9NE
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Internet Data Sheet
HYS72T[64/128/256][4/5][00/20]HFD–3S–B
1
Overview
This chapter describes the main characteristics of the 240-Pin Fully-Buffered DDR2 SDRAM Modules product family.
1.1
Features
•
•
•
240-pin Fully-Buffered ECC Dual-In-Line
DDR2 SDRAM Module for PC, Workstation and Server
main memory applications.
Module organisation one rank 64M × 72,
one rank 128M × 72, two ranks 128M × 72,
two ranks 256M ×72
JEDEC Standard Double Data Rate 2
Synchronous DRAMs (DDR2 SDRAMs) with 1.8 V
(± 0.1 V) power supply.
•
Detects errors on the channel and reports them to the host
memory controller.
Automatic DDR2 DRAM Bus Calibration.
Automatic Channel Calibration.
•
•
•
•
•
•
•
•
•
Full Host Control of the DDR2 DRAMs.
Over-Temperature Detection and Alert.
Hot Add-on and Hot Remove Capability.
MBIST and IBIST Test Functions.
Transparent Mode for DRAM Test Support.
Low profile: 133.35mm x 30.35 mm
240 Pin gold plated card connector with 1.00 mm contact
centers (JEDEC standard pending).
Based on JEDEC standard reference card designs (Jedec
standard pending).
•
•
•
•
•
Built with 512Mb DDR2 SDRAMs in 60-ball FBGA
Chipsize Packages.
Re-drive and re-sync of all address, command, clock and
data signals using AMB (Advanced Memory Buffer).
High-Speed Differential Point-to-Point Link Interface at
1.5 V (Jedec standard pending).
Host Interface and AMB component industry standard
compliant.
•
•
•
SPD (Serial Presence Detect) with 256 Byte serial
E2PROM.Performance:
RoHS Compliant Products1)
Supports SMBus protocol interface for access to the AMB
configuration registers.
TABLE 1
Performance for DDR2–667
Product Type Speed Code
Speed Grade
–3S
Unit
PC2–5300 5–5–5
—
max. Clock Frequency
@CL5
@CL4
@CL3
fCK5
fCK4
fCK3
tRCD
tRP
333
266
200
15
MHz
MHz
MHz
ns
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
15
ns
tRAS
tRC
45
ns
60
ns
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
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1.2
Description
This document describes the electrical and mechanical
features of a 240-pin, PC2-5300F ECC type, Fully Buffered
Double-Data-Rate Two Synchronous DRAM Dual In-Line
Memory Modules (DDR2 SDRAM FB-DIMMs). Fully Buffered
DIMMs use commodity DRAMs isolated from the memory
channel behind a buffer on the DIMM. They are intended for
use as main memory when installed in systems such as
servers and workstations. PC2-5300 refers to the DIMM
naming convention indicating the DDR2 SDRAMs running at
333 MHz clock speed and offering 5300 MB/s peak
bandwidth. FB-DIMM features a novel architecture including
the Advanced Memory Buffer. This single chip component,
located in the center of each DIMM, acts as a repeater and
buffer for all signals and commands which are exchanged
between the host controller and the DDR2 SDRAMs including
data in- and output. The AMB communicates with the host
controller and / or the adjacent DIMMs on a system board
using an Industry Standard High-Speed Differential Point-to-
Point Link Interface at 1.5 V.
The Advanced Memory Buffer also allows buffering of
memory traffic to support large memory capacities. All
memory control for the DRAM resides in the host, including
memory request initiation, timing, refresh, scrubbing, sparing,
configuration access, and power management. The
Advanced Memory Buffer interface is responsible for handling
channel and memory requests to and from the local DIMM
and for forwarding requests to other DIMMs on the memory
channel. Fully Buffered DIMM provides a high memory
bandwidth, large capacity channel solution that has a narrow
host interface. The maximum memory capacity is 288 DDR2
SDRAM devices per channel or 8 DIMMs.
TABLE 2
Ordering Information (Pb-free components and assembly)
Product Type1)
Compliance Code2)
Description
SDRAM Technology
PC2-5300F (DDR2-667):
HYS72T64400HFD–3S–B
HYS72T64500HFD–3S–B
HYS72T128420HFD–3S–B
HYS72T128520HFD–3S–B
HYS72T256420HFD–3S–B
HYS72T256520HFD–3S–B
512MB 1Rx8 PC2–4200F–444–11–A
512MB 1Rx8 PC2–4200F–444–11–A
1GB 2Rx8 PC2–4200F–444–11–B
1GB 2Rx8 PC2–4200F–444–11–B
2GB 2Rx4 PC2–4200F–444–11–H
2GB 2Rx4 PC2–4200F–444–11–H
1 Rank, FB-DIMM
1 Rank, FB-DIMM
2 Ranks, FB-DIMM
2 Ranks, FB-DIMM
2 Ranks, FB-DIMM
2 Ranks, FB-DIMM
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×4)
512 Mbit (×4)
1) All product types end with a place code, designating the silicon die revision. Example: HYS 72T64000HFA-3.7-A, indicating Rev. A dice
are used for DDR2 SDRAM components. To learn more on QIMONDA DDR2 module and component nomenclature see Chapter 8 of this
datasheet.
2) The Compliance Code is printed on the module label and describes the speed grade, e.g. “PC2-4200F-444-11-A”, where 4200F means
Fully Buffered DIMM with 4.26 GB/sec. Module Bandwidth and “444-11” means CAS latency = 4, trcd latency = 4 and trp latency = 4 using
JEDEC SPD Revision 1.1 and assembled on Raw Card “A”.
TABLE 3
Address Format
DIMM
Density
Module
Organization
Memory
Ranks
ECC/
Non-ECC
# of
SDRAMs
# of row/bank/columns bits
Raw
Card
512 MB
1 GB
64M ×72
128M ×72
256M ×72
1
2
2
ECC
ECC
ECC
9
13/2/10
13/2/10
13/2/11
A
B
H
18
36
2 GB
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TABLE 4
Components on Modules
Product Type
DRAM components1)
DRAM Density
DRAM Organisation
Note2)
HYS72T64000HF
HYS72T128020HF
HYB18T512800BF
HYB18T512800BF
HYB18T512400BF
512 Mbit
512 Mbit
512 Mbit
64M ×8
64M ×8
128M ×4
HYS72T256020HF
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component datasheet.
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2
Pin Configuration
The pin configuration of the DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations used in columns
Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1.
TABLE 5
Pin Configuration of FB-DIMM
Pin#
Name
Pin
Type
Buffer
Type
Function
Clock Signals
228
SCK
SCK
I
I
HSDL_15
HSDL_15
System Clock Input, positive line
System Clock Input, negative line
229
Control Signals
17
RESET
I
LV-CMOS
AMB reset signal
Northbound
22
25
28
31
34
37
51
54
57
60
63
66
48
40
23
26
29
32
35
38
52
55
58
61
64
PN0
PN1
PN2
PN3
PN4
PN5
PN6
PN7
PN8
PN9
PN10
PN11
PN12
PN13
PN0
PN1
PN2
PN3
PN4
PN5
PN6
PN7
PN8
PN9
PN10
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
Primary Northbound Data, positive lines
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Pin#
Name
Pin
Type
Buffer
Type
Function
67
PN11
PN12
PN13
SN0
O
O
O
I
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
49
41
142
145
148
151
154
157
171
174
177
180
183
186
168
160
143
146
149
152
155
158
172
175
178
181
184
187
169
161
Southbound
70
Secondary Northbound Data, positive
lines
SN1
I
SN2
I
SN3
I
SN4
I
SN5
I
SN6
I
SN7
I
SN8
I
SN9
I
SN10
SN11
SN12
SN13
SN0
I
I
I
I
I
SN1
I
SN2
I
SN3
I
SN4
I
SN5
I
SN6
I
SN7
I
SN8
I
SN9
I
SN10
SN11
SN12
SN13
I
I
I
I
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
I
I
I
I
I
I
I
I
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
Primary Southbound Data, positive lines
73
76
79
82
93
96
99
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Pin#
Name
Pin
Type
Buffer
Type
Function
102
90
PS8
PS9
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
SS0
SS1
SS2
SS3
SS4
SS5
SS6
SS7
SS8
SS9
SS0
SS1
SS2
SS3
SS4
SS5
SS6
SS7
SS8
SS9
I
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
HSDL_15
I
71
I
Primary Southbound Data, negative lines
74
I
77
I
80
I
83
I
94
I
97
I
100
103
91
I
I
I
190
193
196
199
202
213
216
219
222
210
191
194
197
200
203
214
217
220
223
211
EEPROM
120
119
239
240
118
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Secondary Southbound data, positive
lines
Secondary Southbound data, negative
lines
SCL
SDA
SA0
SA1
SA2
I
CMOS
OD
Serial Bus Clock
I/O
Serial Bus Data
I
I
I
CMOS
CMOS
CMOS
Serial Address Select Bus 2:0
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Pin#
Name
Pin
Type
Buffer
Type
Function
Power Supplies
238
VDDSPD
VCC
PWR
PWR
—
—
EEPROM Power Supply
9,10,12,13,129,130,132,133
AMB Core Power / Channel Interface
Power
15,117,135,237
VTT
PWR
PWR
—
—
Address/Command/Clock Termination
Power
1,2,3,5,6,7,108,109,111,112,113,
115,116,121,122,123,125,126,
127,231,232,233,235,236
VDD
Power Supply
4,8,11,14,18,21,24,27,30,33,36,
39,42,43,46,47,50,53,56,59,62,
65,68,69,72,75,78,81,84,85,88,
89,92,95,98,101,104,107,110,
114,124,128,131,134,138,141,
144,147,150,153,156,159,162,
163,166,167,170,173,176,179,
182,185,188,189,192,195,198,
201,204,205,208,209,212,215,
218,221,224,227,230,234
VSS
GND
—
Ground Plane
Other Pins
19,20,44,45,86,87,105,106,139,
140,164,165,206,207,225,226
RFU
NC
—
Not connected
Voltage ID
136
16
VID0
VID1
Test
—
—
AI
—
—
—
137
VREF
TABLE 6
Abbreviations for Buffer Type
Abbreviation
Description
HSDL_15
LV-CMOS
CMOS
High-Speed Differential Point-to-Point Link Interface at 1.5 V
Low Voltage CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate,
and allows multiple devices to share as a wire-OR.
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TABLE 7
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
Output. Digital levels.
O
I/O
AI
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
PWR
GND
NU
NC
Ground
Not Usable
Not Connected
Rev. 1.2, 2006-02
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09142006-Q5TN-B9NE
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Internet Data Sheet
HYS72T[64/128/256][4/5][00/20]HFD–3S–B
FIGURE 1
Pin Configuration for FB-DIMM (240 pin)
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Rev. 1.2, 2006-02
09142006-Q5TN-B9NE
11
Internet Data Sheet
HYS72T[64/128/256][4/5][00/20]HFD–3S–B
3
Basic Functionality
The Advanced Memory Buffer (AMB) reference design complies with the FB-DIMM Architecture and Protocol Specification.
3.1
Advanced Memory Buffer Functionality
The Advanced Memory Buffer will perform the following FB-
DIMM channel functions:
•
•
•
Detects errors on the channel and reports them to the host
memory controller.
Support the FB-DIMM configuration register set as defined
in the register chapters.
Acts as DRAM memory buffer for all read, write, and
configuration accesses addressed to the DIMM.
Provides a read buffer FIFO and a write buffer FIFO.
Supports an SMBus protocol interface for access to the
AMB configuration registers.
Provides logic to support MEMBIST and IBIST Design for
Test functions.
Provides a register interface for the thermal sensor and
status indicator.
Functions as a repeater to extend the maximum length of
FB-DIMM Links.
•
Supports channel initialization procedures as defined in
the initialization chapter of the FB-DIMM Architecture and
Protocol Specification to align the clocks and the frame
boundaries, verify channel connectivity, and identify AMB
DIMM position.
•
•
•
•
Supports the forwarding of southbound and northbound
frames, servicing requests directed to a specific AMB or
DIMM, as defined in the protocol chapter, and merging the
return data into the northbound frames.
If the AMB resides on the last DIMM in the channel, the
AMB initializes northbound frames.
•
•
•
Transparent Mode for DRAM Test Support
In this mode, the Advanced Memory Buffer will provide lower
speed tester access to DRAM pins through the FB-DIMM I/O
pins. This allows the tester to send an arbitrary test pattern to
the DRAMs. Transparent mode only supports a maximum
DRAM frequency equivalent to DDR2 400. Transparent mode
functionality:
•
Reconfigures FB-DIMM inputs from differential high speed
link receivers to two single ended lower speed receivers
(~200 MHz)
These inputs directly control DDR2 Command/Address
and input data that is replicated to all DRAMs
Uses low speed direct drive FB-DIMM outputs to bypass
high speed Parallel/Serial circuitry and provide test results
back to tester
•
•
DDR2 SDRAM Interface
•
•
Supports DDR2 at speeds of 667MT/s
Supports 256Mb, 512Mb and 1Gb devices in x4 and x8
configurations
•
72-bit DDR2 SDRAM memory array
Rev. 1.2, 2006-02
12
09142006-Q5TN-B9NE
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Internet Data Sheet
HYS72T[64/128/256][4/5][00/20]HFD–3S–B
3.2
Interfaces
Figure 2 illustrates the Advanced Memory Buffer and all of its
interfaces. They consist of two FB-DIMM links, one DDR2
channel and an SMBus interface. Each FB-DIMM link
connects the Advanced Memory Buffer to a host memory
controller or an adjacent FB-DIMM. The DDR2 channel
supports direct connection to the DDR2 SDRAMs on a Fully
Buffered DIMM.
FIGURE 2
Block Diagram Advanced Memory Buffer Interface
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Interface Topology
The FB-DIMM channel uses a daisy-chain topology to provide
expansion from a single DIMM per channel to up to 8 DIMMs
per channel. The host sends data on the southbound link to
the first DIMM where it is received and redriven to the second
DIMM. On the southbound data path each DIMM receives the
data and again re-drives the data to the next DIMM until the
last DIMM receives the data. The last DIMM in the chain
initiates the transmission of data in the direction of the host
(a.k.a. northbound). On the northbound data path each DIMM
receives the data and re-drives the data to the next DIMM
until the host is reached.
Rev. 1.2, 2006-02
13
09142006-Q5TN-B9NE
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Internet Data Sheet
HYS72T[64/128/256][4/5][00/20]HFD–3S–B
FIGURE 3
Block Diagram of Channel Southbound and Northbound Paths
+RVWꢁ
Rev. 1.2, 2006-02
14
09142006-Q5TN-B9NE
Internet Data Sheet
HYS72T[64/128/256][4/5][00/20]HFD–3S–B
3.3
High-Speed Differential Point-to-Point Link (at 1.5 V)
Interfaces
The Advanced Memory Buffer supports one FB-DIMM
Channel consisting of two bidirectional link interfaces using
highspeed differential point-to-point electrical signaling. The
southbound input link is 10 lanes wide and carries commands
and write data from the host memory controller or the
adjacent DIMM in the host direction. The southbound output
link forwards this same data to the next FB-DIMM. The
northbound input link is 14 lanes wide and carries read return
data or status information from the next FB-DIMM in the chain
back towards the host. The northbound output link forwards
this information back towards the host and multiplexes in any
read return data or status information that is generated
internally. Data and commands sent to the DRAMs travel
southbound on 10 primary differential signal line pairs. Data
received from the DRAMs and status information travel
northbound on 14 primary differential pairs. Data and
commands sent to the adjacent DIMM upstream are repeated
and travel further southbound on 10 secondary differential
pairs. Data and status information received from the adjacent
DIMM upstream travel further northbound on 14 secondary
differential pairs.
3.3.1
DDR2 Channel
The DDR2 channel on the Advanced Memory Buffer supports
direct connection to DDR2 SDRAMs. The DDR2 channel
supports two ranks of eight banks with 16 row/column
request, 64 data, and eight check-bit signals. There are two
copies of address and command signals to support DIMM
routing and electrical requirements. Four transfer bursts are
driven on the data and check-bit lines at 800 MHz.
Propagation delays between read data/check-bit strobe lanes
on a given channel can differ. Each strobe can be calibrated
by hardware state machines using write/read trial and error.
Hardware aligns the read data and check-bits to a single core
clock. The Advanced Memory Buffer provides four copies of
the command clock phase references (CLK[3:0]) and write
data/check-bit strobes (DQSs) for each DRAM nibble.
3.3.2
SMBus Slave Interface
The Advanced Memory Buffer supports an SMBus interface
to allow system access to configuration registers independent
of the FB-DIMM link. The Advanced Memory Buffer will never
be a master on the SMBus, only a slave. Serial SMBus data
transfer is supported at 100 kHz. SMBus access to the
Advanced Memory Buffer may be a requirement to boot and
to set link strength, frequency and other parameters needed
to insure robust configurations. It is also required for
diagnostic support when the link is down. The SMBus
address straps located on the DIMM connector are used by
the unique ID.
3.3.3
Channel Latency
FB-DIMM channel latency is measured from the time a read
request is driven on the FB-DIMM channel pins to the time
when the first 16 bytes (2nd chunk) of read completion data is
sampled by the memory controller. When not using the
Variable Read Latency capability, the latency for a specific
DIMM on a channel is always equal to the latency for any
other DIMM on that channel. However, the latency for each
DIMM in a specific configuration with some number of DIMMs
installed may not be equal to the latency for each FB-DIMM
in a configuration with some different number of DIMMs
installed. As more DIMMs are added to the channel,
additional latency is required to read from each DIMM on the
channel. Because the channel is based on the point-to-point
interconnection of buffer components between DIMMs,
memory requests are required to travel through N-1 buffers
before reaching the Nth buffer. The result is that a 4 DIMM
channel configuration will have greater idle read latency
compared to a 1 DIMM channel configuration. The Variable
Read Latency capability can be used to reduce latency for
DIMMs closer to the host. The idle latencies listed in this
section are representative of what might be achieved in
typical AMB designs. Actual implementations with latencies
less than the values listed will have higher application
performance and vice versa.
Rev. 1.2, 2006-02
15
09142006-Q5TN-B9NE
Internet Data Sheet
HYS72T[64/128/256][4/5][00/20]HFD–3S–B
3.3.4
Peak Theoretical Channel Throughput
An FB-DIMM channel transfers read completion data on the
Northbound data connection. 144 bits of data are transferred
for every Northbound data frame. This matches the 18-byte
data transfer of an ECC DDR DRAM in a single DRAM
command clock. A DRAM burst of 8 from a single channel or
a DRAM burst of four from two lock stepped channels
provides a total of 72 bytes of data (64 bytes plus 8 bytes
ECC). The FB-DIMM frame rate matches the DRAM
command clock because of the fixed 6:1 ratio of the FB-DIMM
channel clock to the DRAM command clock. Therefore, the
Northbound data connection will exhibit the same peak
theoretical throughput as a single DRAM channel. For
example, when using DDR2 533 DRAMs, the peak theoretical
bandwidth of the Northbound data connection is 4.267
GB/sec. Write data is transferred on the Southbound
command and data connection, via Command+Wdata
frames. 72 bits of data are transferred for every
Command+Wdata frame. Two Command+Wdata frames
match the 18-byte data transfer of an ECC DDR DRAM in a
single DRAM command clock. A DRAM burst of 8 transfers
from a single channel, or a burst of 4 from two lock-step
channels provides a total of 72 bytes of data (64 bytes plus 8
bytes ECC). When the frame rate matches the DRAM
command clock, the Southbound command and data
connection will exhibit one half the peak theoretical
throughput of a single DRAM channel. For example, when
using DDR2 533 DRAMs, the peak theoretical bandwidth of
the Southbound command and data connection is 2.133
GB/sec. The total peak theoretical throughput for a single FB-
DIMM channel is defined as the sum of the peak theoretical
throughput of the Northbound data connection and the
Southbound command and data connection. When the frame
rate matches the DRAM command clock, this is equal to 1.5
times the peak theoretical throughput of a single DRAM
channel. For example, when using DDR2 533 DRAMs, the
peak theoretical throughput of a single DDR2-533 channel
would be 4.267 GB/sec., while the peak theoretical
throughput of the entire FB-DIMM PC4200F channel would
be 6.4 GB/sec.
3.4
Hot-add
The FB-DIMM channel does not provide a mechanism to
automatically detect and report the addition of a new DIMM
south of the currently active last DIMM. It is assumed the
system will be notified through some means of the addition of
one or more new DIMMs so that specific commands can be
sent to the host controller to initialize the newly added
DIMM(s) and perform a Hot-Add Reset to bring them into the
channel timing domain. It should be noted that the power to
the DIMM socket must be removed before a “hot-add” DIMM
is inserted or removed. Applying or removing the power to a
DIMM socket is a system platform function.
3.5
Hot-remove
In order to accomplish removal of DIMMs the host must
perform a Fast Reset sequence targeted at the last DIMM that
will be retained on the channel. The Fast Reset re-establish
the appropriate last DIMM so that the Southbound Tx outputs
of the last active DIMM and the Southbound and Northbound
outputs of the DIMMs beyond the last active DIMM are
disabled. Once the appropriate outputs are disabled the
system can coordinate the procedure to remove power in
preparation for physical removal of the DIMM if needed. It
should be noted that the power to the DIMM socket must be
removed before a “hot-add” DIMM is inserted or removed.
Applying or removing the power to a DIMM socket is a system
platform function.
3.6
Hot-replace
Hot replace of DIMM is accomplished through combining the Hot-Remove and Hot-Add process.
Rev. 1.2, 2006-02
16
09142006-Q5TN-B9NE
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HYS72T[64/128/256][4/5][00/20]HFD–3S–B
4
Electrical Characteristics
4.1
Operating Conditions
TABLE 8
Absolute Maximum Ratings
Symbol
Parameter
Rating
Min.
Unit
Note
Max.
1)
VDD
Voltage on VDD pin relative to VSS
Voltage on VCC pin relative to VSS
Voltage on VDDQ pin relative to VSS
Voltage on VDDL pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
–0.5
–0,3
–0.5
–0.5
–0.3
–55
+2.3
1.75
+2.3
+2.3
+1.75
+100
2.3
V
V
V
V
V
°C
V
VCC
—
1)2)
VDDQ
VDDL
VIN, VOUT
TSTG
VTT
1)2)
1)
1)2)
Voltage on VTT pin relative to VSS
–0.5
—
1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 9
Operating Temperature Range
Symbol
Parameter
Values
Min.
Unit
Note
Max.
1)2)3)
1)
TCASE
TCASE
DRAM Component Case Temperature Range
AMB Component Case Temperature Range
0
0
+95
°C
°C
+110
1) Within the DRAM Component Case Temperature range all DRAM specification will be supported.
2) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85C case
temperature before initiating self-refresh operation.
3) Above 85C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.
Rev. 1.2, 2006-02
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09142006-Q5TN-B9NE
Internet Data Sheet
HYS72T[64/128/256][4/5][00/20]HFD–3S–B
TABLE 10
Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Limit Values
Unit
Note
Min.
Nom.
Max.
AMB Supply Voltage
VCC
1.455
1.7
1.5
1.575
1.9
V
—
—
—
DRAM Supply Voltage
VDD
1.8
V
Termination Voltage
VTT
0.48 × VDD
3.0
0.50 ×VDD
0.52 × VDD
3.6
V
EEPROM Supply Voltage
DC Input Logic High(SPD)
DC Input Logic Low(SPD)
DC Input Logic High(RESET)
DC Input Logic Low(RESET)
Leakage Current (RESET)
Leakage Current (Link)
VDDSPD
VIH(DC)
VIL(DC)
VIH(DC)
VIL(DC)
IL
3.3
—
—
—
—
—
—
V
—
1)
2.1
VDDSPD
0.8
V
1)
2)
1)
2)
3)
—
V
1.0
—
V
—
+0.5
+90
V
–90
–5
µΑ
µΑ
IL
+5
1) applies for SMB and SPD Bus Signals
2) applies for AMB CMOS Signal RESET
3) for all other AMB related DC parameters, please refer to the High Speed Differential Link Interface Specifications
TABLE 11
Timing Parameters
Parameter
Symbol
Min.
Typ.
Max.
Units
Note
EI Assertion Pass-Thru Timing
EI Deassertion Pass-Thru Timing
EI Assertion Duration
tEI Propagate
t
—
—
100
—
—
—
—
—
—
—
—
4
clks
clks
clks
ns
—
2)
tEID
tEI
—
Bitlock
—
1)2)
3)
—
FBD Cmd to DDR Clk out that latches Cmd
FBD Cmd to DDR Write
—
8.1
TBD
5.0
1.075
2.075
—
—
—
—
ns
—
4)
DDR Read to FBD (last DIMM)
Resample Pass-Thru time
ResynchPass-Thru time
—
—
ns
—
—
ns
—
—
—
ns
—
1)
Bit Lock Interval
tBitLock
tFrameLock
119
154
frames
frames
1)
Frame Lock Interval
—
1) Defined in FB-DIMM Architecture and Protocol Spec
2) Clocks defined as core clocks = 2x SCK input
3) @ DDR2-667 - measured from beginning of frame at southbound input to DDR clock output that latches the first command of a frame to
the DRAMs
4) @ DDR2-667 - measured from latest DQS input to AMB to start of matching data frame at northbound FB-DIMM outputs
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TABLE 12
Environmental Parameters
Parameter
Symbol
Rating
Units
Note
1)
Operating Temperature
TOPR
HOPR
TSTG
HSTG
PBAR
PBAR
See Note
10 to 90
-50 to +100
5 to 95
—
%
°C
%
m
2)
2)
2)
2)
2)
Operating Humidity (relative)
Storage Temperature
Storage Humidity (without condensation)
Barometric pressure (operating)
Barometric pressure (storage)
3050
14240
m
1) The designer must meet the case temperature specifications for individual module components.
2) Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and the device funcional
operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
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5
Current Spec. and Conditions
The following table provides an overview of the measurement conditions.
TABLE 13
IDD Measurement Conditions
Parameter
Symbol
Idle Current, single or last DIMM
L0 state, idle (0 BW)
ICC_Idle_0
IDD_Idle_0
Primary channel enabled, Secondary channel disabled
CKE high. Command and address lines stable.
DRAM clock active
Idle Current, first DIMM
L0 state, idle (0 BW)
ICC_Idle_1
IDD_Idle_1
Primary and Secondary channels enabled.
CKE high. Command and address lines stable.
DRAM clock active
Active Power
L0 state
ICC_Active_1
IDD_Active_1
50% DRAM BW, 67% read, 33% write.
Primary and Secondary channels enabled.
DRAM clock active, CKE high.
Active Power, data pass through
L0 state
ICC_Active_2
IDD_Active_2
50% DRAM BW to downstream DIMM, 67% read, 33% write.
Primary and Secondary channels enabled.
CKE high. Command and address lines stable.
DRAM clock active.
Training
ICC_Training
IDD_Training
Primary and Secondary channels enabled.
100% toggle on all channels lanes.
DRAMs idle (0 BW).
CKE high. Command and address lines stable.
DRAM clock active.
IBIST
Over all IBIST modes
DRAM Idle (0 BW)
ICC_IBIST
IDD_IBIST
Primary channel Enabled
Secondary channel Enabled
CKE high. Command and Address lines stable
DRAM clock active
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Parameter
Symbol
MemBIST
ICC_MEMBIST
IDD_MEMBIST
Over all MemBIST modes >50% DRAM BW (as dictated by the AMB)
Primary channel Enabled
Secondary channel Enabled
CKE high. Command and Address lines stable
DRAM clock active
Electrical Idle
DRAM Idle (0 BW)
ICC_EI
IDD_EI
Primary channel Disabled
Secondary channel Disabled
CKE low. Command and Address lines Floated
DRAM clock active, ODT and CKE driven low
Notes
1. Primary channel Drive strength at 100 % with De-emphasis at -6.5 dB
2. Secondary channel drive strength at 60 % with De-emphasis at -3 dB when enabled.
3. Address and Data fields provide a 50 % toggle rate on DRAM data and link lanes.
4. Burst Length = 4.
5. 10 lanes southbound and 14 lanes northbound are enabled and active (12 lanes NB if non-ECC DIMM).
6. Modeled with 27 Ω termination for command, address, and clocks, and 47 Ω termination for control.
7. Termination is referenced to VTT = VDD / 2.
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5.1
ICC/IDD Conditions
In the following table you can find the Measurement Conditions and Power Supply Currents1)2)
TABLE 14
ICC/IDD Specification for PC2-5300F
Product Type
Unit
Note
Speed Grade
Symbol
PC2-5300F
Typ.
PC2-5300F
Typ.
PC2-5300F
Typ.
ICC_Idle_0
2.18
2.98
0.94
1.61
3.19
4.76
2.99
4.37
0.94
1.61
4.01
6.14
3.14
4.54
2.07
3.46
5.25
8.13
3.06
4.47
0.8
2.2
2.19
3.32
2.22
3.91
4.42
7.24
3.02
4.51
2.2
A
PCC_Idle_0
IDD_Idle_0
3.32
1.28
2.27
3.5
W
A
PDD_Idle_0
ITOT_Idle_0
PTOT_Idle_0
ICC_Idle_1
W
A
5.61
3.01
4.5
W
A
PCC_Idle_1
IDD_Idle_1
W
A
1.27
2.24
4.32
6.77
3.16
4.71
2.44
4.29
5.63
9.03
3.06
4.57
0.8
PDD_Idle_1
ITOT_Idle_1
PTOT_Idle_1
ICC_Active_1
PCC_Active_1
IDD_Active_1
PDD_Active_1
ITOT_Active_1
PTOT_Active_1
ICC_Active_2
PCC_Active_2
IDD_Active_2
PDD_Active_2
ITOT_Active_2
3.87
5.25
8.4
W
A
W
A
3.19
4.75
4.23
7.39
7.43
12.15
3.14
4.68
2.06
3.63
5.24
W
A
W
A
W
A
W
A
1.35
3.92
1.41
3.93
W
A
1) Measured currents on raw card A/B/H/D according to the INTEL/ JEDEC specifcation.The measurements are done in a INTEL Blackford
system.
2) The Power is calculated as follows: Pcc = Vcc x Icc where Vcc = 1.5 V
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Product Type
Unit
Note
Speed Grade
Symbol
PC2-5300F
Typ.
PC2-5300F
Typ.
PC2-5300F
Typ.
PTOT_Active_2
ICC_IBIST
5.87
3.5
6.04
3.52
5.23
1.12
1.97
4.66
7.22
3.07
4.59
1.12
1.98
4.21
6.59
2.18
3.29
0.18
0.31
2.45
3.68
3.17
4.73
2.82
4.96
6.02
9.72
8.35
3.52
5.24
1.94
3.42
5.48
8.68
3.07
4.59
1.94
3.42
5.03
8.02
2.2
W
A
PCC_IBIST
IDD_IBIST
5.06
0.8
W
A
PDD_IBIST
ITOT_IBIST
PTOT_IBIST
ICC_Training
PCC_Training
IDD_Trainig
PDD_Training
ITOT_Trainig
PTOT_Training
ICC_EI
1.35
4.36
6.45
3.05
4.43
0.8
W
A
W
A
W
A
1.35
3.93
5.8
W
A
W
A
2.18
3.18
0.16
0.24
2.4
PCC_EI
3.31
0.25
0.45
2.61
3.9
W
A
IDD_EI
PDD_EI
W
A
ITOT_EI
PTOT_EI
3.48
3.15
4.39
2.44
3.85
5.68
8.31
W
A
ICC_MEMBIST
PCC_MEMBIST
IDD_MEMBIST
PDD_MEMBIST
ITOT_MEMBIST
PTOT_MEMBIST
3.19
4.76
4.45
7.78
7.67
12.56
W
A
W
A
W
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TABLE 15
ICC/IDD Specification for PC2-5300F
Product Type
Unit
Note
Speed Grade
Symbol
PC2-5300F
Typ.
PC2-5300F
Typ.
PC2-5300F
Typ.
ICC_Idle_0
2.18
3.29
0.94
1.66
3.19
5.02
2.99
4.47
0.94
1.67
4.01
6.2
2.2
2.19
3.32
2.22
3.91
4.42
7.24
3.02
4.51
2.2
A
PCC_Idle_0
IDD_Idle_0
3.32
1.28
2.27
3.5
W
A
PDD_Idle_0
ITOT_Idle_0
PTOT_Idle_0
ICC_Idle_1
W
A
5.61
3.01
4.5
W
A
PCC_Idle_1
IDD_Idle_1
W
A
1.27
2.24
4.32
6.77
3.16
4.71
2.44
4.29
5.63
9.03
3.06
4.57
0.8
PDD_Idle_1
ITOT_Idle_1
PTOT_Idle_1
ICC_Active_1
PCC_Active_1
IDD_Active_1
PDD_Active_1
ITOT_Active_1
PTOT_Active_1
ICC_Active_2
PCC_Active_2
IDD_Active_2
PDD_Active_2
ITOT_Active_2
PTOT_Active_2
ICC_IBIST
3.87
5.25
8.4
W
A
W
A
3.14
4.68
2.07
3.65
5.25
8.37
3.06
4.57
0.8
3.19
4.75
4.23
7.39
7.43
12.15
3.14
4.68
2.06
3.63
5.24
8.35
3.52
5.24
1.94
3.42
5.48
W
A
W
A
W
A
W
A
1.41
3.92
6.03
3.5
1.41
3.93
6.04
3.52
5.23
1.12
1.97
4.66
W
A
W
A
PCC_IBIST
5.2
W
A
IDD_IBIST
0.8
PDD_IBIST
1.41
4.36
W
A
ITOT_IBIST
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Product Type
Unit
Note
Speed Grade
Symbol
PC2-5300F
Typ.
PC2-5300F
Typ.
PC2-5300F
Typ.
PTOT_IBIST
ICC_Training
PCC_Training
IDD_Trainig
PDD_Training
ITOT_Trainig
PTOT_Training
ICC_EI
6.67
3.05
4.56
0.8
7.22
3.07
4.59
1.12
1.98
4.21
6.59
2.18
3.29
0.18
0.31
2.45
3.68
3.17
4.73
2.82
4.96
6.02
9.72
8.68
3.07
4.59
1.94
3.42
5.03
8.02
2.2
W
A
W
A
1.41
3.93
6.04
2.18
3.29
0.16
0.27
2.4
W
A
W
A
PCC_EI
3.31
0.25
0.45
2.61
3.9
W
A
IDD_EI
PDD_EI
W
A
ITOT_EI
PTOT_EI
3.62
3.15
4.7
W
A
ICC_MEMBIST
PCC_MEMBIST
IDD_MEMBIST
PDD_MEMBIST
ITOT_MEMBIST
PTOT_MEMBIST
3.19
4.76
4.45
7.78
7.67
12.56
W
A
2.44
4.29
5.68
9.08
W
A
W
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6
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
•
•
Table 16 “SPD Codes for PC2–5300F–555” on Page 26
Table 17 “SPD Codes for PC2–5300F–555” on Page 31
TABLE 16
SPD Codes for PC2–5300F–555
Product Type
Organization
512MB
×72
1 GByte
2 GByte
×72
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–5300F–555 PC2–5300F–555 PC2–5300F–555
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
0
SPD Size CRC / Total / Used
SPD Revision
92
11
09
12
44
23
07
09
00
01
04
0C
20
33
92
11
09
12
44
23
07
11
00
01
04
0C
20
33
92
11
09
12
48
23
07
10
00
01
04
0C
20
33
1
2
Key Byte / DRAM Device Type
Voltage Level of this Assembly
SDRAM Addressing
3
4
5
Module Physical Attributes
Module Type
6
7
Module Organization
8
Fine Timebase (FTB) Dividend and Divisor
Medium Timebase (MTB) Dividend
Medium Timebase (MTB) Divisor
9
10
11
12
13
t
t
CK.MIN (min. SDRAM Cycle Time)
CK.MAX (max. SDRAM Cycle Time)
CAS Latencies Supported
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Product Type
Organization
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–5300F–555 PC2–5300F–555 PC2–5300F–555
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
CAS.MIN (min. CAS Latency Time)
Write Recovery Values Supported (WR)
WR.MIN (Write Recovery Time)
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
t
3C
42
3C
72
50
3C
1E
3C
00
B4
F0
A4
01
1E
3C
42
3C
72
50
3C
1E
3C
00
B4
F0
A4
01
1E
1E
03
07
01
C2
50
7A
48
2E
36
27
4C
3C
42
3C
72
50
3C
1E
3C
00
B4
F0
A4
01
1E
1E
03
07
01
C2
50
7A
48
2E
36
27
4C
t
Write Latency Times Supported
Additive Latency Times Supported
t
t
t
t
t
t
t
t
t
t
RCD.MIN (min. RAS# to CAS# Delay)
RRD.MIN (min. Row Active to Row Active Delay)
RP.MIN (min. Row Precharge Time)
RAS and tRC Extension
RAS.MIN (min. Active to Precharge Time)
RC.MIN (min. Active to Active / Refresh Time)
RFC.MIN LSB (min. Refresh Recovery Time Delay)
RFC.MIN MSB (min. Refresh Recovery Time Delay)
WTR.MIN (min. Internal Write to Read Cmd Delay)
RTP.MIN (min. Internal Read to Precharge Cmd Delay) 1E
Burst Lengths Supported
Terminations Supported
Drive Strength Supported
03
07
01
C2
50
7A
48
2E
36
27
4C
t
REFI (avg. SDRAM Refresh Period)
CASE.MAX Delta / ∆T4R4W Delta
T
Psi(T-A) DRAM
∆T0 (DT0) DRAM
∆T2Q (DT2Q) DRAM
∆T2P (DT2P) DRAM
∆T3N (DT3N) DRAM
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W) DRAM
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Product Type
Organization
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–5300F–555 PC2–5300F–555 PC2–5300F–555
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
40
41
∆T5B (DT5B) DRAM
∆T7 (DT7) DRAM
20
23
00
01
00
02
00
00
36
36
34
2A
56
6B
5C
91
76
00
00
1F
CA
00
40
C0
12
44
20
23
00
22
00
02
00
00
36
36
34
2A
56
6B
5C
91
76
00
00
1F
CA
00
40
C0
12
44
20
23
00
22
00
02
00
00
36
36
34
2A
62
77
61
9F
84
00
00
1F
CA
00
40
C0
12
44
42 - 78 Not used
FBDIMM ODT Values
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
Not used
Channel Protocols Supported LSB
Channel Protocols Supported MSB
Back-to-Back Access Turnaround Time
AMB Read Access Delay for DDR2-800
AMB Read Access Delay for DDR2-667
AMB Read Access Delay for DDR2-533
Psi(T-A) AMB
∆TIdle_0 (DT Idle_0) AMB
∆TIdle_1 (DT Idle_1) AMB
∆TIdle_2 (DT Idle_2) AMB
∆TActive_1 (DT Active_1) AMB
∆TActive_2 (DT Active_2) AMB
∆TL0s (DT L0s) AMB
94 - 97 Not used
98
AMB Junction Temperature Maximum (Tjmax)
99
Category Byte
100
101
102
103
104
Not used
AMB Personality Bytes: Pre-initialization (1)
AMB Personality Bytes: Pre-initialization (2)
AMB Personality Bytes: Pre-initialization (3)
AMB Personality Bytes: Pre-initialization (4)
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Product Type
Organization
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–5300F–555 PC2–5300F–555 PC2–5300F–555
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
AMB Personality Bytes: Pre-initialization (5)
AMB Personality Bytes: Pre-initialization (6)
AMB Personality Bytes: Post-initialization (1)
AMB Personality Bytes: Post-initialization (2)
AMB Personality Bytes: Post-initialization (3)
AMB Personality Bytes: Post-initialization (4)
AMB Personality Bytes: Post-initialization (5)
AMB Personality Bytes: Post-initialization (6)
AMB Personality Bytes: Post-initialization (7)
AMB Personality Bytes: Post-initialization (8)
AMB Manufacturers JEDEC ID Code LSB
AMB Manufacturers JEDEC ID Code MSB
DIMM Manufacturers JEDEC ID Code LSB
DIMM Manufacturers JEDEC ID Code MSB
Module Manufacturing Location
9C
30
60
33
60
1B
60
1B
60
1B
80
B3
85
51
xx
9C
30
60
33
60
1B
60
1B
60
1B
80
B3
85
51
xx
9C
30
60
33
60
1B
60
1B
60
1B
80
B3
85
51
xx
Module Manufacturing Date Year
xx
xx
xx
Module Manufacturing Date Week
xx
xx
xx
122 -
125
Module Serial Number
xx
xx
xx
126
127
128
129
130
131
132
Cyclical Redundancy Code LSB
Cyclical Redundancy Code MSB
Module Product Type, Char #1
Module Product Type, Char #2
Module Product Type, Char #3
Module Product Type, Char #4
Module Product Type, Char #5
99
C9
37
32
54
36
34
A5
C1
37
32
54
31
32
7C
74
37
32
54
32
35
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Product Type
Organization
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–5300F–555 PC2–5300F–555 PC2–5300F–555
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
Module Product Type, Char #6
Module Product Type, Char #7
Module Product Type, Char #8
Module Product Type, Char #9
Module Product Type, Char #10
Module Product Type, Char #11
Module Product Type, Char #12
Module Product Type, Char #13
Module Product Type, Char #14
Module Product Type, Char #15
Module Product Type, Char #16
Module Product Type, Char #17
Module Product Type, Char #18
Module Revision Code
34
30
30
48
46
44
33
53
42
20
20
20
20
3x
xx
38
34
32
30
48
46
44
33
53
42
20
20
20
3x
xx
36
34
32
30
48
46
44
33
53
42
20
20
20
3x
xx
Test Program Revision Code
DRAM Manufacturers JEDEC ID Code LSB
DRAM Manufacturers JEDEC ID Code MSB
informal AMB content revision tag (MSB)
informal AMB content revision tag (LSB)
Not used
85
51
01
05
00
85
51
01
05
00
85
51
01
05
00
152 -
175
176 -
255
Blank for customer use
FF
FF
FF
Rev. 1.2, 2006-02
30
09142006-Q5TN-B9NE
Internet Data Sheet
HYS72T[64/128/256][4/5][00/20]HFD–3S–B
TABLE 17
SPD Codes for PC2–5300F–555
Product Type
Organization
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–5300F–555 PC2–5300F–555 PC2–5300F–555
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
0
SPD Size CRC / Total / Used
SPD Revision
92
11
09
12
44
23
07
09
00
01
04
0C
20
33
3C
42
3C
72
50
3C
1E
3C
00
92
11
09
12
44
23
07
11
00
01
04
0C
20
33
3C
42
3C
72
50
3C
1E
3C
00
92
11
09
12
48
23
07
10
00
01
04
0C
20
33
3C
42
3C
72
50
3C
1E
3C
00
1
2
Key Byte / DRAM Device Type
Voltage Level of this Assembly
SDRAM Addressing
3
4
5
Module Physical Attributes
Module Type
6
7
Module Organization
8
Fine Timebase (FTB) Dividend and Divisor
Medium Timebase (MTB) Dividend
Medium Timebase (MTB) Divisor
9
10
11
12
13
14
15
16
17
18
19
20
21
22
t
t
CK.MIN (min. SDRAM Cycle Time)
CK.MAX (max. SDRAM Cycle Time)
CAS Latencies Supported
CAS.MIN (min. CAS Latency Time)
Write Recovery Values Supported (WR)
WR.MIN (Write Recovery Time)
t
t
Write Latency Times Supported
Additive Latency Times Supported
t
t
t
t
RCD.MIN (min. RAS# to CAS# Delay)
RRD.MIN (min. Row Active to Row Active Delay)
RP.MIN (min. Row Precharge Time)
RAS and tRC Extension
Rev. 1.2, 2006-02
31
09142006-Q5TN-B9NE
Internet Data Sheet
HYS72T[64/128/256][4/5][00/20]HFD–3S–B
Product Type
Organization
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–5300F–555 PC2–5300F–555 PC2–5300F–555
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
t
t
t
t
t
t
RAS.MIN (min. Active to Precharge Time)
B4
F0
A4
01
1E
B4
F0
A4
01
1E
1E
03
07
01
C2
50
7A
48
2E
36
27
4C
20
23
00
22
00
02
00
10
36
B4
F0
A4
01
1E
1E
03
07
01
C2
50
7A
48
2E
36
27
4C
20
23
00
22
00
02
00
10
36
RC.MIN (min. Active to Active / Refresh Time)
RFC.MIN LSB (min. Refresh Recovery Time Delay)
RFC.MIN MSB (min. Refresh Recovery Time Delay)
WTR.MIN (min. Internal Write to Read Cmd Delay)
RTP.MIN (min. Internal Read to Precharge Cmd Delay) 1E
Burst Lengths Supported
Terminations Supported
Drive Strength Supported
03
07
01
C2
50
7A
48
2E
36
27
4C
20
23
00
01
00
02
00
10
36
t
REFI (avg. SDRAM Refresh Period)
CASE.MAX Delta / ∆T4R4W Delta
T
Psi(T-A) DRAM
∆T0 (DT0) DRAM
∆T2Q (DT2Q) DRAM
∆T2P (DT2P) DRAM
∆T3N (DT3N) DRAM
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W) DRAM
∆T5B (DT5B) DRAM
∆T7 (DT7) DRAM
42 - 78 Not used
79
80
81
82
83
84
FBDIMM ODT Values
Not used
Channel Protocols Supported LSB
Channel Protocols Supported MSB
Back-to-Back Access Turnaround Time
AMB Read Access Delay for DDR2-800
Rev. 1.2, 2006-02
32
09142006-Q5TN-B9NE
Internet Data Sheet
HYS72T[64/128/256][4/5][00/20]HFD–3S–B
Product Type
Organization
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–5300F–555 PC2–5300F–555 PC2–5300F–555
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
85
86
87
88
89
90
91
92
93
AMB Read Access Delay for DDR2-667
AMB Read Access Delay for DDR2-533
Psi(T-A) AMB
34
32
2A
56
6B
5C
91
76
00
00
1F
0A
00
00
E2
62
20
80
9C
00
00
F0
70
60
60
60
34
32
2A
56
6B
5C
91
76
00
00
1F
0A
00
00
E2
62
20
80
9C
00
00
F0
70
60
60
60
34
32
2A
62
77
61
9F
84
00
00
1F
0A
00
00
E2
62
20
80
9C
00
00
F0
70
60
60
60
∆TIdle_0 (DT Idle_0) AMB
∆TIdle_1 (DT Idle_1) AMB
∆TIdle_2 (DT Idle_2) AMB
∆TActive_1 (DT Active_1) AMB
∆TActive_2 (DT Active_2) AMB
∆TL0s (DT L0s) AMB
94 - 97 Not used
98
AMB Junction Temperature Maximum (Tjmax)
99
Category Byte
100
101
102
103
104
105
106
107
108
109
110
111
112
113
Not used
AMB Personality Bytes: Pre-initialization (1)
AMB Personality Bytes: Pre-initialization (2)
AMB Personality Bytes: Pre-initialization (3)
AMB Personality Bytes: Pre-initialization (4)
AMB Personality Bytes: Pre-initialization (5)
AMB Personality Bytes: Pre-initialization (6)
AMB Personality Bytes: Post-initialization (1)
AMB Personality Bytes: Post-initialization (2)
AMB Personality Bytes: Post-initialization (3)
AMB Personality Bytes: Post-initialization (4)
AMB Personality Bytes: Post-initialization (5)
AMB Personality Bytes: Post-initialization (6)
AMB Personality Bytes: Post-initialization (7)
Rev. 1.2, 2006-02
33
09142006-Q5TN-B9NE
Internet Data Sheet
HYS72T[64/128/256][4/5][00/20]HFD–3S–B
Product Type
Organization
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–5300F–555 PC2–5300F–555 PC2–5300F–555
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
114
115
116
117
118
119
120
121
AMB Personality Bytes: Post-initialization (8)
AMB Manufacturers JEDEC ID Code LSB
AMB Manufacturers JEDEC ID Code MSB
DIMM Manufacturers JEDEC ID Code LSB
DIMM Manufacturers JEDEC ID Code MSB
Module Manufacturing Location
60
7F
B3
85
51
xx
xx
xx
xx
60
7F
B3
85
51
xx
xx
xx
xx
60
7F
B3
85
51
xx
xx
xx
xx
Module Manufacturing Date Year
Module Manufacturing Date Week
Module Serial Number
122 -
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
Cyclical Redundancy Code LSB
Cyclical Redundancy Code MSB
Module Product Type, Char #1
Module Product Type, Char #2
Module Product Type, Char #3
Module Product Type, Char #4
Module Product Type, Char #5
Module Product Type, Char #6
Module Product Type, Char #7
Module Product Type, Char #8
Module Product Type, Char #9
Module Product Type, Char #10
Module Product Type, Char #11
Module Product Type, Char #12
Module Product Type, Char #13
Module Product Type, Char #14
15
FF
37
32
54
36
34
35
30
30
48
46
44
33
53
42
29
F7
37
32
54
31
32
38
35
32
30
48
46
44
33
53
F0
42
37
32
54
32
35
36
35
32
30
48
46
44
33
53
Rev. 1.2, 2006-02
34
09142006-Q5TN-B9NE
Internet Data Sheet
HYS72T[64/128/256][4/5][00/20]HFD–3S–B
Product Type
Organization
512MB
×72
1 GByte
×72
2 GByte
×72
1 Rank (×8)
2 Ranks (×8)
2 Ranks (×4)
Label Code
PC2–5300F–555 PC2–5300F–555 PC2–5300F–555
JEDEC SPD Revision
Rev. 1.1
HEX
Rev. 1.1
HEX
Rev. 1.1
HEX
Byte#
Description
142
143
144
145
146
147
148
149
150
151
Module Product Type, Char #15
Module Product Type, Char #16
Module Product Type, Char #17
Module Product Type, Char #18
Module Revision Code
20
20
20
20
1x
xx
85
51
43
10
00
42
20
20
20
1x
xx
85
51
43
10
00
42
20
20
20
1x
xx
85
51
43
10
00
Test Program Revision Code
DRAM Manufacturers JEDEC ID Code LSB
DRAM Manufacturers JEDEC ID Code MSB
informal AMB content revision tag (MSB)
informal AMB content revision tag (LSB)
Not used
152 -
175
176 -
255
Blank for customer use
FF
FF
FF
Rev. 1.2, 2006-02
35
09142006-Q5TN-B9NE
Internet Data Sheet
HYS72T[64/128/256][4/5][00/20]HFD–3S–B
7
Package Outline
All Components are surface mounted on one or both sides of
the PCB and positioned on the PCB to meet the minimum and
maximum trace lengths required for DDR2 SDRAM signals.
Bypass capacitors for DDR2 SDRAM devices are located
near the device power pins. The AMB device in the center of
the DIMM has a metal Heat Sink. The FB-DIMM mechanical
outlines are consistent with JEDEC MO-256.
TABLE 18
Raw Card Reference
JEDEC Raw Card
Qimonda PCB
Dimensions
Width [mm]
Height [mm]
Thickness [mm]
Note
1)
R/C A
R/C B
R/C H
L-DIM-240-21
L-DIM-240-22
L-DIM-240-25
Figure 4
Figure 5
Figure 6
133.35
133.35
133.35
30.35
30.35
30.35
8.2
8.2
8.2
1)
1)
1) Thickness includes Qimonda Heat Sink. Some early production modules with Jedec Heatspreader may be thicker up to 8.2 mm.
Attention: Heat Sink heat up during operation. When unplugging a DIMM from a system direct skin contact should be
avoided until the Heat Sink has reached room temperature.
Attention: The Heat Sink is mechanically loaded. Do not remove. Removal of the clip may cause injuries.
Attention: Any mechanical stress on the Heat Sink should be avoided. Touching the Heat Sink while plugging or
unplugging the module may permanently damage the DIMM.
Rev. 1.2, 2006-02
36
09142006-Q5TN-B9NE
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HYS72T[64/128/256][4/5][00/20]HFD–3S–B
FIGURE 4
Package Outline L-DIM-240-21 with Full Heat Sink
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Notes
2. Drawing according to ISO 8015
3. Dimensions in mm
4. General tolerances +/- 0.15
1. Please contact your sales or marketing representative for
more details on package dimensions.
Rev. 1.2, 2006-02
37
09142006-Q5TN-B9NE
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HYS72T[64/128/256][4/5][00/20]HFD–3S–B
FIGURE 5
Package Outline L-DIM-240-22 with Full Heat Sink
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Notes
2. Drawing according to ISO 8015
3. Dimensions in mm
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1. Please contact your sales or marketing representative for
more details on package dimensions.
Rev. 1.2, 2006-02
38
09142006-Q5TN-B9NE
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HYS72T[64/128/256][4/5][00/20]HFD–3S–B
FIGURE 6
Package Outline L-DIM-240-25 with Full Heat Sink
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Notes
2. Drawing according to ISO 8015
3. Dimensions in mm
4. General tolerances +/- 0.15
1. Please contact your sales or marketing representative for
more details on package dimensions.
Rev. 1.2, 2006-02
39
09142006-Q5TN-B9NE
Internet Data Sheet
HYS72T[64/128/256][4/5][00/20]HFD–3S–B
8
DDR2 Nomenclature
TABLE 19
Nomenclature Fields and Examples
Example for
Field Number
1
2
3
4
5
6
7
8
9
10
11
Micro-DIMM
DDR2 DRAM
HYS
HYB
64
18
T
T
64128
0
2
0
0
K
A
M
C
–5
–5
–A
—
5121G 16
TABLE 20
DDR2 DIMM Nomenclature
Field
Description
Values
Coding
1
QIMONDA
HYS
Constant
Module Prefix
2
Module Data Width [bit]
64
Non-ECC
ECC
72
3
4
DRAM Technology
T
DDR2
Memory Density per I/O [Mbit];
Module Density1)
32
256 MByte
512 MByte
1 GByte
2 GByte
4 GByte
64
128
256
512
0 .. 9
0, 2, 4
0 .. 9
A .. Z
5
6
7
8
Raw Card Generation
Number of Module Ranks
Product Variations
Look up table
1, 2, 4
Look up table
Look up table
Package,
Lead-Free Status
9
Module Type
D
SO-DIMM
M
Micro-DIMM
R
Registered
U
Unbuffered
F
Fully Buffered
PC2–6400 6–6–6
PC2–5300 4–4–4
PC2–5300 5–5–5
PC2–4200 4–4–4
PC2–3200 3–3–3
10
Speed Grade
–2.5
–3
–3S
–3.7
–5
Rev. 1.2, 2006-02
40
09142006-Q5TN-B9NE
Internet Data Sheet
HYS72T[64/128/256][4/5][00/20]HFD–3S–B
Field
Description
Values
Coding
11
Die Revision
–A
–B
First
Second
1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall
module memory density in MBytes as listed in column “Coding”.
TABLE 21
DDR2 DRAM Nomenclature
Field
Description
Values
Coding
1
QIMONDA
HYB
Constant
Component Prefix
2
3
4
Interface Voltage [V]
DRAM Technology
18
T
SSTL_18
DDR2
256 Mbit
512 Mbit
1 Gbit
2 Gbit
×4
Component Density [Mbit]
256
512
1G
2G
40
80
16
0 .. 9
A
5+6
Number of I/Os
×8
×16
7
8
Product Variations
Die Revision
Look up table
First
B
Second
9
Package,
C
FBGA,
Lead-Free Status
lead-containing
F
FBGA, lead-free
DDR2-800 6-6-6
DDR2-667 4-4-4
DDR2-667 5-5-5
DDR2-533 4-4-4
DDR2-400 3-3-3
10
Speed Grade
–2.5
–3
–3S
–3.7
–5
Rev. 1.2, 2006-02
41
09142006-Q5TN-B9NE
Internet Data Sheet
HYS72T[64/128/256][4/5][00/20]HFD–3S–B
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.4
Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Advanced Memory Buffer Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
High-Speed Differential Point-to-Point Link (at 1.5 V) Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DDR2 Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SMBus Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Channel Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Peak Theoretical Channel Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Hot-add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Hot-remove . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Hot-replace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5
3.6
4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5
5.1
Current Spec. and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ICC/IDD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6
7
8
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DDR2 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Rev. 1.2, 2006-02
42
09142006-Q5TN-B9NE
Internet Data Sheet
Edition 2006-02
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
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The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
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information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
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