HYS72T256322HP [QIMONDA]
240-Pin Dual-Die Registered DDR2 SDRAM Modules; 240针双芯片寄存器的DDR2 SDRAM模块型号: | HYS72T256322HP |
厂家: | QIMONDA AG |
描述: | 240-Pin Dual-Die Registered DDR2 SDRAM Modules |
文件: | 总36页 (文件大小:2052K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
September 2006
HYS72T256322HP–3S–A
HYS72T256322HP–3.7–A
240-Pin Dual-Die Registered DDR2 SDRAM Modules
DDR2 SDRAM
RDIMM SDRAM
RoHs Compliant
Internet Data Sheet
Rev. 1.01
Internet Data Sheet
HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
HYS72T256322HP–3S–A, HYS72T256322HP–3.7–A
Revision History: 2006-09, Rev. 1.01
Page
Subjects (major changes since last revision)
All
All
Qimonda update
Adapted internet edition
Previous Revision: 2005-11, Rev. 1.0
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03062006-PK3L-ZYSE
2
Internet Data Sheet
HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
1
Overview
This chapter gives an overview of the 240-pin Dual Die Registered Very Low Profile DDR2 SDRAM Modules with parity product
family and describes its main characteristics.
1.1
Features
•
240-pin PC2-5300 and PC2-4200 DDR2 SDRAM memory
modules for PC, Workstation and Server main memory
applications
Two ranks 256M x 72 module organization and
2 x 128M × 4 chip organization
•
Programmable CAS Latencies (3, 4 & 5), Burst Length (4
& 8) and Burst Type
Auto Refresh (CBR) and Self Refresh
High Temperature Self Refresh
All inputs and outputs SSTL_18 compatible
Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT)
•
•
•
•
•
•
•
2 GByte module built with 512-Mbit DDR2 SDRAMs in P-
TFBGA-63 chipsize packages.
Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
All speed grades faster than DDR2-400 comply with
DDR2-400 timing specifications as well.
VLP (Very Low Profile) Registered DIMM Parity bit for
address and control bus
•
•
•
Serial Presence Detect with E2PROM
Based on standard reference layouts Raw Card “W”
RDIMM with parity Dimensions (nominal): 18.30 mm high,
133.35 mm wide
•
•
•
RoHS compliant products1)
TABLE 1
Performance for –3S & –3.7
Product Type Speed Code
–3S
–3.7
Unit
Speed Grade
PC2–5300 5–5–5
PC2–4200 4–4–4
—
max. Clock Frequency
@CL5
@CL4
@CL3
fCK5
fCK4
fCK3
tRCD
tRP
333
266
200
15
266
266
200
15
MHz
MHz
MHz
ns
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
15
15
ns
tRAS
tRC
45
45
ns
60
60
ns
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.01, 2006-09
3
03062006-PK3L-ZYSE
Internet Data Sheet
HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
1.2
Description
The Qimonda HYS72T256322HP–[3S/3.7]–A module family
are Very Low Profile (VLP) Registered Dual-Die DIMM
(RDIMM with parity) with 18.30 mm height based on DDR2
technology. DIMMs are available as ECC modules in
256M x 72 (2 GByte) organization and density, intended for
mounting into 240-Pin connector sockets.
devices and a PLL for the clock distribution. This reduces
capacitive loading to the system bus, but adds one cycle to
the SDRAM timing. Decoupling capacitors are mounted on
the PCB board. The DIMMs feature serial presence detect
based on a serial E2PROM device using the 2-pin I2C
protocol. The first 128 bytes are programmed with
configuration data and the second 128 bytes are available to
the customer.
The memory array is designed with 512-Mbit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs. All control and
address signals are re-driven on the DIMM using register
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type1)
Compliance Code2)
Description
SDRAM Technology
PC2-5300
HYS72T256322HP–3S–A
PC2-4200
2 GB 2R×4 PC2–5300P–555–12–W0
2 GB 2R×4 PC2–4200P–444–12–W0
2 Ranks, ECC 512 Mbit (×4)
2 Ranks, ECC 512 Mbit (×4)
HYS72T256322HP–3.7–A
1) All part numbers end with a place code, designating the silicon die revision. Example: HYS72T256322HP–3.7–A, indicating Rev. “A” dies
are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200P–444–12–W0”, where
4200P means Registered Parity DIMM modules with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address Strobe (CAS)
latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and
produced on the Raw Card “W”
TABLE 3
Address Format
DIMM
Density
Module
Organization
Memory
Ranks
ECC/
Non-ECC
# of
SDRAMs
# of row/bank/columns bits
Raw Card
2 GB
256M × 72
2
ECC
18
14/2/11
W
TABLE 4
Components on Modules
Product Type1)
DRAM Components1)
DRAM Density
DRAM Organization
2 x 128M × 4
Note2)
HYS72T256322HP
1) Green Product
HYB18T1G402AF
512 Mbit
2) For a detailed description of all available functions of the DRAM components on these modules see the component data sheet.
Rev. 1.01, 2006-09
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03062006-PK3L-ZYSE
Internet Data Sheet
HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
2
Pin Configuration
This chapter contains the pin configuration.
2.1
Pin Configuration
The pin configuration of the Registered DDR2 SDRAM DIMM
is listed by function in Table 6 (240 pins). The abbreviations
used in columns Pin and Buffer Type are explained in Table 7
and Table 8 respectively. The pin numbering is depicted in
Figure 1.
TABLE 6
Pin Configuration of RDIMM
Ball No.
Name
Pin
Buffer
Function
Type Type
Clock Signals
185
186
52
CK0
CK0
CKE0
CKE1
NC
I
SSTL
SSTL
SSTL
SSTL
—
Clock Signal CK0, Complementary Clock Signal CK0
I
I
Clock Enables 1:0
Note: 2-Ranks module
171
I
NC
Not Connected
Note: 1-Rank module
Control Signals
193
76
S0
S1
NC
I
SSTL
SSTL
—
Chip Select Rank 1:0
Note: 2-Ranks module
I
NC
Not Connected
Note: 1-Rank module
192
RAS
I
I
I
I
SSTL
SSTL
SSTL
CMOS
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
74
CAS
73
WE
18
RESET
Register Reset
Address Signals
71
BA0
BA1
BA2
I
I
I
SSTL
SSTL
SSTL
Bank Address Bus 1:0
Bank Address Bus 2
190
54
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03062006-PK3L-ZYSE
Internet Data Sheet
HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Ball No.
Name
Pin
Buffer
Function
Type Type
188
183
63
A0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Address Bus 12:0, Address Signal 10/AutoPrecharge
A1
A2
182
61
A3
A4
60
A5
180
58
A6
A7
179
177
70
A8
A9
A10
AP
A11
A12
A13
57
176
196
Address Signal 13
Note: Modules based on ×4, ×8
Not Connected
NC
NC
I
—
Note: Modules based on ×16
Address Signal 14
174
A14
SSTL
Note: 2 Gbit based module
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Internet Data Sheet
HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Ball No.
Name
Pin
Buffer
Function
Type Type
Data Signals
3
DQ0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
4
DQ1
9
DQ2
10
DQ3
122
123
128
129
12
DQ4
DQ5
DQ6
DQ7
DQ8
13
DQ9
21
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
22
131
132
140
141
24
25
30
31
143
144
149
150
33
34
39
40
152
153
158
159
80
81
86
87
199
200
205
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Internet Data Sheet
HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Ball No.
Name
Pin
Buffer
Function
Type Type
206
89
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
90
95
96
208
209
214
215
98
99
107
108
217
218
226
227
110
111
116
117
229
230
235
236
Check Bits
42
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Check Bits 7:0
43
48
49
161
162
167
168
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Internet Data Sheet
HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Ball No.
Name
Pin
Buffer
Function
Type Type
Data Strobe Bus
7
DQS0
DQS0
DQS1
DQS1
DQS2
DQS2
DQS3
DQS3
DQS4
DQS4
DQS5
DQS5
DQS6
DQS6
DQS7
DQS7
DQS8
DQS8
DQS9
DQS9
DQS10
DQS10
DQS11
DQS11
DQS12
DQS12
DQS13
DQS13
DQS14
DQS14
DQS15
DQS15
DQS16
DQS16
DQS17
DQS17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Strobes 17:0
6
16
15
28
27
37
36
84
83
93
92
105
104
114
113
46
45
126
125
135
134
147
146
156
155
203
202
212
211
224
223
233
232
165
164
Rev. 1.01, 2006-09
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Internet Data Sheet
HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Ball No.
Name
Pin
Buffer
Function
Type Type
EEPROM
120
SCL
SDA
SA0
SA1
SA2
I
CMOS
OD
Serial Bus Clock
119
I/O
Serial Bus Data
239
I
I
I
CMOS
CMOS
CMOS
Serial Address Select Bus 2:0
240
101
Parity
55
ERR_OUT
PAR_IN
O
I
CMOS
CMOS
Parity bits
Power Supplies
1
VREF
AI
—
—
—
I/O Reference Voltage
EEPROM Power Supply
I/O Driver Power Supply
238
VDDSPD
PWR
PWR
51, 56, 62, 72, 75, VDDQ
78, 170, 175, 181,
191, 194
53, 59, 64, 67, 69, VDD
172, 178, 184, 187,
189, 197
PWR
GND
—
—
Power Supply
Ground Plane
2, 5, 8, 11, 14, 17, VSS
20, 23, 26, 29, 32,
35, 38, 41, 44, 47,
50, 65, 66, 79, 82,
85, 88, 91, 94, 97,
100, 103, 106, 109,
112, 115, 118, 121,
124, 127, 130, 133,
136, 139, 142, 145,
148, 151, 154, 157,
160, 163, 166, 169,
198, 201, 204, 207,
210, 213, 216, 219,
222, 225, 228, 231,
234, 237
Other Pins
19, 55, 68, 102,
137, 138, 173, 220,
221
NC
NC
—
Not connected
195
77
ODT0
ODT1
NC
I
SSTL
SSTL
—
On-Die Termination Control 1:0
Note: 2-Ranks module
I
NC
Note: 1-Rank modules
Rev. 1.01, 2006-09
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03062006-PK3L-ZYSE
Internet Data Sheet
HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
TABLE 7
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
CMOS
OD
Serial Stub Terminated Logic (SSTL_18)
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate,
and allows multiple devices to share as a wire-OR.
TABLE 8
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NU
NC
Ground
Not Usable
Not Connected
Rev. 1.01, 2006-09
12
03062006-PK3L-ZYSE
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Internet Data Sheet
HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
FIGURE 1
Pin Configuration for RDIMM (240 pins)
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Rev. 1.01, 2006-09
03062006-PK3L-ZYSE
13
Internet Data Sheet
HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
3
Electrical Characteristics
This chapter lists the electrical characteristics.
3.1
Absolute Maximum Ratings
This chapter contains the absolute maximum ratings table.
TABLE 9
Absolute Maximum Ratings
Parameter
Symbol
Values
Min.
Unit
Note/Test
Condition
Max.
Voltage on any pins relative to VSS
Voltage on VDD relative to VSS
VIN, VOUT
VDD
–0.5
–1.0
–0.5
5
2.3
2.3
2.3
95
V
V
V
%
Voltage on VDDQ relative to VSS
VDDQ
Storage Humidity (without condensation)
HSTG
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings
are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated
circuit.
3.2
DC Operating Conditions
This chapter contains the DC operating conditions tables.
TABLE 10
Operating Conditions
Parameter
Symbol
Values
Min.
Unit
Note
Max.
DIMM Module Operating Temperature Range (ambient)
DRAM Component Case Temperature Range
Storage Temperature
TOPR
TCASE
TSTG
0
+55
+95
+100
+105
90
°C
°C
°C
kPa
%
1)2)3)4)
5)
0
–50
+69
10
Barometric Pressure (operating & storage)
Operating Humidity (relative)
PBar
HOPR
1) DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.
2) Within the DRAM Component Case Temperature range all DRAM specification will be supported.
3) Above 85 °C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. Note, when the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%
5) Up to 3000 m
Rev. 1.01, 2006-09
14
03062006-PK3L-ZYSE
Internet Data Sheet
HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
TABLE 11
Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Values
Min.
Unit
Note
Typ.
Max.
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
SPD Supply Voltage
VDD
1.7
1.8
1.9
V
1)
2)
VDDQ
VREF
1.7
1.8
1.9
V
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
V
VDDSPD
VIH(DC)
VIL (DC
IL
1.7
—
—
—
—
3.6
V
DC Input Logic High
V
REF + 0.125
V
V
5
DDQ + 0.3
V
DC Input Logic Low
)
– 0.30
– 5
REF – 0.125
V
3)
In / Output Leakage Current
µA
1) Under all conditions, VDDQ must be less than or equal to VDD
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise in VDDQ
3) Input voltage for any connector pin under test of 0 V ≤ VIN ≤ VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
.
Rev. 1.01, 2006-09
15
03062006-PK3L-ZYSE
Internet Data Sheet
HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
3.3
AC Characteristics
This chapter describes the AC characteristics.
3.3.1
Speed Grades Definitions
This chapter contains the Speed Grades Definitions tables.
TABLE 12
Speed Grade Definition Speed Bins for DDR2–667
Speed Grade
DDR2–667
Unit
Note
IFX Sort Name
–3S
CAS-RCD-RP latencies
5–5–5
Min.
tCK
Parameter
Symbol
Max.
—
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
tCK
5
8
ns
ns
ns
ns
ns
ns
ns
tCK
3.75
3
8
tCK
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
45
60
15
15
70000
—
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) only.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS, RDQS/RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT
.
5) RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI
t
.
Rev. 1.01, 2006-09
16
03062006-PK3L-ZYSE
Internet Data Sheet
HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
TABLE 13
Speed Grade Definition Speed Bins for DDR2-533
Speed Grade
DDR2–533C
Unit
Note
QAG Sort Name
CAS-RCD-RP latencies
–3.7
4–4–4
tCK
Parameter
Symbol
Min.
Max.
—
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
tCK
5
8
ns
ns
ns
ns
ns
ns
ns
tCK
3.75
3.75
45
8
tCK
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
70000
—
60
15
—
15
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) .
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT
.
5) RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI
t
.
Rev. 1.01, 2006-09
17
03062006-PK3L-ZYSE
Internet Data Sheet
HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
3.3.2
AC Timing Parameters
This chapter contains the AC Timing Parameters.
TABLE 14
DRAM Component Timing Parameter by Speed Grade - DDR2–667
Parameter
Symbol
DDR2–667
Unit
Note1)2)3)4)5)6)7)
8)
Min.
Max.
9)
DQ output access time from CK / CK
DQS output access time from CK / CK
Average clock high pulse width
Average clock low pulse width
Average clock period
tAC
–450
–400
0.48
0.48
3000
100
+450
+400
0.52
0.52
8000
––
ps
9)
tDQSCK
tCH.AVG
tCL.AVG
tCK.AVG
tDS.BASE
tDH.BASE
ps
10)11)
10)11)
tCK.AVG
tCK.AVG
ps
12)13)14)
13)14)15)
DQ and DM input setup time
DQ and DM input hold time
ps
175
––
ps
Control & address input pulse width for each input tIPW
0.6
—
tCK.AVG
tCK.AVG
ps
DQ and DM input pulse width for each input
Data-out high-impedance time from CK / CK
DQS/DQS low-impedance time from CK / CK
DQ low impedance time from CK/CK
tDIPW
tHZ
tLZ.DQS
tLZ.DQ
0.35
—
—
9)16)
9)16)
9)16)
17)
tAC.MAX
tAC.MAX
tAC.MAX
240
tAC.MIN
2 x tAC.MIN
—
ps
ps
DQS-DQ skew for DQS & associated DQ signals tDQSQ
ps
18)
CK half pulse width
tHP
Min(tCH.ABS
,
__
ps
tCL.ABS
)
19)
20)
DQ hold skew factor
tQHS
tQH
—
340
—
ps
DQ/DQS output hold time from DQS
t
HP – tQHS
ps
Write command to DQS associated clock edges WL
RL–1
nCK
tCK.AVG
21)
DQS latching rising transition to associated clock tDQSS
– 0.25
+ 0.25
edges
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Write postamble
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
—
—
—
—
0.6
—
—
—
1.1
0.6
—
—
—
—
tCK.AVG
tCK.AVG
tCK.AVG
tCK.AVG
tCK.AVG
tCK.AVG
ps
21)
21)
tDSH
0.2
tWPST
tWPRE
tIS.BASE
tIH.BASE
tRPRE
tRPST
tCCD
0.4
Write preamble
0.35
200
275
0.9
22)23)
23)24)
25)26)
25)27)
Address and control input setup time
Address and control input hold time
Read preamble
ps
tCK.AVG
tCK.AVG
nCK
Read postamble
0.4
CAS to CAS command delay
Write recovery time
2
1)
tWR
15
ns
28)29)
1)30)
Auto-Precharge write recovery + precharge time tDAL
WR + tnRP
7.5
nCK
Internal write to read command delay
tWTR
ns
Rev. 1.01, 2006-09
18
03062006-PK3L-ZYSE
Internet Data Sheet
HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol
DDR2–667
Unit
Note1)2)3)4)5)6)7)
8)
Min.
Max.
1)
1)
Internal Read to Precharge command delay
Exit self-refresh to a non-read command
Exit self-refresh to read command
tRTP
tXSNR
tXSRD
tXP
7.5
—
—
—
—
ns
t
RFC +10
ns
200
2
nCK
nCK
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit power down to read command
tXARD
2
—
—
nCK
nCK
Exit active power-down mode to read command tXARDS
7 – AL
(slow exit, lower power)
31)
CKE minimum pulse width ( high and low pulse tCKE
3
—
nCK
width)
Mode register set command cycle time
MRS command to ODT update delay
OCD drive mode output delay
tMRD
tMOD
tOIT
2
0
0
—
12
12
––
nCK
ns
28)
28)
ns
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK .AVG
tIH
+
ns
1) For details and notes see the relevant Qimonda component data sheet
2)
DDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V. See notes 5)6)7)8)
V
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT
.
8) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min)
.
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272
ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and
tDQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to
DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and
the absolute instantaneous timing holds all the times.
12) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See
Figure 3.
13) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
14) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and
VIH.DC.MIN. See Figure 3.
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Registered DDR2 SDRAM Modules
16) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) .
17) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
18) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter.
It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the
following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the
minimum of the actual instantaneous clock low time.
19) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
20) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under
the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}
Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system
provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
21) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
22) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied
to the device under test. See Figure 4.
23) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC
,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
24) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied
to the device under test. See Figure 4.
25) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(tRPST), or begins driving (tRPRE). Figure 2 shows a method to calculate these points when the device is no longer driving (tRPST), or begins
driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
26) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps
and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX
+ tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
27) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps
and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+ tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
28) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result
of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For
DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
29) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR.
30) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
31) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2 x tCK + tIH.
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Registered DDR2 SDRAM Modules
FIGURE 2
Method for calculating transitions and endpoint
VOH - x mV
VTT + 2x mV
VOH - 2x mV
VTT + x mV
tLZ
tHZ
tRPRE begin point
tRPST end point
VOL + 2x mV
VOL + x mV
VTT - x mV
VTT - 2x mV
T1 T2
tLZ,tRPRE begin point = 2*T1-T2
T1 T2
tHZ,tRPST end point = 2*T1-T2
FIGURE 3
Differential input waveform timing - tDS and tDS
DQS
DQS
tDH
tDH
tDS
tDS
VDDQ
VIH(ac) min
VIH(dc) min
V
REF(dc)
VIL(dc) max
VIL(ac) max
VSS
FIGURE 4
Differential input waveform timing - tlS and tlH
CK
CK
tIH
tIH
tIS
tIS
VDDQ
VIH(ac) min
VIH(dc) min
VREF(dc)
VIL(dc) max
VIL(ac) max
VSS
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HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
TABLE 15
DRAM Component Timing Parameter by Speed Grade - DDR2–533
Parameter
Symbol
DDR2–533
Unit
Note1)2)3)4)5)
6)7)
Min.
Max.
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
tAC
–500
2
+500
—
ps
tCCD
tCH
tCKE
tCL
tCK
tCK
tCK
tCK
tCK
0.45
3
0.55
—
CKE minimum high and low pulse width
CK, CK low-level width
0.45
WR + tRP
0.55
—
8)18)
9)
Auto-Precharge write recovery + precharge
time
tDAL
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK + tIH
225
––
––
—
ns
ps
ps
10)
11)
DQ and DM input hold time (differential data
strobe)
t
t
DH(base)
DQ and DM input hold time (single ended data
strobe)
DH1(base)
–25
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
tDIPW
0.35
–450
0.35
—
—
tCK
ps
tCK
ps
tDQSCK
+450
—
DQS input low (high) pulse width (write cycle) tDQSL,H
11)
DQS-DQ skew (for DQS & associated DQ
signals)
tDQSQ
300
Write command to 1st DQS latching transition tDQSS
– 0.25
100
+ 0.25
—
tCK
11)
11)
DQ and DM input setup time (differential data
strobe)
t
DS(base)
ps
DQ and DM input setup time (single ended data tDS1(base)
strobe)
–25
0.2
—
—
—
ps
DQS falling edge hold time from CK (write
cycle)
tDSH
tCK
tCK
DQS falling edge to CK setup time (write cycle) tDSS
0.2
12)
13)
11)
Clock half period
tHP
MIN. (tCL, tCH)
Data-out high-impedance time from CK / CK
Address and control input hold time
tHZ
—
tAC.MAX
—
ps
ps
tCK
tIH(base)
tIPW
375
0.6
Address and control input pulse width
(each input)
—
11)
14)
14)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
250
—
ps
ps
ps
tCK
ns
2 × tAC.MIN
tAC.MAX
tAC.MAX
—
tAC.MIN
2
0
tOIT
12
Data output hold time from DQS
Data hold skew factor
tQH
t
HP –tQHS
—
tQHS
—
400
ps
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HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol
DDR2–533
Min.
Unit
Note1)2)3)4)5)
6)7)
Max.
14)15)
16)18)
17)
Average periodic refresh Interval
tREFI
tRFC
—
7.8
3.9
—
µs
µs
ns
—
Auto-Refresh to Active/Auto-Refresh
command period
105
Precharge-All (4 banks) command period
Precharge-All (8 banks) command period
Read preamble
tRP
t
RP + 1tCK
—
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
ns
tRP
15 + 1tCK
0.9
—
14)
tRPRE
tRPST
tRRD
1.1
0.60
—
14)
Read postamble
0.40
7.5
14)18)
16)20)
Active bank A to Active bank B command
period
10
—
Internal Read to Precharge command delay
Write preamble
tRTP
7.5
—
tWPRE
tWPST
tWR
0.25 x tCK
0.40
15
—
19)
20)
Write postamble
0.60
—
Write recovery time for write without Auto-
Precharge
Write recovery time for write with Auto-
Precharge
WR
t
WR/tCK
tCK
21)
22)
Internal Write to Read command delay
tWTR
7.5
2
—
—
ns
Exit power down to any valid command
(other than NOP or Deselect)
tXARD
tCK
22)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
tXP
6 – AL
2
—
—
tCK
tCK
Exit precharge power-down to any valid
command (other than NOP or Deselect)
Exit Self-Refresh to non-Read command
Exit Self-Refresh to Read command
tXSNR
tXSRD
t
RFC +10
—
—
ns
200
tCK
1) For details and notes see the relevant Qimonda component data sheet
2)
DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V. See notes 5)6)7)8)
V
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT
.
8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
10) For timing definition, refer to the Component data sheet.
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
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Registered DDR2 SDRAM Modules
13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
15) 0 °C≤ TCASE ≤ 85 °C
16) 85 °C < TCASE ≤ 95 °C
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 2 “Ordering Information for RoHS
Compliant Products” on Page 4.
19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
20) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
21) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
22) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
3.3.3
ODT AC Electrical Characteristics
This chapter contains the ODT AC electrical characteristics tables.
TABLE 16
ODT AC Characteristics and Operating Conditions for DDR2-667
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
tAOND
tAON
ODT turn-on delay
2
2
tCK
ns
ns
tCK
ns
ns
tCK
tCK
1)
2)
ODT turn-on
tAC.MIN
tAC.MAX + 0.7 ns
tAONPD
tAOFD
tAOF
ODT turn-on (Power-Down Modes)
ODT turn-off delay
t
AC.MIN + 2 ns
2 tCK + tAC.MAX + 1 ns
2.5
2.5
ODT turn-off
tAC.MIN
tAC.MAX + 0.6 ns
tAOFPD
tANPD
tAXPD
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
t
AC.MIN + 2 ns
2.5 tCK + tAC.MAX + 1 ns
3
8
—
—
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measure from tAOND
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
.
Both are measured from tAOFD
.
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HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
TABLE 17
ODT AC Characteristics and Operating Conditions for DDR2-533 &DDR2-400
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
tAOND
tAON
ODT turn-on delay
2
2
tCK
ns
ns
tCK
ns
ns
tCK
tCK
1)
2)
ODT turn-on
tAC.MIN
tAC.MAX + 1 ns
tAONPD
tAOFD
tAOF
ODT turn-on (Power-Down Modes)
ODT turn-off delay
t
AC.MIN + 2 ns
2 tCK + tAC.MAX + 1 ns
2.5
2.5
ODT turn-off
tAC.MIN
tAC.MAX + 0.6 ns
tAOFPD
tANPD
tAXPD
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
t
AC.MIN + 2 ns
2.5 tCK + tAC.MAX + 1 ns
3
8
—
—
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measure from tAOND
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
.
Both are measured from tAOFD
.
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HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
3.4
Currents Specifications and Conditions
This chapter contains the Specifications and Conditions.
TABLE 18
IDD Measurement Conditions
Parameter
Symbol Note1)2)3)4)5)6)7)8)
Operating Current 0
IDD0
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is
HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs
are SWITCHING.
Operating Current 1
IDD1
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS
RAS.MIN, tRCD = tRCD.MIN, AL = 0, CL = CL.MIN; CKE is HIGH, CS is HIGH between valid
=
t
commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Standby Current
IDD2N
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are
SWITCHING, Data bus inputs are SWITCHING
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2P
IDD2Q
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are
STABLE, Data bus inputs are FLOATING.
Active Power-Down Current
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data
bus inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
IDD3P(0)
IDD3P(1)
IDD3N
Active Power-Down Current
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data
bus inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN
;
t
RAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address
inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
Operating Current
IDD4R
IDD4W
IDD5B
IDD5D
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN
;
t
RAS = tRAS.MAX., tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address
inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
Operating Current
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN
;
t
RAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address
inputs are SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
t
CK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH
between valid commands, Other control and address inputs are SWITCHING, Data bus inputs
are SWITCHING.
Distributed Refresh Current
t
CK = tCK.MIN, Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH
between valid commands, Other control and address inputs are SWITCHING, Data bus inputs
are SWITCHING.
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HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol Note1)2)3)4)5)6)7)8)
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are
FLOATING, Data bus inputs are FLOATING. RESET is LOW. IDD6 current values are
guaranteed up to TCASE of 85 °C max.
All Bank Interleave Read Current
IDD7
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4.
Control and address bus inputs are STABLE during DESELECTS. IOUT = 0 mA.
1)
VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
3) Definitions for IDD see Table 19
4)
IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
6) RESET signal is HIGH for all currents, except for IDD6 (Self Refresh)
7) All current measurements includes Register and PLL current consumption
8) For details and notes see the relevant Qimonda component data sheet
TABLE 19
Definitions for IDD
Parameter
Description
LOW
VIN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN
inputs are stable at a HIGH or LOW level
inputs are VREF = VDDQ /2
STABLE
FLOATING
SWITCHING
inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes.
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HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
TABLE 20
IDD Specification for HYS72T256322HP–[3S/3.7]–A
Product Type
Unit
Note1)
Organization
2 GB
2 Ranks
×72
2 GB
2 Ranks
×72
–3S
–3.7
Symbol
Max.
Max.
2)
IDD0
1960
2220
2400
780
1740
1920
1940
640
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
2)
IDD1
3)
IDD2N
3)
IDD2P
3)
IDD2Q
2040
2400
1280
810
1580
1940
1080
680
3)
IDD3N
3)
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD4R
3)
2)
3030
3210
3210
810
2190
2280
2910
720
2)
IDD4W
IDD5B
2)
3)4)
3)4)
2)
IDD5D
IDD6
180
144
IDD7
3330
3100
1) Module IDD is calculated on the basis of component IDD and currents includes Registers and PLL. ODT disabled. IDD1, IDD4R and IDD7 are
defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Standby Current mode
3) Both ranks are in the same IDD mode
4) Values for 0 °C ≤ TCASE ≤ 85 °C
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HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
•
Table 21 “SPD Codes for PC2–4200P–444” on Page 29
TABLE 21
SPD Codes for PC2–4200P–444
Product Type
Organization
HYS72T256322HP–3.7–A HYS72T256322HP–3S–A
2 GByte
×72
2 GByte
×72
2 Ranks (×4)
PC2–4200P–444
Rev. 1.2
HEX
2 Ranks (×4)
PC2–5300P–555
Rev. 1.2
HEX
Label Code
JEDEC SPD Revision
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0E
0B
11
48
00
05
3D
50
06
82
04
04
00
0C
04
38
00
01
05
80
08
08
0E
0B
11
48
00
05
30
45
06
82
04
04
00
0C
04
38
00
01
05
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
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HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
HYS72T256322HP–3.7–A HYS72T256322HP–3S–A
2 GByte
×72
2 GByte
×72
2 Ranks (×4)
PC2–4200P–444
Rev. 1.2
HEX
2 Ranks (×4)
PC2–5300P–555
Rev. 1.2
HEX
Label Code
JEDEC SPD Revision
Byte#
Description
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Component Attributes
03
3D
50
50
60
3C
1E
3C
2D
01
25
37
10
22
3C
1E
1E
00
00
3C
69
80
1E
28
0F
51
78
3F
22
1E
1E
24
17
03
3D
50
50
60
3C
1E
3C
2D
01
20
27
10
17
3C
1E
1E
00
00
3C
69
80
18
22
0F
53
78
4B
2E
26
26
2B
1B
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
T
Psi(T-A) DRAM
∆T0 (DT0)
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
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HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
HYS72T256322HP–3.7–A HYS72T256322HP–3S–A
2 GByte
×72
2 GByte
×72
2 Ranks (×4)
PC2–4200P–444
Rev. 1.2
HEX
2 Ranks (×4)
PC2–5300P–555
Rev. 1.2
HEX
Label Code
JEDEC SPD Revision
Byte#
Description
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
34
1E
20
C4
8C
61
78
12
44
7F
7F
7F
7F
7F
51
00
00
xx
4A
20
22
C4
8C
68
94
12
72
7F
7F
7F
7F
7F
51
00
00
xx
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
37
32
54
32
35
36
33
32
32
48
50
33
2E
37
41
37
32
54
32
35
36
33
32
32
48
50
33
53
41
20
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
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HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Product Type
Organization
HYS72T256322HP–3.7–A HYS72T256322HP–3S–A
2 GByte
×72
2 GByte
×72
2 Ranks (×4)
PC2–4200P–444
Rev. 1.2
HEX
2 Ranks (×4)
PC2–5300P–555
Rev. 1.2
HEX
Label Code
JEDEC SPD Revision
Byte#
Description
88
89
90
91
92
93
94
Product Type, Char 16
20
20
20
2x
xx
xx
xx
xx
00
FF
20
20
20
2x
xx
xx
xx
xx
00
FF
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
128 -
255
Blank for customer use
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HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
5
Package Outlines
This chapter contains the package outlines of the products.
FIGURE 5
Package Outline Raw Card XX - L-DIM-240-54
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',$ꢀꢁꢀꢂꢃ
Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
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HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
6
Product Type Nomenclature
Qimonda’s nomenclature uses simple coding combined with
some propriatory coding. Table 22 provides examples for
module and component product type number as well as the
field number. The detailed field description together with
possible values and coding explanation is listed for modules
in Table 23 and for components in Table 24.
TABLE 22
Nomenclature Fields and Examples
Example for
Field Number
1
2
3
4
5
6
7
8
9
10
11
Micro-DIMM
DDR2 DRAM
HYS
HYB
64
18
T
T
64/128
0
2
0
0
K
A
M
C
–5
–5
–A
512/1G 16
TABLE 23
DDR2 DIMM Nomenclature
Field
Description
Values
Coding
1
2
Qimonda Module Prefix
Module Data Width [bit]
HYS
64
Constant
Non-ECC
ECC
72
3
4
DRAM Technology
T
DDR2
Memory Density per I/O [Mbit];
Module Density1)
32
256 MByte
512 MByte
1 GByte
2 GByte
4 GByte
64
128
256
512
0 .. 9
0, 2, 4
0 .. 9
A .. Z
D
5
6
7
8
9
Raw Card Generation
Number of Module Ranks
Product Variations
Look up table
1, 2, 4
Look up table
Look up table
SO-DIMM
Package, Lead-Free Status
Module Type
M
Micro-DIMM
Registered
Unbuffered
Fully Buffered
R
U
F
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HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Field
Description
Values
Coding
10
Speed Grade
–2.5F
–2.5
–3
PC2–6400 5–5–5
PC2–6400 6–6–6
PC2–5300 4–4–4
PC2–5300 5–5–5
PC2–4200 4–4–4
PC2–3200 3–3–3
First
–3S
–3.7
–5
11
Die Revision
–A
–B
Second
1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall
module memory density in MBytes as listed in column “Coding”.
TABLE 24
DDR2 DRAM Nomenclature
Field
Description
Values
Coding
1
2
3
4
Qimonda Component Prefix
Interface Voltage [V]
HYB
18
Constant
SSTL_18
DRAM Technology
T
DDR2
Component Density [Mbit]
256
512
1G
2G
40
256 Mbit
512 Mbit
1 Gbit
2 Gbit
5+6
Number of I/Os
×4
80
×8
16
×16
7
8
Product Variations
Die Revision
0 .. 9
A
Look up table
First
B
Second
9
Package, Lead-Free Status
Speed Grade
C
FBGA, lead-containing
FBGA, lead-free
DDR2-800 5-5-5
DDR2-800 6-6-6
DDR2-667 4-4-4
DDR2-667 5-5-5
DDR2-533 4-4-4
DDR2-400 3-3-3
F
10
–25F
–2.5
–3
–3S
–3.7
–5
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HYS72T256322HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Speed Grades Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Currents Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4
5
6
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Rev. 1.01, 2006-09
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03062006-PK3L-ZYSE
Internet Data Sheet
Edition 2006-09
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2006.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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