HYS72T128000EU-2.5-B2 [QIMONDA]
DRAM;
| 型号： | HYS72T128000EU-2.5-B2 |
| 厂家： | 
QIMONDA AG |
| 描述： | DRAM 动态存储器 |
| 文件： | 总48页 (文件大小：2828K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2008
HYS64T128000EU–[25F/2.5/3S]–B2
HYS72T128000EU–[25F/2.5/3S]–B2
HYS64T256020EU–[25F/2.5/3S]–B2
240-Pin Unbuffered DDR2 SDRAM Modules
UDIMM SDRAM
RoHS Compliant
Advance
Internet Data Sheet
Rev. 0.50
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
HYS64T128000EU–[25F/2.5/3S]–B2, HYS72T128000EU–[25F/2.5/3S]–B2, HYS64T256020EU–[25F/2.5/3S]–B2
Advance
Revision History: 2008-01, Rev. 0.50
Page
Subjects (major changes since last revision)
All
New Document and adapted to internet edition.
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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qag_techdoc_A4, 4.20, 2008-01-25
01282008-JC1K-XBCR
2
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
1
Overview
This chapter gives an overview of the 240-pin Unbuffered DDR2 SDRAM modules product family and describes its main
characteristics.
1.1
Features
•
•
•
•
240-Pin PC2-6400 and PC2-5300 DDR2 SDRAM memory
modules.
One rank 128M × 64, 128M × 72, and two rank 256M × 64
module organization, and 128M × 8 chip organization.
2GB, 1GB Modules built with 1 Gbit DDR2 SDRAMs in
chipsize packages PG-TFBGA-60.
Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply.
All speed grades faster than DDR2-400 comply with
DDR2-400 timing specifications.
•
•
•
•
•
•
Auto Refresh (CBR) and Self Refresh
Auto Refresh for temperatures above 85 °C tREFI = 3.9 µs.
Programmable self refresh rate via EMRS2 setting.
Programmable partial array refresh via EMRS2 settings.
All inputs and outputs SSTL_1.8 compatible
Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT).
•
•
Serial Presence Detect with E2PROM.
UDIMM and EDIMM Dimensions (nominal): 30 mm high,
133.35 mm wide.
•
•
•
•
Based on standard reference layouts Raw Cards 'D', 'E'
and 'F'
Programmable CAS Latencies (3, 4, 5 and 6 ), Burst
Length (8 & 4).
RoHS compliant products1).
TABLE 1
Performance Table
QAG Speed Code
–25F
–2.5
–3S
Unit
DRAM Speed Grade
Module Speed Grade
DDR2
PC2
–800D
–6400D
5–5–5
–800E
–6400E
6–6–6
–667D
–5300D
5–5–5
CAS-RCD-RP latencies
tCK
Max. Clock Frequency
CL3
CL4
CL5
CL6
fCK3
fCK4
fCK5
fCK6
tRCD
tRP
200
266
400
–
200
266
333
400
15
200
266
333
–
MHz
MHz
MHz
MHz
ns
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
12.5
12.5
45
15
15
15
ns
tRAS
tRC
45
45
ns
57.5
15
60
60
ns
Precharge-All (8 banks) command
period
tPREA
17.5
18
ns
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 0.50, 2008-01
3
01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
1.2
Description
The Qimonda HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–
B2 module family are Unbuffered DIMM modules “UDIMMs”
with 30 mm height based on DDR2 technology.
The memory array is designed with 1 Gbit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs.
Decoupling
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E2PROM
device using the 2-pin I2C protocol. The first 128 bytes are
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
DIMMs are available as non-ECC modules in 128M × 64
(1GB), 256M × 64 (2GB) and as ECC modules
in
128M × 72 (1GB) in organization and density, intended for
mounting into 240-pin connector sockets.
TABLE 2
Ordering Information
Product Type1)
Compliance Code2)
Description
SDRAM Technology
PC2-6400 (5-5-5)
HYS64T256020EU–25F–B2
HYS64T128000EU–25F–B2
HYS72T128000EU–25F–B2
PC2-6400 (6-6-6)
2GB 2R×8 PC2–6400U–555–12–E0
1GB 1R×8 PC2–6400U–555–12–D0
1GB 1R×8 PC2–6400E–555–12–F0
2 Ranks, Non-ECC 1Gbit (×8)
1 Rank, Non-ECC 1Gbit (×8)
1 Rank, ECC
1Gbit (×8)
HYS64T256020EU–2.5–B2
HYS64T128000EU–2.5–B2
HYS72T128000EU–2.5–B2
PC2-5300 (5-5-5)
2GB 2R×8 PC2–6400U–666–12–E0
1GB 1R×8 PC2–6400U–666–12–D0
1GB 1R×8 PC2–6400E–666–12–F0
2 Ranks, Non-ECC 1Gbit (×8)
1 Rank, Non-ECC 1Gbit (×8)
1 Rank, ECC
1Gbit (×8)
HYS64T256020EU–3S–B2
HYS64T128000EU–3S–B2
HYS72T128000EU–3S–B2
2GB 2R×8 PC2–5300U–555–12–E0
1GB 1R×8 PC2–5300U–555–12–D0
1GB 1R×8 PC2–5300E–555–12–F0
2 Ranks, Non-ECC 1Gbit (×8)
1 Rank, Non-ECC 1Gbit (×8)
1 Rank, ECC
1Gbit (×8)
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this datasheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400E–555–12–F0" where 6400E
means Unbuffered DIMM modules with 6.40 GB/sec Module Bandwidth and "555–12" means Column Address Strobe (CAS) latency =5,
Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the latest JEDEC SPD Revision 1.2 and produced on
the Raw Card "F".
TABLE 3
Address Format
DIMM
Density
Module
Organization
Memory
Ranks
ECC/
Non-ECC
# of SDRAMs # of row/bank/column
bits
Raw
Card
2GB
1GB
1GB
256M × 64
128M × 64
128M × 72
2
1
1
Non-ECC
Non-ECC
ECC
16
8
14/3/10
14/3/10
14/3/10
E
D
F
9
Rev. 0.50, 2008-01
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01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
TABLE 4
Components on Modules
Product Type1)2)
DRAM Components1)
DRAM Density
DRAM Organisation
HYS64T256020EU
HYS64T128000EU
HYB18T1G800B2F
HYB18T1G800B2F
HYB18T1G800B2F
1Gbit
1Gbit
1Gbit
128M × 8
128M × 8
128M × 8
HYS72T128000EU
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 0.50, 2008-01
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01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
2
Pin Configurations
2.1
Pin Configurations
The pin configuration of the Unbuffered DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations used
in columns Pin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1
for non-ECC modules (×64) and Figure 2 for ECC modules (×72).
TABLE 5
Pin Configuration of UDIMM
Ball No.
Name Pin
Buffer Function
Type Type
Clock Signals
185
137
220
186
138
221
52
CK0
CK1
CK2
CK0
CK1
CK2
CKE0
CKE1
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Clock Signals 2:0, Complement Clock Signals 2:0
The system clock inputs. All address and command lines are sampled on the
cross point of the rising edge of CK and the falling edge of CK. A Delay
Locked Loop (DLL) circuit is driven from the clock inputs and output timing for
read operations is synchronized to the input clock.
Clock Enable Rank 1:0
Activates the DDR2 SDRAM CK signal when HIGH and deactivates the CK
signal when LOW. By deactivating the clocks, CKE LOW initiates the Power
Down Mode or the Self Refresh Mode.
171
Note: 2 Ranks module
Not Connected
NC
NC
—
Note: 1 Rank module
Control Signals
193
76
S0
S1
I
I
SSTL
SSTL
Chip Select Rank 1:0
Enables the associated DDR2 SDRAM command decoder when LOW and
disables the command decoder when HIGH. When the command decoder is
disabled, new commands are ignored but previous operations continue. Rank
0 is selected by S0; Rank 1 is selected by S1. Ranks are also called "Physical
banks".
Note: 2 Ranks module
Not Connected
NC
NC
I
—
Note: 1 Rank module
192
74
RAS
SSTL
Row Address Strobe
When sampled at the cross point of the rising edge of CK,and falling edge of
CK, RAS, CAS and WE define the operation to be executed by the SDRAM.
CAS
I
SSTL
Column Address Strobe
Rev. 0.50, 2008-01
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01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
Ball No.
Name Pin
Buffer Function
Type Type
73
WE
I
SSTL
Write Enable
Address Signals
71
BA0
BA1
BA2
I
I
I
SSTL
SSTL
SSTL
Bank Address Bus 1:0
Selects which DDR2 SDRAM internal bank of four or eight is activated.
190
54
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
NC
NC
—
Not Connected
Less than 1Gb DDR2 SDRAMS
188
183
63
A0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Address Bus 12:0
During a Bank Activate command cycle, defines the row address when
sampled at the crosspoint of the rising edge of CK and falling edge of CK.
During a Read or Write command cycle, defines the column address when
sampled at the cross point of the rising edge of CK and falling edge of CK. In
addition to the column address, AP is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If AP is HIGH, autoprecharge is
selected and BA0-BAn defines the bank to be precharged. If AP is LOW,
autoprecharge is disabled. During a Precharge command cycle, AP is used
in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is
HIGH, all banks will be precharged regardless of the state of BA0-BAn inputs.
If AP is LOW, then BA0-BAn are used to define which bank to precharge.
A1
A2
182
61
A3
A4
60
A5
180
58
A6
A7
179
177
70
A8
A9
A10
AP
A11
A12
A13
57
176
196
Address Signal 13
Note: 1 Gbit based module and 512M ×4/×8
Not Connected
NC
A14
NC
NC
I
—
Note: Module based on 1 Gbit ×16Module based on 512 Mbit ×16 or smaller
Address Signal 14
174
SSTL
—
Note: Modules based on 2 Gbit
Not Connected
NC
Note: Modules based on 1 Gbit or smaller
Data Signals
3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
Data Input / Output pins
4
9
10
122
123
128
129
Rev. 0.50, 2008-01
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01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
Ball No.
Name Pin
Buffer Function
Type Type
12
DQ8
DQ9
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
Data Input / Output pins
13
21
DQ10 I/O
DQ11 I/O
DQ12 I/O
DQ13 I/O
DQ14 I/O
DQ15 I/O
DQ16 I/O
DQ17 I/O
DQ18 I/O
DQ19 I/O
DQ20 I/O
DQ21 I/O
DQ22 I/O
DQ23 I/O
DQ24 I/O
DQ25 I/O
DQ26 I/O
DQ27 I/O
DQ28 I/O
DQ29 I/O
DQ30 I/O
DQ31 I/O
DQ32 I/O
DQ33 I/O
DQ34 I/O
DQ35 I/O
DQ36 I/O
DQ37 I/O
DQ38 I/O
DQ39 I/O
DQ40 I/O
DQ41 I/O
DQ42 I/O
DQ43 I/O
DQ44 I/O
DQ45 I/O
DQ46 I/O
DQ47 I/O
22
131
132
140
141
24
25
30
31
143
144
149
150
33
34
39
40
152
153
158
159
80
81
86
87
199
200
205
206
89
90
95
96
208
209
214
215
Rev. 0.50, 2008-01
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01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
Ball No.
Name Pin
Buffer Function
Type Type
98
DQ48 I/O
DQ49 I/O
DQ50 I/O
DQ51 I/O
DQ52 I/O
DQ53 I/O
DQ54 I/O
DQ55 I/O
DQ56 I/O
DQ57 I/O
DQ58 I/O
DQ59 I/O
DQ60 I/O
DQ61 I/O
DQ62 I/O
DQ63 I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Bus 63:0
Data Input / Output pins
99
107
108
217
218
226
227
110
111
116
117
229
230
235
236
Check Bit Signals
42
CB0
NC
I/O
NC
I/O
NC
I/O
NC
I/O
NC
I/O
NC
I/O
NC
SSTL
—
Check Bit 0
Note: ECC type module only
Not Connected
Note: Non-ECC type module only
Check Bit 1
43
CB1
NC
SSTL
—
Note: ECC type module only
Not Connected
Note: Non-ECC type module only
Check Bit 2
48
CB2
NC
SSTL
—
Note: ECC type module only
Not Connected
Note: Non-ECC type module only
Check Bit 3
49
CB3
NC
SSTL
—
Note: ECC type module only
Not Connected
Note: Non-ECC type module only
Check Bit 4
161
162
CB4
NC
SSTL
—
Note: ECC type module only
Not Connected
Note: Non-ECC type module only
Check Bit 5
CB5
NC
SSTL
—
Note: ECC type module only
Not Connected
Note: Non-ECC type module only
Rev. 0.50, 2008-01
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01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
Ball No.
Name Pin
Buffer Function
Type Type
167
CB6
NC
I/O SSTL
Check Bit 6
Note: ECC type module only
Not Connected
NC
—
Note: Non-ECC type module only
Check Bit 7
168
CB7
NC
I/O
NC
SSTL
—
Note: ECC type module only
Not Connected
Note: Non-ECC module only
Data Strobe Bus
7
DQS0 I/O
DQS1 I/O
DQS2 I/O
DQS3 I/O
DQS4 I/O
DQS5 I/O
DQS6 I/O
DQS7 I/O
DQS8 I/O
DQS0 I/O
DQS1 I/O
DQS2 I/O
DQS3 I/O
DQS4 I/O
DQS5 I/O
DQS6 I/O
DQS7 I/O
DQS8 I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Strobe Bus 8:0
The data strobes, associated with one data byte, sourced with data transfers.
In Write mode, the data strobe is sourced by the controller and is centered in
the data window. In Read mode the data strobe is sourced by the DDR2
SDRAM and is sent at the leading edge of the data window. DQS signals are
complements, and timing is relative to the crosspoint of respective DQS and
DQS. If the module is to be operated in single ended strobe mode, all DQS
signals must be tied on the system board to VSS and DDR2 SDRAM mode
registers programmed appropriately.
16
28
37
84
93
105
114
46
6
Complement Data Strobe Bus 8:0
15
27
36
83
92
104
113
45
Data Mask Signals
125
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Mask Bus 8:0
The data write masks, associated with one data byte. In Write mode, DM
operates as a byte mask by allowing input data to be written if it is LOW but
blocks the write operation if it is HIGH. In Read mode, DM lines have no effect.
134
146
155
202
211
223
232
164
EEPROM
120
SCL
I
CMOS Serial Bus Clock
This signal is used to clock data into and out of the SPD EEPROM.
Rev. 0.50, 2008-01
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01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
Ball No.
Name Pin
Buffer Function
Type Type
119
SDA
I/O
OD
Serial Bus Data
This is a bidirectional pin used to transfer data into or out of the SPD
EEPROM. A resistor must be connected from SDA to VDDSPD on the
motherboard to act as a pull-up.
239
SA0
SA1
SA2
I
I
I
CMOS Serial Address Select Bus 2:0
Address pins used to select the Serial Presence Detect base address.
240
CMOS
101
CMOS
Power Supplies
1
VREF
AI
—
—
I/O Reference Voltage
Reference voltage for the SSTL-18 inputs.
238
VDDSPD PWR
EEPROM Power Supply
Power supplies for core, I/O, Serial Presence Detect, and ground for the
module.
51,56,62,72,75,,
78,170,175,181,,
191,194
VDDQ
VDD
VSS
PWR
PWR
GND
—
—
—
I/O Driver Power Supply
53,59,64,67,69,,
172,178,184,187,
189,197
Power Supply
Power supplies for core, I/O, Serial Presence Detect, and ground for the
module.
2,5,8,11,14,17,,
20,23,26,29,32,
35,38,41,44,47,,
50,65,66,79,82,
85,88,91,94,97,,
100,103,106,
Ground Plane
Power supplies for core, I/O, Serial Presence Detect, and ground for the
module.
109,112,115,118,
121,124,127,,
130,133,136,139,
142,145,148,,
151,154,157,160,
163,166,169,
198,201,204,207,
210,213,216,,
219,222,225,228,
231,234,237
Other Pins
195
77
ODT0
ODT1
I
I
SSTL
SSTL
On-Die Termination Control 0
On-Die Termination Control 1
Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via
the DDR2 SDRAM mode register.
Note: 2 Rank modules
NC
NC
NC
—
—
Not Connected
Note: 1 Rank modules
18,19,55,68,102,1 NC
26,135,147,
Not connected
Note: Pins not connected on Qimonda UDIMMs
156,165,173,203,
212, 224,233
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Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
TABLE 6
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NC
Ground
Not Connected
TABLE 7
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
LV-CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tri-state,
and allows multiple devices to share as a wire-OR.
Rev. 0.50, 2008-01
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01282008-JC1K-XBCR
9ꢀ
66ꢀ
ꢄꢀ3
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
Qꢀ
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3
3
3
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Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
FIGURE 1
Pin Configuration UDIMM ×72 (240 Pin)
9
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9ꢀ
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4
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L
L
L
L
L
L
L
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L
L
L
L
L
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L
L
L
L
L
L
L
L
L
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L
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3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
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3
3
3
3
3
3
3
3
3
3
3
L
L
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3
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3
3
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Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
FIGURE 2
Pin Configuration UDIMM ×64 (240 Pin)
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Rev. 0.50, 2008-01
01282008-JC1K-XBCR
14
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
3
Electrical Characteristics
This chapter contains speed grade definition, AC timing parameter and ODT tables.
3.1
Absolute Maximum Ratings
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 8
Absolute Maximum Ratings
Symbol
Parameter
Rating
Min.
Unit
Note
Max.
1)
VDD
Voltage on VDD pin relative to VSS
Voltage on VDDQ pin relative to VSS
Voltage on VDDL pin relative to VSS
Voltage on any pin relative to VSS
–1.0
–0.5
–0.5
–0.5
+2.3
+2.3
+2.3
+2.3
V
V
V
V
VDDQ
VDDL
VIN, VOUT
1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
TABLE 9
Environmental Requirements
Parameter
Symbol
Values
Min.
Unit
Note
Max.
1)
2)
3)
Operating temperature (ambient)
Storage Temperature
TOPR
TSTG
PBar
HOPR
HSTG
0
+55
+100
+105
90
°C
°C
kPa
%
– 50
+69
10
5
Barometric Pressure (operating & storage)
Operating Humidity (relative)
Storage Humidity (without condensation)
95
%
1) The component maximum case temperature (Tcase) shall not exceed the value specified in the DDR2 DRAM component specification.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
3) Up to 3000 m.
Rev. 0.50, 2008-01
15
01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
TABLE 10
DRAM Component Operating Temperature Range
Symbol
Parameter
Rating
Unit
Note
Min.
Max.
1)2)3)4)
TCASE
Operating Temperature
0
95
°C
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case
temperature must be maintained between 0 - 95 °C under all other specification parameters.
3) Above 85 °C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 µs
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%
3.2
DC Operating Conditions
TABLE 11
Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Values
Min.
Unit
Note
Typ.
Max.
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
SPD Supply Voltage
VDD
1.7
1.8
1.9
V
1)
2)
VDDQ
VREF
1.7
1.8
1.9
V
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
V
VDDSPD
VIH(DC)
VIL (DC
IL
1.7
—
—
—
—
3.6
V
DC Input Logic High
V
REF + 0.125
V
V
5
DDQ + 0.3
V
DC Input Logic Low
)
– 0.30
– 5
REF – 0.125
V
3)
In / Output Leakage Current
µA
1) Under all conditions, VDDQ must be less than or equal to VDD
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise in VDDQ
3) Input voltage for any connector pin under test of 0 V ≤ VIN ≤ VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
.
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Unbuffered DDR2 SDRAM Modules
3.3
Speed Grade Definitions
TABLE 12
Speed Grade Definition
Speed Grade
DDR2–800D
–25F
DDR2–800E
–2.5
Unit
Note
QAG Sort Name
CAS-RCD-RP latencies
Parameter
5–5–5
Min.
6–6–6
tCK
Symbol
Max.
Min.
Max.
—
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Period
@ CL = 3
tCK
5
8
5
8
ns
ns
ns
ns
ns
ns
ns
ns
@ CL = 4
@ CL = 5
@ CL = 6
tCK
3.75
2.5
2.5
45
8
3.75
3
8
tCK
8
8
tCK
8
2.5
45
60
15
15
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
tRAS
tRC
tRCD
tRP
70k
—
—
—
70k
—
—
—
57.5
12.5
12.5
Row Precharge Time
TABLE 13
Speed Grade Definition
Speed Grade
DDR2–667D
–3S
Unit
Note
QAG Sort Name
CAS-RCD-RP latencies
Parameter
5–5–5
tCK
Symbol
Min.
Max.
—
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Period
@ CL = 3
tCK
5
8
ns
ns
ns
ns
ns
ns
ns
@ CL = 4
@ CL = 5
tCK
3.75
3
8
tCK
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
45
60
15
15
70k
—
—
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI
.
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Unbuffered DDR2 SDRAM Modules
3.4
Component AC Timing Parameters
TABLE 14
DRAM Component Timing Parameter by Speed Grade - DDR2–800 and DDR2–667
Parameter
Symbol DDR2–800
DDR2–667
Unit
Note1)2)3
)4)5)6)7)
Min.
Max.
Min.
Max.
CAS to CAS command delay
Average clock high pulse width
Average clock period
tCCD
2
—
2
—
nCK
tCK.AVG
ps
9)10)
11)
tCH.AVG
tCK.AVG
0.48
2500
3
0.52
8000
—
0.48
3000
3
0.52
8000
—
CKE minimum pulse width ( high and tCKE
nCK
low pulse width)
9)10)
Average clock low pulse width
tCL.AVG
tDAL
0.48
0.52
—
0.48
0.52
—
tCK.AVG
12)13)
Auto-Precharge write recovery +
precharge time
WR + tnRP
WR + tnRP
nCK
Minimum time clocks remain ON after tDELAY
CKE asynchronously drops LOW
tIS + tCK .AVG ––
+ tIH
tIS +
tCK .AVG + tIH
––
ns
14)18)19)
DQ and DM input hold time
tDH.BASE
125
––
—
175
––
—
ps
DQ and DM input pulse width for each tDIPW
0.35
0.35
tCK.AVG
input
DQS input high pulse width
DQS input low pulse width
tDQSH
tDQSL
0.35
0.35
—
—
0.35
0.35
—
—
tCK.AVG
tCK.AVG
ps
—
—
15)
16)
DQS-DQ skew for DQS & associated tDQSQ
200
240
DQ signals
DQS latching rising transition to
associated clock edges
tDQSS
– 0.25
+ 0.25
– 0.25
+ 0.25
tCK.AVG
17)18)19)
16)
DQ and DM input setup time
tDS.BASE
50
––
—
—
—
100
0.2
––
—
—
—
ps
DQS falling edge hold time from CK tDSH
DQS falling edge to CK setup time tDSS
0.2
0.2
35
tCK.AVG
tCK.AVG
ns
16)
0.2
34)
Four Activate Window for 1KB page tFAW
37.5
size products
20)
CK half pulse width
tHP
Min(tCH.ABS
,
__
Min(tCH.ABS
tCL.ABS)
,
__
ps
ps
tCL.ABS
)
8)21)
22)24)
Data-out high-impedance time from tHZ
CK / CK
—
tAC.MAX
—
tAC.MAX
Address and control input hold time tIH.BASE
250
0.6
—
—
275
0.6
—
—
ps
Control & address input pulse width tIPW
tCK.AVG
for each input
23)24)
8)21)
8)21)
Address and control input setup time tIS.BASE
DQ low impedance time from CK/CK tLZ.DQ
175
—
200
—
ps
ps
ps
2 x tAC.MIN
tAC.MAX
tAC.MAX
2 x tAC.MIN
tAC.MAX
tAC.MAX
DQS/DQS low-impedance time from tLZ.DQS
tAC.MIN
tAC.MIN
CK / CK
34)
MRS command to ODT update delay tMOD
0
12
0
12
ns
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Parameter
Symbol DDR2–800
Min.
DDR2–667
Unit
Note1)2)3
)4)5)6)7)
Max.
Min.
Max.
Mode register set command cycle
time
tMRD
2
—
2
—
nCK
34)
OCD drive mode output delay
tOIT
0
12
0
12
ns
ps
ps
µs
µs
ns
25)
DQ/DQS output hold time from DQS tQH
t
HP – tQHS
—
t
HP – tQHS
—
26)
DQ hold skew factor
tQHS
tREFI
—
300
7.8
3.9
—
—
340
7.8
3.9
—
27)28)
27)29)
30)
Average periodic refresh Interval
—
—
—
—
Auto-Refresh to Active/Auto-Refresh tRFC
127.5
127.5
command period
31)32)
31)33)
34)
Read preamble
Read postamble
tRPRE
tRPST
0.9
0.4
7.5
1.1
0.6
—
0.9
0.4
7.5
1.1
0.6
—
tCK.AVG
tCK.AVG
ns
Active to active command period for tRRD
1KB page size products
34)
Internal Read to Precharge command tRTP
7.5
—
7.5
—
ns
delay
Write preamble
tWPRE
tWPST
tWR
0.35
0.4
—
0.6
—
—
—
—
0.35
0.4
—
0.6
—
—
—
—
tCK.AVG
tCK.AVG
ns
Write postamble
Write recovery time
34)
15
15
34)35)
Internal write to read command delay tWTR
Exit power down to read command tXARD
7.5
7.5
ns
2
2
nCK
nCK
Exit active power-down mode to read tXARDS
8 – AL
7 – AL
command (slow exit, lower power)
Exit precharge power-down to any
valid command (other than NOP or
Deselect)
tXP
2
—
2
—
nCK
ns
34)
Exit self-refresh to a non-read
command
tXSNR
t
RFC +10
—
—
t
RFC +10
—
—
Exit self-refresh to read command
tXSRD
200
200
nCK
nCK
Write command to DQS associated
clock edges
WL
RL – 1
RL–1
1) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V.
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
6) The output timing reference voltage level is VTT.
7) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min)
.
8) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272
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ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and
t
DQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
9) Input clock jitter spec parameter. The jitter specified is a random jitter meeting a Gaussian distribution.
10) These parameters are specified per their average values.
11) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2 x tCK + tIH.
12) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result
of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For
DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
13) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR.
14) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and
VIH.DC.MIN. See Figure 4.
15) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
16) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
17) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See
Figure 4.
18) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
19) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
20) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter.
It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the
following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the
minimum of the actual instantaneous clock low time.
21) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) .
22) input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied
to the device under test. See Figure 5.
23) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied
to the device under test. See Figure 5.
24) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC
,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
25) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under
the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}
Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system
provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
26) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
27) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
28) 0 °C≤ TCASE ≤ 85 °C.
29) 85 °C < TCASE ≤ 95 °C.
30) A maximum of eight Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between
any Refresh command and the next Refresh command is 9 x tREFI
.
31) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(tRPST), or begins driving (tRPRE). Figure 3 shows a method to calculate these points when the device is no longer driving (tRPST), or begins
Rev. 0.50, 2008-01
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Unbuffered DDR2 SDRAM Modules
driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
32) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps
and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX
+ tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps
and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+ tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
34) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support
t
nRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
35) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
36) This timing parameter is relaxed than Industry Standard
FIGURE 3
Method for Calculating Transitions and Endpoint
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FIGURE 4
Differential Input Waveform Timing tDS and tDH
'46
'46
W'6
W'6
W'+
W'+
9''4
'4
9,+ꢍ$&ꢍ0,1
9,+ꢍ'&ꢍ0,1
95()
9,/ꢍ'&ꢍ0$;
9,/ꢍ$&ꢍ0$;
966
03(7ꢁꢅꢅꢂ
FIGURE 5
Differential Input Waveform Timing tlS and tlH
&.
&.
W,6
W,+
W,6
W,+
9''4
9,+ꢍ$&ꢍ0,1
&0'
$GGUHVV
9,+ꢍ'&ꢍ0,1
95()
9,/ꢍ'&ꢍ0$;
9,/ꢍ$&ꢍ0$;
966
03(7ꢁꢉꢉꢁ
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Unbuffered DDR2 SDRAM Modules
3.5
ODT AC Electrical Characteristics
This chapter describes the ODT AC electrical characteristics.
TABLE 15
ODT AC Characteristics and Operating Conditions for DDR2-667 , DDR2-800
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
1)
tAOND
tAON
ODT turn-on delay
2
2
nCK
ns
1)2)
1)
ODT turn-on
tAC.MIN
tAC.MAX + 0.7 ns
tAONPD
tAOFD
tAOF
ODT turn-on (Power-Down Modes)
ODT turn-off delay
tAC.MIN + 2 ns
2 tCK + tAC.MAX + 1 ns
ns
1)
2.5
2.5
nCK
ns
1)3)
1)
ODT turn-off
tAC.MIN
tAC.MAX + 0.6 ns
tAOFPD
tANPD
tAXPD
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
tAC.MIN + 2 ns
2.5 tCK + tAC.MAX + 1 ns ns
1)
3
8
—
—
nCK
nCK
1)
1) New units, “tCK.AVG” and “nCK”, are introduced in DDR2-667 and DDR2-800 Unit “tCK.AVG” represents the actual tCK.AVG of the input clock
under operation. Unit “nCK” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
DDR2-533, “tCK” is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may
be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min)
.
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-667/800 tAOND is
2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-667/800, if tCK(avg) = 3 ns is assumed,
tAOFD is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by
counting the actual input clock edges.
Rev. 0.50, 2008-01
23
01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
3.6
IDD Specifications and Conditions
List of tables defining IDD Specifications and Conditions.
TABLE 16
DD Measurement Conditions
I
Parameter
Symbol Note1)2)
3)4)5)
Operating Current 0
IDD0
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
6)
Operating Current 1
IDD1
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN
,
t
RCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Standby Current
IDD2N
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING,
Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2P
IDD2Q
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
Active Standby Current
IDD3N
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN
;
t
RAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
Active Power-Down Current
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
IDD3P(0)
IDD3P(1)
IDD4R
Active Power-Down Current
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
6)
Operating Current - Burst Read
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCKMIN; tRAS = tRASMAX
;
t
RP = tRPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data
bus inputs are SWITCHING; IOUT = 0mA.
Operating Current - Burst Write
IDD4W
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN
;
t
RAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
IDD5B
t
CK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Distributed Refresh Current
IDD5D
t
CK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Rev. 0.50, 2008-01
24
01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
Parameter
Symbol Note1)2)
3)4)5)
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data
bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 °C max.
6)
All Bank Interleave Read Current
IDD7
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1)
2)
V
DDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
3) Definitions for IDD see Table 17
4) For two rank modules: All active current measurements in the same IDD current mode. The other rank is in IDD2P Precharge Power-Down
Mode.
5) For details and notes see the relevant Qimonda component data sheet.
6)
IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
TABLE 17
Definitions for IDD
Parameter
LOW
Description
VIN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN
Inputs are stable at a HIGH or LOW level.
Inputs are VREF = VDDQ /2
STABLE
FLOATING
SWITCHING
Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes.
Rev. 0.50, 2008-01
25
01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
TABLE 18
I
DD Specification for HYS[64/72]T[128/256]0x0EU–25F–B2
Product Type
Unit
Note1)
Organization
1GB
1GB
2GB
1 Rank (×8)
×64
1 Rank (×8)
×72
2 Ranks (×8)
×64
-25F
-25F
-25F
Symbol
Max.
Max.
Max.
2)
IDD0
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
2)
IDD1
3)
IDD2N
3)
IDD2P
3)
IDD2Q
IDD3N
3)
3)4)
3)5)
2)
IDD3P_0 (fast)
IDD3P_1 (slow)
IDD4R
2)
IDD4W
IDD5B
2)
3)6)
3)6)
2)
IDD5D
IDD6
IDD7
1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode.
3) Both ranks are in the same IDDcurrent mode.
4) Fast: MRS(12)=0
5) Slow: MRS(12)=1
6)
IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 0.50, 2008-01
26
01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
TABLE 19
DD Specification for HYS[64/72]T[128/256]0x0EU–2.5–B2
I
Product Type
Unit
Note1)
Organization
1GB
1GB
2GB
1 Rank (×8)
×64
1 Rank (×8)
×72
2 Ranks (×8)
×64
-2.5
-2.5
-2.5
Symbol
Max.
Max.
Max.
2)
IDD0
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
2)
IDD1
3)
IDD2N
3)
IDD2P
3)
IDD2Q
IDD3N
3)
3)4)
3)5)
2)
IDD3P_0 (fast)
IDD3P_1 (slow)
IDD4R
2)
IDD4W
IDD5B
2)
3)6)
3)6)
2)
IDD5D
IDD6
IDD7
1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode.
3) Both ranks are in the same IDDcurrent mode.
4) Fast: MRS(12)=0
5) Slow: MRS(12)=1
6)
IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 0.50, 2008-01
27
01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
TABLE 20
DD Specification for HYS[64/72]T[128/256]0x0EU–3S–B2
I
Product Type
Unit
Note1)
Organization
1GB
1GB
2GB
1 Rank (×8)
×64
1 Rank (×8)
×72
2 Ranks (×8)
×64
-3S
-3S
-3S
Symbol
Max.
Max.
Max.
2)
IDD0
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
2)
IDD1
3)
IDD2N
3)
IDD2P
3)
IDD2Q
IDD3N
3)
3)4)
3)5)
2)
IDD3P_0 (fast)
IDD3P_1 (slow)
IDD4R
2)
IDD4W
IDD5B
2)
3)6)
3)6)
2)
IDD5D
IDD6
IDD7
1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Current mode.
3) Both ranks are in the same IDDcurrent mode.
4) Fast: MRS(12)=0
5) Slow: MRS(12)=1
6)
IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 0.50, 2008-01
28
01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
•
•
•
Table 21 “HYS64T128000EU-[25F/2.5/3S]-B2” on Page 29
Table 22 “HYS72T128000EU-[25F/2.5/3S]-B2” on Page 34
Table 23 “HYS64T256020EU-[25F/2.5/3S]-B2” on Page 38
TABLE 21
HYS64T128000EU-[25F/2.5/3S]-B2
Product Type
Organization
1 GByte
×64
1 GByte
×64
1 GByte
×64
1 Rank (×8)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–6400U–555 PC2–6400U–666 PC2–5300U–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0E
0A
60
40
00
05
25
40
00
82
80
08
08
0E
0A
60
40
00
05
25
40
00
82
80
08
08
0E
0A
60
40
00
05
30
45
00
82
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Rev. 0.50, 2008-01
29
01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
Product Type
Organization
1 GByte
×64
1 GByte
×64
1 GByte
×64
1 Rank (×8)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–6400U–555 PC2–6400U–666 PC2–5300U–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Primary SDRAM Width
Error Checking SDRAM Width
Not used
08
00
00
0C
08
70
01
02
00
07
25
40
3D
50
32
1E
32
2D
01
17
25
05
12
3C
1E
1E
08
00
00
0C
08
70
01
02
00
07
30
45
3D
50
3C
1E
3C
2D
01
17
25
05
12
3C
1E
1E
08
00
00
0C
08
38
01
02
00
07
3D
50
50
60
3C
1E
3C
2D
01
20
27
10
17
3C
1E
1E
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Rev. 0.50, 2008-01
30
01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
Product Type
Organization
1 GByte
×64
1 GByte
×64
1 GByte
×64
1 Rank (×8)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–6400U–555 PC2–6400U–666 PC2–5300U–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Analysis Characteristics
00
06
39
7F
80
14
1E
00
51
60
4F
3D
3D
2C
35
24
46
24
27
00
00
00
00
12
49
7F
00
06
3C
7F
80
14
1E
00
51
60
4F
3D
3D
2C
35
24
46
24
27
00
00
00
00
12
70
7F
00
06
3C
7F
80
18
22
00
51
60
47
39
3D
28
31
24
3E
22
23
00
00
00
00
12
84
7F
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
T
Psi(T-A) DRAM
∆T0 (DT0)
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Rev. 0.50, 2008-01
31
01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
Product Type
Organization
1 GByte
×64
1 GByte
×64
1 GByte
×64
1 Rank (×8)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–6400U–555 PC2–6400U–666 PC2–5300U–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
7F
7F
7F
7F
51
00
00
xx
7F
7F
7F
7F
51
00
00
xx
7F
7F
7F
7F
51
00
00
xx
36
34
54
31
32
38
30
30
30
45
55
32
35
46
42
32
20
20
36
34
54
31
32
38
30
30
30
45
55
32
2E
35
42
32
20
20
36
34
54
31
32
38
30
30
30
45
55
33
53
42
32
20
20
20
Product Type, Char 2
Product Type, Char 3
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Rev. 0.50, 2008-01
32
01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
Product Type
Organization
1 GByte
×64
1 GByte
×64
1 GByte
×64
1 Rank (×8)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–6400U–555 PC2–6400U–666 PC2–5300U–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
91
92
93
94
Module Revision Code
0x
xx
xx
xx
xx
00
FF
0x
xx
xx
xx
xx
00
FF
0x
xx
xx
xx
xx
00
FF
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
128 -
255
Blank for customer use
Rev. 0.50, 2008-01
33
01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
TABLE 22
HYS72T128000EU-[25F/2.5/3S]-B2
Product Type
Organization
1 GByte
×72
1 GByte
×72
1 GByte
×72
1 Rank (×8)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–6400E–555 PC2–6400E–666 PC2–5300E–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0E
0A
60
48
00
05
25
40
02
82
08
08
00
0C
08
70
01
02
00
07
80
08
08
0E
0A
60
48
00
05
25
40
02
82
08
08
00
0C
08
70
01
02
00
07
80
08
08
0E
0A
60
48
00
05
30
45
02
82
08
08
00
0C
08
38
01
02
00
07
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
Rev. 0.50, 2008-01
34
01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
Product Type
Organization
1 GByte
×72
1 GByte
×72
1 GByte
×72
1 Rank (×8)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–6400E–555 PC2–6400E–666 PC2–5300E–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
25
40
3D
50
32
1E
32
2D
01
17
25
05
12
3C
1E
1E
00
06
39
7F
80
14
1E
00
51
60
30
45
3D
50
3C
1E
3C
2D
01
17
25
05
12
3C
1E
1E
00
06
3C
7F
80
14
1E
00
51
60
3D
50
50
60
3C
1E
3C
2D
01
20
27
10
17
3C
1E
1E
00
06
3C
7F
80
18
22
00
51
60
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
Psi(T-A) DRAM
T
Rev. 0.50, 2008-01
35
01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
Product Type
Organization
1 GByte
×72
1 GByte
×72
1 GByte
×72
1 Rank (×8)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–6400E–555 PC2–6400E–666 PC2–5300E–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
∆T0 (DT0)
4F
3D
3D
2C
35
24
46
24
27
00
00
00
00
12
5B
7F
7F
7F
7F
7F
51
00
00
xx
4F
3D
3D
2C
35
24
46
24
27
00
00
00
00
12
82
7F
7F
7F
7F
7F
51
00
00
xx
47
39
3D
28
31
24
3E
22
23
00
00
00
00
12
96
7F
7F
7F
7F
7F
51
00
00
xx
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
37
32
37
32
37
32
Product Type, Char 2
Rev. 0.50, 2008-01
36
01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
Product Type
Organization
1 GByte
×72
1 GByte
×72
1 GByte
×72
1 Rank (×8)
1 Rank (×8)
1 Rank (×8)
Label Code
PC2–6400E–555 PC2–6400E–666 PC2–5300E–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Product Type, Char 3
54
31
32
38
30
30
30
45
55
32
35
46
42
32
20
20
0x
xx
xx
xx
xx
00
FF
54
31
32
38
30
30
30
45
55
32
2E
35
42
32
20
20
0x
xx
xx
xx
xx
00
FF
54
31
32
38
30
30
30
45
55
33
53
42
32
20
20
20
0x
xx
xx
xx
xx
00
FF
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
128 -
255
Blank for customer use
Rev. 0.50, 2008-01
37
01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
TABLE 23
HYS64T256020EU-[25F/2.5/3S]-B2
Product Type
Organization
2 GByte
×64
2 GByte
×64
2 GByte
×64
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–6400U–555 PC2–6400U–666 PC2–5300U–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
0
Programmed SPD Bytes in EEPROM
Total number of Bytes in EEPROM
Memory Type (DDR2)
80
08
08
0E
0A
61
40
00
05
25
40
00
82
08
00
00
0C
08
70
01
02
00
07
80
08
08
0E
0A
61
40
00
05
25
40
00
82
08
00
00
0C
08
70
01
02
00
07
80
08
08
0E
0A
61
40
00
05
30
45
00
82
08
00
00
0C
08
38
01
02
00
07
1
2
3
Number of Row Addresses
Number of Column Addresses
DIMM Rank and Stacking Information
Data Width
4
5
6
7
Not used
8
Interface Voltage Level
9
t
t
CK @ CLMAX (Byte 18) [ns]
10
11
12
13
14
15
16
17
18
19
20
21
22
AC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC)
Refresh Rate and Type
Primary SDRAM Width
Error Checking SDRAM Width
Not used
Burst Length Supported
Number of Banks on SDRAM Device
Supported CAS Latencies
DIMM Mechanical Characteristics
DIMM Type Information
DIMM Attributes
Component Attributes
Rev. 0.50, 2008-01
38
01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
Product Type
Organization
2 GByte
×64
2 GByte
×64
2 GByte
×64
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–6400U–555 PC2–6400U–666 PC2–5300U–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
t
t
t
t
t
t
t
t
CK @ CLMAX -1 (Byte 18) [ns]
AC SDRAM @ CLMAX -1 [ns]
CK @ CLMAX -2 (Byte 18) [ns]
AC SDRAM @ CLMAX -2 [ns]
RP.MIN [ns]
25
40
3D
50
32
1E
32
2D
01
17
25
05
12
3C
1E
1E
00
06
39
7F
80
14
1E
00
51
60
30
45
3D
50
3C
1E
3C
2D
01
17
25
05
12
3C
1E
1E
00
06
3C
7F
80
14
1E
00
51
60
3D
50
50
60
3C
1E
3C
2D
01
20
27
10
17
3C
1E
1E
00
06
3C
7F
80
18
22
00
51
60
RRD.MIN [ns]
RCD.MIN [ns]
RAS.MIN [ns]
Module Density per Rank
t
t
t
t
t
t
t
AS.MIN and tCS.MIN [ns]
AH.MIN and tCH.MIN [ns]
DS.MIN [ns]
DH.MIN [ns]
WR.MIN [ns]
WTR.MIN [ns]
RTP.MIN [ns]
Analysis Characteristics
t
t
t
t
t
t
RC and tRFC Extension
RC.MIN [ns]
RFC.MIN [ns]
CK.MAX [ns]
DQSQ.MAX [ns]
QHS.MAX [ns]
PLL Relock Time
CASE.MAX Delta / ∆T4R4W Delta
Psi(T-A) DRAM
T
Rev. 0.50, 2008-01
39
01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
Product Type
Organization
2 GByte
×64
2 GByte
×64
2 GByte
×64
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–6400U–555 PC2–6400U–666 PC2–5300U–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
∆T0 (DT0)
4F
3D
3D
2C
35
24
46
24
27
00
00
00
00
12
4A
7F
7F
7F
7F
7F
51
00
00
xx
4F
3D
3D
2C
35
24
46
24
27
00
00
00
00
12
71
7F
7F
7F
7F
7F
51
00
00
xx
47
39
3D
28
31
24
3E
22
23
00
00
00
00
12
85
7F
7F
7F
7F
7F
51
00
00
xx
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
∆T2P (DT2P)
∆T3N (DT3N)
∆T3P.fast (DT3P fast)
∆T3P.slow (DT3P slow)
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
∆T5B (DT5B)
∆T7 (DT7)
Psi(ca) PLL
Psi(ca) REG
∆TPLL (DTPLL)
∆TREG (DTREG) / Toggle Rate
SPD Revision
Checksum of Bytes 0-62
Manufacturer’s JEDEC ID Code (1)
Manufacturer’s JEDEC ID Code (2)
Manufacturer’s JEDEC ID Code (3)
Manufacturer’s JEDEC ID Code (4)
Manufacturer’s JEDEC ID Code (5)
Manufacturer’s JEDEC ID Code (6)
Manufacturer’s JEDEC ID Code (7)
Manufacturer’s JEDEC ID Code (8)
Module Manufacturer Location
Product Type, Char 1
36
34
36
34
36
34
Product Type, Char 2
Rev. 0.50, 2008-01
40
01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
Product Type
Organization
2 GByte
×64
2 GByte
×64
2 GByte
×64
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–6400U–555 PC2–6400U–666 PC2–5300U–555
JEDEC SPD Revision
Rev. 1.2
HEX
Rev. 1.2
HEX
Rev. 1.2
HEX
Byte#
Description
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Product Type, Char 3
54
32
35
36
30
32
30
45
55
32
35
46
42
32
20
20
0x
xx
xx
xx
xx
00
FF
54
32
35
36
30
32
30
45
55
32
2E
35
42
32
20
20
0x
xx
xx
xx
xx
00
FF
54
32
35
36
30
32
30
45
55
33
53
42
32
20
20
20
0x
xx
xx
xx
xx
00
FF
Product Type, Char 4
Product Type, Char 5
Product Type, Char 6
Product Type, Char 7
Product Type, Char 8
Product Type, Char 9
Product Type, Char 10
Product Type, Char 11
Product Type, Char 12
Product Type, Char 13
Product Type, Char 14
Product Type, Char 15
Product Type, Char 16
Product Type, Char 17
Product Type, Char 18
Module Revision Code
Test Program Revision Code
Module Manufacturing Date Year
Module Manufacturing Date Week
95 - 98 Module Serial Number
99 - 127 Not used
128 -
255
Blank for customer use
Rev. 0.50, 2008-01
41
01282008-JC1K-XBCR
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Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
5
Package Outlines
FIGURE 6
Package Outline L-DIM-240-6 Raw Card F
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2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 0.50, 2008-01
42
01282008-JC1K-XBCR
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Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
FIGURE 7
Package Outline L-DIM-240-8 Raw Card D
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1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 0.50, 2008-01
43
01282008-JC1K-XBCR
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Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
FIGURE 8
Package Outline L-DIM-240-9 Raw Card E
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Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 0.50, 2008-01
44
01282008-JC1K-XBCR
Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
6
Product Type Nomenclature
Qimonda’s nomenclature uses simple coding combined with
some proprietary coding. Table 24 provides examples for
module and component product type number as well as the
field number. The detailed field description together with
possible values and coding explanation is listed for modules
in Table 25 and for components in Table 26.
TABLE 24
Nomenclature Fields and Examples
Example for
Field Number
1
2
3
4
5
6
7
8
9
10
11
Micro-DIMM
DDR2 DRAM
HYS
HYB
64
18
T
T
64/128
0
2
0
0
K
A
M
C
–5
–5
–A
512/1G 16
TABLE 25
DDR2 DIMM Nomenclature
Field
Description
Values
Coding
1
2
Qimonda Module Prefix
Module Data Width [bit]
HYS
64
Constant
Non-ECC
ECC
72
3
4
DRAM Technology
T
DDR2
Memory Density per I/O [Mbit];
Module Density1)
32
256 MByte
512 MByte
1 GByte
2 GByte
4 GByte
64
128
256
512
0 .. 9
0, 2, 4
0 .. 9
A .. Z
D
5
6
7
8
9
Raw Card Generation
Number of Module Ranks
Product Variations
Look up table
1, 2, 4
Look up table
Look up table
SO-DIMM
Package, Lead-Free Status
Module Type
M
Micro-DIMM
Registered
Unbuffered
Fully Buffered
R
U
F
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Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
Field
Description
Values
Coding
10
Speed Grade
–19F
–1.9
–25F
–2.5
–3
PC2–8500 6–6–6
PC2–8500 7–7–7
PC2–6400 5–5–5
PC2–6400 6–6–6
PC2–5300 4–4–4
PC2–5300 5–5–5
PC2–4200 4–4–4
PC2–3200 3–3–3
First
–3S
–3.7
–5
11
Die Revision
–A
–B
Second
1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall
module memory density in MBytes as listed in column “Coding”.
TABLE 26
DDR2 DRAM Nomenclature
Field
Description
Values
Coding
1
2
3
4
Qimonda Component Prefix
Interface Voltage [V]
HYB
18
Constant
SSTL_18
DRAM Technology
T
DDR2
Component Density [Mbit]
256
512
1G
2G
40
256 Mbit
512 Mbit
1 Gbit
2 Gbit
5+6
Number of I/Os
×4
80
×8
16
×16
7
8
Product Variations
Die Revision
0 .. 9
A
Look up table
First
B
Second
9
Package, Lead-Free Status
Speed Grade
C
FBGA, lead-containing
FBGA, lead-free
PC2–8500 6–6–6
PC2–8500 7–7–7
PC2–6400 5–5–5
PC2–6400 6–6–6
PC2–5300 4–4–4
PC2–5300 5–5–5
PC2–4200 4–4–4
PC2–3200 3–3–3
F
10
–19F
–1.9
–25F
–2.5
–3
–3S
–3.7
–5
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Advance Internet Data Sheet
HYS[64/72]T[128/256]0x0EU–[25F/2.5/3S]–B2
Unbuffered DDR2 SDRAM Modules
Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Component AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
IDD Specifications and Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1
3.2
3.3
3.4
3.5
3.6
4
5
6
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Rev. 0.50, 2008-01
47
01282008-JC1K-XBCR
Advance Internet Data Sheet
Edition 2008-01
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2008.
All Rights Reserved.
Legal Disclaimer
THE INFORMATION GIVEN IN THIS INTERNET DATA SHEET SHALL IN NO EVENT BE REGARDED AS A GUARANTEE
OF CONDITIONS OR CHARACTERISTICS. WITH RESPECT TO ANY EXAMPLES OR HINTS GIVEN HEREIN, ANY
TYPICAL VALUES STATED HEREIN AND/OR ANY INFORMATION REGARDING THE APPLICATION OF THE DEVICE,
QIMONDA HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND, INCLUDING WITHOUT
LIMITATION WARRANTIES OF NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
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body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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