HYB25D512400BC-5 [QIMONDA]
512-Mbit Double-Data-Rate SDRAM; 512 - Mbit的双数据速率SDRAM
| 型号： | HYB25D512400BC-5 |
| 厂家： | 
QIMONDA AG |
| 描述： | 512-Mbit Double-Data-Rate SDRAM |
| 文件： | 总38页 (文件大小：2063K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2006
HYB25D512[40/80/16]0B[C/T](L)
HYB25D512[40/80/16]0B[E/F](L)
512-Mbit Double-Data-Rate SDRAM
DDR SDRAM
Internet Data Sheet
Rev. 1.63
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
HYB25D512[40/80/16]0B[C/T](L), HYB25D512[40/80/16]0B[E/F](L)
Revision History: 2006-09, Rev. 1.63
Page
Subjects (major changes since last revision)
All
All
Qimonda update
Adapted internet edition
Previous Revision: 2005-10, Rev. 1.62
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-01
03062006-PFFJ-YJY2
2
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
1
Overview
This chapter gives an overview of the 512-Mbit Double-Data-Rate SDRAM product family and describes its main
characteristics
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Double data rate architecture: two data transfers per clock cycle
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
DQS is edge-aligned with data for reads and is center-aligned with data for writes
Differential clock inputs (CK and CK)
Four internal banks for concurrent operation
Data mask (DM) for write data
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Burst Lengths: 2, 4, or 8
CAS Latency: (1.5), 2, 2.5, 3
Auto Pre charge option for each burst access
Auto Refresh and Self Refresh Modes
RAS-lockout supported tRAP=tRCD
7.8 µs Maximum Average Periodic Refresh Interval
2.5 V (SSTL_2 compatible) I/O
V
V
DDQ = 2.5 V ± 0.2 V and 2.6 V ± 0.1 V for DDR400
DD = 2.5 V ± 0.2 V and 2.6 V ± 0.1 V for DDR400
P-TFBGA-60 and P-TSOPII-66 package
TABLE 1
Performance
Part Number Speed Code
–5
–6
–7
Unit
Speed Grade Component
Module
DDR400B
PC3200–3033
200
DDR333B
PC2700–2533
166
DDR266A
—
PC2100–2033
—
max. Clock
Frequency
@CL3
@CL2.5
@CL2
fCK3
–
MHz
MHz
MHz
fCK2.5
fCK2
166
166
143
133
133
133
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03062006-PFFJ-YJY2
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
1.2
Description
The 512-Mbit Double-Data-Rate SDRAM is a high-speed
CMOS, dynamic random-access memory containing
536,870,912 bits. It is internally configured as a quad-bank
DRAM.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write
command. The address bits registered coincident with the
Active command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
The 512-Mbit Double-Data-Rate SDRAM uses a double-
data-rate architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n pre fetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access
for
the
512-Mbit Double-Data-Rate SDRAM
effectively consists of a single 2n-bit wide, one clock cycle
data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4 or 8 locations. An Auto Precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads and
by the memory controller during Writes. DQS is edge-aligned
with data for Reads and center-aligned with data for Writes.
As with standard SDRAMs, the pipelined, multibank
architecture of DDR SDRAMs allows for concurrent
operation, thereby providing high effective bandwidth by
hiding row precharge and activation time.
An auto refresh mode is provided along with a power-saving
power-down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II
compatible.
The 512-Mbit Double-Data-Rate SDRAM operates from a
differential clock (CK and CK; the crossing of CK going HIGH
and CK going LOW is referred to as the positive edge of CK).
Commands (address and control signals) are registered at
every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Note: The functionality described and the timing
specifications included in this data sheet are for the
DLL Enabled mode of operation.
Rev. 1.63, 2006-09
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Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 2
Ordering Information
Part Number1)
Org. CAS-RCD-RP Clock CAS-RCD-RP
Clock Speed
(MHz)
Package
Latencies
(MHz) Latencies
HYB25D512800BT–5
HYB25D512160BT–5
HYB25D512400BT–6
HYB25D512800BT–6
HYB25D512160BT–6
HYB25D512160BTL–6
HYB25D512400BT–7
HYB25D512400BC–5
HYB25D512800BC–5
HYB25D512160BC–5
HYB25D512400BC–6
HYB25D512800BC–6
HYB25D512160BC–6
×8
3.0-3-3
200
166
2.5-3-3
2-3-3
166
DDR400B
P-TSOPII-66
×16
×4
2.5-3-3
133
DDR333
×8
×16
×16
×4
143
200
DDR266
×4
3.0-3-3
2.5-3-3
2.5-3-3
2-3-3
166
133
DDR400B
P-TFBGA-60
×8
×16
×4
166
DDR333
×8
×16
1) HYB: designator for memory components
25D: DDR SDRAMs at VDDQ = 2.5 V
512: 512-Mbit density
400/800/160: Product variations x4, ×8 and ×16
B: Die revision B
C/F/E/T: Package type FBGA and TSOP
L: Low power (on request)
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Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 3
Ordering Information for RoHS compliant products
Part Number
Org. CAS-RCD-RP
Latencies
Clock
(MHz)
CAS-RCD-RP
Latencies
Clock
(MHz)
Speed
Package
HYB25D512400BF–5
HYB25D512800BF–5
HYB25D512160BF–5
HYB25D512400BF–6
HYB25D512800BF–6
HYB25D512160BF–6
HYB25D512400BE–5
HYB25D512800BE–5
HYB25D512160BE–5
HYB25D512400BE–6
HYB25D512800BE–6
HYB25D512800BEL–6
HYB25D512160BE–6
HYB25D512160BEL–6
HYB25D512400BE–7
×4
3.0-3-3
2.5-3-3
3.0-3-3
2.5-3-3
200
166
200
166
2.5-3-3
2-3-3
166
133
166
133
DDR400B
P-TFBGA-60
×8
×16
×4
DDR333
DDR400B
DDR333
×8
×16
×4
2.5-3-3
2-3-3
P-TSOPII-66
×8
×16
×4
×8
×8
×16
×16
×4
143
DDR266A
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Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
2
Pin Configuration
The pin configuration of a DDR SDRAM is listed by function in Table 4 (60 pins). The abbreviations used in the Pin#/Buffer#
column are explained in Table 5 and Table 6 respectively. The pin numbering for FBGA is depicted in Figure 1 and that of the
TSOP package in Figure 2
TABLE 4
Pin Configuration of DDR SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
Clock Signals
G2, 45
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal
G3, 46
CK
Complementary Clock Signal
Clock Enable
H3, 44
CKE
Control Signals
H7, 23
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe
Column Address Strobe
Write Enable
G8, 22
G7, 21
H8, 24
CS
Chip Select
Address Signals
J8, 26
J7, 27
K7, 29
L8, 30
L7, 31
M8, 32
M2, 35
L3, 36
L2, 37
K3, 38
K2, 39
J3, 40
K8, 28
BA0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 2:0
Address Bus 11:0
BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
J2, 41
H2, 42
Address Signal 12
Note: 256 Mbit or larger dies
Note: 128 Mbit or smaller dies
Address Signal 13
NC
NC
I
—
F9, 17
A13
SSTL
Note: 1 Gbit based dies
Note: 512 Mbit or smaller dies
NC
NC
—
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Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
Data Signals ×4 organization
B7, 5
DQ0
DQ1
DQ2
DQ3
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
Data Signal 3:0
D7, 11
D3, 56
B3, 62
Data Strobe ×4 organisation
E3, 51
Data Mask ×4 organization
F3, 47 DM
DQS
I/O
I
SSTL
SSTL
Data Strobe
Data Mask
Data Signals ×8 organization
A8, 2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Signal 7:0
B7, 5
C7, 8
D7, 11
D3, 56
C3, 59
B3, 62
A2, 65
Data Signal
Data Strobe ×8 organisation
E3, 51
Data Mask ×8 organization
F3, 47 DM
DQS
I/O
I
SSTL
SSTL
Data Strobe
Data Mask
Data Signals ×16 organization
A8, 2
DQ0
DQ1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Signal 15:0
B9, 4
B7, 5
DQ2
C9, 7
DQ3
C7, 8
DQ4
D9, 10
D7, 11
E9, 13
E1, 54
D3, 56
D1, 57
C3, 59
C1, 60
B3, 62
B1, 63
A2, 65
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
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Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
Data Strobe ×16 organization
E3, 51
UDQS
I/O
SSTL
SSTL
Data Strobe Upper Byte
Data Strobe Lower Byte
E7, 16
LDQS
I/O
Data Mask ×16 organization
F3, 47
UDM
LDM
I
I
SSTL
SSTL
Data Mask Upper Byte
Data Mask Lower Byte
F7, 20
Power Supplies
F1, 49
VREF
AI
—
—
I/O Reference Voltage
A9, B2, C8, D2, VDDQ
E8, 3, 9, 15, 55,
61
PWR
I/O Driver Power Supply
A7, F8, M7, 1, VDD
18, 33
PWR
PWR
—
—
Power Supply
Power Supply
A1, B8, C2, D8, VSSQ
E2, 6, 12, 52,
58, 64
A3,F2, M3, 34, VSS
PWR
—
Power Supply
48, 66,
Not Connected
A2, 65
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
—
—
—
—
—
—
—
—
—
—
—
Not Connected
Note: ×4 organization
Not Connected
A8, 2
Note: ×4 organization
Not Connected
B1, 63
B9, 4
Note: ×8 and ×4 organisation
Not Connected
Note: ×8 and ×4 organization
Not Connected
C1, 60
C3, 59
C7, 8
Note: ×8 and ×4 organization
Not Connected
Note: ×4 organization
Not Connected
Note: ×4 organization
Not Connected
C9, 7
Note: ×8 and ×4 organization
Not Connected
D1, 57
D9, 10
E1, 54
Note: ×8 and ×4 organization
Not Connected
Note: ×8 and ×4 organization
Not Connected
Note: ×8 and ×4 organization
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Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
Ball#/Pin#
E7, 16
Name
NC
Pin
Type
Buffer
Type
Function
NC
NC
NC
NC
—
—
—
—
Not Connected
Note: ×8 and ×4 organization
Not Connected
E9, 13
NC
Note: ×8 and ×4 organization
Not Connected
F7, 20
NC
Note: ×8 and ×4 organization
Not Connected
F9, 14, 17, 19, NC
25,43, 50, 53
Note: ×16, ×8 and ×4 organization
TABLE 5
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NC
Ground
Not Connected
TABLE 6
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL2)
Low Voltage CMOS
LV-CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Rev. 1.63, 2006-09
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Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
FIGURE 1
Pin Configuration P-TFBGA-60 Top View, see the balls throught the package
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ꢀꢅꢅ
ꢃ
ꢀꢁꢅꢆꢃ
ꢁꢒ
ꢃꢄꢄꢅꢆꢆꢇꢆ
Rev. 1.63, 2006-09
11
03062006-PFFJ-YJY2
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
FIGURE 2
Pin Configuration P-TSOPII-66-1
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!"!ꢑ
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ꢀꢅꢅ
ꢊꢋꢀꢋ
ꢀꢅꢅꢈ
ꢊꢋꢀꢋ
ꢅꢈꢆ
ꢀꢂꢂꢈ
ꢊꢋꢀꢋ
ꢊꢋꢀꢋ
ꢀꢅꢅꢈ
ꢊꢋꢀꢋ
ꢅꢈꢏ
ꢀꢂꢂꢈ
ꢊꢋꢀꢋ
ꢊꢋꢀꢋ
ꢀꢅꢅꢈ
ꢊꢋꢀꢋ
ꢀꢅꢅ
ꢅꢈꢆ
ꢀꢅꢅꢈ
ꢊꢋꢀꢋ
ꢅꢈꢏ
ꢀꢂꢂꢈ
ꢊꢋꢀꢋ
ꢅꢈꢐ
ꢀꢅꢅꢈ
ꢊꢋꢀꢋ
ꢅꢈꢖ
ꢀꢂꢂꢈ
ꢊꢋꢀꢋ
ꢊꢋꢀꢋ
ꢀꢅꢅꢈ
ꢊꢋꢀꢋ
ꢀꢅꢅ
ꢅꢈꢆ
ꢀꢅꢅꢈ
ꢅꢈꢏ
ꢅꢈꢐ
ꢀꢂꢂꢈ
ꢅꢈꢖ
ꢅꢈꢒ
ꢀꢅꢅꢈ
ꢅꢈꢕ
ꢅꢈꢇ
ꢀꢂꢂꢈ
ꢅꢈꢔ
ꢊꢋꢀꢋ
ꢀꢅꢅꢈ
ꢞꢅꢈꢂ
ꢏ
ꢇꢇ
ꢇꢕ
ꢇꢒ
ꢇꢖ
ꢇꢐ
ꢇꢏ
ꢇꢆ
ꢕꢓ
ꢕꢑ
ꢕꢔ
ꢕꢇ
ꢕꢕ
ꢕꢒ
ꢕꢖ
ꢕꢐ
ꢕꢏ
ꢕꢆ
ꢒꢓ
ꢒꢑ
ꢒꢔ
ꢒꢇ
ꢒꢕ
ꢒꢒ
ꢒꢖ
ꢒꢐ
ꢒꢏ
ꢒꢆ
ꢖꢓ
ꢖꢑ
ꢖꢔ
ꢖꢇ
ꢖꢕ
ꢖꢒ
ꢀꢂꢂ
ꢀꢂꢂ
ꢀꢂꢂ
ꢐ
ꢅꢈꢏꢕ
ꢀꢂꢂꢈ
ꢅꢈꢏꢒ
ꢅꢈꢏꢖ
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ꢅꢈꢏꢐ
ꢅꢈꢏꢏ
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ꢅꢈꢓ
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ꢅꢈꢂ
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ꢐꢔ
ꢐꢑ
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ꢀꢅꢅ
ꢊꢋꢀꢋ
ꢊꢋꢀꢋ
ꢗꢍ
ꢀꢅꢅ
ꢊꢋꢀꢋ
ꢊꢋꢀꢋ
ꢗꢍ
ꢀꢅꢅ
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ꢞꢅꢃ
ꢗꢍ
ꢅꢃ
ꢀꢉ
ꢅꢃ
ꢅꢃ
ꢀꢉ
ꢀꢉ
ꢀꢁꢂ
ꢌꢁꢂ
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ꢀꢉ
ꢀꢉ
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ꢀꢉꢍ
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ꢁꢇ
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ꢁꢒ
ꢀꢂꢂ
ꢁꢏꢏ
ꢁꢓ
ꢁꢑ
ꢁꢔ
ꢁꢇ
ꢁꢕ
ꢁꢒ
ꢀꢂꢂ
ꢁꢏꢏ
ꢁꢓ
ꢁꢑ
ꢁꢔ
ꢁꢇ
ꢁꢕ
ꢁꢒ
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ꢁꢆ
ꢁꢏ
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ꢁꢏ
ꢁꢐ
ꢁꢐ
ꢁꢐ
ꢁꢖ
ꢁꢖ
ꢁꢖ
ꢀꢅꢅ
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ꢀꢅꢅ
ꢃꢄꢄꢅꢆꢆꢔꢐ
Rev. 1.63, 2006-09
12
03062006-PFFJ-YJY2
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
3
Functional Description
The 512-Mbit Double-Data-Rate SDRAM is a high-speed
CMOS, dynamic random-access memory containing
536,870,912 bits. The 512-Mbit Double-Data-Rate SDRAM
is internally configured as a quad-bank DRAM.
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write
command. The address bits registered coincident with the
Active command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0-A12 select the row).
The address bits registered coincident with the Read or Write
command are used to select the starting column location for
the burst access.
The 512-Mbit Double-Data-Rate SDRAM uses a double-
data-rate architecture to achieve high-speed operation. The
double-data-rate architecture is essentially a 2n pre fetch
architecture, with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 512-Mbit Double-Data-Rate SDRAM consists
of a single 2n-bit wide, one clock cycle data transfer at the
internal DRAM core and two corresponding n-bit wide, one-
half clock cycle data transfers at the I/O pins.
Prior to normal operation, the DDR SDRAM must be
initialized. The following sections provide detailed information
covering device initialization, register definition, command
descriptions and device operation.
Rev. 1.63, 2006-09
13
03062006-PFFJ-YJY2
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
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TABLE 7
Mode Register Definition
Field Bits
Type Description
BL
[2:0]
w
Burst Length
Number of sequential bits per DQ related to one read/write command.
Note: All other bit combinations are RESERVED.
001B
010B
011B
2
4
8
BT
CL
3
w
w
Burst Type
See Table 8 for internal address sequence of low order address bits.
0B
1B
Sequential
Interleaved
[6:4]
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED.
010B
011B
2
3
101B (1.5 Optional, not covered by this data sheet)
110B 2.5
MODE [12:7]
w
Operating Mode
Note: All other bit combinations are RESERVED.
000000B Normal Operation without DLL Reset
000010B DLL Reset
Rev. 1.63, 2006-09
14
03062006-PFFJ-YJY2
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 8
Burst Definition
Burst Length
Starting Column Address
Order of Accesses Within a Burst
A2
A1
A0
Type = Sequential
Type = Interleaved
2
4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0-1
0-1
1-0
1-0
0
0
1
1
0
0
1
1
0
0
1
1
0-1-2-3
0-1-2-3
1-2-3-0
1-0-3-2
2-3-0-1
2-3-0-1
3-0-1-2
3-2-1-0
8
0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0
0
0
1
1
1
1
Notes
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block.
3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
Rev. 1.63, 2006-09
15
03062006-PFFJ-YJY2
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
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TABLE 9
Extended Mode Register Definition
Field
Bits
Type
Description
DLL Status
DLL
0
w
0B
1B
Enabled
Disabled
DS
1
w
w
Drive Strength
0B
1B
Normal
Weak
MODE
[12:2]
Operating Mode
Note: All other bit combinations are RESERVED.
0B
Normal Operation
Rev. 1.63, 2006-09
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03062006-PFFJ-YJY2
Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 10
Truth Table 1a: Commands
Name (Function)
CS RAS CAS WE Address
MNE
Note
1)2)
Deselect (NOP)
H
L
L
L
L
L
L
L
L
X
H
L
X
H
H
L
X
H
H
H
L
X
X
NOP
NOP
1)2)
No Operation (NOP)
1)3)
Active (Select Bank And Activate Row)
Read (Select Bank And Column, And Start Read Burst)
Write (Select Bank And Column, And Start Write Burst)
Burst Terminate
Bank/Row ACT
1)4)
H
H
H
L
Bank/Col
Bank/Col
X
Read
Write
BST
1)4)
L
1)5)
H
H
L
L
1)6)
Precharge (Deactivate Row In Bank Or Banks)
Auto Refresh Or Self Refresh (Enter Self Refresh Mode)
L
Code
PRE
1)7)8)
1)9)
L
H
L
X
AR/SR
MRS
Mode Register Set
L
L
Op-Code
1) CKE is HIGH for all commands shown except Self Refresh.
VREF must be maintained during Self Refresh operation
2) Deselect and NOP are functionally interchangeable.
3) BA0-BA1 provide bank address and A0-A12 provide row address.
4) BA0, BA1 provide bank address; A0-Ai provide column address (where i = 8 for ×16, i = 9 for ×8 and 9, 11 for ×4);
A10 HIGH enables the Auto Precharge feature (non persistent), A10 LOW disables the Auto Precharge feature.
5) Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto
Precharge enabled or for write bursts.
6) A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
7) This command is AUTO REFRESH if CKE is HIGH; Self Refresh if CKE is LOW.
8) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
9) BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects
Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode
Register).
TABLE 11
Truth Table 1b: DM Operation
Name (Function)
DM
DQs
Note
1)
Write Enable
L
Valid
X
1)
Write Inhibit
H
1) Used to mask write data; provided coincident with the corresponding data.
Rev. 1.63, 2006-09
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Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 12
Truth Table 2: Clock Enable (CKE)
Current State CKE n-1
CKEn
Command n
Action n
Note
Previous
Cycle
Current
Cycle
1)
2)
Self Refresh
Self Refresh
Power Down
Power Down
All Banks Idle
All Banks Idle
Bank(s) Active
L
L
X
Maintain Self-Refresh
Exit Self-Refresh
L
H
L
Deselect or NOP
X
L
Maintain Power-Down
Exit Power-Down
–
–
–
–
–
–
L
H
L
Deselect or NOP
Deselect or NOP
AUTO REFRESH
Deselect or NOP
See Table 13
H
H
H
H
Precharge Power-Down Entry
Self Refresh Entry
Active Power-Down Entry
–
L
L
H
1)
VREF must be maintained during Self Refresh operation
2) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A minimum of 200
clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
Notes
1. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.
4. All states and sequences not shown are illegal or reserved.
Rev. 1.63, 2006-09
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Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 13
Truth Table 3: Current State Bank n - Command to Bank n (same bank)
Current State CS
RAS CAS WE
Command
Action
Note
1)2)3)4)5)6)
1) to 6)
Any
H
L
L
L
L
X
H
L
L
L
X
H
H
L
X
H
H
H
L
Deselect
NOP. Continue previous operation.
No Operation
Active
NOP. Continue previous operation.
1) to 6)
Idle
Select and activate row
1) to 7)
AUTO REFRESH
–
–
1) to 7)
L
MODE REGISTER
SET
1) to 6), 8)
1) to 6), 8)
1) to 6), 9)
1) to 6), 8)
1) to 6), 9)
1) to 6), 10)
Row Active
L
L
L
L
L
L
H
H
L
L
H
L
Read
Select column and start Read burst
Select column and start Write burst
Deactivate row in bank(s)
L
Write
H
L
L
Precharge
Read
Read (Auto
Precharge
Disabled)
H
L
H
L
Select column and start new Read burst
Truncate Read burst, start Precharge
BURST TERMINATE
H
H
Precharge
H
L
BURST
TERMINATE
1) to 6), 8), 11)
1) to 6), 8)
Write (Auto
Precharge
Disabled)
L
L
L
H
H
L
L
L
H
H
L
Read
Select column and start Read burst
Select column and start Write burst
Truncate Write burst, start Precharge
Write
1) to 6), 9), 11)
L
Precharge
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 12 and after tXSNR/tXSRD has been met (if the previous state
was self refresh).
2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed
to be issued to that bank when in that state. Exceptions are covered in the notes below.
3) Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in
progress.
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
4) The following states must not be interrupted by a command issued to the same bank.
Pre charging: Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in the idle state.
Row Activating: Starts with registration of an Active command and ends when tRCD is met. Once tRCD is met, the bank is in the “row active”
state.
Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state.
Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state.
Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states.
Allowable commands to the other bank are determined by its current state and according to Table 14.
5) The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive
clock edge during these states.
Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. Once tRFC is met, the DDR SDRAM is in the
“all banks idle” state.
Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met. Once tMRD is met,
the DDR SDRAM is in the “all banks idle” state.
Pre charging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in the idle state.
6) All states and sequences not shown are illegal or reserved.
7) Not bank-specific; requires that all banks are idle.
8) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
9) May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for pre charging.
Rev. 1.63, 2006-09
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Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
10) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank.
11) Requires appropriate DM masking.
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Double-Data-Rate SDRAM
TABLE 14
Truth Table 4: Current State Bank n - Command to Bank m (different bank)
Current State
CS
RAS CAS WE Command
Action
Note
1)2)3)4)5)6)
Any
H
L
X
H
X
X
H
X
X
H
X
Deselect
NOP. Continue previous operation.
1) to 6)
No Operation
NOP. Continue previous operation.
–
1) to 6)
Idle
X
Any Command
Otherwise Allowed to
Bank m
1) to 6)
Row Activating,
Active, or Pre
charging
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
H
L
Active
Select and activate row
Select column and start Read burst
Select column and start Write burst
–
1) to 7)
H
H
L
Read
1) to 7)
L
Write
1) to 6)
H
H
L
L
Precharge
Active
1) to 6)
Read (Auto
Precharge
Disabled)
L
H
H
L
Select and activate row
Select column and start new Read burst
–
1) to 7)
H
L
Read
1) to 6)
H
H
L
Precharge
Active
1) to 6)
Write (Auto
Precharge
Disabled)
L
H
H
L
Select and activate row
Select column and start Read burst
Select column and start new Write burst
–
1) to 8)
H
H
L
Read
1) to 7)
L
Write
1) to 6)
H
H
L
L
Precharge
Active
1) to 6)
Read (With Auto
Precharge)
L
H
H
L
Select and activate row
Select column and start new Read burst
Select column and start Write burst
–
1) to 7), 9)
1) to 7), 9), 10)
1) to 6)
H
H
L
Read
L
Write
H
H
L
L
Precharge
Active
1) to 6)
Write (With Auto
Precharge)
L
H
H
L
Select and activate row
Select column and start Read burst
Select column and start new Write burst
–
1) to 7), 9)
1) to 7), 9)
1) to 6)
H
H
L
Read
L
Write
H
L
Precharge
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 12: Clock Enable (CKE) and after tXSNR/tXSRD has been met (if
the previous state was self refresh).
2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those
allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in
the notes below.
3) Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in
progress.
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Read with Auto Precharge Enabled: See 10)
Write with Auto Precharge Enabled: See 10)
.
.
4) AUTO REFRESH and Mode Register Set commands may only be issued when all banks are idle.
5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.
6) All states and sequences not shown are illegal or reserved.
7) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
8) Requires appropriate DM masking.
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HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
9) Concurrent Auto Precharge:
This device supports “Concurrent Auto Precharge”. When a read with auto precharge or a write with auto precharge is enabled any
command may follow to the other banks as long as that command does not interrupt the read or write data transfer and all other limitations
apply (e.g. contention between READ data and WRITE data must be avoided). The minimum delay from a read or write command with
auto precharge enable, to a command to a different banks is summarized in Table 15.
10) A Write command may be applied after the completion of data output.
TABLE 15
Truth Table 5: Concurrent Auto Precharge
From Command
To Command (different bank)
Minimum Delay with Concurrent Auto Unit
Precharge Support
1)
WRITE w/AP
Read or Read w/AP
Write to Write w/AP
Precharge or Activate
Read or Read w/AP
Write or Write w/AP
Precharge or Activate
1 + (BL/2) + RU(tWTR/tCK
)
tCK
tCK
tCK
tCK
tCK
tCK
BL/2
1
Read w/AP
BL/2
RU(CL)1) + BL/2
1
1) RU means rounded to the next integer
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HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
4
Electrical Characteristics
4.1
Operating Conditions
TABLE 16
Absolute Maximum Ratings
Parameter
Symbol
Values
typ.
Unit Note/ Test
Condition
max.
min.
Voltage on I/O pins relative to VSS
VIN, VOUT
–0.5
–
VDDQ
+
V
–
0.5
Voltage on inputs relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
Operating temperature (ambient)
Storage temperature (plastic)
VIN
–1
–1
–1
0
–
+3.6
+3.6
+3.6
+70
+150
–
V
–
–
–
–
–
–
–
VDD
VDDQ
TA
–
V
–
V
–
°C
°C
W
mA
TSTG
PD
-55
–
–
Power dissipation (per SDRAM component)
Short circuit output current
1
IOUT
–
50
–
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This is a stress
rating only, and functional operation should be restricted to recommended operation conditions. Exposure
to absolute maximum rating conditions for extended periods of time may affect device reliability and
exceeding only one of the values may cause irreversible damage to the integrated circuit.
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HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 17
Input and Output Capacitances
Parameter
Symbol
Values
Typ.
Unit
Note/
Test Condition
Min.
Max.
Input Capacitance: CK, CK
Delta Input Capacitance
CI1
1.5
2.0
—
—
—
—
—
—
—
2.5
3.0
0.25
2.5
3.0
0.5
pF
pF
pF
pF
pF
pF
TSOPII 1)
TFBGA 1)
1)
CdI1
CI2
Input Capacitance:
All other input-only pins
1.5
2.0
—
TFBGA 1)
TSOPII 1)
1)
Delta Input Capacitance:
All other input-only pins
CdIO
CIO
Input/Output Capacitance: DQ, DQS, DM
3.5
4.0
—
—
—
—
4.5
5.0
0.5
pF
pF
pF
TFBGA 1)2)
TSOPII 1)2)
1)
Delta Input/Output Capacitance:
DQ, DQS, DM
CdIO
1) These values are guaranteed by design and are tested on a sample base only. VDDQ = VDD = 2.5 V ± 0.2 V, f= 100 MHz, TA = 25 °C, VOUT(DC)
= VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground.
2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the
board level.
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HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 18
Electrical Characteristics and DC Operating Conditions
Parameter
Symbol
Values
Unit Note1)/Test Condition
Min.
Typ.
Max.
Device Supply Voltage
Device Supply Voltage
Output Supply Voltage
Output Supply Voltage
EEPROM supply voltage
VDD
2.3
2.5
2.3
2.5
2.3
0
2.5
2.6
2.5
2.6
2.5
—
2.7
2.7
2.7
2.7
3.6
0
V
V
V
V
V
V
fCK ≤ 166 MHz
CK > 166 MHz 2)
fCK ≤ 166 MHz 3)
CK > 166 MHz 2)3)
VDD
f
VDDQ
VDDQ
VDDSPD
f
—
—
Supply Voltage, I/O Supply
Voltage
VSS,
VSSQ
4)
5)
Input Reference Voltage
VREF
VTT
0.49 × VDDQ 0.5 × VDDQ 0.51 × VDDQ
V
V
I/O Termination Voltage
(System)
V
REF – 0.04
—
VREF + 0.04
6)
6)
6)
Input High (Logic1) Voltage VIH(DC)
V
REF + 0.15
—
—
—
VDDQ + 0.3
VREF – 0.15
VDDQ + 0.3
V
V
V
Input Low (Logic0) Voltage
VIL(DC)
VIN(DC)
–0.3
–0.3
Input Voltage Level,
CK and CK Inputs
6)7)
8)
Input Differential Voltage,
CK and CK Inputs
VID(DC)
0.36
0.71
–2
—
—
—
V
DDQ + 0.6
V
VI-Matching Pull-up Current VIRatio
to Pull-down Current
1.4
2
—
µA
Input Leakage Current
II
Any input 0 V ≤ VIN ≤ VDD;
All other pins not under test
= 0 V 9)
Output Leakage Current
IOZ
–5
—
—
—
5
µA
DQs are disabled;
0 V ≤ VOUT ≤ VDDQ
9)
Output High Current, Normal IOH
Strength Driver
—
–16.2
—
mA
mA
V
OUT = 1.95 V
Output Low Current, Normal IOL
16.2
V
OUT = 0.35 V
Strength Driver
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V; VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400);
2) DDR400 conditions apply for all clock frequencies above 166 MHz
3) Under all conditions, VDDQ must be less than or equal to VDD
4) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ
5) TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in the DC level of VREF
6) Inputs are not recognized as valid until VREF stabilizes.
7) ID is the magnitude of the difference between the input level on CK and the input level on CK.
.
.
V
.
V
8) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and
voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between
pull-up and pull-down drivers due to process variation.
9) Values are shown per pin.
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HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
4.2
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, IDD
Specifications and Conditions, and Electrical Characteristics and AC Timing.)Note
Note
1. All voltages referenced to VSS
referenced to VREF (or to the crossing point for CK, CK),
and parameter specifications are guaranteed for the
specified AC input levels under normal use conditions.
The minimum slew rate for the input signals is 1 V/ns in
2. Tests for AC timing, IDD, and electrical, AC and DC
characteristics, may be conducted at nominal
reference/supply voltage levels, but the related
specifications and device operation are guaranteed for
the full voltage range specified.
3. Figure 3 represents the timing reference load used in
defining the relevant timing parameters of the part. It is not
intended to be either a precise representation of the
typical system environment nor a depiction of the actual
load presented by a production tester. System designers
will use IBIS or other simulation tools to correlate the
timing reference load to a system environment.
Manufacturers will correlate to their production test
conditions (generally a coaxial transmission line
terminated at the tester electronics).
the range between VIL(AC) and VIH(AC)
.
5. The AC and DC input level specifications are as defined
in the SSTL_2 Standard (i.e. the receiver effectively
switches as a result of the signal crossing the AC input
level, and remains in that state as long as the signal does
not ring back above (below) the DC input LOW (HIGH)
level).
6. For System Characteristics like Setup & Holdtime
Derating for Slew Rate, I/O Delta Rise/Fall Derating, DDR
SDRAM Slew Rate Standards, Overshoot & Undershoot
specification and Clamp V-I characteristics see the latest
JEDEC specification for DDR components.
4. AC timing and IDD tests may use a VIL to VIH swing of up
to 1.5 V in the test environment, but input timing is still
FIGURE 3
AC Output Load Circuit Diagram / Timing Reference Load
VTT
50 Ω
Output
(VOUT
Timing Reference Point
)
30 pF
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HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 19
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter
Symbol –5
–6
Unit Note1)/Test
Condition
DDR400B
DDR333
Min.
Max.
Min.
Max.
2)3)4)5)
DQ output access time from
CK/CK
tAC
–0.5
+0.5
–0.7
+0.7
ns
2)3)4)5)
CK high-level width
Clock cycle time
tCH
tCK
0.45
0.55
8
0.45
6
0.55
12
tCK
5
ns
ns
ns
tCK
tCK
CL = 3.0 2)3)4)5)
CL = 2.5 2)3)4)5)
CL = 2.0 2)3)4)5)
6
12
6
12
7.5
12
7.5
0.45
12
2)3)4)5)
CK low-level width
tCL
0.45
0.55
0.55
2)3)4)5)6)
Auto precharge write recovery + tDAL
(tWR/tCK)+(tRP/tCK)
precharge time
2)3)4)5)
DQ and DM input hold time
tDH
0.4
—
—
0.45
1.75
—
—
ns
ns
2)3)4)5)6)
DQ and DM input pulse width
(each input)
tDIPW
1.75
2)3)4)5)
2)3)4)5)
DQS output access time from
CK/CK
tDQSCK
–0.6
0.35
—
+0.6
—
–0.6
0.35
—
+0.6
—
ns
tCK
ns
ns
tCK
DQS input low (high) pulse width tDQSL,H
(write cycle)
DQS-DQ skew (DQS and
associated DQ signals)
tDQSQ
+0.40
+0.40
1.25
+0.40
+0.45
1.25
TFBGA
2)3)4)5)
—
—
TSOPII
2)3)4)5)
2)3)4)5)
Write command to 1st DQS
latching transition
tDQSS
tDS
0.72
0.75
2)3)4)5)
2)3)4)5)
DQ and DM input setup time
0.4
0.2
—
—
0.45
0.2
—
—
ns
DQS falling edge hold time from tDSH
tCK
CK (write cycle)
2)3)4)5)
DQS falling edge to CK setup time tDSS
0.2
—
0.2
—
tCK
(write cycle)
2)3)4)5)
Clock Half Period
tHP
tHZ
min. (tCL, tCH
)
—
min. (tCL, tCH
)
—
ns
ns
2)3)4)5)7)
Data-out high-impedance time
from CK/CK
—
+0.7
–0.7
+0.7
Address and control input hold
time
tIH
0.6
0.7
2.2
—
—
—
0.75
0.8
—
—
—
ns
ns
ns
fast slew rate
3)4)5)6)8)
slow slew
rate3)4)5)6)8)
2)3)4)5)9)
Control and Addr. input pulse
width (each input)
tIPW
2.2
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HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
Parameter
Symbol –5
DDR400B
–6
Unit Note1)/Test
Condition
DDR333
Min.
Max.
Min.
Max.
Address and control input setup tIS
time
0.6
—
0.75
—
ns
ns
ns
tCK
fast slew rate
3)4)5)6)8)
0.7
–0.7
2
—
0.8
–0.70
2
—
slow slew
rate3)4)5)6)8)
2)3)4)5)7)
Data-out low-impedance time
from CK/CK
tLZ
+0.70
—
+0.70
—
2)3)4)5)
2)3)4)5)
Mode register set command cycle tMRD
time
DQ/DQS output hold time
Data hold skew factor
tQH
t
HP –tQHS
—
tHP –tQHS
—
ns
ns
tQHS
—
+0.50
—
+0.50
TFBGA
2)3)4)5)
—
+0.50
—
+0.55
ns
TSOPII
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Active to Autoprecharge delay
Active to Precharge command
tRAP
tRAS
tRC
tRCD
40
—
tRCD
42
—
ns
70E+3
—
70E+3 ns
Active to Active/Auto-refresh
command period
55
60
—
ns
2)3)4)5)
2)3)4)5)8)
2)3)4)5)
Active to Read or Write delay
tRCD
15
—
65
—
18
—
72
—
ns
µs
ns
Average Periodic Refresh Interval tREFI
7.8
—
7.8
—
Auto-refresh to Active/Auto-
refresh command period
tRFC
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Precharge command period
Read preamble
tRP
15
—
18
—
ns
tCK
tCK
ns
tRPRE
tRPST
tRRD
0.9
0.40
10
1.1
0.60
—
0.9
0.40
12
1.1
0.60
—
Read postamble
Active bank A to Active bank B
command
2)3)4)5)
Write preamble
tWPRE
tWPRES
tWPST
tWR
0.25
0
—
0.25
0
—
tCK
ns
tCK
ns
tCK
2)3)4)5)10)
2)3)4)5)11)
2)3)4)5)
Write preamble setup time
Write postamble
—
—
0.40
15
2
0.60
—
0.40
15
0.60
—
Write recovery time
2)3)4)5)
Internal write to read command
delay
tWTR
—
1
—
2)3)4)5)
Exit self-refresh to non-read
command
tXSNR
75
—
75
—
ns
2)3)4)5)
Exit self-refresh to read command tXSRD
200
—
200
—
tCK
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ± 0.1 V (DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT
.
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
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Double-Data-Rate SDRAM
7)
tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VIH(ac) and VIL(ac)
.
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW at this time, depending
on tDQSS
.
11) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
TABLE 20
AC Timing - Absolute Specifications for PC2100
Parameter
Symbol
–7
Unit
Note1)/Test
Condition
DDR266A
Min.
Max.
2)3)4)5)
2)3)4)5)
DQ output access time from CK/CK
CK high-level width
tAC
tCH
tCK
–0.75
+0.75
0.55
12
ns
tCK
ns
ns
ns
tCK
tCK
ns
ns
ns
tCK
ns
tCK
ns
tCK
tCK
ns
ns
ns
0.45
Clock cycle time
7.5
CL = 3.02)3)4)5)
CL = 2.52)3)4)5)
CL = 2.02)3)4)5)
7.5
12
7.5
12
2)3)4)5)
CK low-level width
tCL
0.45
0.55
—
2)3)4)5)6)
2)3)4)5)
Auto precharge write recovery + precharge time
DQ and DM input hold time
tDAL
(tWR/tCK)+(tRP/tCK)
tDH
0.5
—
2)3)4)5)6)
2)3)4)5)
DQ and DM input pulse width (each input)
DQS output access time from CK/CK
DQS input low (high) pulse width (write cycle)
tDIPW
tDQSCK
tDQSL,H
1.75
–0.75
0.35
—
—
+0.75
—
2)3)4)5)
DQS-DQ skew (DQS and associated DQ signals) tDQSQ
Write command to 1st DQS latching transition
+0.5
1.25
—
TSOPII 2)3)4)5)
2)3)4)5)
tDQSS
tDS
0.75
0.5
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)7)
DQ and DM input setup time
DQS falling edge hold time from CK (write cycle) tDSH
0.2
—
DQS falling edge to CK setup time (write cycle)
Clock Half Period
tDSS
tHP
tHZ
tIH
0.2
—
min. (tCL, tCH
)
Data-out high-impedance time from CK/CK
Address and control input hold time
–0.75
+0.75
—
0.9
fast slew rate
3)4)5)6)8)
1.0
—
ns
slow slew rate
3)4)5)6)8)
2)3)4)5)9)
Control and Addr. input pulse width (each input)
Address and control input setup time
tIPW
tIS
2.2
0.9
—
—
ns
ns
fast slew rate
3)4)5)6)8)
1.0
—
ns
ns
slow slew rate
3)4)5)6)8)
2)3)4)5)7)
Data-out low-impedance time from CK/CK
tLZ
–0.75
+0.75
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HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
Parameter
Symbol
–7
DDR266A
Min.
Unit
Note1)/Test
Condition
Max.
2)3)4)5)
2)3)4)5)
Mode register set command cycle time
DQ/DQS output hold time
tMRD
tQH
2
—
tCK
ns
ns
ns
t
HP –tQHS
Data hold skew factor
tQHS
tRAP
tRAS
tRC
—
0.75
—
TSOPII 2)3)4)5)
2)3)4)5)
Active to Read w/AP delay
tRCD
45
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)10)
2)3)4)5)
Active to Precharge command
Active to Active/Auto-refresh command period
Active to Read or Write delay
Average Periodic Refresh Interval
120E+3 ns
65
—
—
—
—
ns
ns
µs
ns
tRCD
tREFI
tRFC
20
7.8
75
Auto-refresh to Active/Auto-refresh command
period
2)3)4)5)
Precharge command period
Read preamble
tRP
20
0.9
0.4
15
0.25
0
—
1.1
0.6
—
—
—
—
—
—
ns
tCK
tCK
ns
tCK
ns
tCK
ns
tCK
ns
tCK
2)3)4)5)
tRPRE
tRPST
tRRD
2)3)4)5)
Read postamble
2)3)4)5)
Active bank A to Active bank B command
Write preamble
2)3)4)5)
tWPRE
tWPRES
tWPST
tWR
2)3)4)5)11)
2)3)4)5)12)
2)3)4)5)
Write preamble setup time
Write postamble
0.4
15
1
Write recovery time
2)3)4)5)
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
tWTR
2)3)4)5)13)
2)3)4)5)
tXSNR
tXSRD
75
200
—
1)
VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V ; 0 °C ≤ TA ≤ 70 °C
2) Input slew rate ≥ 1 V/ns
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT
6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time.
7) HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between VIH(ac) and VIL(ac)
.
t
.
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on tDQSS
.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
13) In all circumstances, tXSNR can be satisfied using tXSNR = tRFC,min + 1 × tCK
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HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 21
IDD Conditions
Parameter
Symbol
Operating Current: one bank; active/ precharge; tRC = tRCMIN; tCK = tCKMIN
;
IDD0
DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two
clock cycles.
Operating Current: one bank; active/read/precharge; Burst = 4;
IDD1
Refer to the following page for detailed test conditions.
Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE ≤ VILMAX; tCK = tCKMIN
IDD2P
IDD2F
Precharge Floating Standby Current: CS ≥ VIHMIN, all banks idle;
CKE ≥ VIHMIN; tCK = tCKMIN, address and other control inputs changing once per clock cycle, VIN = VREF for DQ, DQS
and DM.
Precharge Quiet Standby Current:
IDD2Q
CS ≥ VIHMIN, all banks idle; CKE ≥ VIHMIN; tCK = tCKMIN, address and other control inputs stable
at ≥ VIHMIN or ≤ VILMAX; VIN = VREF for DQ, DQS and DM.
Active Power-Down Standby Current: one bank active; power-down mode;
CKE ≤ VILMAX; tCK = tCKMIN; VIN = VREF for DQ, DQS and DM.
IDD3P
Active Standby Current: one bank active; CS ≥ VIHMIN; CKE ≥ VIHMIN; tRC = tRASMAX; tCK = tCKMIN; DQ, DM and DQS IDD3N
inputs changing twice per clock cycle; address and control inputs changing once per clock cycle.
Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs changing
once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A,
CL = 3 for DDR333; tCK = tCKMIN; IOUT = 0 mA
IDD4R
Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs changing
once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A,
CL = 3 for DDR333; tCK = tCKMIN
IDD4W
Auto-Refresh Current: tRC = tRFCMIN, burst refresh
IDD5
IDD6
IDD7
Self-Refresh Current: CKE ≤ 0.2 V; external clock on; tCK = tCKMIN
Operating Current: four bank; four bank interleaving with BL = 4; Refer to the following page for detailed test
conditions.
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HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
TABLE 22
IDD Specification
–7
DDR266A
–6
–5
Unit
Note1)/Test Condition
DDR333
Typ.
DDR400B
Symbol
Typ.
Max.
Max.
Typ.
Max.
IDD0
65
80
75
90
1.5
20
15
9
78
75
90
80
100
120
110
140
4
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
×4/×8 2)3)
×16 3)
×4/×8 3)
×16 3)
3)
95
90
110
100
125
4
100
90
IDD1
90
85
110
4
105
1.6
25
115
1.7
30
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
3)
3)
3)
24
30
36
21
17
24
19
26
13
11
15
12
16
29
31
67
85
71
90
170
2.6
2.5
204
215
35
35
41
39
47
×4/×8 3)
×16 3)
×4/×8 3)
×16 3)
×4/×8 3)
×16 3)
37
37
44
42
50
IDD4R
IDD4W
78
77
90
85
100
145
105
150
245
5.0
2.5
310
340
100
83
105
81
125
95
120
90
105
205
5.0
2.5
243
255
110
185
2.7
2.5
234
255
130
220
5.0
2.5
279
310
125
205
2.8
2.5
260
285
3)4)
IDD5
IDD6
3)
low power
×4/×8 3)
×16 3)
IDD7
1) Test conditions for typical values: VDD = 2.5 V (DDR266, DDR333), VDD = 2.6 V (DDR400), TA = 25 °C, test conditions for maximum values:
DD = 2.7 V, TA = 10 °C
DD specifications are tested after the device is properly initialized and measured at 133 MHz for DDR266, 166 MHz for DDR333, and 200
MHz for DDR400.
V
2)
I
3) Input slew rate = 1 V/ns.
4) Enables on-chip refresh and address counters.
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HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
5
Package Outlines
There are two package types used for this product family each in lead-free and lead-containing assembly:
• P-TFBGA: Plastic Thin Fine-Pitch Ball Grid Array Package
TABLE 23
TFBGA Common Package Properties (non-green/green)
Description
Size
Units
Ball Size
0.460
0.350
0.450
mm
mm
mm
Recommended Landing Pad
Recommended Solder Mask
•
P-TSOPII: Plastic Thin Small Outline Package Type II
FIGURE 4
Package Outline of P-TFBGA-60-[9/22] (green/non-green)
12
11 x 1 = 11
0.18 MAX.
1
0.2
2)
B
2)
4)
3)
1) 5)
A
0.1
C
0.1
C
60x
ø0.15
ø0.08
±0.05
ø0.46
M
M
A B
C SEATING PLANE
C
1) Dummy Pads without Ball
2) Middle of Packages Edges
3) Package Orientation Mark A1
4) Bad Unit Marking (BUM)
5) Die Sort Fiducial
GPA09554
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HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
FIGURE 5
Package Outline of P-TSOPII-66-1 (Lead-Free/Lead-Containing)
Gage Plane
±0.13
10.16
±0.1
0.65 Basic
0.5
+0.1
0.805 REF
0.1
Seating Plane
0.35
±0.2
-0.05
11.76
±0.13
22.22
Lead 1
GPX09261
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Internet Data Sheet
HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Pin Configuration P-TFBGA-60 Top View, see the balls throught the package . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Configuration P-TSOPII-66-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
AC Output Load Circuit Diagram / Timing Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Package Outline of P-TFBGA-60-[9/22] (green/non-green) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Package Outline of P-TSOPII-66-1 (Lead-Free/Lead-Containing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering Information for RoHS compliant products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration of DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Mode Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Burst Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Extended Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Truth Table 1a: Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Truth Table 1b: DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Truth Table 2: Clock Enable (CKE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Truth Table 3: Current State Bank n - Command to Bank n (same bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Truth Table 4: Current State Bank n - Command to Bank m (different bank). . . . . . . . . . . . . . . . . . . . . . . . . . 21
Truth Table 5: Concurrent Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Input and Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Electrical Characteristics and DC Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AC Timing - Absolute Specifications for PC3200 and PC2700. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AC Timing - Absolute Specifications for PC2100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
I
DD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
IDD Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TFBGA Common Package Properties (non-green/green) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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HYB25D512[40/16/80]0B[E/F/C/T](L)
Double-Data-Rate SDRAM
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
3
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
4.1
4.2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Rev. 1.63, 2006-09
37
03062006-PFFJ-YJY2
Internet Data Sheet
Edition 2006-09
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2006.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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