HYB18T1G161C2F-20 [QIMONDA]
DDR DRAM, 64MX16, 0.45ns, CMOS, PBGA84, GREEN, PLASTIC, TFBGA-84;
| 型号： | HYB18T1G161C2F-20 |
| 厂家： | 
QIMONDA AG |
| 描述： | DDR DRAM, 64MX16, 0.45ns, CMOS, PBGA84, GREEN, PLASTIC, TFBGA-84 时钟 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总40页 (文件大小：1442K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 2008
HYB18T1G161C2F–16/20/25
1-Gbit Double-Data-Rate-Two SDRAM
DDR2 SDRAM
EU RoHS Compliant Products
Internet Data Sheet
Rev. 1.00
Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
HYB18T1G161C2F–16/20/25
Revision History: 2008-08, Rev. 1.00
Page
Subjects (major changes since last revision)
Adapted Internet Edition
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qag_techdoc_A4, 4.20, 2008-01-25
08062008-JJWD-BZ23
2
Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
1
Overview
This chapter gives an overview of the 1-Gbit Double-Data-Rate-Two SDRAM product family for graphics applications and
describes its main characteristics.
1.1
Features
The 1-Gbit Double-Data-Rate-Two SDRAM offers the following key features:
•
•
•
•
•
•
1.8 V ± 0.1 V VDD for [–16/–20/–25]
1.8 V ± 0.1 V VDDQ for [–16/–20/–25]
1.5 V ± 0.05 V VDD for [–20/–25]
1.5 V ± 0.05 V VDDQ for [–20/–25]
DRAM organizations with 16 data in/outputs
•
Commands entered on each positive clock edge, data and
data mask are referenced to both edges of DQS
Data masks (DM) for write data
Posted CAS by programmable additive latency (0-7) for
better command and data bus efficiency
Off-Chip-Driver impedance adjustment (OCD) and On-
Die-Termination (ODT) for better signal quality.
Auto-Precharge operation for read and write bursts
Auto-Refresh, Self-Refresh and power saving Power-
Down modes
Average Refresh Period 7.8 μs at a TCASE lower than 85°C,
3.9 μs between 85°C and 95°C
Full Strength and reduced Strength (60%) Data-Output
Drivers
2 K page size
•
•
Double Data Rate architecture:
•
– two data transfers per clock cycle
– eight internal banks for concurrent operation
Programmable CAS Latency: 3, 4, 5, 6, 7
Programmable Burst Length: 4 and 8
Differential clock inputs (CK and CK)
Bi-directional, differential data strobes (DQS and DQS) are
transmitted / received with data. Edge aligned with read
data and center-aligned with write data.
DLL aligns DQ and DQS transitions with clock
DQS can be disabled for single-ended data strobe
operation
•
•
•
•
•
•
•
•
•
•
•
•
•
Package: PG-TFBGA-84
RoHS Compliant Products1)
TABLE 1
Ordering Information for RoHS compliant products
Product Number
Org.
Clock (MHz)
Package
HYB18T1G161C2F–16/20/25
×16
600/500/400
PG-TFBGA-84
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.00, 2008-08
3
08062008-JJWD-BZ23
Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
1.2
Description
The 1-Gbit Double-Data-Rate-Two SDRAM is a high-speed Double-Data-Rate-Two CMOS Synchronous DRAM device
containing 1,073,741,824 bits and internally configured as a quad bank DRAM. The 1-Gb device is organized as
8 Mbit × 16 I/O × 8 banks chip. These synchronous devices achieve high speed transfer rates starting at 800 Mb/sec/pin for
general applications.
The device is designed to comply with all DDR2 DRAM key features:
1. posted CAS with additive latency,
2. write latency = read latency - 1,
3. normal and weak strength data-output driver,
4. Off-Chip Driver (OCD) impedance adjustment
5. On-Die Termination (ODT) function.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched
at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or
differential DQS-DQS pair in a source synchronous fashion.
A 16-bit address bus is used to convey row, column and bank address information in a RAS-CAS multiplexing style.
An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes.
The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
The DDR2 SDRAM is available in P-TFBGA package.
Rev. 1.00, 2008-08
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08062008-JJWD-BZ23
Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
2
Configuration
2.1
Chip Configuration
The chip configuration of a DDR2 SDRAM is listed by function in Table 2. The abbreviations used in the Ball# and Buffer Type
columns are explained in Table 3 and Table 4 respectively. The ball numbering for the FBGA package is depicted in Figure 1.
TABLE 2
Chip Configuration of DDR2 SDRAM
Ball#
Name
Ball Type Buffer Type Function
Clock Signals
J8
CK
CK
I
I
SSTL
SSTL
Clock Signal CK, Complementary Clock Signal CK
Note: CK and CK are differential system clock inputs. All address
and control inputs are sampled on the crossing of the positive
edge of CK and negative edge of CK. Output (read) data is
referenced to the crossing of CK and CK (both direction of
crossing)
K8
K2
CKE
I
SSTL
Clock Enable
Note: CKE HIGH activates and CKE LOW deactivates internal
clock signals and device input buffers and output drivers.
Taking CKE LOW provides Precharge Power-Down and Self-
Refresh operation (all banks idle), or Active Power-Down
(row Active in any bank). CKE is synchronous for power down
entry and exit and for self-refresh entry. Input buffers
excluding CKE are disabled during self-refresh. CKE is used
asynchronously to detect self-refresh exit condition. Self-
refresh termination itself is synchronous. After VREF has
become stable during power-on and initialisation sequence, it
must be maintained for proper operation of the CKE receiver.
For proper self-refresh entry and exit, VREF must be
maintained to this input. CKE must be maintained HIGH
throughout read and write accesses. Input buffers, excluding
CK, CK, ODT and CKE are disabled during power-down
Control Signals
K7
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
L7
K3
L8
CS
Chip Select
Address Signals
L2
L3
L1
BA0
BA1
BA2
I
I
I
SSTL
SSTL
SSTL
Bank Address Bus 2:0
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08062008-JJWD-BZ23
Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
Ball#
Name
Ball Type Buffer Type Function
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
A0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Address Signal 12:0, Address Signal 10/Autoprecharge
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
P7
R2
Data Signals
G8
DQ0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Signal 15:0
Note: Bi-directional data bus. DQ[15:0]
G2
DQ1
H7
DQ2
H3
DQ3
H1
DQ4
H9
DQ5
F1
DQ6
F9
DQ7
C8
DQ8
C2
DQ9
D7
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D3
D1
D9
B1
B9
Data Strobe
B7
UDQS I/O
UDQS I/O
SSTL
SSTL
SSTL
SSTL
Data Strobe Upper Byte
Note: UDQS corresponds to the data on DQ[15:8]
A8
F7
LDQS
LDQS
I/O
I/O
Data Strobe Lower Byte
Note: LDQS corresponds to the data on DQ[7:0]
E8
Data Mask
B3
F3
UDM
LDM
I
I
SSTL
SSTL
Data Mask Upper/Lower Byte
Note: LDM and UDM are the input mask signals and control the
lower or upper bytes.
Power Supplies
Rev. 1.00, 2008-08
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08062008-JJWD-BZ23
Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
Ball#
Name
Ball Type Buffer Type Function
A9,C1,C3,C7,C9
A1
VDDQ
VDD
PWR
PWR
PWR
PWR
–
–
–
–
I/O Driver Power Supply
Power Supply
A7,B2,B8,D2,D8
A3,E3
VSSQ
VSS
I/O Driver Power Supply
Power Supply
Power Supplies
J2
VREF
AI
–
–
–
–
–
–
–
I/O Reference Voltage
I/O Driver Power Supply
Power Supply
E9, G1, G3, G7, G9 VDDQ
PWR
PWR
PWR
PWR
PWR
PWR
J1
VDDL
VDD
E1, J9, M9, R1
Power Supply
E7, F2, F8, H2, H8 VSSQ
I/O Driver Power Supply
Power Supply
J7
VSSDL
VSS
A3, E3,J3,N1,P9
Not Connected
Power Supply
A2, E2, R3, R7, R8 NC
NC
I
–
Not Connected
Other Balls
K9
ODT
SSTL
On-Die Termination Control
Note: ODT is applied to each DQ, UDQS, UDQS, LDQS, LDQS,
UDM and LDM signal. An EMRS(1) control bit enables or
disables the ODT functionality.
TABLE 3
Abbreviations for Ball Type
Abbreviation
Description
I
Standard input-only ball. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
O
I/O
AI
PWR
GND
NC
Ground
Not Connected
TABLE 4
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
LV-CMOS
CMOS
OD
CMOS Levels
Open Drain. The corresponding ball has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Rev. 1.00, 2008-08
7
08062008-JJWD-BZ23
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Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
FIGURE 1
Chip Configuration, PG-TFBGA-84 (top view)
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Notes
2. LDM is the data mask signal for DQ[7:0], UDM is the data
mask signal for DQ[15:8]
3. VDDL and VSSDL are power and ground for the DLL. VDDL is
connected to VDD on the device. VSSDL is connected to VSS
internally. VDD, VDDQ and VSSQ are isolated on the device.
1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is
data strobe for DQ[7:0]
Rev. 1.00, 2008-08
8
08062008-JJWD-BZ23
Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
2.2
DDR2 Addressing
This chapter describes the DDR2 addressing.
TABLE 5
DDR2 Addressing
Configuration
64 Mb x161)
Note
Bank Address
BA[2:0]
8
Number of Banks
Auto Precharge
A10 / AP
A[12:0]
A[9:0]
10
Row Address
Column Address
Number of Column Address Bits
Number of I/Os
2)
3)
16
Page Size [Bytes]
2048 (2 K)
1) Referred to as ’org’
2) Referred to as ’colbits’
3) PageSize = 2colbits × org/8 [Bytes]
Rev. 1.00, 2008-08
9
08062008-JJWD-BZ23
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Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
3
Functional Description
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TABLE 6
Mode Register Definition (BA[2:0] = 000B)
Field
Bits
Type1)
Description
Bank Address [2]
0B BA2 Bank Address
Bank Address [1]
BA2
15
reg. addr.
BA1
BA0
PD
14
13
12
0B
BA1 Bank Address
Bank Address [0]
0B
BA0 Bank Address
w
w
Active Power-Down Mode Select
0B
1B
PD Fast exit
PD Slow exit
WR
[11:9]
Write Recovery2)
Note: All other bit combinations are illegal.
000B WR 93)
001B WR 2
010B WR 3
011B WR 4
100B WR 5
101B WR 6
110B WR 7
111B WR 8
DLL
TM
8
7
w
w
DLL Reset
0B
1B
DLL No Reset
DLL Reset
Test Mode
0B
1B
TM Normal Mode
TM Vendor specific test mode
Rev. 1.00, 2008-08
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08062008-JJWD-BZ23
Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
Field
Bits
Type1)
Description
CL
[6:4]
w
CAS Latency
Note: All other bit combinations are illegal.
000B Reserved
001B Reserved
010B Reserved
011B CL 3
100B CL 4
101B CL 5
110B CL 6
111B CL 7
BT
BL
3
w
w
Burst Type
0B
1B
BT Sequential
BT Interleaved
[2:0]
Burst Length
Note: All other bit combinations are illegal.
010B BL 4
011B BL 8
1) w = write only register bits
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and
rounding up to the next integer: WR [cycles] ≥ tWR (ns) / tCK (ns). The mode register must be programmed to fulfill the minimum requirement
for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by tCK.MIN
.
3) Write Recovery time WR = 9 is only necessary for clock frequency above 500 MHz.
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TABLE 7
Extended Mode Register Definition (BA[2:0] = 001B)
Field
Bits Type1)
Description
Bank Address [2]
0B BA2 Bank Address
Bank Address [1]
BA2
15
14
13
12
reg. addr
BA1
BA0
Qoff
0B
BA1 Bank Address
Bank Address [0]
1B
BA0 Bank Address
w
w
Output Disable
0B
1B
QOff Output buffers enabled
QOff Output buffers disabled
A11
11
Address Bus [11]
0B A11 Address bit 11
Rev. 1.00, 2008-08
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08062008-JJWD-BZ23
Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
Field
Bits Type1)
Description
DQS
10
w
Complement Data Strobe (DQS Output)
0B
1B
DQS Enable
DQS Disable
OCD
9:7
w
Off-Chip Driver Calibration Program
Program
000B OCD OCD calibration mode exit, maintain setting
001B OCD Drive (1)
010B OCD Drive (0)
100B OCD Adjust mode
111B OCD OCD calibration default
AL
5:3
w
Additive Latency
Note: All other bit combinations are illegal.
000B AL 0
001B AL 1
010B AL 2
011B AL 3
100B AL 4
101B AL 5
110B AL 6
111B AL 7
RTT
6,2
w
Nominal Termination Resistance of ODT
Note: See Table 18 “ODT DC Electrical Characteristics” on Page 19
00B RTT ∞ (ODT disabled)
01B RTT 75 Ohm
10B RTT 150 Ohm
11B RTT 50 Ohm
DIC
DLL
1
0
w
w
Off-chip Driver Impedance Control
0B
1B
DIC Full (Driver Size = 100%)
DIC Reduced
DLL Enable
0B
1B
DLL Enable
DLL Disable
1) w = write only register bits
A0 is used for DLL enable or disable. A1 is used for enabling
half-strength data-output driver. A2 and A6 enables On-Die
termination (ODT) and sets the Rtt value. A[5:3] are used for
additive latency settings and A[9:7] enables the OCD
impedance adjustment mode. A10 enables or disables the
differential DQS. Address bit A12 have to be set to 0 for
normal operation. With A12 set to 1 the SDRAM outputs are
disabled and in Hi-Z. 1 on BA0 and 0 for BA[2:1] have to be
set to access the EMRS(1).
Rev. 1.00, 2008-08
12
08062008-JJWD-BZ23
Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
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TABLE 8
EMRS(2) Programming Extended Mode Register Definition (BA[2:0]=010B)
Field Bits
Type1)
Description
BA2
15
w
Bank Address
0B
BA2 Bank Address
BA
14:13
w
Bank Adress
00B BA MRS
01B BA EMRS(1)
10B BA EMRS(2)
11B BA EMRS(3): Reserved
A
[12:8]
7
w
w
Address Bus
00000B
A Address bits
SRF
Address Bus, High Temperature Self Refresh Rate for TCASE > 85°C
0B
1B
A7 disable
A7 enable 2)
A
[6:4]
3
w
w
Address Bus
000B A Address bits
DCC
Address Bus, Duty Cycle Correction (DCC)
0B
1B
A3 DCC disabled
A3 DCC enabled
Partial Self Refresh for 8 banks
PASR [2:0]
w
Address Bus, Partial Array Self Refresh for 8 Banks3)
Note: Only for 1G and 2G components
000B PASR0 Full Array
001B PASR1 Half Array (BA[2:0]=000, 001, 010 & 011)
010B PASR2 Quarter Array (BA[2:0]=000, 001)
011B PASR3 1/8 array (BA[2:0] = 000)
100B PASR4 3/4 array (BA[2:0]= 010, 011, 100, 101, 110 & 111)
101B PASR5 Half array (BA[2:0]=100, 101, 110 & 111)
110B PASR6 Quarter array (BA[2:0]= 110 & 111)
111B PASR7 1/8 array(BA[2:0]=111)
1) w = write only
2) When DRAM is operated at 85°C ≤ TCase ≤ 95°C the extended self refresh rate must be enabled by setting bit A7 to "1" before the self
refresh mode can be entered.
3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refreshis
entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued
Rev. 1.00, 2008-08
13
08062008-JJWD-BZ23
UH
J
ꢌꢃD
GGUꢃꢃ
Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
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TABLE 9
EMR(3) Programming Extended Mode Register Definition( BA[2:0]=011B)
Field
Bits
Type1)
Description
BA2
15
reg.addr
Bank Address
0B
BA2 Bank Address
BA1
BA0
A
14
13
reg.addr
Bank Adress
1B
BA1 Bank Address
Bank Adress
1B
BA0 Bank Address
[12:0]
w
Address Bus
0000000000000B Address bits
1) w = write only
Rev. 1.00, 2008-08
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08062008-JJWD-BZ23
Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
TABLE 10
ODT Truth Table
Input Pin
EMRS(1) Address Bit A10
EMRS(1) Address Bit A11
DQ[7:0]
DQ[15:8]
LDQS
LDQS
UDQS
UDQS
LDM
X
X
X
0
X
X
X
0
X
X
UDM
Note: X = don’t care; 0 = bit set to low; 1 = bit set to high
TABLE 11
Burst Length and Sequence
Burst Length
Starting Address
(A2 A1 A0)
Sequential Addressing
(decimal)
Interleave Addressing
(decimal)
4
× 0 0
× 0 1
×1 0
0, 1, 2, 3
0, 1, 2, 3
1, 2, 3, 0
1, 0, 3, 2
2, 3, 0, 1
2, 3, 0, 1
×1 1
3, 0, 1, 2
3, 2, 1, 0
8
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Notes
2. Order of burst access for sequential addressing is “nibble-
based” and therefore different from SDR or DDR
components
1. Page Size and Length is a function of I/O organization:
Page Size = 2 KByte; Page Length = 1024
Rev. 1.00, 2008-08
15
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Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
4
Truth Tables
TABLE 12
Command Truth Table
Function
CKE
CS RAS CAS WE BA0 A[12:11] A10 A[9:0]
Note1)2)3)
BA1
BA2
Previous Current
Cycle
Cycle
4)5)
4)
(Extended) Mode Register Set H
H
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
L
L
BA OP Code
Auto-Refresh
H
H
L
L
L
H
H
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
4)6)
4)6)7)
Self-Refresh Entry
Self-Refresh Exit
L
L
H
X
H
L
X
H
H
H
H
L
4)5)
4)
Single Bank Precharge
Precharge all Banks
Bank Activate
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
L
BA
X
X
X
L
X
X
L
L
H
4)5)
4)5)8)
4)5)8)
4)5)8)
4)5)8)
4)
L
H
L
BA Row Address
Write
H
H
H
H
H
X
X
H
X
H
BA Column
BA Column
BA Column
BA Column
L
Column
Column
Column
Column
X
Write with Auto-Precharge
Read
L
L
H
L
L
H
H
H
X
X
H
X
H
Read with Auto-Precharge
No Operation
L
H
X
X
X
H
X
X
H
X
H
X
X
X
X
X
X
4)
Device Deselect
Power Down Entry
X
4)9)
X
4)9)
Power Down Exit
L
H
X
X
X
X
1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
2) “X” means “H or L (but a defined logic level)”.
3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock.
5) Bank addresses BA[2:0] determine which bank is to be operated upon. For (E)MRS BA[2:0] selects an (Extended) Mode Register.
6)
VREF must be maintained during Self Refresh operation.
7) Self Refresh Exit is asynchronous.
8) Burst reads or writes at BL = 4 cannot be terminated.
9) The Power Down Mode does not perform any refresh operations.
Rev. 1.00, 2008-08
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Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
TABLE 13
Clock Enable (CKE) Truth Table for Synchronous Transitions
Current State1) CKE
Command (N)2)3)RAS, Action (N)2)
CAS, WE, CS
Note4)5)
Previous Cycle6) Current Cycle6)
(N-1)
(N)
7)8)11)
Power-Down
Self Refresh
L
L
X
Maintain Power-Down
7)9)10)11)
8)11)12)
L
H
L
DESELECT or NOP
X
Power-Down Exit
L
Maintain Self Refresh
Self Refresh Exit
9)12)13)14)
7)9)10)11)15)
9)10)11)15)
7)11)14)16)
17)
L
H
L
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
AUTOREFRESH
Bank(s)Active
All Banks Idle
H
H
H
H
Active Power-Down Entry
Precharge Power-Down Entry
Self Refresh Entry
L
L
Any State other
than listed above
H
Refer to the Command Truth Table
1) Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
2) Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N)
3) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
4) CKE must be maintained HIGH while the device is in OCD calibration mode.
5) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
6) CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
7) The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by the refresh
requirements
8) “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven HIGH or LOW in
Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1)).
9) All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
10) Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
11) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2×tCKE + tIH.
12) VREF must be maintained during Self Refresh operation.
13) On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. Read
commands may be issued only after tXSRD (200 clocks) is satisfied.
14) Valid commands for Self Refresh Exit are NOP and DESELCT only.
15) Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations, Precharge or
Refresh operations are in progress.
16) Self Refresh mode can only be entered from the All Banks Idle state.
17) Must be a legal command as defined in the Command Truth Table.
TABLE 14
Data Mask (DM) Truth Table
Name (Function)
DM
DQs
Note
1)
Write Enable
L
Valid
X
1)
Write Inhibit
H
1) Used to mask write data; provided coincident with the corresponding data.
Rev. 1.00, 2008-08
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08062008-JJWD-BZ23
Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
5
Electrical Characteristics
This chapter describes the Electrical Characteristics.
5.1
Absolute Maximum Ratings
Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 18 at any time.
TABLE 15
Absolute Maximum Ratings
Symbol
Parameter
Rating
Min.
Unit
Note
Max.
1)
VDD
Voltage on VDD pin relative to VSS
Voltage on VDDQ pin relative to VSS
Voltage on VDDL pin relative to VSS
Voltage on any pin relative to VSS
Junction Temperature
–1.0
–0.5
–0.5
–0.5
–
+2.3
+2.3
+2.3
+2.3
+125
+150
V
1)2)
1)2)
1)
VDDQ
VDDL
VIN, VOUT
TJ
V
V
V
1)
°C
°C
1)2)
TSTG
Storage Temperature
–55
1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 16
DRAM Component Operating Temperature Range
Symbol
Parameter
Rating
Unit
Note
Min.
Max.
1)2)3)4)
TCASE
Operating Temperature
0
95
°C
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case
temperature must be maintained between 0 - 95 °C under all other specification parameters.
3) Above 85 °C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 μs
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%
Rev. 1.00, 2008-08
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Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
5.2
DC Characteristics
TABLE 17
Recommended DC Operating Conditions (SSTL_18)
Symbol
Parameter
Rating
Min.
Unit
Notes
Typ.
Max.
1)3)
1)3)
1)3)
2)3)
2)3)
2)3)
4)5)
6)
VDD
Supply Voltage
1.45
1.5
1.55
V
V
V
V
V
V
V
V
VDDDL
VDDQ
VDD
Supply Voltage for DLL
Supply Voltage for Output
Supply Voltage
1.45
1.5
1.55
1.45
1.5
1.55
1.7
1.8
1.9
VDDDL
VDDQ
VREF
VTT
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.8
1.9
1.7
1.8
1.9
0.49 × VDDQ
0.5 × VDDQ
VREF
0.51 × VDDQ
V
REF – 0.04
VREF + 0.04
1) HYB18T1G161C2F–[20/25]
2) HYB18T1G161C2F–[16/20/25]
3)
VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.
4) The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to
be about 0.5 × VDDQ of the transmitting device and VREF is expected to track variations in VDDQ
5) Peak to peak ac noise on VREF may not exceed ± 2% VREF (dc)
.
6)
V
TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in die dc level of VREF
.
TABLE 18
ODT DC Electrical Characteristics
Parameter / Condition
Symbol
Min.
Nom.
Max.
Unit
Note
1)
Termination resistor impedance value for
EMRS(1)[A6,A2] = [0,1]; 75 Ohm
Rtt1(eff)
60
75
90
Ω
1)
1)
2)
Termination resistor impedance value for
EMRS(1)[A6,A2] =[1,0]; 150 Ohm
Rtt2(eff)
Rtt3(eff)
delta VM
120
40
150
50
180
Ω
Ω
%
Termination resistor impedance value for
EMRS(1)(A6,A2)=[1,1]; 50 Ohm
60
Deviation of VM with respect to VDDQ / 2
–6.00
—
+ 6.00
1) Measurement Definition for Rtt(eff): Apply VIH(ac) and VIL(ac) to test pin separately, then measure current I(VIHac) and I(VILac) respectively.
Rtt(eff) = (VIH(ac) – VIL(ac)) /(I(VIHac) – I(VILac)).
2) Measurement Definition for VM: Turn ODT on and measure voltage (VM) at test pin (midpoint) with no load: delta VM = ((2 x VM / VDDQ) –
1) x 100%
Rev. 1.00, 2008-08
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08062008-JJWD-BZ23
Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
TABLE 19
Input and Output Leakage Currents
Symbol
Parameter / Condition
Min.
Max.
Unit
Notes
1)
IIL
Input Leakage Current; any input 0 V < VIN < VDD
Output Leakage Current; 0 V < VOUT < VDDQ
–2
–5
+2
+5
μA
μA
2)
IOL
1) all other pins not under test = 0 V
2) DQ’s, LDQS, LDQS, UDQS, UDQS, DQS, DQS are disabled and ODT is turned off
5.3
DC & AC Characteristics
DDR2 SDRAM pin timing are specified for either single ended
or differential mode depending on the setting of the EMRS(1)
“Enable DQS” mode bit; timing advantages of differential
mode are realized in system design. The method by which the
DDR2 SDRAM pin timing are measured is mode dependent.
In single ended mode, timing relationships are measured
In differential mode, these timing relationships are measured
relative to the crosspoint of DQS and its complement, DQS.
This distinction in timing methods is verified by design and
characterization but not subject to production test. In single
ended mode, the DQS signals are internally disabled and
don’t care.
relative to the rising or falling edges of DQS crossing at VREF
.
TABLE 20
DC & AC Logic Input Levels
Symbol
Parameter
Min.
Max.
Units
VIH(dc)
VIL(dc)
VIH(ac)
VIL(ac)
DC input logic high
DC input low
V
REF + 0.125
V
DDQ + 0.3
REF – 0.125
V
V
V
V
–0.3
V
AC input logic high
AC input low
V
REF + 0.250
—
—
VREF – 0.250
TABLE 21
Single-ended AC Input Test Conditions
Symbol
Condition
Value
Unit
Notes
1)
VREF
Input reference voltage
0.5 x VDDQ
1.0
V
1)
VSWING.MAX
SLEW
Input signal maximum peak to peak swing
Input signal minimum Slew Rate
V
2)3)
1.0
V / ns
1) Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.
2) The input signal minimum Slew Rate is to be maintained over the range from VIH(ac).MIN to VREF for rising edges and the range from VREF
to VIL(ac).MAX for falling edges as shown in Figure 2
3) AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative
transitions.
Rev. 1.00, 2008-08
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Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
FIGURE 2
Single-ended AC Input Test Conditions Diagram
9,+ꢍDFꢎPLQ
9,+ꢍGFꢎPLQ
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TABLE 22
Differential DC and AC Input and Output Logic Levels
Symbol
Parameter
Min.
Max.
Unit
Notes
1)
2)
3)
4)
5)
VIN(dc)
VID(dc)
VID(ac)
VIX(ac)
VOX(ac)
DC input signal voltage
–0.3
V
V
V
DDQ + 0.3
—
—
V
DC differential input voltage
AC differential input voltage
AC differential cross point input voltage
0.25
DDQ + 0.6
DDQ + 0.6
0.5
0.5 × VDDQ – 0.175
0.5 × VDDQ + 0.175
0.5 × VDDQ + 0.125
V
AC differential cross point output voltage 0.5 × VDDQ – 0.125
V
1)
2)
3)
V
V
V
IN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.
ID(dc) specifies the input differential voltage VTR– VCP required for switching. The minimum value is equal to VIH(dc) – VIL(dc)
ID(ac) specifies the input differential voltage VTR – VCP required for switching. The minimum value is equal to VIH(ac) – VIL(ac)
.
.
4) The value of VIX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VIX(ac) is expected to track variations in VDDQ. VIX(ac)
indicates the voltage at which differential input signals must cross.
5) The value of VOX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VOX(ac) is expected to track variations in VDDQ. VOX(ac)
indicates the voltage at which differential input signals must cross.
FIGURE 3
Differential DC and AC Input and Output Logic Levels Diagram
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Rev. 1.00, 2008-08
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Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
5.4
Output Buffer Characteristics
TABLE 23
Full Strength Calibrated Pull-up Driver Characteristics
Calibrated Pull-up Driver Current [mA]
Voltage (V)
Nominal Minimum1)
(21 Ohms)
Nominal Low2) (18.75 Nominal(18 Nominal High2)
Nominal Maximum4)
(15 Ohms)
Ohms)
ohms)3)
(17.25 Ohms)
0.2
0.3
0.4
–9.5
–10.7
–16.0
–21.0
–11.4
–16.5
–21.2
–11.8
–17.4
–23.0
–13.3
–20.0
–27.0
–14.3
–18.3
1) The driver characteristics evaluation conditions are Nominal Minimum 95 °C (TCASE). VDDQ = 1.45 V, any process
2) The driver characteristics evaluation conditions are Nominal Low and Nominal High 25 °C (TCASE), VDDQ = 1.5 V, any process
3) The driver characteristics evaluation conditions are Nominal 25 °C (TCASE), VDDQ = 1.5 V, typical process
4) The driver characteristics evaluation conditions are Nominal Maximum 0 °C (TCASE), VDDQ = 1.55 V, any process
TABLE 24
Full Strength Calibrated Pull-down Driver Characteristics
Calibrated Pull-down Driver Current [mA]
Voltage (V)
Nominal Minimum1)
(21 Ohms)
Nominal Low2)(18.75 Nominal3) Nominal High2)
Nominal Maximum4)
(15 Ohms)
Ohms)
(18 ohms) (17.25 Ohms)
0.2
0.3
0.4
9.5
10.7
16.0
21.0
11.5
16.6
21.6
11.8
17.4
23.0
13.3
20.0
27.0
14.3
18.7
1) The driver characteristics evaluation conditions are Nominal Minimum 95 °C (TCASE). VDDQ = 1.45 V, any process
2) The driver characteristics evaluation conditions are Nominal Low and Nominal High 25 °C (TCASE), VDDQ = 1.5 V, any process
3) The driver characteristics evaluation conditions are Nominal 25 °C (TCASE), VDDQ = 1.5 V, typical process
4) The driver characteristics evaluation conditions are Nominal Maximum 0 °C (TCASE), VDDQ = 1.55 V, any process
Rev. 1.00, 2008-08
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Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
5.5
Input / Output Capacitance
TABLE 25
Input / Output Capacitance
Symbol
Parameter
Min.
Max.
Unit
CCK
CDCK
CI
Input capacitance, CK and CK
1.0
—
2.0
pF
pF
pF
pF
pF
Input capacitance delta, CK and CK
Input capacitance, all other input-only pins
Input capacitance delta, all other input-only pins
0.25
1.75
0.25
3.5
1.0
—
CDI
CIO
Input/output capacitance,
DQ, DM, DQS, DQS
2.5
CDIO
Input/output capacitance delta,
DQ, DM, DQS, DQS
—
0.5
pF
Rev. 1.00, 2008-08
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Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
5.6
Overshoot and Undershoot Specification
TABLE 26
AC Overshoot / Undershoot Specification for Address and Control Pins
Parameter
–16
–20
–25
Unit
Maximum peak amplitude allowed for overshoot area
Maximum peak amplitude allowed for undershoot area
Maximum overshoot area above VDD
0.5
0.5
0.5
V
0.5
0.5
0.5
V
0.80
0.80
0.80
0.80
0.80
0.80
V.ns
V.ns
Maximum undershoot area below VSS
FIGURE 4
AC Overshoot / Undershoot Diagram for Address and Control Pins
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Rev. 1.00, 2008-08
24
08062008-JJWD-BZ23
Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
TABLE 27
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins
Parameter
–16
–20
–25
Unit
Maximum peak amplitude allowed for overshoot area
Maximum peak amplitude allowed for undershoot area
Maximum overshoot area above VDDQ
0.9
0.9
0.9
V
0.9
0.9
0.9
V
0.23
0.23
0.23
0.23
0.23
0.23
V.ns
V.ns
Maximum undershoot area below VSSQ
FIGURE 5
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins
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03(7ꢀꢆꢊꢀ
Rev. 1.00, 2008-08
25
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Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
5.7
AC Characteristics
5.7.1
Speed Grade Definitions
TABLE 28
Speed Grade Definition
Speed Grade
Parameter
Symbol
–16
–20
–25
Unit
Note
Min.
Max.
Min.
Max.
Min.
Max.
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock
Frequency
@ CL = 3
@ CL = 4
@ CL = 5
@ CL = 6
@ CL = 7
tCK
tCK
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
5
8
5
8
5
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
3.75
3
8
3.75
3
8
3.75
3
8
8
8
8
2.5
1.66
45
60
15
15
8
2.5
2.0
45
60
15
15
8
2.5
2.5
45
60
15
15
8
8
8
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
70k
—
—
—
70k
—
—
—
70k
—
—
—
1)Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are
further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) under the “Reference Load for Timing Measurements” .
2)The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4)The output timing reference voltage level is VTT.
5)
tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
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HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
5.7.2
AC Timing Parameters
List of Timing Parameters
TABLE 29
Timing Parameter by Speed Grade
Parameter
Symbol –16
Min.
–20
–25
Unit Notes
1)2)3)4)
5)6)
Max.
Min.
Max.
Min.
Max.
DQ output access time from CK / CK tAC
–400
2
+400
—
–450
2
+450
—
–500
2
+500
—
ps
CAS A to CAS B command period
CK, CK high-level width
tCCD
tCK
tCK
tCK
tCH
0.45
3
0.55
—
0.45
3
0.55
—
0.45
3
0.55
—
CKE minimum high and low pulse
width
tCKE
CK, CK low-level width
tCL
0.45
0.55
—
0.45
0.55
—
0.45
0.55
—
tCK
7)
Auto-Precharge write recovery +
precharge time
tDAL
WR + tRP
WR + tRP
WR + tRP
tCK
8)
Minimum time clocks remain ON
after CKE asynchronously drops
LOW
tDELAY
tIS + tCK
tIH
+
––
tIS + tCK
tIH
+
––
tIS + tCK
tIH
+
––
ns
9)
DQ and DM input hold time
(differential data strobe)
tDH
90
––
145
-105
0.35
–450
0.35
—
––
250
0
––
ps
9)
DQ and DM input hold time (single tDH1
ended data strobe)
-160
0.35
–400
0.35
—
––
––
––
ps
DQ and DM input pulse width (each tDIPW
input)
—
—
0.35
–500
0.35
—
—
tCK
9)
DQS output access time from CK / tDQSCK
CK
+400
—
+450
—
+500
—
ps
DQS input low (high) pulse width
(write cycle)
tDQSL,H
tDQSQ
tCK
10)
DQS-DQ skew (for DQS &
associated DQ signals)
280
280
280
ps
Write command to 1st DQS latching tDQSS
transition
WL –
0.25
WL + WL –
WL +
0.25
WL –
0.25
WL +
0.25
tCK
0.25
0.25
9)
DQ and DM input setup time
(differential data strobe)
tDS
-35
-160
0.2
0.2
40
20
125
––
––
—
—
ps
9)
DQ and DM input setup time (single tDS1
ended data strobe)
-105
0.2
0.2
40
0
ps
DQS falling edge hold time from CK tDSH
(write cycle)
—
—
—
—
0.2
0.2
45
tCK
tCK
DQS falling edge to CK setup time tDSS
(write cycle)
11)
Four Activate Window period
Clock half period
tFAW
tHP
—
—
—
—
—
—
ns
12)
MIN. (tCL,
tCH
MIN. (tCL,
tCH
MIN. (tCL,
tCH
)
)
)
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HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
Parameter
Symbol –16
Min.
–20
Min.
—
–25
Min.
—
Unit Notes
1)2)3)4)
5)6)
Max.
Max.
Max.
tAC.MAX ps
13)
Data-out high-impedance time from tHZ
—
tAC.MAX
tAC.MAX
CK / CK
Address and control input hold time tIH
475
0.6
525
0.6
575
0.6
—
—
ps
Address and control input pulse
width (each input)
tIPW
—
—
tCK
Address and control input setup time tIS
350
400
450
—
ps
13)
13)
DQ low-impedance time from CK /
CK
tLZ(DQ)
2 × tAC.MIN tAC.MAX 2 × tAC.MIN tAC.MAX 2 × tAC.MIN tAC.MAX ps
DQS low-impedance from CK / CK tLZ(DQS) tAC.MIN
tAC.MAX tAC.MIN tAC.MAX tAC.MIN tAC.MAX ps
Mode register set command cycle
time
tMRD
2
—
2
0
—
2
0
—
tCK
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
tOIT
0
12
12
12
ns
tQH
t
HP–tQHS
—
t
HP–tQHS
—
t
HP–tQHS
—
tQHS
tREFI
—
380
7.8
3.9
—
—
380
7.8
3.9
—
—
380
7.8
3.9
—
ps
μs
μs
ns
14)15)
14)16)
17)
Average periodic refresh Interval
—
—
—
—
—
—
Auto-Refresh toActive/Auto-Refresh tRFC
127.5
127.5
127.5
command period
13)
Read preamble
Read postamble
tRPRE
tRPST
tRRD
0.9
0.40
10
1.1
0.60
—
0.9
0.40
10
1.1
0.60
—
0.9
0.40
10
1.1
0.60
—
tCK
tCK
ns
13)
18)15)
Active bank A to Active bank B
command period
Internal Read to Precharge
command delay
tRTP
7.5
—
7.5
—
7.5
—
ns
Write preamble
Write postamble
tWPRE
tWPST
0.35 x tCK
0.40
—
0.35 x tCK
0.40
—
0.35 x tCK
0.40
—
tCK
tCK
ns
18)
0.60
—
0.60
—
0.60
—
Write recovery time for write without tWR
14
14
15
Auto-Precharge
19)
20)
21)
Write recovery time for write with
Auto-Precharge
WR
t
WR/tCK
t
WR/tCK
t
WR/tCK
tCK
ns
Internal Write to Read command
delay
tWTR
tXARD
7.5
2
—
—
7.5
2
—
—
7.5
2
—
—
Exit power down to any valid
command
tCK
(other than NOP or Deselect)
21)
Exit active power-down mode to
Read command (slow exit, lower
power)
tXARDS
10 – AL
2
—
—
10 – AL
2
—
—
8 – AL
2
—
—
tCK
Exit precharge power-down to any
valid command (other than NOP or
Deselect)
tXP
tCK
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HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
Parameter
Symbol –16
Min.
–20
–25
Unit Notes
1)2)3)4)
5)6)
Max.
Min.
Max.
Min.
Max.
Exit Self-Refresh to non-Read
command
tXSNR
t
RFC +10
—
t
RFC +10
—
t
RFC +10
—
ns
Exit Self-Refresh to Read command tXSRD
1) VDDQ, VDD refer to Chapter 1.
200
—
200
—
200
—
tCK
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. For other Slew Rates see Chapter 5 of this
data sheet.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross.The DQS / DQS, input reference
level is the crosspoint when in differential strobe mode;The input reference level for signals other than CK/CK, DQS / DQS, is defined in
Chapter 5.3 of this data sheet.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
6) The output timing reference voltage level is VTT. See Chapter 5 for the reference load for timing measurements.
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock frequency change
during power-down, a specific procedure is required.
9) timing is referenced to JEDEC definition;
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
11) ×16 (2k page size)
12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 μs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
15) 0 °C ≤ TCASE ≤ 85 °C
16) 85 °C < TCASE ≤ 95 °C
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
19) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
Rev. 1.00, 2008-08
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Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
5.7.3
ODT AC Electrical Characteristics
TABLE 30
ODT AC Characteristics and Operating Conditions for all bins
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
1)
tAOND
tAON
ODT turn-on delay
2
2
nCK
ns
1)2)
1)
ODT turn-on
tAC.MIN
tAC.MAX + 0.7 ns
tAONPD
tAOFD
tAOF
ODT turn-on (Power-Down Modes)
ODT turn-off delay
t
AC.MIN + 2 ns
2 tCK +
t
AC.MAX + 1 ns
ns
1)
2.5
2.5
nCK
ns
1)3)
1)
ODT turn-off
tAC.MIN
tAC.MAX + 0.6 ns
tAOFPD
tANPD
tAXPD
ODT turn-off (Power-Down Modes)
ODT to Power Down Mode Entry Latency
ODT Power Down Exit Latency
t
AC.MIN + 2 ns
2.5 tCK +
t
AC.MAX + 1 ns
ns
1)
3
8
—
—
nCK
nCK
1)
1) Unit “tCK.AVG” represents the actual tCK.AVG of the input clock under operation. Unit “nCK” represents one clock cycle of the input clock,
counting the actual clock edges. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be
registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min)
.
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. tAOND is 2 clock cycles after
the clock edge that registered a first ODT HIGH counting the actual input clock edges.
3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD, which is interpreted differently per speed bin. If tCK(avg) = 3 ns is assumed, tAOFD is 1.5 ns (= 0.5 x 3 ns) after
the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges.
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HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
6
Currents Measurement Conditions
TABLE 31
DD Measurement Conditions
I
Parameter
Symbol Note
1)2)3)4)5)6)
Operating Current - One bank Active - Precharge
IDD0
t
CK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), CKE is HIGH, CS is HIGH between valid commands.
Address and control inputs are switching; Databus inputs are switching.
1)2)3)4)5)6)
Operating Current - One bank Active - Read - Precharge
IDD1
I
OUT = 0 mA, BL = 4, tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), tRCD = tRCD(IDD), AL = 0, CL = CL(IDD);
CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are switching; Databus
inputs are switching.
1)2)3)4)5)6)
1)2)3)4)5)6)
1)2)3)4)5)6)
1)2)3)4)5)6)
1)2)3)4)5)6)
1)2)3)4)5)6)
1)2)3)4)5)6)
Precharge Power-Down Current
All banks idle; CKE is LOW; tCK = tCK(IDD);Other control and address inputs are stable; Data bus inputs
are floating.
IDD2P
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are switching,
Data bus inputs are switching.
IDD2N
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are stable,
Data bus inputs are floating.
IDD2Q
IDD3P(0)
IDD3P(1)
IDD3N
Active Power-Down Current
All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable; Data bus inputs
are floating. MRS A12 bit is set to “0” (Fast Power-down Exit).
Active Power-Down Current
All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable, Data bus inputs
are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);
Active Standby Current
All banks open; tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid
commands. Address inputs are switching; Data Bus inputs are switching;
Operating Current
IDD4R
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS
RAS.MAX.(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are
=
t
switching; Data Bus inputs are switching; IOUT = 0 mA.
1)2)3)4)5)6)
Operating Current
IDD4W
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD); tRAS
=
t
RAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address inputs are
switching; Data Bus inputs are switching;
1)2)3)4)5)6)
1)2)3)4)5)6)
Burst Refresh Current
IDD5B
t
CK = tCK(IDD), Refresh command every tRFC = tRFC(IDD) interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are switching, Data bus inputs are switching.
Distributed Refresh Current
IDD5D
t
CK = tCK(IDD), Refresh command every tREFI = 7.8 μs interval, CKE is LOW and CS is HIGH between
valid commands, Other control and address inputs are switching, Data bus inputs are switching.
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HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
Parameter
Symbol Note
1)2)3)4)5)6)
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating, Data
bus inputs are floating.
1)2)3)4)5)6)7)
Operating Bank Interleave Read Current
IDD7
All banks interleaving reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 × tCK(IDD); tCK = tCK(IDD)
,
t
RC = tRC(IDD), tRRD = tRRD(IDD); tFAW = tFAW(IDD); CKE is HIGH, CS is HIGH between valid commands.
Address bus inputs are stable during deselects; Data bus is switching.
1) HYB18T1G161C2F–20/25 with VDDQ = 1.5 V ± 0.05 V; VDD = 1.5 V ± 0.05 V
HYB18T1G161C2F–16/20/25 with VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) IDD specifications are tested after the device is properly initialized
3) IDD parameter are specified with ODT disabled
4) Data Bus consists of DQ, DM, DQS, DQS, LDQS, LDQS, UDQS and UDQS
5) Definitions for IDD: see Table 32
6) Timing parameter minimum and maximum values for IDD current measurements
7) A = Activate, RA = Read with Auto-Precharge, D=DESELECT
Detailed IDD7
The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the
specification. Legend: A = Active; RA = Read with Autoprecharge; D = Deselect.
IDD7 : Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum tRC.IDD without violating tRRD.IDD and tFAW.IDD using a burst length of 4. Control and
address bus inputs are STABLE during DESELECTs. IOUT = 0 mA.
Timing Patterns for devices with 2KB page size
HYB18T1G161C2F–25 (400 MHz): A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6
RA6 D D A7 RA7 D D D D
HYB18T1G161C2F–20 (500 MHz): A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D A4 RA4 D D D A5 RA5 D D
D A6 RA6 D D D A7 RA7 D D D
HYB18T1G161C2F–16 (600 MHz): A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D A4 RA4 D D D D
A5 RA5 D D D D A6 RA6 D D D D A7 RA7 D D D D
TABLE 32
Definition for IDD
Parameter
Description
LOW
defined as VIN ≤ VIL(ac).MAX
HIGH
defined as VIN ≥ VIH(ac).MIN
STABLE
FLOATING
SWITCHING
defined as inputs are stable at a HIGH or LOW level
defined as inputs are VREF = VDDQ / 2
defined as: Inputs are changing between high and low every other clock (once per two clocks) for address
and control signals, and inputs changing between high and low every other clock (once per clock) for DQ
signals not including mask or strobes
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Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
TABLE 33
DD Specification (1.5 V)
I
Speed Grade
Symbol
–20
typ.
–25
typ.
Unit
Note
IDD0
83
94
5
79
90
4
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1
IDD2P
IDD2N
IDD2Q
IDD3P(0)
IDD3P(1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
46
42
28
8
41
37
25
8
1)
2)
52
190
170
193
8
46
162
146
188
7
3)
3)
5
5
IDD7
298
291
1) MRS(12)=0
2) MRS(12)=1
3) 0 ≤ TCASE ≤ 85°C
TABLE 34
DD Specification (1.8 V)
I
Speed Grade
Symbol
–16
–20
typ.
–25
typ.
Unit
Note
typ.
IDD0
101
114
5
88
99
5
83
95
5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1
IDD2P
IDD2N
IDD2Q
IDD3P(0)
IDD3P(1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
57
52
32
8
51
46
29
8
45
42
26
8
1)
2)
63
223
204
203
8
56
195
179
197
8
50
168
154
192
8
3)
3)
5
5
5
IDD7
308
302
296
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Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
1) MRS(12)=0
2) MRS(12)=1
3) 0 ≤ TCASE ≤ 85°C
6.1
IDD Test Conditions
For testing the IDD parameters, the following timing parameters are used:
TABLE 35
DD Measurement Test Condition
I
Parameter
Symbol
–16
–20
–25
Unit
Notes
CAS Latency
CLIDD
7
7
6
tCK
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
Clock Cycle Time
tCKIDD
1.66 2.0
2.5
15
60
10
45
45
70k
15
Active to Read or Write delay
Active to Active / Auto-Refresh command period
Active bank A to Active bank B command delay
Four Active Window Period
tRCD.IDD
tRC.IDD
15
60
10
40
45
15
60
10
40
45
70k
15
—
1)
tRRD.IDD
tFAW(IDD)
tRAS.MIN.IDD
—
—
—
—
—
—
—
Active to Precharge Command
tRAS.MAX.IDD 70k
Precharge Command Period
tRP.IDD
tRFC.IDD
tREFI
15
Auto-Refresh to Active / Auto-Refresh command period
127.5 127.5 127.5 ns
Average periodic Refresh interval
0°C ≤ TCASE ≤ 85°C
85°C ≤ TCASE ≤ 95°C
7.8
3.9
7.8
3.9
7.8
3.9
μs
μs
1) 2 kB page size;
6.1.1
On Die Termination (ODT) Current
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on
address bits A6 & A2 in the EMRS(1) a “weak” or “strong” termination can be selected. The current consumption for any
terminated input pin depends on whether the input pin is in tri-state or driving “0” or “1”, as long a ODT is enabled during a given
period of time.. See Table 36.
TABLE 36
ODT current per terminated input pin
ODT Current
EMRS(1) State
Min.
Typ.
Max.
Unit
Enabled ODT current per DQadded IDDQ current for IODTO
ODT enabled;ODT is HIGH; Data Bus inputs are
floating
A6 = 0, A2 = 1
A6 = 1, A2 = 0
A6 = 1, A2 = 1
A6 = 0, A2 = 1
A6 = 1, A2 = 0
A6 = 1, A2 = 1
5
6
7.5
mA/DQ
mA/DQ
mA/DQ
mA/DQ
mA/DQ
mA/DQ
2.5
7.5
10
5
3
3.75
11.25
15
9
Active ODT current per DQadded IDDQ current for
ODT enabled;ODT is HIGH; worst case of Data Bus
inputs are stable or switching.
IODTT
12
6
7.5
15
18
22.5
Note: For power consumption calculations the ODT duty cycle has to be taken into account
Rev. 1.00, 2008-08
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08062008-JJWD-BZ23
Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
7
Package
7.1
Package Dimension
FIGURE 6
Package Outline PG-TFBGA-84
ꢂꢄꢃꢈ
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ꢊꢃꢂꢄ -!8ꢃ
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ꢀꢁ
"
ꢀꢁ
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ꢅꢁ
ꢄꢁ
!
ꢊꢃꢂ
#
ꢊꢃꢂ
#
ꢋꢀX
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-
-
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#
#
#
,EAD FREE SOLDER BALLS ꢆGREEN SOLDER BALLSꢁ
ꢂꢁ 3"!ꢉFIDUCIAL
ꢄꢁ 0ACKAGE ORIENTATION MARK !ꢂ
ꢅꢁ "AD UNIT MARKING ꢆ"5-ꢁ ꢆLIGHT ꢇ GOODꢁ
ꢀꢁ -IDDLE OF PACKAGES EDGES
ꢈꢁ $UMMY PADS WITHOUT BALL
ꢌꢁ 3OLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION
PREꢉREFLOW DIAMETER ꢊꢃꢀꢈ MM
&0/?0'ꢉ4&"'!??ꢉꢊꢋꢀꢉꢊꢌꢊ
Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
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08062008-JJWD-BZ23
Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
7.2
Package Thermal Characteristics
TABLE 37
Package thermal characteristics
JESD51
Theta_jA1)
Theta_jC2)
JEDEC Board
Air Flow
1s0p
0 m/s
69
2s0p
0 m/s
41
1 m/s
53
3 m/s
47
1 m/s
35
3 m/s
33
Rth[K/W]
5
1) Junction to Ambient thermal resistance. The value has been obtained by simulation using the conditions stated in the Industrial standard.
2) Junction to Case thermal resistance. The value has been obtained by simulation.
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Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
List of Illustrations
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Chip Configuration, PG-TFBGA-84 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Single-ended AC Input Test Conditions Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . 25
Package Outline PG-TFBGA-84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Ordering Information for RoHS compliant products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Chip Configuration of DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Abbreviations for Ball Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Mode Register Definition (BA[2:0] = 000B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Extended Mode Register Definition (BA[2:0] = 001B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
EMRS(2) Programming Extended Mode Register Definition (BA[2:0]=010B). . . . . . . . . . . . . . . . . . . . . . . . . . 13
EMR(3) Programming Extended Mode Register Definition( BA[2:0]=011B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ODT Truth Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Command Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clock Enable (CKE) Truth Table for Synchronous Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Data Mask (DM) Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DRAM Component Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Recommended DC Operating Conditions (SSTL_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ODT DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input and Output Leakage Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DC & AC Logic Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Single-ended AC Input Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Differential DC and AC Input and Output Logic Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Full Strength Calibrated Pull-up Driver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Full Strength Calibrated Pull-down Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
AC Overshoot / Undershoot Specification for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . . . . . . . 25
Speed Grade Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Timing Parameter by Speed Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ODT AC Characteristics and Operating Conditions for all bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
IDD Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Definition for IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
IDD Specification (1.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
IDD Specification (1.8 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
IDD Measurement Test Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ODT current per terminated input pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 37
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08062008-JJWD-BZ23
Internet Data Sheet
HYB18T1G161C2F
1-Gbit Double-Data-Rate-Two SDRAM
Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
2.1
2.2
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chip Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DDR2 Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
4
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DC & AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output Buffer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Input / Output Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Overshoot and Undershoot Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Speed Grade Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.7.1
5.7.2
5.7.3
6
6.1
6.1.1
Currents Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
IDD Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
On Die Termination (ODT) Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7
7.1
7.2
Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Package Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Package Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Rev. 1.00, 2008-08
39
08062008-JJWD-BZ23
Internet Data Sheet
Edition 2008-08
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2008.
All Rights Reserved.
Legal Disclaimer
THE INFORMATION GIVEN IN THIS INTERNET DATA SHEET SHALL IN NO EVENT BE REGARDED AS A GUARANTEE
OF CONDITIONS OR CHARACTERISTICS. WITH RESPECT TO ANY EXAMPLES OR HINTS GIVEN HEREIN, ANY
TYPICAL VALUES STATED HEREIN AND/OR ANY INFORMATION REGARDING THE APPLICATION OF THE DEVICE,
QIMONDA HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND, INCLUDING WITHOUT
LIMITATION WARRANTIES OF NON-INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Under no circumstances may the Qimonda product as referred to in this Internet Data Sheet be used in
1. Any applications that are intended for military usage (including but not limited to weaponry), or
2. Any applications, devices or systems which are safety critical or serve the purpose of supporting, maintaining, sustaining
or protecting human life (such applications, devices and systems collectively referred to as "Critical Systems"), if
a) A failure of the Qimonda product can reasonable be expected to - directly or indirectly -
(i) Have a detrimental effect on such Critical Systems in terms of reliability, effectiveness or safety; or
(ii) Cause the failure of such Critical Systems; or
b) A failure or malfunction of such Critical Systems can reasonably be expected to - directly or indirectly -
(i) Endanger the health or the life of the user of such Critical Systems or any other person; or
(ii) Otherwise cause material damages (including but not limited to death, bodily injury or significant damages to
property, whether tangible or intangible).
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