EFM32GG990F512-BGA112 [QIMONDA]
EFM32GG990 DATASHEET;型号: | EFM32GG990F512-BGA112 |
厂家: | QIMONDA AG |
描述: | EFM32GG990 DATASHEET |
文件: | 总73页 (文件大小:3730K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
EFM32GG990 DATASHEET
F1024/F512
Preliminary
• ARM Cortex-M3 CPU platform
• Communication interfaces
• High Performance 32-bit processor @ up to 48 MHz
• Memory Protection Unit
• 3× Universal Synchronous/Asynchronous Receiv-
er/Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S
• 2× Universal Asynchronous Receiver/Transmitter
• 2× Low Energy UART
• Flexible Energy Management System
• 20 nA @ 3 V Shutoff Mode
• 0.4µA @ 3 V Shutoff Mode with RTC
• 0.9 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out
Detector, RAM and CPU retention
• 1.1 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz
oscillator, Power-on Reset, Brown-out Detector, RAM and CPU
retention
• Autonomous operation with DMA in Deep Sleep
Mode
• 2× I2C Interface with SMBus support
• Address recognition in Stop Mode
• Universal Serial Bus (USB) with Host and OTG sup-
port
• 50 µA/MHz @ 3 V Sleep Mode
• 200 µA/MHz @ 3 V Run Mode, with code executed from Flash
• 1024/512 KB Flash
• Read-while-write support
• 128/128 KB RAM
• 86 General Purpose I/O pins
• Configurable Push-pull, Open-drain, pull resistor, drive strength
• Configurable peripheral I/O locations
• 16 asynchronous external interrupts
• Output state retention and wakeup from Shutoff Mode
• 12 Channel DMA Controller
• 12 Channel Peripheral Reflex System (PRS) for autonomous in-
ter-peripheral signaling
• Hardware AES with 128/256-bit keys in 54/75 cycles
• Timers/Counters
• Fully USB 2.0 compliant
• On-chip PHY and embedded 5V to 3.3V regulator
• Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• 8 single ended channels/4 differential channels
• On-chip temperature sensor
• 12-bit 500 ksamples/s Digital to Analog Converter
• 2 single ended channels/1 differential channel
• 2× Analog Comparator
• Capacitive sensing with up to 16 inputs
• 3× Operational Amplifier
• 6.1 MHz GBW, Rail-to-rail, Programmable Gain
• Supply Voltage Comparator
• Low Energy Sensor Interface (LESENSE)
• Autonomous sensor monitoring in Deep Sleep Mode
• Wide range of sensors supported, including LC sen-
sors and capacitive buttons
• 4× 16-bit Timer/Counter
• 4×3 Compare/Capture/PWM channels
• 16-bit Low Energy Timer
• 1× 24-bit and 1× 32-bit Real-Time Counter
• 3× 16/8-bit Pulse Counter with asynchronous operation
• Watchdog Timer with dedicated RC oscillator @ 50 nA
• Integrated LCD Controller for up to 8×34 segments
• Voltage boost, adjustable contrast and autonomous animation
• Backup Power Domain
• RTC and retention registers in a separate power domain, avail-
able in all energy modes
• Operation from backup battery when main power drains out
• External Bus Interface for up to 4×256 MB of external memory
mapped space
• Ultra efficient Power-on Reset and Brown-Out Detec-
tor
• Debug Interface
• 2-pin Serial Wire Debug interface
• 1-pin Serial Wire Viewer
• Embedded Trace Module v3.5 (ETM)
• Pre-Programmed Serial Bootloader
• Temperature range -40 to 85 ºC
• Single power supply 1.85 to 3.8 V
• BGA112 package
• TFT Controller with Direct Drive
32-bit ARM Cortex-M0+, Cortex-M3 and Cortex-M4F microcontrollers for:
• Energy, gas, water and smart metering
• Health and fitness applications
• Smart accessories
• Alarm and security systems
• Industrial and home automation
• www.energymicro.com/gecko
Preliminary
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1 Ordering Information
Table 1.1 (p. 2) shows the available EFM32GG990 devices.
Table 1.1. Ordering Information
Ordering Code
Flash (KB) RAM
(KB)
Max
Speed
(MHz)
Supply
Voltage
(V)
Temperature
Package
EFM32GG990F512-BGA112
512
128
128
48
48
1.85 - 3.8 -40 - 85 ºC
1.85 - 3.8 -40 - 85 ºC
BGA112
BGA112
EFM32GG990F1204-BGA112 1024
Visit www.energymicro.com for information on global distributors and representatives or contact
sales@energymicro.com for additional information.
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2 System Summary
2.1 System Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of
the powerful 32-bit ARM Cortex-M3, innovative low energy techniques, short wake-up time from energy
saving modes, and a wide selection of peripherals, the EFM32GG microcontroller is well suited for
any battery operated application as well as other systems requiring high performance and low-energy
consumption. This section gives a short introduction to each of the modules in general terms and also
and shows a summary of the configuration for the EFM32GG990 devices. For a complete feature set
and in-depth information on the modules, the reader is referred to the EFM32GG Reference Manual.
A block diagram of the EFM32GG990 is shown in Figure 2.1 (p. 3) .
Figure 2.1. Block Diagram
GG990F512/1024
Core and Memory
Clock Management
Energy Management
High Freq.
Crystal
Oscillator
High Freq
RC
Oscillator
Voltage
Regulator
Voltage
Comparator
Memory
Protection
Unit
ARM Cortex™-M3 processor
Low Freq.
Crystal
Oscillator
Low Freq.
RC
Oscillator
Brown-out
Detector
Power-on
Reset
Flash
Program
Memory
Debug
Interface
w/ ETM
DMA
Controller
RAM
Memory
Ultra Low Freq.
RC
Oscillator
Back-up
Power
Domain
32-bit bus
Peripheral Reflex System
Serial Interfaces
I/O Ports
Analog Interfaces
Security
Timers and Triggers
Timer/
Counter
LCD
ADC
Ext. Bus
Interface
TFT
Driver
LESENSE
USART
UART
Hardware
AES
Controller
Low Energy Real Time
General
Purpose
I/O
Low
Energy
UART
Timer
Counter
Operational
Amplifier
External
Interrupts
I 2C
DAC
Watchdog
Timer
Pulse
Counter
Pin
Reset
Pin
Wakeup
Pulse
Counter
Back-up
RTC
USB
2.1.1 ARM Cortex-M3 Core
The ARM Cortex-M3 includes a 32-bit RISC processor which can achieve as much as 1.25 Dhrystone
MIPS/MHz. A Memory Protection Unit with support for up to 8 memory segments is included, as well
as a Wake-up Interrupt Controller handling interrupts triggered while the CPU is asleep. The EFM32
implementation of the Cortex-M3 is described in detail in EFM32 Cortex-M3 Reference Manual.
2.1.2 Debug Interface (DBG)
This device includes hardware debug support through a 2-pin serial-wire debug interface and an Embed-
ded Trace Module (ETM) for data/instruction tracing. In addition there is also a 1-wire Serial Wire Viewer
pin which can be used to output profiling information, data trace and software-generated messages.
2.1.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the EFM32GG microcontroller.
The flash memory is readable and writable from both the Cortex-M3 and DMA. The flash memory is
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divided into two blocks; the main block and the information block. Program code is normally written to
the main block. Additionally, the information block is available for special user data and flash lock bits.
There is also a read-only page in the information block containing system and device calibration data.
Read and write operations are supported in the energy modes EM0 and EM1.
2.1.4 Direct Memory Access Controller (DMA)
The Direct Memory Access (DMA) controller performs memory operations independently of the CPU.
This has the benefit of reducing the energy consumption and the workload of the CPU, and enables
the system to stay in low energy modes when moving for instance data from the USART to RAM or
from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230 µDMA
controller licensed from ARM.
2.1.5 Reset Management Unit (RMU)
The RMU is responsible for handling the reset functionality of the EFM32GG.
2.1.6 Energy Management Unit (EMU)
The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32GG microcon-
trollers. Each energy mode manages if the CPU and the various peripherals are available. The EMU
can also be used to turn off the power to unused SRAM blocks.
2.1.7 Clock Management Unit (CMU)
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the
EFM32GG. The CMU provides the capability to turn on and off the clock on an individual basis to all
peripheral modules in addition to enable/disable and configure the available oscillators. The high degree
of flexibility enables software to minimize energy consumption in any specific application by not wasting
power on peripherals and oscillators that are inactive.
2.1.8 Watchdog (WDOG)
The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase appli-
cation reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by a
software failure.
2.1.9 Peripheral Reflex System (PRS)
The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module
communicate directly with each other without involving the CPU. Peripheral modules which send out
Reflex signals are called producers. The PRS routes these reflex signals to consumer peripherals which
apply actions depending on the data received. The format for the Reflex signals is not given, but edge
triggers and other functionality can be applied by the PRS.
2.1.10 External Bus Interface (EBI)
The External Bus Interface provides access to external parallel interface devices such as SRAM, FLASH,
ADCs and LCDs. The interface is memory mapped into the address bus of the Cortex-M3. This enables
seamless access from software without manually manipulating the IO settings each time a read or write
is performed. The data and address lines are multiplexed in order to reduce the number of pins required
to interface the external devices. The timing is adjustable to meet specifications of the external devices.
The interface is limited to asynchronous devices.
2.1.11 TFT Direct Drive
The EBI contains a TFT controller which can drive a TFT via a 565 RGB interface. The TFT controller
supports programmable display and port sizes and offers accurate control of frequency and setup and
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hold timing. Direct Drive is supported for TFT displays which do not have their own frame buffer. In
that case TFT Direct Drive can transfer data from either on-chip memory or from an external memory
device to the TFT at low CPU load. Automatic alpha-blending and masking is also supported for transfers
through the EBI interface.
2.1.12 Universal Serial Bus Controller (USB)
The USB is a full-speed USB 2.0 compliant OTG host/device controller. The USB can be used in Device,
On-the-go (OTG) Dual Role Device or Host-only configuration. In OTG mode the USB supports both
Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The device supports both full-
speed (12MBit/s) and low speed (1.5MBit/s) operation. The USB device includes an internal dedicated
Descriptor-Based Scatter/Garther DMA and supports up to 6 OUT endpoints and 6 IN endpoints, in
addition to endpoint 0. The on-chip PHY includes all OTG features, except for the voltage booster for
supplying 5V to VBUS when operating as host.
2.1.13 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C-bus. It is capable of acting as
both a master and a slave, and supports multi-master buses. Both standard-mode, fast-mode and fast-
mode plus speeds are supported, allowing transmission rates all the way from 10 kbit/s up to 1 Mbit/s.
Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system.
The interface provided to software by the I2C module, allows both fine-grained control of the transmission
process and close to automatic transfers. Automatic recognition of slave addresses is provided in all
energy modes.
2.1.14 Universal Synchronous/Asynchronous Receiver/Transmitter (US-
ART)
The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible
serial I/O module. It supports full duplex asynchronous UART communication as well as RS-485, SPI,
MicroWire and 3-wire. It can also interface with ISO7816 SmartCards, I2S devices and IrDA devices.
2.1.15 Pre-Programmed Serial Bootloader
The bootloader presented in application note AN0003 is pre-programmed in the device at factory. Auto-
baud and destructive write are supported. The autobaud feature, interface and commands are described
further in the application note.
2.1.16 Universal Asynchronous Receiver/Transmitter (UART)
The Universal Asynchronous serial Receiver and Transmitter (UART) is a very flexible serial I/O module.
It supports full- and half-duplex asynchronous UART communication.
2.1.17 Low Energy Universal Asynchronous Receiver/Transmitter
(LEUART)
The unique LEUARTTM, the Low Energy UART, is a UART that allows two-way UART communication on
a strict power budget. Only a 32.768 kHz clock is needed to allow UART communication up to 9600 baud/
s. The LEUART includes all necessary hardware support to make asynchronous serial communication
possible with minimum of software intervention and energy consumption.
2.1.18 Timer/Counter (TIMER)
The 16-bit general purpose Timer has 3 compare/capture channels for input capture and compare/Pulse-
Width Modulation (PWM) output. TIMER0 also includes a Dead-Time Insertion module suitable for motor
control applications.
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2.1.19 Real Time Counter (RTC)
The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystal
oscillator, or a 32.768 kHz RC oscillator. In addition to energy modes EM0 and EM1, the RTC is also
available in EM2. This makes it ideal for keeping track of time since the RTC is enabled in EM2 where
most of the device is powered down.
2.1.20 Backup Real Time Counter (BURTC)
The Backup Real Time Counter (BURTC) contains a 32-bit counter and is clocked either by a 32.768 kHz
crystal oscillator, a 32.768 kHz RC oscillator or a 1 kHz ULFRCO. The BURTC is available in all Energy
Modes and it can also run in backup mode, making it operational even if the main power should drain out.
2.1.21 Low Energy Timer (LETIMER)
The unique LETIMERTM, the Low Energy Timer, is a 16-bit timer that is available in energy mode EM2
in addition to EM1 and EM0. Because of this, it can be used for timing and output generation when most
of the device is powered down, allowing simple tasks to be performed while the power consumption of
the system is kept at an absolute minimum. The LETIMER can be used to output a variety of waveforms
with minimal software intervention. It is also connected to the Real Time Counter (RTC), and can be
configured to start counting on compare matches from the RTC.
2.1.22 Pulse Counter (PCNT)
The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadrature
encoded inputs. It runs off either the internal LFACLK or the PCNTn_S0IN pin as external clock source.
The module may operate in energy mode EM0 – EM3.
2.1.23 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indi-
cating which input voltage is higher. Inputs can either be one of the selectable internal references or from
external pins. Response time and thereby also the current consumption can be configured by altering
the current supply to the comparator.
2.1.24 Voltage Comparator (VCMP)
The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can
be generated when the supply falls below or rises above a programmable threshold. Response time and
thereby also the current consumption can be configured by altering the current supply to the comparator.
2.1.25 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits
at up to one million samples per second. The integrated input mux can select inputs from 8 external
pins and 6 internal signals.
2.1.26 Digital to Analog Converter (DAC)
The Digital to Analog Converter (DAC) can convert a digital value to an analog output voltage. The DAC
is fully differential rail-to-rail, with 12-bit resolution. It has two single ended output buffers which can be
combined into one differential output. The DAC may be used for a number of different applications such
as sensor interfaces or sound output.
2.1.27 Operational Amplifier (OPAMP)
The EFM32GG990 features 3 Operational Amplifiers. The Operational Amplifier is a versatile general
purpose amplifier with rail-to-rail differential input and rail-to-rail single ended output. The input can be set
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to pin, DAC or OPAMP, whereas the output can be pin, OPAMP or ADC. The current is programmable
and the OPAMP has various internal configurations such as unity gain, programmable gain using internal
resistors etc.
2.1.28 Low Energy Sensor Interface (LESENSE)
The Low Energy Sensor Interface (LESENSETM), is a highly configurable sensor interface with support
for up to 16 individually configurable sensors. By controlling the analog comparators and DAC, LESENSE
is capable of supporting a wide range of sensors and measurement schemes, and can for instance mea-
sure LC sensors, resistive sensors and capacitive sensors. LESENSE also includes a programmable
FSM which enables simple processing of measurement results without CPU intervention. LESENSE is
available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in
applications with a strict energy budget.
2.1.29 Backup Power Domain
The backup power domain is a separate power domain containing a Backup Real Time Counter, BURTC,
and a set of retention registers, available in all energy modes. This power domain can be configured to
automatically change power source to a backup battery when the main power drains out. The backup
power domain enables the EFM32GG990 to keep track of time and retain data, even if the main power
source should drain out.
2.1.30 Advanced Encryption Standard Accelerator (AES)
The AES accelerator performs AES encryption and decryption with 128-bit or 256-bit keys. Encrypting or
decrypting one 128-bit data block takes 52 HFCORECLK cycles with 128-bit keys and 75 HFCORECLK
cycles with 256-bit keys. The AES module is an AHB slave which enables efficient access to the data
and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or 16-bit
operations are not supported.
2.1.31 General Purpose Input/Output (GPIO)
In the EFM32GG990, there are 86 General Purpose Input/Output (GPIO) pins, which are divided into
ports with up to 16 pins each. These pins can individually be configured as either an output or input. More
advances configurations like open-drain, filtering and drive strength can also be configured individually
for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM
outputs or USART communication, which can be routed to several locations on the device. The GPIO
supports up to 16 asynchronous external pin interrupts, which enables interrupts from any pin on the
device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other
peripherals.
2.1.32 Liquid Crystal Display Driver (LCD)
The LCD driver is capable of driving a segmented LCD display with up to segments. A voltage boost
function enables it to provide the LCD display with higher voltage than the supply voltage for the device.
In addition, an animation feature can run custom animations on the LCD display without any CPU inter-
vention. The LCD driver can also remain active even in Energy Mode 2 and provides a Frame Counter
interrupt that can wake-up the device on a regular basis for updating data.
2.2 Configuration Summary
The features of the EFM32GG990 is a subset of the feature set described in the EFM32GG Reference
Manual. Table 2.1 (p. 7) describes device specific implementation of the features.
Table 2.1. Configuration Summary
Module
Configuration
Pin Connections
Cortex-M3
Full configuration
NA
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Module
Configuration
Pin Connections
DBG
Full configuration
DBG_SWCLK, DBG_SWDIO,
DBG_SWO
MSC
DMA
RMU
EMU
CMU
WDOG
PRS
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
NA
NA
NA
NA
CMU_OUT0, CMU_OUT1
NA
NA
USB
USB_VBUS, USB_VBUSEN,
USB_VREGI, USB_VREGO, USB_DM,
USB_DMPU, USB_DP, USB_ID
EBI
Full configuration
EBI_A[27:0], EBI_AD[15:0], EBI_ARDY,
EBI_ALE, EBI_BL[1:0], EBI_CS[3:0],
EBI_CSTFT, EBI_DCLK, EBI_DTEN,
EBI_HSNC, EBI_NANDREn,
EBI_NANDWEn, EBI_REn, EBI_VSNC,
EBI_WEn
I2C0
Full configuration
Full configuration
IrDA
I2C0_SDA, I2C0_SCL
I2C1_SDA, I2C1_SCL
US0_TX, US0_RX. US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
US2_TX, US2_RX, US2_CLK, US2_CS
U0_TX, U0_RX
I2C1
USART0
USART1
USART2
UART0
UART1
LEUART0
LEUART1
TIMER0
TIMER1
TIMER2
TIMER3
RTC
I2S
I2S
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration with DTI.
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
U1_TX, U1_RX
LEU0_TX, LEU0_RX
LEU1_TX, LEU1_RX
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIM1_CC[2:0]
TIM2_CC[2:0]
TIM3_CC[2:0]
NA
BURTC
LETIMER0
PCNT0
PCNT1
PCNT2
ACMP0
ACMP1
VCMP
NA
LET0_O[1:0]
PCNT0_S[1:0]
8-bit count register
8-bit count register
Full configuration
Full configuration
Full configuration
Full configuration
PCNT1_S[1:0]
PCNT2_S[1:0]
ACMP0_CH[7:0], ACMP0_O
ACMP1_CH[7:0], ACMP1_O
NA
ADC0
ADC0_CH[7:0]
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Module
DAC0
Configuration
Pin Connections
Full configuration
Full configuration
DAC0_OUT[1:0], DAC0_OUTxALT
OPAMP
Outputs: OPAMP_OUTx,
OPAMP_OUTxALT, Inputs:
OPAMP_Px, OPAMP_Nx
AES
Full configuration
86 pins
NA
GPIO
Available pins are shown in
Table 4.3 (p. 58)
LCD
Full configuration
LCD_SEG[33:0], LCD_COM[7:0],
LCD_BCAP_P, LCD_BCAP_N,
LCD_BEXT
2.3 Memory Map
The EFM32GG990 memory map is shown in Figure 2.2 (p. 9), with RAM and Flash sizes for the
largest memory configuration.
Figure 2.2. EFM32GG990 Memory Map with largest RAM and Flash sizes
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3 Electrical Characteristics
3.1 Test Conditions
3.1.1 Typical Values
The typical data are based on TAMB=25°C and VDD=3.0 V, as defined in Table 3.2 (p. 10), by simu-
lation and/or technology characterisation unless otherwise specified.
3.1.2 Minimum and Maximum Values
The minimum and maximum values represent the worst conditions of ambient temperature, supply volt-
age and frequencies, as defined in Table 3.2 (p. 10), by simulation and/or technology characterisa-
tion unless otherwise specified.
3.2 Absolute Maximum Ratings
The absolute maximum ratings are stress ratings, and functional operation under such conditions are
not guaranteed. Stress beyond the limits specified in Table 3.1 (p. 10) may affect the device reliability
or cause permanent damage to the device. Functional operating conditions are given in Table 3.2 (p.
10) .
Table 3.1. Absolute Maximum Ratings
Symbol
TSTG
TS
Parameter
Condition
Min
Typ
Max
Unit
1501 °C
Storage temperature range
-40
Maximum soldering tem-
perature
Latest IPC/JEDEC J-STD-020
Standard
260 °C
VDDMAX
External main supply volt-
age
0
3.8
V
VIOPIN
Voltage on any I/O pin
-0.3
VDD+0.3
V
1Based on programmed devices tested for 10000 hours at 150ºC. Storage temperature affects retention of preprogrammed cal-
ibration values stored in flash. Please refer to the Flash section in the Electrical Characteristics for information on flash data re-
tention for different temperatures.
3.3 General Operating Conditions
3.3.1 General Operating Conditions
Table 3.2. General Operating Conditions
Symbol
TAMB
VDDOP
fAPB
Parameter
Min
Typ
Max
Unit
85 °C
3.8
Ambient temperature range
Operating supply voltage
Internal APB clock frequency
Internal AHB clock frequency
-40
1.85
V
48 MHz
48 MHz
fAHB
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3.3.2 Environmental
Table 3.3. Environmental
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VESDHBM
ESD (Human Body Model
HBM)
TAMB=25°C
2
1
kV
VESDCDM
ESD (Charged Device
Model, CDM)
TAMB=25°C
kV
Latch-up sensitivity test passed level A according to JEDEC JESD 78B method Class II, 85°C.
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3.4 Current Consumption
Table 3.4. Current Consumption
Symbol
Parameter
Condition
Min
Typ
Max
Unit
32 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V
200
201
203
204
207
212
244
50
µA/
MHz
28 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V
261 µA/
MHz
21 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V
263 µA/
MHz
EM0 current. No prescal-
ing. Running prime num-
ber calculation code from
Flash.
14 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V
270 µA/
MHz
IEM0
11 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V
273 µA/
MHz
6.6 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V
282 µA/
MHz
1.2 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V
µA/
MHz
32 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V
µA/
MHz
28 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V
52
69 µA/
MHz
21 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V
53
71 µA/
MHz
14 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V
56
77 µA/
MHz
IEM1
EM1 current
11 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V
57
80 µA/
MHz
6.6 MHz HFRCO, all peripher-
al clocks disabled, VDD= 3.0 V
62
92 µA/
MHz
1.2 MHz HFRCO. all peripher-
al clocks disabled, VDD= 3.0 V
114
1.1
µA/
MHz
EM2 current with RTC at 1
Hz, RTC prescaled to 1kHz,
32.768 kHz LFRCO, VDD= 3.0
V, TAMB=25°C
µA
IEM2
EM2 current
EM2 current with RTC at 1
Hz, RTC prescaled to 1kHz,
32.768 kHz LFRCO, VDD= 3.0
V, TAMB=85°C
4.0
8.0 µA
VDD= 3.0 V, TAMB=25°C
VDD= 3.0 V, TAMB=85°C
VDD= 3.0 V, TAMB=25°C
VDD= 3.0 V, TAMB=85°C
0.9
3.8
µA
7.8 µA
µA
IEM3
EM3 current
EM4 current
0.02
0.25
IEM4
0.7 µA
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2012-09-11 - EFM32GG990FXX - d0046_Rev1.00
12
Preliminary
...the world's most energy friendly microcontrollers
3.5 Transition between Energy Modes
Table 3.5. Energy Modes Transitions
Symbol
Parameter
Min
Typ
Max
Unit
tEM10
Transition time from EM1 to EM0
01
HF
core
CLK
cycles
tEM20
tEM30
tEM40
Transition time from EM2 to EM0
Transition time from EM3 to EM0
Transition time from EM4 to EM0
2
2
µs
µs
µs
163
1Core wakeup time only.
3.6 Power Management
Table 3.6. Power Management
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VBODextthr-
BOD threshold on falling
external supply voltage
1.82
1.85
V
VBODintthr-
BOD threshold on falling
internally regulated supply
voltage
1.62
1.68
V
VBODextthr+
BOD threshold on rising ex-
ternal supply voltage
1.85
V
V
VPORthr+
Power-on Reset (POR)
threshold on rising external
supply voltage
1.98
tRESET
Delay from reset is re-
leased until program execu- Brown-out Reset and pin re-
tion starts
Applies to Power-on Reset,
163
1
µs
µF
µF
µF
set.
CDECOUPLE
CUSB_VREGO
CUSB_VREGI
Voltage regulator decou-
pling capacitor.
X5R capacitor recommended.
Apply between DECOUPLE
pin and GROUND
USB voltage regulator out
decoupling capacitor.
X5R capacitor recommended.
Apply between USB_VREGO
pin and GROUND
1
USB voltage regulator in
decoupling capacitor.
X5R capacitor recommended.
Apply between USB_VREGI
pin and GROUND
4.7
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2012-09-11 - EFM32GG990FXX - d0046_Rev1.00
13
Preliminary
...the world's most energy friendly microcontrollers
3.7 Flash
Table 3.7. Flash
Symbol
Parameter
Flash erase cycles before
Condition
Min
Typ
Max
Unit
ECFLASH
20000
cycles
failure
TAMB<150°C
TAMB<85°C
TAMB<70°C
10000
10
h
RETFLASH
Flash data retention
years
years
µs
20
tW_PROG
Word (32-bit) programming
time
20
< 512KB
20
20
40
40
20.4
20.4
40.4
40.8
20.8 ms
tPERASE
tDERASE
IERASE
Page erase time
Device erase time
Erase current
>= 512KB, LPERASE == 0
>= 512KB, LPERASE == 1
< 512KB
20.8 ms
40.8 ms
41.6 ms
161.6 ms
71 mA
>= 512KB
< 512KB
>= 512KB, LPERASE == 0
>= 512KB, LPERASE == 1
< 512KB
141 mA
71 mA
71 mA
IWRITE
Write current
>= 512KB, LPWRITE == 0
>= 512KB, LPWRITE == 1
141 mA
71 mA
VFLASH
Supply voltage during flash
erase and write
1.8
3.8 V
1Measured at 25°C
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2012-09-11 - EFM32GG990FXX - d0046_Rev1.00
14
Preliminary
...the world's most energy friendly microcontrollers
3.8 General Purpose Input Output
Table 3.8. GPIO
Symbol
VIOIL
Parameter
Condition
Min
Typ
Max
0.3VDD
Unit
V
Input low voltage
Input high voltage
VIOIH
0.7VDD
V
Sourcing 6 mA, VDD=1.8V,
GPIO_Px_CTRL DRIVE-
MODE = STANDARD
0.75VDD
0.95VDD
0.7VDD
0.9VDD
V
Sourcing 6 mA, VDD=3.0V,
GPIO_Px_CTRL DRIVE-
MODE = STANDARD
V
V
V
V
V
V
V
VIOOH
Output high voltage
Sourcing 20 mA, VDD=1.8V,
GPIO_Px_CTRL DRIVE-
MODE = HIGH
Sourcing 20 mA, VDD=3.0V,
GPIO_Px_CTRL DRIVE-
MODE = HIGH
Sinking 6 mA, VDD=1.8V,
GPIO_Px_CTRL DRIVE-
MODE = STANDARD
0.25VDD
0.05VDD
0.3VDD
0.1VDD
Sinking 6 mA, VDD=3.0V,
GPIO_Px_CTRL DRIVE-
MODE = STANDARD
VIOOL
Output low voltage
Sinking 20 mA, VDD=1.8V,
GPIO_Px_CTRL DRIVE-
MODE = HIGH
Sinking 20 mA, VDD=3.0V,
GPIO_Px_CTRL DRIVE-
MODE = HIGH
IIOLEAK
Input leakage current
High Impedance IO connect-
ed to GROUND or Vdd
+/-25 nA
RPU
I/O pin pull-up resistor
40
40
kOhm
kOhm
Ohm
RPD
I/O pin pull-down resistor
Internal ESD series resistor
RIOESD
tIOGLITCH
200
Pulse width of pulses to be
removed by the glitch sup-
pression filter
10
50 ns
0.5 mA drive strength
and load capacitance
CL=12.5-25pF.
20+0.1CL
250 ns
tIOOF
Output fall time
2mA drive strength and load
capacitance CL=350-600pF
20+0.1CL
0.1VDD
250 ns
V
VIOHYST
I/O pin hysteresis (VIOTHR+
VDD = 1.8 - 3.8 V
- VIOTHR-
)
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2012-09-11 - EFM32GG990FXX - d0046_Rev1.00
15
Preliminary
...the world's most energy friendly microcontrollers
Figure 3.1. Typical Low-Level Output Current, 2V Supply Voltage
0.20
0.15
0.10
0.05
0.00
5
4
3
2
1
-40°C
25°C
85°C
-40°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Low-Level Output Voltage [V]
Low-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
20
45
40
35
30
25
20
15
10
5
15
10
5
-40°C
25°C
-40°C
25°C
85°C
85°C
0
0.0
0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Low-Level Output Voltage [V]
Low-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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2012-09-11 - EFM32GG990FXX - d0046_Rev1.00
16
Preliminary
...the world's most energy friendly microcontrollers
Figure 3.2. Typical High-Level Output Current, 2V Supply Voltage
0.00
–0.05
–0.10
–0.15
–0.20
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
-40°C
25°C
85°C
-40°C
25°C
85°C
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
High-Level Output Voltage [V]
High-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
0
0
-40°C
-40°C
25°C
85°C
25°C
85°C
–10
–20
–30
–40
–50
–5
–10
–15
–20
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
High-Level Output Voltage [V]
High-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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2012-09-11 - EFM32GG990FXX - d0046_Rev1.00
17
Preliminary
...the world's most energy friendly microcontrollers
Figure 3.3. Typical Low-Level Output Current, 3V Supply Voltage
0.5
0.4
0.3
0.2
0.1
0.0
10
8
6
4
2
-40°C
25°C
85°C
-40°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Low-Level Output Voltage [V]
Low-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
40
35
30
25
20
15
10
50
40
30
20
10
0
5
-40°C
-40°C
25°C
85°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Low-Level Output Voltage [V]
Low-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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2012-09-11 - EFM32GG990FXX - d0046_Rev1.00
18
Preliminary
...the world's most energy friendly microcontrollers
Figure 3.4. Typical High-Level Output Current, 3V Supply Voltage
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0
-40°C
25°C
85°C
-40°C
25°C
85°C
–1
–2
–3
–4
–5
–6
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
High-Level Output Voltage [V]
High-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
0
0
-40°C
-40°C
25°C
85°C
25°C
85°C
–10
–20
–30
–40
–50
–10
–20
–30
–40
–50
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
High-Level Output Voltage [V]
High-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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2012-09-11 - EFM32GG990FXX - d0046_Rev1.00
19
Preliminary
...the world's most energy friendly microcontrollers
Figure 3.5. Typical Low-Level Output Current, 3.8V Supply Voltage
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
14
12
10
8
6
4
2
-40°C
25°C
85°C
-40°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Low-Level Output Voltage [V]
Low-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
50
40
30
20
10
50
40
30
20
10
0
-40°C
25°C
-40°C
25°C
85°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Low-Level Output Voltage [V]
Low-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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2012-09-11 - EFM32GG990FXX - d0046_Rev1.00
20
Preliminary
...the world's most energy friendly microcontrollers
Figure 3.6. Typical High-Level Output Current, 3.8V Supply Voltage
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
0
-40°C
25°C
85°C
-40°C
25°C
85°C
–1
–2
–3
–4
–5
–6
–7
–8
–9
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
High-Level Output Voltage [V]
High-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
0
0
-40°C
-40°C
25°C
85°C
25°C
85°C
–10
–20
–30
–40
–50
–10
–20
–30
–40
–50
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
High-Level Output Voltage [V]
High-Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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2012-09-11 - EFM32GG990FXX - d0046_Rev1.00
21
Preliminary
...the world's most energy friendly microcontrollers
3.9 Oscillators
3.9.1 LFXO
Table 3.9. LFXO
Symbol
Parameter
Supported nominal crystal
Condition
Min
Typ
32.768
Max
Unit
fLFXO
kHz
frequency
ESRLFXO
Supported crystal equiv-
alent series resistance
(ESR)
30
120 kOhm
25 pF
CLFXOL
Supported crystal external
load range
5
DCLFXO
ILFXO
Duty cycle
48
50
53.5
%
Current consumption for
core and buffer after start-
up.
ESR=30 kOhm, CL=10 pF,
LFXOBOOST in CMU_CTRL
is 1
190
nA
tLFXO
Start- up time.
ESR=30 kOhm, CL=10 pF,
40% - 60% duty cycle has
been reached, LFXOBOOST
in CMU_CTRL is 1
400
ms
For safe startup of a given crystal, the load capacitance should be larger than the value indicated in
Figure 3.7 (p. 22) and in Table 3.10 (p. 23) for a given LFXOBOOST setting. The minimum
supported load capacitance depends on the crystal shunt capacitance, C0, which is specified in crystal
vendors’ datasheet.
Figure 3.7. Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup
20
LFXOBOOST= 0,REDLFXOBOOST= 1
LFXOBOOST= 0,REDLFXOBOOST= 0
18
LFXOBOOST= 1,REDLFXOBOOST= 1
LFXOBOOST= 1,REDLFXOBOOST= 0
16
14
12
10
8
6
4
2
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
C0 [pF]
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2012-09-11 - EFM32GG990FXX - d0046_Rev1.00
22
Preliminary
...the world's most energy friendly microcontrollers
Table 3.10. Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup
Symbol
Capacitance [pF]
Shunt Capacitance C0 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
CLmin lfxoboost = 0
redlfxoboost = 1
3.7 4.0 4.3 4.5 4.8 5.0 5.3 5.5 5.7 5.9 6.0 6.2 6.4 6.5 6.7 6.9
7.3 7.7 8.2 8.6 9.0 9.3 9.6 10.0 10.3 10.5 10.8 11.1 11.3 11.6 11.8 12.1
10.0 10.6 11.1 11.6 12.1 12.6 13.0 13.4 13.8 14.1 14.5 14.8 15.1 15.4 15.7 16.0
12.5 13.2 13.9 14.5 15.0 15.5 16.0 16.5 16.9 17.4 17.8 18.2 18.5 18.9 19.3 19.6
CLmin lfxoboost = 1
redlfxoboost = 0
CLmin lfxoboost = 1
redlfxoboost = 1
CLmin lfxoboost = 1
redlfxoboost = 0
3.9.2 HFXO
Table 3.11. HFXO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fHFXO
Supported nominal crystal
Frequency
4
48 MHz
Supported crystal equiv-
alent series resistance
(ESR)
Crystal frequency 32 MHz
Crystal frequency 4 MHz
30
60 Ohm
ESRHFXO
400
1500 Ohm
gmHFXO
The transconductance of
the HFXO input transistor
at crystal startup
HFXOBOOST in CMU_CTRL
equals 0b11
20
mS
CHFXOL
Supported crystal external
load range
5
25 pF
DCHFXO
Duty cycle
46
50
85
54
%
4 MHz: ESR=400 Ohm,
CL=20 pF, HFXOBOOST in
CMU_CTRL equals 0b11
µA
Current consumption for
HFXO after startup
IHFXO
32 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST in
CMU_CTRL equals 0b11
165
400
µA
µs
tHFXO
Startup time
32 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST in
CMU_CTRL equals 0b11
3.9.3 LFRCO
Table 3.12. LFRCO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fLFRCO
Oscillation frequency ,
VDD= 3.0 V, TAMB=25°C
32.768
kHz
tLFRCO
Startup time not including
software calibration
150
µs
ILFRCO
Current consumption
190
1.5
nA
%
TUNESTEPL- Frequency step for LSB
change in TUNING value
FRCO
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2012-09-11 - EFM32GG990FXX - d0046_Rev1.00
23
Preliminary
...the world's most energy friendly microcontrollers
Figure 3.8. Calibrated LFRCO Frequency vs Temperature and Supply Voltage
42
40
38
36
34
32
30
42
40
38
36
34
32
30
-40°C
25°C
85°C
1.8 V
3 V
3.8 V
1.8
2.2
2.6
3.0
3.4
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
3.9.4 HFRCO
Table 3.13. HFRCO
Symbol
Parameter
Condition
Min
Typ
28
Max
Unit
MHz
MHz
MHz
MHz
MHz
MHz
Cycles
µA
28 MHz frequency band
21 MHz frequency band
14 MHz frequency band
11 MHz frequency band
7 MHz frequency band
1 MHz frequency band
fHFRCO = 14 MHz
21
14
Oscillation frequency, VDD
3.0 V, TAMB=25°C
=
fHFRCO
11
6.61
1.22
0.6
106
93
tHFRCO_settling Settling time after start-up
fHFRCO = 28 MHz
fHFRCO = 21 MHz
µA
fHFRCO = 14 MHz
77
µA
IHFRCO
Current consumption
fHFRCO = 11 MHz
72
µA
fHFRCO = 6.6 MHz
63
µA
fHFRCO = 1.2 MHz
22
µA
DCHFRCO
Duty cycle
fHFRCO = 14 MHz
48.5
50
51
%
TUNESTEPH- Frequency step for LSB
0.3
%
change in TUNING value
FRCO
17 MHz for devices with prod. rev. < 19.
21 MHz for devices with prod. rev. < 19.
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2012-09-11 - EFM32GG990FXX - d0046_Rev1.00
24
Preliminary
...the world's most energy friendly microcontrollers
Figure 3.9. Calibrated HFRCO 11 MHz Band Frequency vs Temperature and Supply Voltage
11.15
11.10
11.05
11.00
10.95
10.90
10.85
10.80
11.20
11.15
11.10
11.05
11.00
10.95
10.90
10.85
10.80
1.8 V
3 V
3.8 V
-40°C
25°C
85°C
1.8
2.2
2.6
3.0
3.4
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.10. Calibrated HFRCO 14 MHz Band Frequency vs Temperature and Supply Voltage
14.15
14.10
14.05
14.00
13.95
13.90
13.85
14.15
14.10
14.05
14.00
13.95
13.90
13.85
-40°C
25°C
85°C
1.8 V
3 V
3.8 V
1.8
2.2
2.6
3.0
3.4
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.11. Calibrated HFRCO 21 MHz Band Frequency vs Temperature and Supply Voltage
21.2
21.1
21.0
20.9
20.8
20.7
20.6
21.2
21.1
21.0
20.9
20.8
20.7
20.6
-40°C
25°C
85°C
1.8 V
3 V
3.8 V
1.8
2.2
2.6
3.0
3.4
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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2012-09-11 - EFM32GG990FXX - d0046_Rev1.00
25
Preliminary
...the world's most energy friendly microcontrollers
Figure 3.12. Calibrated HFRCO 28 MHz Band Frequency vs Temperature and Supply Voltage
28.1
28.0
27.9
27.8
27.7
27.6
27.5
27.4
28.1
28.0
27.9
27.8
27.7
27.6
27.5
27.4
1.8 V
3 V
3.8 V
-40°C
25°C
85°C
1.8
2.2
2.6
3.0
3.4
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
3.9.5 ULFRCO
Table 3.14. ULFRCO
Symbol
fULFRCO
Parameter
Condition
Min
Typ
Max
Unit
Oscillation frequency
25°C, 3V
0.8
1.5 kHz
%/°C
TCULFRCO
VCULFRCO
Temperature coefficient
Supply voltage coefficient
0.05
-18.2
%/V
3.10 Analog Digital Converter (ADC)
Table 3.15. ADC
Symbol
VADCIN
Parameter
Condition
Single ended
Differential
Min
Typ
Max
Unit
0
VREF
VREF/2
V
V
V
Input voltage range
-VREF/2
1.25
VADCREFIN
Input range of external ref-
erence voltage, single end-
ed and differential
VDD
VDD - 1.1
VDD
VADCREFIN_CH7 Input range of external neg- See VADCREFIN
0
0.625
0
V
V
ative reference voltage on
channel 7
VADCREFIN_CH6 Input range of external pos- See VADCREFIN
itive reference voltage on
channel 6
VADCCMIN
IADCIN
Common mode input range
Input current
VDD
V
2pF sampling capacitors
<100
65
nA
dB
CMRRADC
Analog input common
mode rejection ratio
1 MSamples/s, 12 bit, exter-
nal reference
351
67
µA
µA
IADC
Average active current
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
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26
Preliminary
...the world's most energy friendly microcontrollers
Symbol
Parameter
Condition
Min
Typ
Max
Unit
MODE in ADCn_CTRL set to
0b00
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b01
63
64
µA
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b10
µA
µA
IADCREF
Current consumption of in-
ternal voltage reference
Internal voltage reference
65
2
CADCIN
Input capacitance
pF
RADCIN
Input ON resistance
Input RC filter resistance
1
MOhm
kOhm
fF
RADCFILT
CADCFILT
10
Input RC filter/decoupling
capacitance
250
fADCCLK
ADC Clock Frequency
13 MHz
6 bit
7
11
13
1
ADC-
CLK
Cycles
10 bit
ADC-
CLK
Cycles
tADCCONV
Conversion time
12 bit
ADC-
CLK
Cycles
tADCACQ
Acquisition time
Programmable
256 ADC-
CLK
Cycles
tADCACQVDD3
Required acquisition time
for VDD/3 reference
2
µs
Startup time of reference
generator and ADC core in
NORMAL mode
5
1
µs
tADCSTART
Startup time of reference
generator and ADC core in
KEEPADCWARM mode
µs
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
59
63
dB
dB
1 MSamples/s, 12 bit, single
ended, internal 2.5V refer-
ence
Signal to Noise Ratio
(SNR)
1 MSamples/s, 12 bit, single
ended, VDD reference
65
60
dB
dB
SNRADC
1 MSamples/s, 12 bit, differ-
ential, internal 1.25V refer-
ence
1 MSamples/s, 12 bit, differ-
ential, internal 2.5V reference
65
dB
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2012-09-11 - EFM32GG990FXX - d0046_Rev1.00
27
Preliminary
...the world's most energy friendly microcontrollers
Symbol
Parameter
Condition
Min
Typ
Max
Unit
1 MSamples/s, 12 bit, differ-
ential, 5V reference
54
67
69
62
dB
1 MSamples/s, 12 bit, differ-
ential, VDD reference
dB
dB
dB
1 MSamples/s, 12 bit, differ-
ential, 2xVDD reference
200 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V ref-
erence
200 kSamples/s, 12 bit, sin-
gle ended, internal 2.5V refer-
ence
63
dB
200 kSamples/s, 12 bit, single
ended, VDD reference
67
63
dB
dB
200 kSamples/s, 12 bit, dif-
ferential, internal 1.25V refer-
ence
200 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
66
66
69
70
58
dB
dB
dB
dB
dB
200 kSamples/s, 12 bit, differ-
ential, 5V reference
200 kSamples/s, 12 bit, differ-
ential, VDD reference
200 kSamples/s, 12 bit, differ-
ential, 2xVDD reference
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
1 MSamples/s, 12 bit, single
ended, internal 2.5V refer-
ence
62
dB
1 MSamples/s, 12 bit, single
ended, VDD reference
64
60
dB
dB
1 MSamples/s, 12 bit, differ-
ential, internal 1.25V refer-
ence
1 MSamples/s, 12 bit, differ-
ential, internal 2.5V reference
64
54
66
68
61
dB
dB
dB
dB
dB
Signal to Noise-puls-Distor-
tion Ratio (SNDR)
SNDRADC
1 MSamples/s, 12 bit, differ-
ential, 5V reference
1 MSamples/s, 12 bit, differ-
ential, VDD reference
1 MSamples/s, 12 bit, differ-
ential, 2xVDD reference
200 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V ref-
erence
200 kSamples/s, 12 bit, sin-
gle ended, internal 2.5V refer-
ence
65
dB
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2012-09-11 - EFM32GG990FXX - d0046_Rev1.00
28
Preliminary
...the world's most energy friendly microcontrollers
Symbol
Parameter
Condition
Min
Typ
Max
Unit
200 kSamples/s, 12 bit, single
ended, VDD reference
66
63
dB
200 kSamples/s, 12 bit, dif-
ferential, internal 1.25V refer-
ence
dB
200 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
66
66
68
69
64
dB
dB
dB
dB
dBc
200 kSamples/s, 12 bit, differ-
ential, 5V reference
200 kSamples/s, 12 bit, differ-
ential, VDD reference
200 kSamples/s, 12 bit, differ-
ential, 2xVDD reference
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
1 MSamples/s, 12 bit, single
ended, internal 2.5V refer-
ence
76
dBc
1 MSamples/s, 12 bit, single
ended, VDD reference
73
66
dBc
dBc
1 MSamples/s, 12 bit, differ-
ential, internal 1.25V refer-
ence
1 MSamples/s, 12 bit, differ-
ential, internal 2.5V reference
77
76
75
69
75
dBc
dBc
dBc
dBc
dBc
1 MSamples/s, 12 bit, differ-
ential, VDD reference
1 MSamples/s, 12 bit, differ-
ential, 2xVDD reference
1 MSamples/s, 12 bit, differ-
ential, 5V reference
Spurious-Free Dynamic
Range (SFDR)
SFDRADC
200 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V ref-
erence
200 kSamples/s, 12 bit, sin-
gle ended, internal 2.5V refer-
ence
75
dBc
200 kSamples/s, 12 bit, single
ended, VDD reference
76
79
dBc
dBc
200 kSamples/s, 12 bit, dif-
ferential, internal 1.25V refer-
ence
200 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
79
78
79
dBc
dBc
dBc
200 kSamples/s, 12 bit, differ-
ential, 5V reference
200 kSamples/s, 12 bit, differ-
ential, VDD reference
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2012-09-11 - EFM32GG990FXX - d0046_Rev1.00
29
Preliminary
...the world's most energy friendly microcontrollers
Symbol
Parameter
Condition
Min
Typ
Max
Unit
200 kSamples/s, 12 bit, differ-
ential, 2xVDD reference
79
dBc
After calibration, single ended
After calibration, differential
0.3
0.3
mV
VADCOFFSET
Offset voltage
mV
-1.92
-6.3
mV/°C
Thermometer output gradi-
ent
ADC
Codes/
°C
TGRADADCTH
DNLADC
INLADC
MCADC
GAINED
Differential non-linearity
(DNL)
±0.7
±1.2
12
LSB
LSB
bits
Integral non-linearity (INL),
End point method
No missing codes
11.9991
1.25V reference
2.5V reference
1.25V reference
2.5V reference
0.012
0.012
0.22
0.0333 %/°C
Gain error drift
0.033 %/°C
0.73 LSB/°C
0.623 LSB/°C
OFFSETED
Offset error drift
0.22
1On the average every ADC will have one missing code, most likely to appear around 2048 +/- n*512 where n can be a value in
the set {-3, -2, -1, 1, 2, 3}. There will be no missing code around 2048, and in spite of the missing code the ADC will be monotonic
at all times so that a response to a slowly increasing input will always be a slowly increasing output. Around the one code that is
missing, the neighbour codes will look wider in the DNL plot. The spectra will show spurs on the level of -78dBc for a full scale
input for chips that have the missing code issue.
2Typical numbers given by abs(Mean) / (85 - 25).
3Max number given by (abs(Mean) + 3x stddev) / (85 - 25).
The integral non-linearity (INL) and differential non-linearity parameters are explained in Figure 3.13 (p.
30) and Figure 3.14 (p. 31) , respectively.
Figure 3.13. Integral Non-Linearity (INL)
Digital ouput code
INL= |[(VD-VSS)/VLSBIDEAL] - D| where 0 < D < 2N - 1
4095
4094
Actual ADC
tranfer function
before offset and
4093
Actual ADC
gain correction
4092
tranfer function
after offset and
gain correction
INL Error
(End Point INL)
Ideal transfer
curve
3
2
1
0
VOFFSET
Analog Input
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2012-09-11 - EFM32GG990FXX - d0046_Rev1.00
30
Preliminary
...the world's most energy friendly microcontrollers
Figure 3.14. Differential Non-Linearity (DNL)
Digital
ouput
DNL= |[(VD+ 1 - VD)/VLSBIDEAL] - 1| where 0 < D < 2N - 2
code
4095
4094
4093
4092
Full Scale Range
Example: Adjacent
input value VD+ 1
corrresponds to digital
output code D+ 1
Actual transfer
function with one
missing code.
Example: Input value
VD corrresponds to
digital output code D
Code width = 2 LSB
DNL= 1 LSB
Ideal transfer
curve
0.5
LSB
Ideal spacing
between two
adjacent codes
VLSBIDEAL= 1 LSB
5
4
3
2
1
0
Ideal 50%
Transition Point
Ideal Code Center
Analog Input
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Preliminary
...the world's most energy friendly microcontrollers
3.10.1 Typical performance
Figure 3.15. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°
0
0
–20
–20
–40
–60
–40
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
0
0
0
20
40
60
80
0
20
40
60
80
Frequency [kHz]
Frequency [kHz]
1.25V Reference
2.5V Reference
0
0
–20
–40
–20
–40
–60
–60
–80
–80
–100
–120
–140
–160
–180
–100
–120
–140
–160
20
40
60
80
0
20
40
60
80
Frequency [kHz]
Frequency [kHz]
2XVDDVSS Reference
5VDIFF Reference
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
20
40
60
80
Frequency [kHz]
VDD Reference
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Preliminary
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Figure 3.16. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°
1.5
1.0
1.5
1.0
0.5
0.5
0.0
0.0
–0.5
–1.0
–0.5
–1.0
0
512
512
512
1024
1536
2048
2560
3072
3584
3584
3584
4096
4096
4096
0
512
1024
1536
2048
2560
3072
3584
4096
Output code
Output code
1.25V Reference
2.5V Reference
0.8
0.6
1.0
0.5
0.4
0.2
0.0
0.0
–0.2
–0.4
–0.6
–0.5
0
1024
1536
2048
2560
3072
0
512
1024
1536
2048
2560
3072
3584
4096
Output code
Output code
2XVDDVSS Reference
5VDIFF Reference
0.8
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
0
1024
1536
2048
2560
3072
Output code
VDD Reference
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Preliminary
...the world's most energy friendly microcontrollers
Figure 3.17. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°
1.0
0.5
1.0
0.5
0.0
0.0
–0.5
–1.0
–0.5
–1.0
0
0
0
512
512
512
1024
1536
2048
2560
3072
3584
3584
3584
4096
4096
4096
0
512
1024
1536
2048
2560
3072
3584
4096
Output code
Output code
1.25V Reference
2.5V Reference
1.0
0.5
1.0
0.5
0.0
0.0
–0.5
–1.0
–0.5
–1.0
1024
1536
2048
2560
3072
0
512
1024
1536
2048
2560
3072
3584
4096
Output code
Output code
2XVDDVSS Reference
5VDIFF Reference
1.0
0.5
0.0
–0.5
–1.0
1024
1536
2048
2560
3072
Output code
VDD Reference
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2012-09-11 - EFM32GG990FXX - d0046_Rev1.00
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Preliminary
...the world's most energy friendly microcontrollers
Figure 3.18. ADC Absolute Offset, Common Mode = Vdd /2
5
4
3
2
1
0
2.0
1.5
Vref= 1V25
VRef= 1V25
Vref= 2V5
VRef= 2V5
Vref= 2XVDDVSS
Vref= 5VDIFF
Vref= VDD
VRef= 2XVDDVSS
VRef= 5VDIFF
VRef= VDD
1.0
0.5
–1
0.0
–2
–3
–4
–0.5
–1.0
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd (V)
Temp (C)
Offset vs Supply Voltage, Temp = 25°
Offset vs Temperature, Vdd = 3V
Figure 3.19. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V
71
70
69
68
67
66
65
64
63
79.4
79.2
79.0
78.8
78.6
78.4
78.2
78.0
2XVDDV
Vdd
1V25
Vdd
2V5
5VDIFF
2V5
2XVDDV
5VDIFF
85
1V25
–40
–15
5
25
45
65
85
–40
–15
5
25
45
65
Temperature [°C]
Temperature [°C]
Signal to Noise Ratio (SNR)
Spurious-Free Dynamic Range (SFDR)
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Preliminary
...the world's most energy friendly microcontrollers
Figure 3.20. ADC Temperature sensor readout
2600
Vdd= 1.8
Vdd= 3
Vdd= 3.8
2500
2400
2300
2200
2100
–40
–25 –15 –5
5
15 25 35 45 55 65 75 85
Temperature [°C]
3.11 Digital Analog Converter (DAC)
Table 3.16. DAC
Symbol
VDACOUT
VDACCM
Parameter
Condition
Min
Typ
Max
Unit
VDD voltage reference, single
ended
0
-VDD
0
VDD
VDD
VDD
V
Output voltage range
VDD voltage reference, differ-
ential
V
V
Output common mode volt-
age range
500 kSamples/s, 12bit
400
200
38
µA
µA
µA
Active current including ref-
erences for 2 channels
IDAC
100 kSamples/s, 12 bit
1 kSamples/s 12 bit NORMAL
SRDAC
Sample rate
500 ksam-
ples/s
Continuous Mode
Sample/Hold Mode
Sample/Off Mode
1000 kHz
250 kHz
250 kHz
fDAC
DAC clock frequency
CYCDACCONV Clock cyckles per conver-
sion
2
tDACCONV
Conversion time
Settling time
2
µs
µs
dB
tDACSETTLE
5
500 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V ref-
erence
58
500 kSamples/s, 12 bit, sin-
gle ended, internal 2.5V refer-
ence
59
58
dB
dB
Signal to Noise Ratio
(SNR)
SNRDAC
500 kSamples/s, 12 bit, dif-
ferential, internal 1.25V refer-
ence
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36
Preliminary
...the world's most energy friendly microcontrollers
Symbol
Parameter
Condition
Min
Typ
Max
Unit
500 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
58
59
57
dB
500 kSamples/s, 12 bit, differ-
ential, VDD reference
dB
dB
500 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V ref-
erence
500 kSamples/s, 12 bit, sin-
gle ended, internal 2.5V refer-
ence
54
56
dB
dB
Signal to Noise-pulse Dis-
tortion Ratio (SNDR)
SNDRDAC
500 kSamples/s, 12 bit, dif-
ferential, internal 1.25V refer-
ence
500 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
53
55
62
dB
500 kSamples/s, 12 bit, differ-
ential, VDD reference
dB
500 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V ref-
erence
dBc
500 kSamples/s, 12 bit, sin-
gle ended, internal 2.5V refer-
ence
56
61
dBc
dBc
Spurious-Free Dynamic
Range(SFDR)
SFDRDAC
500 kSamples/s, 12 bit, dif-
ferential, internal 1.25V refer-
ence
500 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
55
60
dBc
dBc
500 kSamples/s, 12 bit, differ-
ential, VDD reference
After calibration, single ended
After calibration, differential
2
2
mV
VDACOFFSET
Offset voltage
mV
DNLDAC
INLDAC
MCDAC
Differential non-linearity
Integral non-linearity
No missing codes
±1
±5
12
LSB
LSB
bits
3.12 Operational Amplifier (OPAMP)
The electrical characteristics for the Operational Amplifiers are based on simulations.
Table 3.17. OPAMP
Symbol
Parameter
Condition
Min
Typ
Max
Unit
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0, Unity
Gain
400
100
µA
IOPAMP
Active Current
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1, Unity
Gain
µA
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Preliminary
...the world's most energy friendly microcontrollers
Symbol
Parameter
Condition
Min
Typ
Max
Unit
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1, Unity
Gain
13
µA
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0
101
98
dB
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1
dB
GOL
Open Loop Gain
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1
91
dB
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0
6.1
1.8
0.25
64
MHz
MHz
MHz
°
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1
GBWOPAMP
Gain Bandwidth Product
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0,
CL=75 pF
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1,
CL=75 pF
58
58
°
°
PMOPAMP
Phase Margin
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1,
CL=75 pF
RINPUT
RLOAD
Input Resistance
Load Resistance
DC Load Current
100
Mohm
Ohm
200
ILOAD_DC
11 mA
OPAxHCMDIS=0
OPAxHCMDIS=1
VSS
VSS
VSS
VDD
V
VINPUT
Input Voltage
VDD-1.2
VDD
V
VOUTPUT
Output Voltage
V
Unity Gain, VSS<Vin<DD
OPAxHCMDIS=0
,
6
1
mV
VOFFSET
Input Offset Voltage
Unity Gain, VSS<Vin<DD-1.2,
OPAxHCMDIS=1
mV
VOFFSET_DRIFT Input Offset Voltage Drift
0.02 mV/°C
V/µs
(OPA2)BIASPROG=0xF,
(OPA2)HALFBIAS=0x0
3.2
0.8
0.1
101
(OPA2)BIASPROG=0x7,
(OPA2)HALFBIAS=0x1
V/µs
SROPAMP
Slew Rate
(OPA2)BIASPROG=0x0,
(OPA2)HALFBIAS=0x1
V/µs
Vout=1V, RESSEL=0,
0.1 Hz<f<10 kHz, OPAx-
HCMDIS=0
µVRMS
NOPAMP
Voltage Noise
Vout=1V, RESSEL=0,
0.1 Hz<f<10 kHz, OPAx-
HCMDIS=1
141
µVRMS
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2012-09-11 - EFM32GG990FXX - d0046_Rev1.00
38
Preliminary
...the world's most energy friendly microcontrollers
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Vout=1V, RESSEL=0,
0.1 Hz<f<1 MHz, OPAx-
HCMDIS=0
196
229
µVRMS
Vout=1V, RESSEL=0,
0.1 Hz<f<1 MHz, OPAx-
HCMDIS=1
µVRMS
RESSEL=7, 0.1 Hz<f<10 kHz,
OPAxHCMDIS=0
1230
2130
1630
2590
µVRMS
µVRMS
µVRMS
µVRMS
RESSEL=7, 0.1 Hz<f<10 kHz,
OPAxHCMDIS=1
RESSEL=7, 0.1 Hz<f<1 MHz,
OPAxHCMDIS=0
RESSEL=7, 0.1 Hz<f<1 MHz,
OPAxHCMDIS=1
Figure 3.21. OPAMP Common Mode Rejection Ratio
Figure 3.22. OPAMP Positive Power Supply Rejection Ratio
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Preliminary
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Figure 3.23. OPAMP Negative Power Supply Rejection Ratio
Figure 3.24. OPAMP Voltage Noise Spectral Density (Unity Gain) Vout=1V
Figure 3.25. OPAMP Voltage Noise Spectral Density (Non-Unity Gain)
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Preliminary
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3.13 Analog Comparator (ACMP)
Table 3.18. ACMP
Symbol
VACMPIN
VACMPCM
Parameter
Condition
Min
Typ
Max
Unit
V
Input voltage range
0
0
VDD
VDD
ACMP Common Mode volt-
age range
V
BIASPROG=0b0000, FULL-
BIAS=0 and HALFBIAS=1 in
ACMPn_CTRL register
0.1
2.87
195
0
µA
µA
µA
µA
BIASPROG=0b1111, FULL-
BIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
IACMP
Active current
BIASPROG=0b1111, FULL-
BIAS=1 and HALFBIAS=0 in
ACMPn_CTRL register
Internal voltage reference off.
Using external voltage refer-
ence
Current consumption of in-
ternal voltage reference
IACMPREF
Internal voltage reference
Single ended
5
10
10
17
39
µA
mV
VACMPOFFSET Offset voltage
Differential
mV
VACMPHYST
ACMP hysteresis
Programmable
mV
CSRESSEL=0b00 in
ACMPn_INPUTSEL
kOhm
CSRESSEL=0b01 in
ACMPn_INPUTSEL
71
104
136
kOhm
kOhm
kOhm
Capacitive Sense Internal
Resistance
RCSRES
CSRESSEL=0b10 in
ACMPn_INPUTSEL
CSRESSEL=0b11 in
ACMPn_INPUTSEL
The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference
as given in Equation 3.1 (p. 41) . IACMPREF is zero if an external voltage reference is used.
Total ACMP Active Current
IACMPTOTAL = IACMP + IACMPREF
(3.1)
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Figure 3.26. Typical ACMP Characteristics
2.5
2.0
1.5
1.0
0.5
0.0
4.5
HYSTSEL= 0.0
HYSTSEL= 2.0
4.0
HYSTSEL= 4.0
HYSTSEL= 6.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
4
8
12
0
2
4
6
8
10
12
14
ACMP_CTRL_BIASPROG
ACMP_CTRL_BIASPROG
Current consumption
Response time
100
80
60
40
20
0
BIASPROG= 0.0
BIASPROG= 4.0
BIASPROG= 8.0
BIASPROG= 12.0
0
1
2
3
4
5
6
7
ACMP_CTRL_HYSTSEL
Hysteresis
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Preliminary
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3.14 Voltage Comparator (VCMP)
Table 3.19. VCMP
Symbol
VVCMPIN
VVCMPCM
Parameter
Condition
Min
Typ
Max
Unit
V
Input voltage range
VDD
VDD
VCMP Common Mode volt-
age range
V
BIASPROG=0b0000
and HALFBIAS=1 in
VCMPn_CTRL register
0.1
µA
µA
IVCMP
Active current
BIASPROG=0b1111
and HALFBIAS=0 in
VCMPn_CTRL register.
LPREF=0.
14.7
tVCMPREF
Startup time reference gen- NORMAL
erator
10
µs
Single ended
Differential
10
10
17
mV
mV
mV
VVCMPOFFSET Offset voltage
VVCMPHYST
VCMP hysteresis
The VDD trigger level can be configured by setting the TRIGLEVEL field of the VCMP_CTRL register in
accordance with the following equation:
VCMP Trigger Level as a Function of Level Setting
VDD Trigger Level=1.667V+0.034 ×TRIGLEVEL
(3.2)
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Preliminary
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3.15 LCD
Table 3.20. LCD
Symbol
fLCDFR
Parameter
Frame rate
Condition
Min
Typ
Max
Unit
200 Hz
30
NUMSEG
Number of segments sup-
ported
34×8
seg
VLCD
LCD supply voltage range
Internal boost circuit enabled
2.0
3.8
V
Display disconnected, stat-
ic mode, framerate 32 Hz, all
segments on.
250
550
nA
Steady state current con-
sumption.
Display disconnected,
nA
ILCD
quadruplex mode, framer-
ate 32 Hz, all segments on,
bias mode to ONETHIRD in
LCD_DISPCTRL register.
Internal voltage boost off
0
µA
µA
Steady state Current contri-
bution of internal boost.
ILCDBOOST
Internal voltage boost on,
8.4
boosting from 2.2 V to 3.0 V.
VBLEV of LCD_DISPCTRL
register to LEVEL0
3.0
3.08
3.17
3.26
3.34
3.43
3.52
3.6
V
V
V
V
V
V
V
V
VBLEV of LCD_DISPCTRL
register to LEVEL1
VBLEV of LCD_DISPCTRL
register to LEVEL2
VBLEV of LCD_DISPCTRL
register to LEVEL3
VBOOST
Boost Voltage
VBLEV of LCD_DISPCTRL
register to LEVEL4
VBLEV of LCD_DISPCTRL
register to LEVEL5
VBLEV of LCD_DISPCTRL
register to LEVEL6
VBLEV of LCD_DISPCTRL
register to LEVEL7
The total LCD current is given by Equation 3.3 (p. 44) . ILCDBOOST is zero if internal boost is off.
Total LCD Current Based on Operational Mode and Internal Boost
ILCDTOTAL = ILCD + ILCDBOOST
(3.3)
3.16 Digital Peripherals
Table 3.21. Digital Peripherals
Symbol
Parameter
Condition
Min
Typ
Max
Unit
IUSART
USART current
USART idle current, clock en-
abled
7.5
µA/
MHz
IUART
UART current
UART idle current, clock en-
abled
5.63
µA/
MHz
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
ILEUART
LEUART current
LEUART idle current, clock
enabled
150
6.25
8.75
150
100
100
100
2.5
nA
II2C
I2C current
I2C idle current, clock en-
abled
µA/
MHz
ITIMER
ILETIMER
IPCNT
IRTC
TIMER current
LETIMER current
PCNT current
RTC current
LCD current
AES current
GPIO current
EBI current
TIMER_0 idle current, clock
enabled
µA/
MHz
LETIMER idle current, clock
enabled
nA
nA
nA
nA
PCNT idle current, clock en-
abled
RTC idle current, clock en-
abled
ILCD
LCD idle current, clock en-
abled
IAES
AES idle current, clock en-
abled
µA/
MHz
IGPIO
GPIO idle current, clock en-
abled
5.31
1.56
2,81
8.12
µA/
MHz
IEBI
EBI idle current, clock en-
abled
µA/
MHz
IPRS
PRS current
DMA current
PRS idle current
µA/
MHz
IDMA
Clock enable
µA/
MHz
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Preliminary
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4 Pinout and Package
Note
Please refer to the application note "AN0002 EFM32 Hardware Design Considerations" for
guidelines on designing Printed Circuit Boards (PCB's) for the EFM32GG990.
4.1 Pinout
The EFM32GG990 pinout is shown in Figure 4.1 (p. 46) and Table 4.1 (p. 46). Alternate locations
are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/").
Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module
in question.
Figure 4.1. EFM32GG990 Pinout (top view, not to scale)
Table 4.1. Device Pinout
BGA112 Pin#
and Name
Pin Alternate Functionality / Description
Pin Name
Analog
EBI
Timers
Communication
Other
A1
A2
PE15
PE14
LCD_SEG11
LCD_SEG10
EBI_AD07 #0/1/2
EBI_AD06 #0/1/2
TIM3_CC1 #0
TIM3_CC0 #0
LEU0_RX #2
LEU0_TX #2
US0_RX #3
US0_CLK #0
I2C0_SDA #6
CMU_CLK1 #2
LES_ALTEX6 #0
A3
PE12
LCD_SEG8
EBI_AD04 #0/1/2
TIM1_CC2 #1
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BGA112 Pin#
and Name
Pin Alternate Functionality / Description
Pin Name
Analog
EBI
Timers
Communication
Other
A4
A5
A6
A7
A8
A9
PE9
PD10
PF7
LCD_SEG5
LCD_SEG29
LCD_SEG25
LCD_SEG3
EBI_AD01 #0/1/2
EBI_CS1 #0/1/2
EBI_BL1 #0/1/2
EBI_REn #0/2
PCNT2_S1IN #1
TIM0_CC1 #2
U0_RX #0
USB_VBUSEN #0
USB_ID #0
PF5
TIM0_CDTI2 #2/5
PRS_CH2 #1
PF12
PE4
LCD_COM0
EBI_A11 #0/1/2
US0_CS #1
U1_TX #1
USB_DM #0
A10
PF10
U1_RX #1
USB_DP #0
A11
B1
PF11
PA15
LCD_SEG12
LCD_SEG9
EBI_AD08 #0/1/2
EBI_AD05 #0/1/2
TIM3_CC2 #0
US0_TX #3
US0_CS #0
I2C0_SCL #6
LES_ALTEX7 #0
ACMP0_O #0
GPIO_EM4WU5
B2
B3
PE13
PE11
LES_ALTEX5 #0
BOOTLOADER_RX
LCD_SEG7
EBI_AD03 #0/1/2
TIM1_CC1 #1
US0_RX #0
B4
B5
PE8
PD11
LCD_SEG4
LCD_SEG30
EBI_AD00 #0/1/2
EBI_CS2 #0/1/2
EBI_WEn #1
PCNT2_S0IN #1
PRS_CH3 #1
B6
PF8
LCD_SEG26
TIM0_CC2 #2
TIM0_CC0 #2
ETM_TCLK #1
B7
PF6
LCD_SEG24
EBI_BL0 #0/1/2
U0_TX #0
B8
USB_VBUS
PE5
USB 5.0 V VBUS input.
LCD_COM1
B9
EBI_A12 #0/1/2
US0_CLK #1
B10
B11
USB_VREGI
USB_VREGO
USB Input to internal 3.3 V regulator.
USB Decoupling for internal 3.3 V USB regulator and regulator output.
CMU_CLK1 #0
PRS_CH1 #0
C1
C2
PA1
PA0
LCD_SEG14
EBI_AD10 #0/1/2
TIM0_CC1 #0/1
I2C0_SCL #0
LEU0_RX #4
I2C0_SDA #0
PRS_CH0 #0
GPIO_EM4WU0
LCD_SEG13
LCD_SEG6
EBI_AD09 #0/1/2
EBI_AD02 #0/1/2
TIM0_CC0 #0/1/4
TIM1_CC0 #1
C3
C4
C5
C6
C7
PE10
PD13
PD12
PF9
US0_TX #0
BOOTLOADER_TX
ETM_TD1 #1
LCD_SEG31
LCD_SEG27
EBI_CS3 #0/1/2
EBI_REn #1
ETM_TD0 #1
VSS
Ground
ACMP1_O #0
DBG_SWO #0
GPIO_EM4WU4
C8
PF2
LCD_SEG0
EBI_ARDY #0/1/2
TIM0_CC2 #5
TIM2_CC2 #2
LEU0_TX #4
C9
PE6
PC10
PC11
LCD_COM2
ACMP1_CH2
ACMP1_CH3
EBI_A13 #0/1/2
EBI_A10 #1/2
EBI_ALE #1/2
US0_RX #1
US0_RX #2
US0_TX #2
C10
C11
LES_CH10 #0
LES_CH11 #0
LES_ALTEX2 #0
ETM_TD1 #3
D1
PA3
LCD_SEG16
LCD_SEG15
EBI_AD12 #0/1/2
EBI_AD11 #0/1/2
TIM0_CDTI0 #0
TIM0_CC2 #0/1
U0_TX #2
CMU_CLK0 #0
ETM_TD0 #3
D2
D3
PA2
PB15
ETM_TD2 #1
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BGA112 Pin#
and Name
Pin Alternate Functionality / Description
Pin Name
Analog
EBI
Timers
Communication
Other
D4
D5
D6
D7
VSS
IOVDD_6
PD9
Ground
Digital IO power supply 6.
LCD_SEG28
EBI_CS0 #0/1/2
IOVDD_5
Digital IO power supply 5.
US1_CS #2
LEU0_RX #3
I2C0_SCL #5
TIM0_CC1 #5
LETIM0_OUT1 #2
DBG_SWDIO #0/1/2/3
GPIO_EM4WU3
D8
D9
PF1
PE7
LCD_COM3
EBI_A14 #0/1/2
EBI_A15 #0/1/2
US0_TX #1
US0_CS #2
D10
D11
PC8
PC9
ACMP1_CH0
TIM2_CC0 #2
TIM2_CC1 #2
LES_CH8 #0
LES_CH9 #0
GPIO_EM4WU2
ACMP1_CH1
LCD_SEG19
LCD_SEG18
EBI_A09 #1/2
EBI_AD15 #0/1/2
EBI_AD14 #0/1/2
US0_CLK #2
LEU1_RX #1
LEU1_TX #1
U0_RX #2
ETM_TCLK #3
GPIO_EM4WU1
E1
E2
PA6
PA5
LES_ALTEX4 #0
ETM_TD3 #3
TIM0_CDTI2 #0
LES_ALTEX3 #0
ETM_TD2 #3
E3
E4
PA4
PB0
LCD_SEG17
LCD_SEG32
EBI_AD13 #0/1/2
EBI_A16 #0/1/2
TIM0_CDTI1 #0
TIM1_CC0 #2
US1_CLK #2
LEU0_TX #3
I2C0_SDA #5
TIM0_CC0 #5
LETIM0_OUT0 #2
E8
PF0
DBG_SWCLK #0/1/2/3
TIM3_CC0 #1
PCNT0_S0IN #1
U0_TX #1
I2C1_SDA #2
E9
PE0
PE1
EBI_A07 #0/1/2
EBI_A08 #0/1/2
TIM3_CC1 #1
PCNT0_S1IN #1
U0_RX #1
I2C1_SCL #2
E10
E11
F1
PE3
PB1
PB2
BU_STAT
LCD_SEG33
LCD_SEG34
EBI_A10 #0
EBI_A17 #0/1/2
EBI_A18 #0/1/2
U1_RX #3
ACMP1_O #1
TIM1_CC1 #2
TIM1_CC2 #2
F2
LCD_SEG20/
LCD_COM4
F3
F4
PB3
PB4
EBI_A19 #0/1/2
EBI_A20 #0/1/2
PCNT1_S0IN #1
PCNT1_S1IN #1
US2_TX #1
US2_RX #1
LCD_SEG21/
LCD_COM5
F8
F9
VDD_DREG
VSS_DREG
PE2
Power supply for on-chip voltage regulator.
Ground for on-chip voltage regulator.
F10
F11
BU_VOUT
EBI_A09 #0
TIM3_CC2 #1
U1_TX #3
ACMP0_O #1
DECOUPLE
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
LCD_SEG22/
LCD_COM6
G1
G2
PB5
PB6
EBI_A21 #0/1/2
EBI_A22 #0/1/2
US2_CLK #1
US2_CS #1
LCD_SEG23/
LCD_COM7
G3
G4
G8
G9
VSS
IOVDD_0
IOVDD_4
VSS
Ground
Digital IO power supply 0.
Digital IO power supply 4.
Ground
LEU1_TX #0
I2C0_SDA #2
LES_CH6 #0
ETM_TCLK #2
G10
G11
PC6
PC7
ACMP0_CH6
ACMP0_CH7
EBI_A05 #0/1/2
EBI_A06 #0/1/2
LEU1_RX #0
LES_CH7 #0
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BGA112 Pin#
and Name
Pin Alternate Functionality / Description
Pin Name
Analog
EBI
Timers
Communication
Other
I2C0_SCL #2
ETM_TD0 #2
DAC0_OUT0ALT #0/
OPAMP_OUT0ALT
ACMP0_CH0
US0_TX #5
US1_TX #0
I2C0_SDA #4
TIM0_CC1 #4
PCNT0_S0IN #2
LES_CH0 #0
PRS_CH2 #0
H1
H2
PC0
PC2
EBI_A23 #0/1/2
EBI_A25 #0/1/2
DAC0_OUT0ALT #2/
OPAMP_OUT0ALT
ACMP0_CH2
TIM0_CDTI0 #4
TIM2_CC0 #0
US2_TX #0
LES_CH2 #0
H3
H4
H5
H6
H7
H8
PD14
PA7
I2C0_SDA #3
LCD_SEG35
LCD_SEG36
EBI_CSTFT #0/1/2
EBI_DCLK #0/1/2
PA8
VSS
Ground
IOVDD_3
PD8
Digital IO power supply 3.
BU_VIN
CMU_CLK1 #1
ETM_TD3 #0/2
ADC0_CH5
DAC0_OUT2 #0/
OPAMP_OUT2
H9
PD5
LEU0_RX #0
ADC0_CH6
DAC0_P1 #0/
OPAMP_P1
TIM1_CC0 #4
LETIM0_OUT0 #0
PCNT0_S0IN #3
LES_ALTEX0 #0
ACMP0_O #2
ETM_TD0 #0
US1_RX #2
I2C0_SDA #1
H10
H11
PD6
PD7
CMU_CLK0 #2
LES_ALTEX1 #0
ACMP1_O #2
ADC0_CH7
DAC0_N1 #0/
OPAMP_N1
TIM1_CC1 #4
LETIM0_OUT1 #0
PCNT0_S1IN #3
US1_TX #2
I2C0_SCL #1
ETM_TCLK #0
DAC0_OUT0ALT #1/
OPAMP_OUT0ALT
ACMP0_CH1
US0_RX #5
US1_RX #0
I2C0_SCL #4
TIM0_CC2 #4
PCNT0_S1IN #2
LES_CH1 #0
PRS_CH3 #0
J1
J2
PC1
PC3
EBI_A24 #0/1/2
DAC0_OUT0ALT #3/
OPAMP_OUT0ALT
ACMP0_CH3
EBI_NANDREn #0/1/2
TIM0_CDTI1 #4
US2_RX #0
LES_CH3 #0
J3
J4
J5
J6
J7
J8
PD15
PA12
PA9
I2C0_SCL #3
LCD_BCAP_P
LCD_SEG37
LCD_SEG38
EBI_A00 #0/1/2
EBI_DTEN #0/1/2
EBI_VSNC #0/1/2
EBI_A03 #0/1/2
EBI_A04 #0/1/2
TIM2_CC0 #1
TIM2_CC1 #0
TIM2_CC2 #0
PA10
PB9
U1_TX #2
U1_RX #2
PB10
US1_CLK #1
USB_DMPU #0
J9
PD2
PD3
ADC0_CH2
EBI_A27 #0/1/2
TIM0_CC1 #3
TIM0_CC2 #3
DBG_SWO #3
ETM_TD1 #0/2
ADC0_CH3
DAC0_N2 #0/
OPAMP_N2
J10
US1_CS #1
LEU0_TX #0
ADC0_CH4
DAC0_P2 #0/
OPAMP_P2
J11
K1
PD4
PB7
PC4
ETM_TD2 #0/2
LES_CH4 #0
US0_TX #4
US1_CLK #0
LFXTAL_P
TIM1_CC0 #3
DAC0_P0 #0/
OPAMP_P0
ACMP0_CH4
TIM0_CDTI2 #4
LETIM0_OUT0 #3
PCNT1_S0IN #0
US2_CLK #0
I2C1_SDA #0
K2
EBI_A26 #0/1/2
EBI_A01 #0/1/2
K3
K4
K5
PA13
VSS
LCD_BCAP_N
Ground
TIM2_CC1 #1
PA11
LCD_SEG39
EBI_HSNC #0/1/2
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BGA112 Pin#
and Name
Pin Alternate Functionality / Description
Pin Name
Analog
EBI
Timers
Communication
Other
Reset input.
Active low, with internal pull-up.
K6
RESETn
K7
K8
K9
AVSS_1
AVDD_2
AVDD_1
Analog ground 1.
Analog power supply 2.
Analog power supply 1.
Analog ground 0.
K10
K11
AVSS_0
PD1
ADC0_CH1
DAC0_OUT1ALT #4/
OPAMP_OUT1ALT
TIM0_CC0 #3
PCNT2_S1IN #0
US1_RX #1
DBG_SWO #2
LES_CH5 #0
US0_RX #4
US1_CS #0
L1
L2
PB8
PC5
LFXTAL_N
TIM1_CC1 #3
DAC0_N0 #0/
OPAMP_N0
ACMP0_CH5
LETIM0_OUT1 #3
PCNT1_S1IN #0
US2_CS #0
I2C1_SCL #0
EBI_NANDWEn #0/1/2
EBI_A02 #0/1/2
L3
L4
PA14
LCD_BEXT
TIM2_CC2 #1
IOVDD_1
Digital IO power supply 1.
DAC0_OUT0 #0/
OPAMP_OUT0
TIM1_CC2 #3
LETIM0_OUT0 #1
L5
PB11
I2C1_SDA #1
I2C1_SCL #1
DAC0_OUT1 #0/
OPAMP_OUT1
L6
L7
L8
PB12
AVSS_2
PB13
LETIM0_OUT1 #1
Analog ground 2.
HFXTAL_P
US0_CLK #4/5
LEU0_TX #1
US0_CS #4/5
LEU0_RX #1
L9
PB14
HFXTAL_N
L10
AVDD_0
Analog power supply 0.
ADC0_CH0
DAC0_OUT0ALT #4/
OPAMP_OUT0ALT
DAC0_OUT2 #1/
OPAMP_OUT2
L11
PD0
PCNT2_S0IN #0
US1_TX #1
4.2 Alternate functionality pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in
Table 4.2 (p. 50). The table shows the name of the alternate functionality in the first column, followed
by columns showing the possible LOCATION bitfield settings.
Note
Some functionality, such as analog interfaces, do not have alternate settings or a LOCA-
TION bitfield. In these cases, the pinout is shown in the column corresponding to LOCA-
TION 0.
Table 4.2. Alternate functionality overview
Alternate
LOCATION
Functionality
ACMP0_CH0
ACMP0_CH1
ACMP0_CH2
0
1
2
3
4
5
6
Description
Analog comparator ACMP0, channel 0.
Analog comparator ACMP0, channel 1.
Analog comparator ACMP0, channel 2.
PC0
PC1
PC2
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Alternate
LOCATION
Functionality
ACMP0_CH3
ACMP0_CH4
ACMP0_CH5
ACMP0_CH6
ACMP0_CH7
ACMP0_O
0
1
2
3
4
5
6
Description
PC3
PC4
PC5
PC6
PC7
PE13
PC8
PC9
PC10
PC11
PF2
Analog comparator ACMP0, channel 3.
Analog comparator ACMP0, channel 4.
Analog comparator ACMP0, channel 5.
Analog comparator ACMP0, channel 6.
Analog comparator ACMP0, channel 7.
PE2
PD6
Analog comparator ACMP0, digital output.
Analog comparator ACMP1, channel 0.
ACMP1_CH0
ACMP1_CH1
ACMP1_CH2
ACMP1_CH3
ACMP1_O
Analog comparator ACMP1, channel 1.
Analog comparator ACMP1, channel 2.
Analog comparator ACMP1, channel 3.
PE3
PD7
Analog comparator ACMP1, digital output.
Analog to digital converter ADC0, input channel number 0.
Analog to digital converter ADC0, input channel number 1.
Analog to digital converter ADC0, input channel number 2.
Analog to digital converter ADC0, input channel number 3.
Analog to digital converter ADC0, input channel number 4.
Analog to digital converter ADC0, input channel number 5.
Analog to digital converter ADC0, input channel number 6.
Analog to digital converter ADC0, input channel number 7.
Bootloader RX
ADC0_CH0
ADC0_CH1
ADC0_CH2
ADC0_CH3
ADC0_CH4
ADC0_CH5
ADC0_CH6
ADC0_CH7
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
BOOTLOADER_RX PE11
BOOTLOADER_TX PE10
Bootloader TX
Backup Power Domain status, whether or not the system
is in backup mode
BU_STAT
PE3
BU_VIN
PD8
PE2
PA2
PA1
Battery input for Backup Power Domain
BU_VOUT
CMU_CLK0
CMU_CLK1
Power output for Backup Power Domain
Clock Management Unit, clock output number 0.
Clock Management Unit, clock output number 1.
PD7
PD8
PE12
DAC0_N0 /
OPAMP_N0
PC5
PD7
PD3
PB11
PC0
PB12
Operational Amplifier 0 external negative input.
Operational Amplifier 1 external negative input.
Operational Amplifier 2 external negative input.
DAC0_N1 /
OPAMP_N1
DAC0_N2 /
OPAMP_N2
DAC0_OUT0 /
OPAMP_OUT0
Digital to Analog Converter DAC0_OUT0 /
OPAMP output channel number 0.
DAC0_OUT0ALT /
OPAMP_OUT0ALT
Digital to Analog Converter DAC0_OUT0ALT /
OPAMP alternative output for channel 0.
PC1
PC2
PC3
PD0
PD1
DAC0_OUT1 /
OPAMP_OUT1
Digital to Analog Converter DAC0_OUT1 /
OPAMP output channel number 1.
DAC0_OUT1ALT /
OPAMP_OUT1ALT
Digital to Analog Converter DAC0_OUT1ALT /
OPAMP alternative output for channel 1.
DAC0_OUT2 /
OPAMP_OUT2
Digital to Analog Converter DAC0_OUT2 /
OPAMP output channel number 2.
PD5
PC4
PD6
PD0
DAC0_P0 /
OPAMP_P0
Operational Amplifier 0 external positive input.
Operational Amplifier 1 external positive input.
DAC0_P1 /
OPAMP_P1
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Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
DAC0_P2 /
OPAMP_P2
PD4
PF0
Operational Amplifier 2 external positive input.
Debug-interface Serial Wire clock input.
DBG_SWCLK
DBG_SWDIO
DBG_SWO
PF0
PF1
PF0
PF1
PD1
PF0
Note that this function is enabled to pin out of reset, and
has a built-in pull down.
Debug-interface Serial Wire data input / output.
PF1
PF2
PF1
PD2
Note that this function is enabled to pin out of reset, and
has a built-in pull up.
Debug-interface Serial Wire viewer Output.
Note that this function is not enabled after reset, and must
be enabled by software to be used.
EBI_A00
EBI_A01
EBI_A02
EBI_A03
EBI_A04
EBI_A05
EBI_A06
EBI_A07
EBI_A08
EBI_A09
EBI_A10
EBI_A11
EBI_A12
EBI_A13
EBI_A14
EBI_A15
EBI_A16
EBI_A17
EBI_A18
EBI_A19
EBI_A20
EBI_A21
EBI_A22
EBI_A23
EBI_A24
EBI_A25
EBI_A26
EBI_A27
PA12
PA13
PA14
PB9
PB10
PC6
PC7
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PC8
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PC0
PC1
PC2
PC4
PD2
PA12
PA13
PA14
PB9
PB10
PC6
PC7
PE0
PE1
PC9
PC10
PE4
PE5
PE6
PE7
PC8
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PC0
PC1
PC2
PC4
PD2
PA12
PA13
PA14
PB9
PB10
PC6
PC7
PE0
PE1
PC9
PC10
PE4
PE5
PE6
PE7
PC8
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PC0
PC1
PC2
PC4
PD2
External Bus Interface (EBI) address output pin 00.
External Bus Interface (EBI) address output pin 01.
External Bus Interface (EBI) address output pin 02.
External Bus Interface (EBI) address output pin 03.
External Bus Interface (EBI) address output pin 04.
External Bus Interface (EBI) address output pin 05.
External Bus Interface (EBI) address output pin 06.
External Bus Interface (EBI) address output pin 07.
External Bus Interface (EBI) address output pin 08.
External Bus Interface (EBI) address output pin 09.
External Bus Interface (EBI) address output pin 10.
External Bus Interface (EBI) address output pin 11.
External Bus Interface (EBI) address output pin 12.
External Bus Interface (EBI) address output pin 13.
External Bus Interface (EBI) address output pin 14.
External Bus Interface (EBI) address output pin 15.
External Bus Interface (EBI) address output pin 16.
External Bus Interface (EBI) address output pin 17.
External Bus Interface (EBI) address output pin 18.
External Bus Interface (EBI) address output pin 19.
External Bus Interface (EBI) address output pin 20.
External Bus Interface (EBI) address output pin 21.
External Bus Interface (EBI) address output pin 22.
External Bus Interface (EBI) address output pin 23.
External Bus Interface (EBI) address output pin 24.
External Bus Interface (EBI) address output pin 25.
External Bus Interface (EBI) address output pin 26.
External Bus Interface (EBI) address output pin 27.
External Bus Interface (EBI) address and data input / out-
put pin 00.
EBI_AD00
EBI_AD01
EBI_AD02
PE8
PE9
PE10
PE8
PE9
PE10
PE8
PE9
PE10
External Bus Interface (EBI) address and data input / out-
put pin 01.
External Bus Interface (EBI) address and data input / out-
put pin 02.
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Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
External Bus Interface (EBI) address and data input / out-
put pin 03.
EBI_AD03
EBI_AD04
EBI_AD05
EBI_AD06
EBI_AD07
EBI_AD08
EBI_AD09
EBI_AD10
EBI_AD11
EBI_AD12
EBI_AD13
EBI_AD14
PE11
PE12
PE13
PE14
PE15
PA15
PA0
PE11
PE11
External Bus Interface (EBI) address and data input / out-
put pin 04.
PE12
PE13
PE14
PE15
PA15
PA0
PE12
PE13
PE14
PE15
PA15
PA0
External Bus Interface (EBI) address and data input / out-
put pin 05.
External Bus Interface (EBI) address and data input / out-
put pin 06.
External Bus Interface (EBI) address and data input / out-
put pin 07.
External Bus Interface (EBI) address and data input / out-
put pin 08.
External Bus Interface (EBI) address and data input / out-
put pin 09.
External Bus Interface (EBI) address and data input / out-
put pin 10.
PA1
PA1
PA1
External Bus Interface (EBI) address and data input / out-
put pin 11.
PA2
PA2
PA2
External Bus Interface (EBI) address and data input / out-
put pin 12.
PA3
PA3
PA3
External Bus Interface (EBI) address and data input / out-
put pin 13.
PA4
PA4
PA4
External Bus Interface (EBI) address and data input / out-
put pin 14.
PA5
PA5
PA5
External Bus Interface (EBI) address and data input / out-
put pin 15.
EBI_AD15
EBI_ALE
PA6
PA6
PC11
PF2
PA6
PC11
PF2
External Bus Interface (EBI) Address Latch Enable output.
External Bus Interface (EBI) Hardware Ready Control in-
put.
EBI_ARDY
PF2
EBI_BL0
PF6
PF6
PF6
External Bus Interface (EBI) Byte Lane/Enable pin 0.
External Bus Interface (EBI) Byte Lane/Enable pin 1.
External Bus Interface (EBI) Chip Select output 0.
External Bus Interface (EBI) Chip Select output 1.
External Bus Interface (EBI) Chip Select output 2.
External Bus Interface (EBI) Chip Select output 3.
External Bus Interface (EBI) Chip Select output TFT.
External Bus Interface (EBI) TFT Dot Clock pin.
External Bus Interface (EBI) TFT Data Enable pin.
EBI_BL1
PF7
PF7
PF7
EBI_CS0
EBI_CS1
EBI_CS2
EBI_CS3
EBI_CSTFT
EBI_DCLK
EBI_DTEN
PD9
PD10
PD11
PD12
PA7
PD9
PD10
PD11
PD12
PA7
PD9
PD10
PD11
PD12
PA7
PA8
PA8
PA8
PA9
PA9
PA9
External Bus Interface (EBI) TFT Horizontal Synchroniza-
tion pin.
EBI_HSNC
PA11
PA11
PA11
EBI_NANDREn
EBI_NANDWEn
EBI_REn
PC3
PC5
PF5
PC3
PC5
PF9
PC3
PC5
PF5
External Bus Interface (EBI) NAND Read Enable output.
External Bus Interface (EBI) NAND Write Enable output.
External Bus Interface (EBI) Read Enable output.
External Bus Interface (EBI) TFT Vertical Synchronization
pin.
EBI_VSNC
PA10
PA10
PA10
EBI_WEn
ETM_TCLK
ETM_TD0
ETM_TD1
PF8
PF8
PF9
PD13
External Bus Interface (EBI) Write Enable output.
Embedded Trace Module ETM clock .
Embedded Trace Module ETM data 0.
Embedded Trace Module ETM data 1.
PD7
PD6
PD3
PC6
PC7
PD3
PA6
PA2
PA3
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Alternate
LOCATION
Functionality
ETM_TD2
0
1
2
PD4
PD5
3
4
5
6
Description
PD4
PD5
PA0
PA6
PC9
PF1
PF2
PE13
PB15
PA4
Embedded Trace Module ETM data 2.
ETM_TD3
PA5
Embedded Trace Module ETM data 3.
GPIO_EM4WU0
GPIO_EM4WU1
GPIO_EM4WU2
GPIO_EM4WU3
GPIO_EM4WU4
GPIO_EM4WU5
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
Pin can be used to wake the system up from EM4
High Frequency Crystal (4 - 48 MHz) negative pin. Also
used as external optional clock input pin.
HFXTAL_N
PB14
HFXTAL_P
I2C0_SCL
I2C0_SDA
I2C1_SCL
I2C1_SDA
PB13
PA1
PA0
PC5
PC4
High Frequency Crystal (4 - 48 MHz) positive pin.
I2C0 Serial Clock Line input / output.
I2C0 Serial Data input / output.
PD7
PC7
PC6
PE1
PE0
PD15
PD14
PC1
PC0
PF1
PF0
PE13
PE12
PD6
PB12
PB11
I2C1 Serial Clock Line input / output.
I2C1 Serial Data input / output.
LCD voltage booster (optional), boost capacitor, negative
pin. If using the LCD voltage booster, connect a 22 nF ca-
pacitor between LCD_BCAP_N and LCD_BCAP_P.
LCD_BCAP_N
LCD_BCAP_P
PA13
PA12
LCD voltage booster (optional), boost capacitor, positive
pin. If using the LCD voltage booster, connect a 22 nF ca-
pacitor between LCD_BCAP_N and LCD_BCAP_P.
LCD voltage booster (optional), boost output. If using the
LCD voltage booster, connect a 1 uF capacitor between
this pin and VSS.
LCD_BEXT
PA14
An external LCD voltage may also be applied to this pin if
the booster is not enabled.
If AVDD is used directly as the LCD supply voltage, this
pin may be left unconnected or used as a GPIO.
LCD_COM0
LCD_COM1
LCD_COM2
LCD_COM3
PE4
PE5
PE6
PE7
LCD driver common line number 0.
LCD driver common line number 1.
LCD driver common line number 2.
LCD driver common line number 3.
LCD segment line 0. Segments 0, 1, 2 and 3 are con-
trolled by SEGEN0.
LCD_SEG0
LCD_SEG3
LCD_SEG4
LCD_SEG5
LCD_SEG6
LCD_SEG7
LCD_SEG8
LCD_SEG9
LCD_SEG10
PF2
LCD segment line 3. Segments 0, 1, 2 and 3 are con-
trolled by SEGEN0.
PF5
LCD segment line 4. Segments 4, 5, 6 and 7 are con-
trolled by SEGEN1.
PE8
LCD segment line 5. Segments 4, 5, 6 and 7 are con-
trolled by SEGEN1.
PE9
LCD segment line 6. Segments 4, 5, 6 and 7 are con-
trolled by SEGEN1.
PE10
PE11
PE12
PE13
PE14
LCD segment line 7. Segments 4, 5, 6 and 7 are con-
trolled by SEGEN1.
LCD segment line 8. Segments 8, 9, 10 and 11 are con-
trolled by SEGEN2.
LCD segment line 9. Segments 8, 9, 10 and 11 are con-
trolled by SEGEN2.
LCD segment line 10. Segments 8, 9, 10 and 11 are con-
trolled by SEGEN2.
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Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD segment line 11. Segments 8, 9, 10 and 11 are con-
trolled by SEGEN2.
LCD_SEG11
LCD_SEG12
LCD_SEG13
LCD_SEG14
LCD_SEG15
LCD_SEG16
LCD_SEG17
LCD_SEG18
LCD_SEG19
PE15
PA15
PA0
PA1
PA2
PA3
PA4
PA5
PA6
LCD segment line 12. Segments 12, 13, 14 and 15 are
controlled by SEGEN3.
LCD segment line 13. Segments 12, 13, 14 and 15 are
controlled by SEGEN3.
LCD segment line 14. Segments 12, 13, 14 and 15 are
controlled by SEGEN3.
LCD segment line 15. Segments 12, 13, 14 and 15 are
controlled by SEGEN3.
LCD segment line 16. Segments 16, 17, 18 and 19 are
controlled by SEGEN4.
LCD segment line 17. Segments 16, 17, 18 and 19 are
controlled by SEGEN4.
LCD segment line 18. Segments 16, 17, 18 and 19 are
controlled by SEGEN4.
LCD segment line 19. Segments 16, 17, 18 and 19 are
controlled by SEGEN4.
LCD segment line 20. Segments 20, 21, 22 and 23 are
controlled by SEGEN5. This pin may also be used as LCD
COM line 4
LCD_SEG20/
LCD_COM4
PB3
PB4
PB5
PB6
LCD segment line 21. Segments 20, 21, 22 and 23 are
controlled by SEGEN5. This pin may also be used as LCD
COM line 5
LCD_SEG21/
LCD_COM5
LCD segment line 22. Segments 20, 21, 22 and 23 are
controlled by SEGEN5. This pin may also be used as LCD
COM line 6
LCD_SEG22/
LCD_COM6
LCD segment line 23. Segments 20, 21, 22 and 23 are
controlled by SEGEN5. This pin may also be used as LCD
COM line 7
LCD_SEG23/
LCD_COM7
LCD segment line 24. Segments 24, 25, 26 and 27 are
controlled by SEGEN6.
LCD_SEG24
LCD_SEG25
LCD_SEG26
LCD_SEG27
LCD_SEG28
LCD_SEG29
LCD_SEG30
LCD_SEG31
LCD_SEG32
LCD_SEG33
LCD_SEG34
LCD_SEG35
LCD_SEG36
PF6
LCD segment line 25. Segments 24, 25, 26 and 27 are
controlled by SEGEN6.
PF7
LCD segment line 26. Segments 24, 25, 26 and 27 are
controlled by SEGEN6.
PF8
LCD segment line 27. Segments 24, 25, 26 and 27 are
controlled by SEGEN6.
PF9
LCD segment line 28. Segments 28, 29, 30 and 31 are
controlled by SEGEN7.
PD9
PD10
PD11
PD12
PB0
PB1
PB2
PA7
PA8
LCD segment line 29. Segments 28, 29, 30 and 31 are
controlled by SEGEN7.
LCD segment line 30. Segments 28, 29, 30 and 31 are
controlled by SEGEN7.
LCD segment line 31. Segments 28, 29, 30 and 31 are
controlled by SEGEN7.
LCD segment line 32. Segments 32, 33, 34 and 35 are
controlled by SEGEN8.
LCD segment line 33. Segments 32, 33, 34 and 35 are
controlled by SEGEN8.
LCD segment line 34. Segments 32, 33, 34 and 35 are
controlled by SEGEN8.
LCD segment line 35. Segments 32, 33, 34 and 35 are
controlled by SEGEN8.
LCD segment line 36. Segments 36, 37, 38 and 39 are
controlled by SEGEN9.
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Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
LCD segment line 37. Segments 36, 37, 38 and 39 are
controlled by SEGEN9.
LCD_SEG37
LCD_SEG38
LCD_SEG39
PA9
LCD segment line 38. Segments 36, 37, 38 and 39 are
controlled by SEGEN9.
PA10
PA11
LCD segment line 39. Segments 36, 37, 38 and 39 are
controlled by SEGEN9.
LES_ALTEX0
LES_ALTEX1
LES_ALTEX2
LES_ALTEX3
LES_ALTEX4
LES_ALTEX5
LES_ALTEX6
LES_ALTEX7
LES_CH0
PD6
PD7
PA3
PA4
PA5
PE11
PE12
PE13
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PD6
PD7
PD5
LESENSE alternate exite output 0.
LESENSE alternate exite output 1.
LESENSE alternate exite output 2.
LESENSE alternate exite output 3.
LESENSE alternate exite output 4.
LESENSE alternate exite output 5.
LESENSE alternate exite output 6.
LESENSE alternate exite output 7.
LESENSE channel 0.
LES_CH1
LESENSE channel 1.
LES_CH2
LESENSE channel 2.
LES_CH3
LESENSE channel 3.
LES_CH4
LESENSE channel 4.
LES_CH5
LESENSE channel 5.
LES_CH6
LESENSE channel 6.
LES_CH7
LESENSE channel 7.
LES_CH8
LESENSE channel 8.
LES_CH9
LESENSE channel 9.
LES_CH10
LES_CH11
LETIM0_OUT0
LETIM0_OUT1
LEU0_RX
LESENSE channel 10.
LESENSE channel 11.
PB11
PB12
PB14
PF0
PC4
Low Energy Timer LETIM0, output channel 0.
Low Energy Timer LETIM0, output channel 1.
LEUART0 Receive input.
PF1
PC5
PF1
PE15
PA0
PF2
LEUART0 Transmit output. Also used as receive input in
half duplex communication.
LEU0_TX
LEU1_RX
LEU1_TX
PD4
PC7
PC6
PB13
PA6
PA5
PE14
PF0
LEUART1 Receive input.
LEUART1 Transmit output. Also used as receive input in
half duplex communication.
Low Frequency Crystal (typically 32.768 kHz) negative
pin. Also used as an optional external clock input pin.
LFXTAL_N
PB8
PB7
LFXTAL_P
Low Frequency Crystal (typically 32.768 kHz) positive pin.
Pulse Counter PCNT0 input number 0.
Pulse Counter PCNT0 input number 1.
Pulse Counter PCNT1 input number 0.
Pulse Counter PCNT1 input number 1.
Pulse Counter PCNT2 input number 0.
Pulse Counter PCNT2 input number 1.
Peripheral Reflex System PRS, channel 0.
PCNT0_S0IN
PCNT0_S1IN
PCNT1_S0IN
PCNT1_S1IN
PCNT2_S0IN
PCNT2_S1IN
PRS_CH0
PE0
PE1
PB3
PB4
PE8
PE9
PC0
PC1
PD6
PD7
PC4
PC5
PD0
PD1
PA0
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Alternate
LOCATION
Functionality
PRS_CH1
PRS_CH2
PRS_CH3
TIM0_CC0
TIM0_CC1
TIM0_CC2
TIM0_CDTI0
TIM0_CDTI1
TIM0_CDTI2
TIM1_CC0
TIM1_CC1
TIM1_CC2
TIM2_CC0
TIM2_CC1
TIM2_CC2
TIM3_CC0
TIM3_CC1
TIM3_CC2
U0_RX
0
1
2
3
4
5
6
Description
PA1
PC0
PC1
PA0
PA1
PA2
PA3
PA4
PA5
Peripheral Reflex System PRS, channel 1.
PF5
PE8
PA0
PA1
PA2
Peripheral Reflex System PRS, channel 2.
Peripheral Reflex System PRS, channel 3.
PF6
PF7
PF8
PD1
PA0
PC0
PC1
PC2
PC3
PC4
PD6
PD7
PF0
PF1
PF2
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 0 Complimentary Deat Time Insertion channel 0.
Timer 0 Complimentary Deat Time Insertion channel 1.
Timer 0 Complimentary Deat Time Insertion channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
Timer 2 Capture Compare input / output channel 0.
Timer 2 Capture Compare input / output channel 1.
Timer 2 Capture Compare input / output channel 2.
Timer 3 Capture Compare input / output channel 0.
Timer 3 Capture Compare input / output channel 1.
Timer 3 Capture Compare input / output channel 2.
UART0 Receive input.
PD2
PD3
PF5
PB0
PB1
PB2
PC8
PC9
PC10
PF5
PE10
PE11
PE12
PA12
PA13
PA14
PE0
PB7
PB8
PB11
PA8
PA9
PA10
PE14
PE15
PA15
PF7
PE1
PE2
PE1
PA4
PA3
PB10
PB9
UART0 Transmit output. Also used as receive input in half
duplex communication.
U0_TX
U1_RX
U1_TX
PF6
PE0
PF11
PF10
PE3
PE2
UART1 Receive input.
UART1 Transmit output. Also used as receive input in half
duplex communication.
US0_CLK
US0_CS
PE12
PE13
PE5
PE4
PC9
PC8
PB13
PB14
PB13
PB14
USART0 clock input / output.
USART0 chip select input / output.
USART0 Asynchronous Receive.
US0_RX
US0_TX
PE11
PE10
PE6
PE7
PC10
PC11
PE12
PE13
PB8
PB7
PC1
PC0
USART0 Synchronous mode Master Input / Slave Output
(MISO).
USART0 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
USART0 Synchronous mode Master Output / Slave Input
(MOSI).
US1_CLK
US1_CS
PB7
PB8
PD2
PD3
PF0
PF1
USART1 clock input / output.
USART1 chip select input / output.
USART1 Asynchronous Receive.
US1_RX
US1_TX
PC1
PC0
PD1
PD0
PD6
PD7
USART1 Synchronous mode Master Input / Slave Output
(MISO).
USART1 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
USART1 Synchronous mode Master Output / Slave Input
(MOSI).
US2_CLK
US2_CS
US2_RX
PC4
PC5
PC3
PB5
PB6
PB4
USART2 clock input / output.
USART2 chip select input / output.
USART2 Asynchronous Receive.
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Alternate
LOCATION
Functionality
0
1
2
3
4
5
6
Description
USART2 Synchronous mode Master Input / Slave Output
(MISO).
USART2 Asynchronous Transmit.Also used as receive in-
put in half duplex communication.
US2_TX
PC2
PB3
USART2 Synchronous mode Master Output / Slave Input
(MOSI).
USB_DM
PF10
PD2
USB D- pin.
USB_DMPU
USB_DP
USB D- Pullup control.
USB D+ pin.
PF11
PF12
USB_ID
USB ID pin. Used in OTG mode.
USB 5 V VBUS input.
USB 5 V VBUS enable.
USB Input to internal 3.3 V regulator
USB_VBUS
USB_VBUSEN
USB_VREGI
USB_VBUS
PF5
USB_VREGI
USB Decoupling for internal 3.3 V USB regulator and reg-
ulator output
USB_VREGO
USV_VREGO
4.3 GPIO pinout overview
The specific GPIO pins available in EFM32GG990 is shown in Table 4.3 (p. 58). Each GPIO port is
organized as 16-bit ports indicated by letters A through F, and the individual pin on this port in indicated
by a number from 15 down to 0.
Table 4.3. GPIO Pinout
Port
Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin
Pin
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Port A
Port B
Port C
Port D
Port E
Port F
PA15 PA14 PA13 PA12 PA11 PA10
PB15 PB14 PB13 PB12 PB11 PB10
PA9
PB9
PC9
PD9
PE9
PF9
PA8
PB8
PC8
PD8
PE8
PF8
PA7
PB7
PC7
PD7
PE7
PF7
PA6
PB6
PC6
PD6
PE6
PF6
PA5
PB5
PC5
PD5
PE5
PF5
PA4
PB4
PC4
PD4
PE4
-
PA3
PB3
PC3
PD3
PE3
-
PA2
PB2
PC2
PD2
PE2
PF2
PA1
PB1
PC1
PD1
PE1
PF1
PA0
PB0
PC0
PD0
PE0
PF0
-
-
-
-
PC11 PC10
PD15 PD14 PD13 PD12 PD11 PD10
PE15 PE14 PE13 PE12 PE11 PE10
-
-
-
PF12
PF11
PF10
4.4 Opamp pinout overview
The specific opamp terminals available in EFM32GG990 is shown in Figure 4.2 (p. 59) .
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Figure 4.2. Opamp Pinout
PB11
PB12
OUT0ALT
PC4
PC5
+
PC0
OPA0
-
OUT0
PC1
PC2
PC3
+
PD4
PD3
OPA2
-
OUT2
PD6
PD7
OUT1ALT
OUT1
+
OPA1
-
PD0
PD1
PD5
4.5 BGA112 Package
Figure 4.3. BGA112
Note:
1. The dimensions in parenthesis are reference.
2. Datum 'C' and seating plane are defined by the crown of the solder balls.
3. All dimensions are in millimeters.
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The BGA112 Package uses SAC105 solderballs.
All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).
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5 PCB Layout and Soldering
5.1 Recommended PCB Layout
Figure 5.1. BGA112 PCB Land Pattern
c1
cn
r1
a
b
e
rn
d
Table 5.1. BGA112 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
Symbol
Row name and
column number
a
b
d
e
0.35
0.80
8.00
8.00
r1
rn
A
L
c1
cn
1
11
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Figure 5.2. BGA112 PCB Solder Mask
a
b
e
d
Table 5.2. BGA112 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
a
b
d
e
0.48
0.80
8.00
8.00
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Figure 5.3. BGA112 PCB Stencil Design
a
b
e
d
Table 5.3. BGA112 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
a
b
d
e
0.33
0.80
8.00
8.00
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
5.2 Soldering Information
The latest IPC/JEDEC J-STD-020 recommendations for Pb-Free reflow soldering should be followed.
The packages have a Moisture Sensitivity Level rating of 3, please see the latest IPC/JEDEC J-STD-033
standard for MSL description and level 3 bake conditions.
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6 Chip Marking, Revision and Errata
6.1 Chip Marking
In the illustration below package fields and position are shown.
Figure 6.1. Example Chip Marking
6.2 Revision
The revision of a chip can be determined from the "Revision" field in Figure 6.1 (p. 64). If the revision
says "ES" (Engineering Sample), the revision must be read out electronically as specified in the reference
manual.
6.3 Errata
Please see the dxxxx_efm32gg990_errata.pdf for description and resolution of device erratas. This doc-
ument is available in Simplicity Studio and online at http://www.energymicro.com/downloads/datasheets.
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7 Revision History
7.1 Revision 1.00
September 11th, 2012
Updated the HFRCO 1 MHz band typical value to 1.2 MHz.
Updated the HFRCO 7 MHz band typical value to 6.6 MHz.
Other minor corrections.
7.2 Revision 0.98
May 25th, 2012
Corrected BGA solder balls material description.
Corrected EM3 current consumption in the Electrical Characteristics section.
7.3 Revision 0.96
February 28th, 2012
Added reference to errata document.
Corrected BGA112 package drawing.
Updated PCB land pattern, solder mask and stencil design.
7.4 Revision 0.95
September 28th, 2011
Flash configuration for Giant Gecko is now 1024KB or 512KB. For flash sizes below 512KB, see the
Leopard Gecko Family.
Corrected operating voltage from 1.8 V to 1.85 V.
Added rising POR level to Electrical Characteristics section.
Updated Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup.
Added Gain error drift and Offset error drift to ADC table.
Added Opamp pinout overview.
Added reference to errata document.
Corrected BGA112 package drawing.
Updated PCB land pattern, solder mask and stencil design.
7.5 Revision 0.91
March 21th, 2011
Added new alternative locations for EBI and SWO.
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Added new USB Pin to pinout table.
Corrected slew rate data for Opamps.
7.6 Revision 0.90
February 4th, 2011
Initial preliminary release.
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A Disclaimer and Trademarks
A.1 Disclaimer
Energy Micro AS intends to provide customers with the latest, accurate, and in-depth documentation of
all peripherals and modules available for system and software implementers using or intending to use
the Energy Micro products. Characterization data, available modules and peripherals, memory sizes and
memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in
different applications. Application examples described herein are for illustrative purposes only. Energy
Micro reserves the right to make changes without further notice and limitation to product information,
specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness
of the included information. Energy Micro shall have no liability for the consequences of use of the infor-
mation supplied herein. This document does not imply or express copyright licenses granted hereunder
to design or fabricate any integrated circuits. The products must not be used within any Life Support
System without the specific written consent of Energy Micro. A "Life Support System" is any product or
system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected
to result in significant personal injury or death. Energy Micro products are generally not intended for
military applications. Energy Micro products shall under no circumstances be used in weapons of mass
destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable
of delivering such weapons.
A.2 Trademark Information
Energy Micro, EFM32, EFR, logo and combinations thereof, and others are the registered trademarks or
trademarks of Energy Micro AS. ARM, CORTEX, THUMB are the registered trademarks of ARM Limited.
Other terms and product names may be trademarks of others.
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B Contact Information
B.1 Energy Micro Corporate Headquarters
Postal Address
Visitor Address
Technical Support
Energy Micro AS
P.O. Box 4633 Nydalen
N-0405 Oslo
Energy Micro AS
Sandakerveien 118
N-0484 Oslo
support.energymicro.com
Phone: +47 40 10 03 01
NORWAY
NORWAY
www.energymicro.com
Phone: +47 23 00 98 00
Fax: + 47 23 00 98 01
B.2 Global Contacts
Visit www.energymicro.com for information on global distributors and representatives or contact
sales@energymicro.com for additional information.
Americas
Europe, Middle East and Africa Asia and Pacific
www.energymicro.com/americas www.energymicro.com/emea
www.energymicro.com/asia
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Table of Contents
1. Ordering Information .................................................................................................................................. 2
2. System Summary ...................................................................................................................................... 3
2.1. System Introduction ......................................................................................................................... 3
2.2. Configuration Summary .................................................................................................................... 7
2.3. Memory Map ................................................................................................................................. 9
3. Electrical Characteristics ........................................................................................................................... 10
3.1. Test Conditions ............................................................................................................................. 10
3.2. Absolute Maximum Ratings ............................................................................................................. 10
3.3. General Operating Conditions .......................................................................................................... 10
3.4. Current Consumption ..................................................................................................................... 12
3.5. Transition between Energy Modes .................................................................................................... 13
3.6. Power Management ....................................................................................................................... 13
3.7. Flash .......................................................................................................................................... 14
3.8. General Purpose Input Output ......................................................................................................... 15
3.9. Oscillators .................................................................................................................................... 22
3.10. Analog Digital Converter (ADC) ...................................................................................................... 26
3.11. Digital Analog Converter (DAC) ...................................................................................................... 36
3.12. Operational Amplifier (OPAMP) ...................................................................................................... 37
3.13. Analog Comparator (ACMP) .......................................................................................................... 41
3.14. Voltage Comparator (VCMP) ......................................................................................................... 43
3.15. LCD .......................................................................................................................................... 44
3.16. Digital Peripherals ....................................................................................................................... 44
4. Pinout and Package ................................................................................................................................. 46
4.1. Pinout ......................................................................................................................................... 46
4.2. Alternate functionality pinout ............................................................................................................ 50
4.3. GPIO pinout overview .................................................................................................................... 58
4.4. Opamp pinout overview .................................................................................................................. 58
4.5. BGA112 Package .......................................................................................................................... 59
5. PCB Layout and Soldering ........................................................................................................................ 61
5.1. Recommended PCB Layout ............................................................................................................ 61
5.2. Soldering Information ..................................................................................................................... 63
6. Chip Marking, Revision and Errata ............................................................................................................ 64
6.1. Chip Marking ................................................................................................................................ 64
6.2. Revision ...................................................................................................................................... 64
6.3. Errata ......................................................................................................................................... 64
7. Revision History ...................................................................................................................................... 65
7.1. Revision 1.00 ............................................................................................................................... 65
7.2. Revision 0.98 ............................................................................................................................... 65
7.3. Revision 0.96 ............................................................................................................................... 65
7.4. Revision 0.95 ............................................................................................................................... 65
7.5. Revision 0.91 ............................................................................................................................... 65
7.6. Revision 0.90 ............................................................................................................................... 66
A. Disclaimer and Trademarks ....................................................................................................................... 67
A.1. Disclaimer ................................................................................................................................... 67
A.2. Trademark Information ................................................................................................................... 67
B. Contact Information ................................................................................................................................. 68
B.1. Energy Micro Corporate Headquarters .............................................................................................. 68
B.2. Global Contacts ............................................................................................................................ 68
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List of Figures
2.1. Block Diagram ....................................................................................................................................... 3
2.2. EFM32GG990 Memory Map with largest RAM and Flash sizes ........................................................................ 9
3.1. Typical Low-Level Output Current, 2V Supply Voltage .................................................................................. 16
3.2. Typical High-Level Output Current, 2V Supply Voltage ................................................................................. 17
3.3. Typical Low-Level Output Current, 3V Supply Voltage .................................................................................. 18
3.4. Typical High-Level Output Current, 3V Supply Voltage ................................................................................. 19
3.5. Typical Low-Level Output Current, 3.8V Supply Voltage ............................................................................... 20
3.6. Typical High-Level Output Current, 3.8V Supply Voltage ............................................................................... 21
3.7. Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup ..................................................... 22
3.8. Calibrated LFRCO Frequency vs Temperature and Supply Voltage ................................................................ 24
3.9. Calibrated HFRCO 11 MHz Band Frequency vs Temperature and Supply Voltage ............................................ 25
3.10. Calibrated HFRCO 14 MHz Band Frequency vs Temperature and Supply Voltage ........................................... 25
3.11. Calibrated HFRCO 21 MHz Band Frequency vs Temperature and Supply Voltage ........................................... 25
3.12. Calibrated HFRCO 28 MHz Band Frequency vs Temperature and Supply Voltage ........................................... 26
3.13. Integral Non-Linearity (INL) ................................................................................................................... 30
3.14. Differential Non-Linearity (DNL) .............................................................................................................. 31
3.15. ADC Frequency Spectrum, Vdd = 3V, Temp = 25° ................................................................................... 32
3.16. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25° ..................................................................... 33
3.17. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25° ................................................................. 34
3.18. ADC Absolute Offset, Common Mode = Vdd /2 ........................................................................................ 35
3.19. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V .............................................. 35
3.20. ADC Temperature sensor readout ......................................................................................................... 36
3.21. OPAMP Common Mode Rejection Ratio ................................................................................................. 39
3.22. OPAMP Positive Power Supply Rejection Ratio ........................................................................................ 39
3.23. OPAMP Negative Power Supply Rejection Ratio ...................................................................................... 40
3.24. OPAMP Voltage Noise Spectral Density (Unity Gain) Vout=1V ..................................................................... 40
3.25. OPAMP Voltage Noise Spectral Density (Non-Unity Gain) .......................................................................... 40
3.26. Typical ACMP Characteristics ............................................................................................................... 42
4.1. EFM32GG990 Pinout (top view, not to scale) ............................................................................................. 46
4.2. Opamp Pinout ...................................................................................................................................... 59
4.3. BGA112 .............................................................................................................................................. 59
5.1. BGA112 PCB Land Pattern ..................................................................................................................... 61
5.2. BGA112 PCB Solder Mask ..................................................................................................................... 62
5.3. BGA112 PCB Stencil Design ................................................................................................................... 63
6.1. Example Chip Marking ........................................................................................................................... 64
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List of Tables
1.1. Ordering Information ................................................................................................................................ 2
2.1. Configuration Summary ............................................................................................................................ 7
3.1. Absolute Maximum Ratings ..................................................................................................................... 10
3.2. General Operating Conditions .................................................................................................................. 10
3.3. Environmental ....................................................................................................................................... 11
3.4. Current Consumption ............................................................................................................................. 12
3.5. Energy Modes Transitions ...................................................................................................................... 13
3.6. Power Management ............................................................................................................................... 13
3.7. Flash .................................................................................................................................................. 14
3.8. GPIO .................................................................................................................................................. 15
3.9. LFXO .................................................................................................................................................. 22
3.10. Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup ................................................... 23
3.11. HFXO ................................................................................................................................................ 23
3.12. LFRCO .............................................................................................................................................. 23
3.13. HFRCO ............................................................................................................................................. 24
3.14. ULFRCO ............................................................................................................................................ 26
3.15. ADC .................................................................................................................................................. 26
3.16. DAC .................................................................................................................................................. 36
3.17. OPAMP ............................................................................................................................................. 37
3.18. ACMP ............................................................................................................................................... 41
3.19. VCMP ............................................................................................................................................... 43
3.20. LCD .................................................................................................................................................. 44
3.21. Digital Peripherals ............................................................................................................................... 44
4.1. Device Pinout ....................................................................................................................................... 46
4.2. Alternate functionality overview ................................................................................................................ 50
4.3. GPIO Pinout ........................................................................................................................................ 58
5.1. BGA112 PCB Land Pattern Dimensions (Dimensions in mm) ......................................................................... 61
5.2. BGA112 PCB Solder Mask Dimensions (Dimensions in mm) ......................................................................... 62
5.3. BGA112 PCB Stencil Design Dimensions (Dimensions in mm) ....................................................................... 63
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List of Equations
3.1. Total ACMP Active Current ..................................................................................................................... 41
3.2. VCMP Trigger Level as a Function of Level Setting ..................................................................................... 43
3.3. Total LCD Current Based on Operational Mode and Internal Boost ................................................................. 44
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