P4C188-12JM [PYRAMID]
ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS; 超高速16K ×4的静态CMOS RAMS
| 型号： | P4C188-12JM |
| 厂家： | 
PYRAMID SEMICONDUCTOR CORPORATION |
| 描述： | ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS |
| 文件： | 总12页 (文件大小：204K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P4C188/P4C188L
ULTRA HIGH SPEED 16K x 4
STATIC CMOS RAMS
FEATURES
Single 5V±10% Power Supply
Full CMOS, 6T Cell
Data Retention with 2.0V Supply
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25 ns (Commercial)
– 12/15/20/25/35 (Industrial)
(P4C188L Military)
Three-State Outputs
TTL/CMOS Compatible Outputs
– 15/20/25/35/45 ns (Military)
Low Power (Commercial/Military)
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
– 22-Pin 300 mil DIP
– 715 mW Active – 12/15
– 550/660 mW Active – 20/25/35/45
– 193/220 mW Standby (TTL Input)
– 83/110 mW Standby (CMOS Input) P4C188
– 15 mW Standby (CMOS Input)
(P4C188L Military)
– 24-Pin 300 mil SOJ
– 22-Pin 290 x 490 mil LCC
DESCRIPTION
Access times as fast as 10 nanoseconds are available,
permitting greatly enhanced system speeds. CMOS is
utilized to reduce power consumption to a low 715mW
active, 193mW standby and only 5mW in the P4C188L
version.
The P4C188 and P4C188L are 65,536-bit ultra high speed
static RAMs organized as 16K x 4. The CMOS memories
require no clocks or refreshing and have equal access and
cycle times. Inputs and outputs are fully TTL-compatible.
The RAMs operate from a single 5V±10% tolerance power
supply. Withbatterybackup, dataintegrityismaintainedfor
supply voltages down to 2.0V. Current drain is typically 10
µA from a 2.0V supply.
The P4C188 and P4C188L are available in 22-pin 300 mil
DIP, 24-pin 300 mil SOJ and 22-pin LCC packages provid-
ing excellent board level densities.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P3, D3, C3)
LCC (L3)
For SOJ pin configuration, please see end of datasheet.
Document # SRAM112 REV A
Revised October 2005
1
P4C188/188L
MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
Symbol
Parameter
Value
Unit
TBIAS
Temperature Under
Bias
–55 to +125
°C
VCC
Power Supply Pin with
Respect to GND
–0.5 to +7
V
TSTG
PT
IOUT
Storage Temperature
Power Dissipation
DC Output Current
–65 to +150
°C
W
mA
Terminal Voltage with
Respect to GND
(up to 7.0V)
–0.5 to
VTERM
TA
VCC +0.5
V
1.0
50
Operating Temperature –55 to +125 °C
CAPACITANCES(4)
RECOMMENDED OPERATING
VCC = 5.0V, TA = 25°C, f = 1.0MHz
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Symbol
Parameter
Conditions Typ. Unit
VCC
Grade(2)
GND
Temperature
Military
Industrial
Commercial
0V
0V
0V
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
CIN
COUT
VIN = 0V
VOUT = 0V
pF
pF
–55°C to +125°C
–40°C to +85°C
0°C to +70°C
Input Capacitance
Output Capacitance
5
7
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2)
P4C188
P4C188L
Symbol
Parameter
Test Conditions
Unit
Min
Max
Min
Max
VIH
VIL
VHC
VLC
Input High Voltage
2.2
–0.5(3)
VCC +0.5
2.2
–0.5(3)
VCC +0.5
V
Input Low Voltage
0.8
0.8
V
V
V
V
V
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage
VCC –0.2 VCC +0.5 VCC –0.2 VCC +0.5
–0.5(3)
0.2
–1.2
0.4
–0.5(3)
0.2
–1.2
0.4
VCD
VOL
VCC = Min., IIN = 18 mA
IOL = +8 mA, VCC = Min.
Output Low Voltage
(TTL Load)
VOH
ILI
Output High Voltage
(TTL Load)
Input Leakage Current
IOH = –4 mA, VCC = Min.
2.4
2.4
V
V
CC = Max.
Mil.
Com’l.
Mil.
–10
–5
+10
+5
–5
+5
µA
n/a
n/a
VIN = GND to VCC
VCC = Max., CE = VIH,
VOUT = GND to VCC
ILO
ISB
Output Leakage Current
–10
–5
+10
+5
–5
+5
µA
n/a
n/a
Com’l.
___
___
___
___
Standby Power Supply
CE ≥ VIH
Mil.
40
35
40
mA
Current (TTL Input Levels)
VCC = Max .,
Ind./Com’l.
n/a
f = Max., Outputs Open
___
___
___
___
ISB1
Standby Power Supply
Current
20
15
2.7
n/a
mA
CE ≥ VHC
Mil.
Ind./Com’l.
VCC = Max.,
(CMOS Input Levels)
f = 0, Outputs Open
VIN ≤ VLC or VIN ≥ VHC
n/a = Not Applicable
Notes:
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V and IIL not more negative than –3.0V and
–100mA, respectively, aILre permissible for pulse widths up to 20ns.
4. This parameter is sampled and not 100% tested.
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
Document # SRAM112 REV A
Page 2 of 12
P4C188/188L
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Temperature
Symbol
Parameter
Unit
Range
Commercial
Industrial
–10 –12 –15 –20 –25 –35 –45
180 170 160 155 150 N/A N/A mA
N/A 180 170 160 155 150 N/A mA
N/A N/A 170 160 155 150 145 mA
ICC
Dynamic Operating Current*
Military
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL
DATA RETENTION CHARACTERISTICS (P4C188L Military Temperature Only)
Typ.*
2.0VCC 3.0V
Max
2.0VCC 3.0V
V
=
V
=
Symbol
Parameter
Test Conditions
Min
Unit
VDR
VCC for Data Retention
Data Retention Current
2.0
V
ICCDR
tCDR
10
15
600
900
µA
ns
CE ≥ VCC –0.2V,
VIN ≥ VCC –0.2V or
VIN ≤ 0.2V
Chip Deselect to
0
Data Retention Time
†
§
tR
Operation Recovery Time
tRC
ns
*TA = +125°C
§tRC = Read Cycle Time
† This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
Document # SRAM112 REV A
Page 3 of 12
P4C188/188L
AC CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-10
Min Max Min Max Min Max Min Max Min Max Min Max Min Max
-12
-15
-20
-25
-35
-45
Sym.
Parameter
Unit
tRC
tAA
Read Cycle Time
Address Access
Time
Chip Enable
Access Time
Output Hold from
Address Change
Chip Enable to
Output in Low Z
Chip Disable to
Output in High Z
Chip Enable to
Power Up Time
Chip Disable to
Power Down
Time
10
12
15
20
25
35
45
ns
ns
10
10
15
15
12
12
20
20
25
25
35
35
45
45
tAC
tOH
tLZ
ns
ns
ns
ns
ns
ns
2
3
2
3
2
2
2
2
2
2
2
3
2
3
tHZ
tPU
tPD
5
6
6
8
10
25
20
35
25
45
0
0
0
0
0
0
0
10
12
15
20
TIMING WAVEFORM OF READ CYCLE NO. 1(5)
TIMING WAVEFORM OF READ CYCLE NO. 2(6)
Notes:
5. CE is LOW and WE is HIGH for READ cycle.
6. WE is HIGH, and address must be valid prior to or coincident with CE
transition LOW.
7. Transition is measured ±200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is sampled
and not 100% tested.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document # SRAM112 REV A
Page 4 of 12
P4C188/188L
AC CHARACTERISTICS - WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-12
-15
-20
-25
-35
-45
Min Max
-10
Sym.
Parameter
Unit
Max Min
Min Max Min Max Min Max Min
Min
10
7
Max
Max
tWC
tCW
Write Cycle Time
12
8
13
10
20
13
25
15
35
25
45
35
ns
ns
Chip Enable
Time to
End of Write
tAW
tAS
tWP
tAH
20
0
Address Valid
to End of Write
7
0
8
8
0
9
10
0
15
0
25
0
35
0
ns
ns
ns
Address
Set-up Time
15
Write Pulse
Width
10
13
0
25
35
Address Hold
Time from
0
0
0
0
0
0
ns
End of Write
10
0
15
0
tDW
tDH
tWZ
Data Valid to
End of Write
5
0
6
0
7
0
8
0
20
5
ns
ns
Data Hold
Time
Write Enable
to Output in
High Z
5
6
6
8
10
15
20
ns
ns
2
tDW
Output Active
from End
2
2
2
2
3
3
of Write
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED) (9)
Notes:
12. Transition is measured ±200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is
sampled and not 100% tested.
9. CE and WE must be LOW for WRITE cycle.
10. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state.
11. Write Cycle Time is measured from the last valid address to the first
transition address.
Document # SRAM112 REV A
Page 5 of 12
P4C188/188L
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(9)
AC TEST CONDITIONS
TRUTH TABLE
Mode
Standby
Read
CE
H
L
WE
X
H
Output
High Z
DOUT
Power
Standby
Active
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
3ns
1.5V
1.5V
Write
L
L
DIN
Active
See Figures 1 and 2
Figure 2. Thevenin Equivalent
Figure 1. Output Load
* including scope and test fixture.
Note:
capacitor is also required between VCC and ground. To avoid signal
reflections, proper termination must be used; for example, a 50Ω test
environment should be terminated into a 50Ω load with 1.73V (Thevenin
Voltage) at the comparator input, and a 116Ω resistor must be used in
series with DOUT to match 166Ω (Thevenin Resistance).
Because of the ultra-high speed of the P4C188/L, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads that
cause supply bounce must be avoided by bringing the V and ground
planes directly up to the contactor fingers. A 0.01 µF hCigCh frequency
Document # SRAM112 REV A
Page 6 of 12
P4C188/188L
ORDERING INFORMATION
SELECTION GUIDE
The P4C188/L is available in the following temperature, speed and package options. The P4C188L is only available
over the Military Temperature range.
Speed (ns)
Temperature
Range
Commercial
Package
10
-10PC
-10JC
N/A
N/A
N/A
N/A
N/A
N/A
N/A
12
-12PC
-12JC
-12PI
-12JI
N/A
N/A
N/A
N/A
N/A
15
-15PC
-15JC
-15PI
-15JI
-15CM
-15DM
-15LM
-15CMB
-15DMB
-15LMB
20
-20PC
-20JC
-20PI
-20JI
-20CM
-20DM
-20LM
-20CMB
-20DMB
-20LMB
25
35
45
Plastic DIP
-25PC
-25JC
-35PC
-35JC
45PC
-45JC
Plastic SOJ
Plastic DIP
Plastic SOJ
Side Brazed DIP
CERDIP
Industrial
-25PI
-35PI
-45PI
-25JI
-35JI
-45JI
Military
Temperature
-25CM
-25DM
-25LM
-25CMB
-25DMB
-25LMB
-35CM
-35DM
-35LM
-35CMB
-35DMB
-35LMB
-45CM
-45DM
-45LM
-45CMB
-45DMB
-45LMB
LCC
Military
Processed*
Side Brazed DIP
CERDIP
LCC
N/A
N/A
* Military temperature range with MIL-STD-883, Class B processing.
N/A = Not Available
Document # SRAM112 REV A
Page 7 of 12
P4C188/188L
SOJ PIN CONFIGURATION
SOJ (J4)
Document # SRAM112 REV A
Page 8 of 12
P4C188/188L
SIDE BRAZED DUAL IN-LINE PACKAGE
Pkg #
C3
# Pins
22 (300 mil)
Symbol
Min
Max
A
b
0.100
0.014
0.030
0.008
1.050
0.260
0.200
0.023
0.060
0.015
1.260
0.310
b2
C
D
E
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
Q
S1
S2
0.015
0.005
0.005
0.070
-
-
CERDIP DUAL IN-LINE PACKAGE
Pkg #
D3
# Pins
22 (300 mil)
Symbol
Min
-
0.015
0.045
0.009
1.060
0.290
Max
A
b
0.225
0.020
0.065
0.012
1.110
0.320
b2
C
D
E
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
0.060
-
Q
S1
α
0.015
0.005
0°
15°
Document # SRAM112 REV A
Page 9 of 12
P4C188/188L
SOJ SMALL OUTLINE IC PACKAGE
Pkg #
# Pins
Symbol
J4
24 (300 mil)
Min
Max
0.148
-
0.020
0.010
0.630
A
A1
b
0.128
0.082
0.016
0.007
0.620
C
D
e
0.050 BSC
0.335 BSC
0.292 0.300
E
E1
E2
Q
0.267 BSC
0.025
-
RECTANGULAR LEADLESS CHIP CARRIER
Pkg #
# Pins
Symbol
A
L3
22
Min
Max
0.060
0.050
0.022
0.284
0.080
0.068
0.028
0.296
A1
B1
D
D1
D2
D3
E
0.150 BSC
0.075 BSC
-
0.296
0.496
0.484
E1
E2
E3
e
0.300 BSC
0.150 BSC
-
0.496
0.050 BSC
R = .012
R = .012
h
j
L
0.039
0.039
0.058
0.051
0.051
0.072
L1
L2
ND
NE
4
7
Document # SRAM112 REV A
Page 10 of 12
P4C188/188L
PLASTIC DUAL IN-LINE PACKAGE
Pkg #
P3
# Pins
22 (300 Mil)
Symbol
Min
-
Max
0.210
-
0.022
0.070
0.014
1.165
0.280
0.325
A
A1
b
0.015
0.014
0.045
0.008
1.145
0.240
0.300
b2
C
D
E1
E
e
0.100 BSC
eB
L
-
0.430
0.150
15°
0.115
0°
α
Document # SRAM112 REV A
Page 11 of 12
P4C188/188L
REVISIONS
DOCUMENTNUMBER:
DOCUMENTTITLE:
SRAM112
P4C188 / P4C188L ULTRA HIGH SPEED 16K x 4 STATIC CMOS RAMS
ORIG. OF
CHANGE
ISSUE
REV.
DESCRIPTIONOFCHANGE
DATE
OR
A
1997
DAB
NewDataSheet
Oct-05
JDB
Change logo to Pyramid
Document # SRAM112 REV A
Page 12 of 12
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