P4C187L-85DM [PYRAMID]
Standard SRAM, 64KX1, 85ns, CMOS, CDIP22, 0.300 INCH, CERDIP-22;
| 型号： | P4C187L-85DM |
| 厂家： | 
PYRAMID SEMICONDUCTOR CORPORATION |
| 描述： | Standard SRAM, 64KX1, 85ns, CMOS, CDIP22, 0.300 INCH, CERDIP-22 CD 静态存储器 内存集成电路 |
| 文件： | 总12页 (文件大小：978K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P4C187/P4C187L
ULTRA HIGH SPEED 64K x 1
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
Three-State Output
ꢀ
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25/35/45 ns (Commercial)
– 12/15/20/25/35 /45 ns (Industrial)
TTL Compatible Output
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
– 15/20/25/35/45/55/70/85 ns (Military)
Low Power Operation
– 22-Pin 300 mil DIP
– 24-Pin 300 mil SOJ
– 22-Pin 290x490 mil LCC
– 28-Pin 350x550 mil LCC
Single 5V±10% Power Supply
Data Retention with 2.0V Supply (P4C187L)
Separate Data I/O
DESCRIPTIOꢀ
TheP4C187/P4C187Lare65,536-bitultrahighspeedstatic
RAMs organized as 64K x 1. The CMOS memories require
no clocks or refreshing and have equal access and cycle
times. The RAMs operate from a single 5V ± 10% toler-
ance power supply. Data integrity is maintained for supply
voltages down to 2.0V for the Low Power version, typically
drawing 10µA.
greatly enhancing system speeds. CMOS reduces power
consumption to a low 743mW active, 193/83mW standby
for TTL/CMOS inputs and only 5.5 mW standby for the
P4C187L.
The P4C187/P4C187L are available in 22-pin 300 mil DIP,
24-pin 300 mil SOJ, 22-pin and 28-pin LCC packages pro-
viding excellent board level densities.
Access times as fast as 10 nanoseconds are available,
FUꢀCTIOꢀAL BLOCk DIAꢁRAM
PIꢀ COꢀFIꢁURATIOꢀS
SOJ (J4)
DIP (P3, D3, C3)
LCC configurations at end of datasheet
Revised October 2013
Document # SRAM111 REV D
P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS
MAꢂIMUM RATIꢀꢁS(1)
RECOMMEꢀDED OPERATIꢀꢁ COꢀDITIOꢀS
Sym Parameter
Value
Unit
ꢁrade(2)
Ambient Temp
0°C to 70°C
ꢁꢀD
0V
VCC
Power Supply Pin with
VCC
Commercial
Industrial
Military
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
-0.5 to +7
V
Respect to GND
-40°C to +85°C
-55°C to +125°C
0V
Terminal Voltage with
VTERM Respect to GND (up to
7.0V)
-0.5 to VCC + 0.5
V
0V
CAPACITAꢀCES(4)
TA
Operating Temperature
-55 to +125
-55 to +125
-65 to +150
1.0
°C
°C
°C
W
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
TBIAS Temperature Under Bias
TSTG Storage Temperature
Sym Parameter
Conditions Typ Unit
PT
Power Dissipation
CIN
Input Capacitance
VIN=0V
5
7
pF
pF
COUT
Output Capacitance
VOUT=0V
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)(2)
P4C187
P4C187L
Sym Parameter
Test Conditions
Unit
Min
2.2
Max
Min
2.2
Max
VIH Input High Voltage
VCC + 0.5
0.8
VCC + 0.5
0.8
V
V
V
V
V
VIL Input Low Voltage
-0.5(3)
-0.5(3)
VHC CMOS Input High Voltage
VLC CMOS Input Low Voltage
VCC - 0.2 VCC + 0.5 VCC - 0.2 VCC + 0.5
-0.5(3)
0.2
-0.5(3)
0.2
VCD Input Clamp Diode Voltage VCC = Min, IIN = 18 mA
Output Low Voltage (TTL
-1.2
-1.2
VOL
IOL = +8 mA, VCC = Min
0.4
0.4
V
V
Load)
Output High Voltage (TTL
Load)
VOH
IOH = -4 mA, VCC = Min
2.4
-10
-5
2.4
-5
MIL
IND/COM
MIL
+10
+5
+5
N/A
+5
VCC = Max,
VIN = GND to VCC
ILI
Input Leakage Current
µA
µA
N/A
-5
-10
-5
+10
+5
VCC = Max, CE = VIH,
VOUT = GND to VCC
ILO Output Leakage Current
IND/COM
MIL
N/A
—
N/A
40
—
40
CE ≥ VIH, VCC = Max, f = Max,
Standby Power Supply
ISB
mA
mA
Current (TTL Input Levels)
Outputs Open
IND/COM
MIL
—
35
—
N/A
1.0
N/A
CE ≥ VHC, VCC = Max, f = 0,
Outputs Open
—
20
—
Standby Power Supply
ISB1 Current (CMOS Input
Levels)
IND/COM
—
15
—
VIN ≤ VLC or VIN ≥ VHC
N/A = Not applicable
ꢀotes:
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20ns.
4. This parameter is sampled and not 100% tested.
1. Stresses greater than those listed under MAꢀIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAꢀIMUM rating conditions for extended
periods may affect reliability.
Document # SRAM111 REV D
Page 2
P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS
POWER DISSIPATIOꢀ CHARACTERISTICS VS. SPEED
Sym Parameter Temperature Range
-10
180
N/A
N/A
-12
170
180
N/A
-15
160
170
170
-20
155
160
160
-25
150
155
155
-35
N/A
150
150
-45
N/A
N/A
145
-55
N/A
N/A
145
-70
N/A
N/A
145
-85
N/A
N/A
145
Unit
mA
mA
mA
Commercial
Dynamic
ICC
Operating
Current*
Industrial
Military
* VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL.
DATA RETEꢀTIOꢀ CHARACTERISTICS (P4C187L Military Temperature Only)
Typ* VCC
=
Max VCC=
Sym Parameter
Test Conditions
Min
Unit
2.0V
3.0V
2.0V
3.0V
VDR VCC for Data Retention
ICCDR Data Retention Current
2.0
V
10
15
600
900
µA
ns
ns
CE ≥ VCC -0.2V,
VIN ≥ VCC -0.2V
or VIN ≤ 0.2V
tCDR Chip Deselect to Data Retention Time
0
†
§
tR
Operation Recovery Time
tRC
* TA = +25°C
§ tRC = Read Cycle Time
† This Parameter is guaranteed but not tested
DATA RETEꢀTIOꢀ WAVEFORM
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-10
-12
-15
-20
-25
-35
-45
-55
-70
-85
Sym Parameter
Unit
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Read Cycle
Time
tRC
10
12
15
20
25
35
45
55
70
85
ns
85 ns
85 ns
Address Access
Time
tAA
tAC
10
10
12
12
15
15
20
20
25
25
35
35
45
45
55
55
70
70
Chip Enable
Access Time
Output Hold
from Address
Change
tOH
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
ns
ns
Chip Enable to
Output in Low Z
tLZ
Chip Disable
to Output in
High Z
tHZ
5
6
8
10
20
12
25
17
35
20
45
25
55
30
70
35 ns
Chip Enable to
Power Up Time
tPU
tPD
0
0
0
0
0
0
0
0
0
0
ns
Chip Disable to
Power Down
10
12
15
85 ns
Document #SRAM111 REV D
Page 3
P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS
TIMIꢀꢁ WAVEFORM OF READ CYCLE ꢀO. 1(5)
TIMIꢀꢁ WAVEFORM OF READ CYCLE ꢀO. 2(6)
ꢀotes:
5. CE is LOW and WE is HIGH for READ cycle.
6. WE is HIGH, and address must be valid prior to or coincident with CE
transition LOW.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
7. Transition is measured ± 200 mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is sampled
and not 100% tested.
Document # SRAM111 REV D
Page 4
P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-10
-12
-15
-20
-25
-35
-45
-55
-70
-85
Sym Parameter
Unit
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Write Cycle
Time
tWC
10
8
12
10
15
12
20
15
25
20
35
25
45
30
55
35
70
40
85
45
ns
ns
Chip Enable
Time to End of
Write
tCW
Address Valid
to End of Wrtite
tAW
tAS
tWP
8
0
8
10
0
12
0
15
0
20
0
25
0
30
0
35
0
40
0
45
0
ns
ns
ns
Address Set-up
Time
Write Pulse
Width
10
12
15
20
25
30
35
40
40
Address Hold
Time from End
of Write
tAH
0
0
0
0
0
0
0
0
0
0
ns
Data Valid to
End of Write
tDW
tDH
6
0
7
0
10
0
13
0
15
0
20
0
25
0
30
0
35
0
40
0
ns
ns
Data Hold Time
Write Enable
to Output in
High Z
tWZ
6
7
8
12
15
17
20
25
30
35 ns
Output Active
from End of
Write
tOW
0
0
0
0
0
0
0
0
0
0
ns
TIMIꢀꢁ WAVEFORM OF WRITE CYCLE ꢀO. 1 (WE COꢀTROLLED)(9)
ꢀotes:
9. CE and WE must be LOW for WRITE cycle.
10. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state.
11. Write Cycle Time is measured from the last valid address to the first
transition address.
Document #SRAM111 REV D
Page 5
P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS
TIMIꢀꢁ WAVEFORM OF WRITE CYCLE ꢀO. 2 (CE COꢀTROLLED)(10)
AC TEST COꢀDITIOꢀS
Input Pulse Levels
TRUTH TABLE
GND to 3.0V
Mode
Standby
Read
CE
WE
X
Output
High Z
DOUT
Power
Standby
Active
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
3ns
1.5V
H
L
H
1.5V
Write
L
L
High Z
Active
See Figures 1 and 2
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
ꢀote:
Becauseoftheultra-highspeedoftheP4C187/L,caremustbetakenwhen
testing this device; an inadequate setup can cause a normal function-
ing part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the VCC and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
is also required between VCC and ground. To avoid signal reflections,
proper termination must be used; for example, a 50Ω test environment
should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at
the comparator input, and a 116Ω resistor must be used in series with
DOUT to match 166Ω (Thevenin Resistance).
Document # SRAM111 REV D
Page 6
P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS
LCC PIꢀ COꢀFIꢁURATIOꢀS
22-Pin LCC (L3)
28-Pin LCC (L5)
Document # SRAM111 REV D
Page 7
P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS
ORDERIꢀꢁ IꢀFORMATIOꢀ
Document #SRAM111 REV D
Page 8
P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS
SIDEBRAZED DUAL Iꢀ-LIꢀE PACkAꢁE
Pkg #
C3
# Pins
22 (300 mil)
Symbol
Min
Max
A
b
0.100
0.014
0.030
0.008
1.050
0.260
0.200
0.023
0.060
0.015
1.260
0.310
b2
C
D
E
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
Q
0.015
0.005
0.005
0.070
S1
S2
-
-
CERDIP DUAL Iꢀ-LIꢀE PACkAꢁE
Pkg #
D3
# Pins
22 (300 mil)
Symbol
Min
-
Max
A
b
0.225
0.020
0.065
0.012
1.110
0.320
0.015
0.045
0.009
1.060
0.290
b2
C
D
E
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
0.060
-
Q
S1
α
0.015
0.005
0°
15°
Document # SRAM111 REV D
Page 9
P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS
SOJ SMALL OUTLIꢀE IC PACkAꢁE
Pkg #
J4
# Pins
24 (300 mil)
Symbol
Min
Max
0.148
-
A
A1
b
0.128
0.082
0.016
0.007
0.620
0.020
0.010
0.630
C
D
e
0.050 BSC
0.335 BSC
0.292 0.300
0.267 BSC
E
E1
E2
Q
0.025
-
RECTAꢀꢁULAR LEADLESS CHIP CARRIER
Pkg #
# Pins
Symbol
A
L3
22
Min
Max
0.060
0.050
0.022
0.284
0.080
0.068
0.028
0.296
A1
B1
D
D1
D2
D3
E
0.150 BSC
0.075 BSC
-
0.296
0.496
0.484
E1
E2
E3
e
0.300 BSC
0.150 BSC
-
0.496
0.050 BSC
R = .012
R = .012
h
j
L
0.039
0.051
0.051
0.072
L1
0.039
0.058
L2
ND
NE
4
7
Document # SRAM111 REV D
Page 10
P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS
RECTAꢀꢁULAR LEADLESS CHIP CARRIER
Pkg #
# Pins
Symbol
A
L5
28
Min
Max
0.060
0.050
0.022
0.342
0.075
0.065
0.028
0.358
A1
B1
D
D1
D2
D3
E
0.200 BSC
0.100 BSC
-
0.358
0.560
0.540
E1
E2
E3
e
0.400 BSC
0.200 BSC
-
0.558
0.050 BSC
0.040 REF
0.020 REF
h
j
L
0.045
0.055
0.055
0.095
L1
0.045
0.075
L2
ND
NE
5
9
PLASTIC DUAL Iꢀ-LIꢀE PACkAꢁE
Pkg #
P3
# Pins
22 (300 Mil)
Symbol
Min
-
Max
0.210
-
A
A1
b
0.015
0.014
0.045
0.008
1.145
0.240
0.300
0.022
0.070
0.014
1.165
0.280
0.325
b2
C
D
E1
E
e
0.100 BSC
eB
L
-
0.430
0.150
15°
0.115
0°
α
Document # SRAM111 REV D
Page 11
P4C187 / P4C187L - ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS
REVISIOꢀS
DOCUMEꢀT ꢀUMBER SRAM 110
DOCUMEꢀT TITLE
P4C116 / P4C116L ULTRA HIGH SPEED 2K ꢀ 8 STATIC CMOS RAMS
REV ISSUE DATE
ORIꢁIꢀATOR DESCRIPTIOꢀ OF CHAꢀꢁE
OR
A
1997
DAB
JDB
JDB
JDB
JDB
New Data Sheet
Oct-2005
Apr-2007
Oct-2011
Oct-2013
Changed logo to Pyramid
B
Added 55, 70, and 85ns speeds
C
Minor correction on LCC pinout; reformatting
Minor correction to Write Cycle 1 timing diagram
D
Document #SRAM111 REV D
Page 12
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