P4C187-25LC [PYRAMID]
ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS; 超高速64K ×1静态CMOS RAMS
| 型号： | P4C187-25LC |
| 厂家： | 
PYRAMID SEMICONDUCTOR CORPORATION |
| 描述： | ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS |
| 文件： | 总12页 (文件大小：315K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P4C187/P4C187L
ULTRA HIGH SPEED 64K x 1
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
Data Retention with 2.0V Supply (P4C187L
Military)
High Speed (Equal Access and Cycle Times)
–10/12/15/20/25/35/45ns(Commercial)
–12/15/20/25/35/45ns(Industrial)
Separate Data I/O
Three-State Output
–15/20/25/35/45/55/70/85ns(Military)
TTL Compatible Output
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
Low Power Operation
– 743 mW Active -10
– 660/770 mW Active for -12/15
– 550/660 mW Active for -20/25/35
– 193/220 mW Standby (TTL Input)
– 83/110 mW Standby (CMOS Input) P4C187
– 5.5 mW Standby (CMOS Input) P4C187L (Military)
– 22-Pin 300 mil DIP
– 24-Pin 300 mil SOJ
– 22-Pin 290x490 mil LCC
– 28-Pin 350x550 mil LCC
Single 5V±10% Power Supply
DESCRIPTION
consumptiontoalow743mWactive,193/83mWstandby
for TTL/CMOS inputs and only 5.5 mW standby for the
P4C187L.
The P4C187/P4C187L are 65, 536-bit ultra high speed
static RAMs organized as 64K x 1. The CMOS memories
requirenoclocksorrefreshingandhaveequalaccessand
cycle times. The RAMs operate from a single 5V ± 10%
tolerancepowersupply.Dataintegrityismaintainedforsup-
plyvoltagesdownto2.0V, typicallydrawing10µA.
TheP4C187/P4C187Lareavailablein22-pin300milDIP,
24-pin300milSOJ,22-pinand28-pinLCCpackagespro-
vidingexcellentboardleveldensities.
Access times as fast as 10 nanoseconds are available,
greatlyenhancingsystemspeeds.CMOSreducespower
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P3, D3, C3)
SOJ (J4)
LCC Pin configurations at end of datasheet.
Document # SRAM111 REV B
Revised April 2007
1
P4C187/187L
MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
Symbol
Parameter
Value
Unit
TBIAS
Temperature Under
Bias
–55 to +125
°C
VCC
Power Supply Pin with
Respect to GND
–0.5 to +7
V
TSTG
PT
Storage Temperature
Power Dissipation
DC Output Current
–65 to +150
°C
W
Terminal Voltage with
Respect to GND
(up to 7.0V)
–0.5 to
VCC +0.5
VTERM
TA
V
1.0
50
IOUT
mA
Operating Temperature –55 to +125 °C
RECOMMENDED OPERATING
CAPACITANCES(4)
VCC = 5.0V, TA = 25°C, f = 1.0MHz
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Temperature
Symbol
Parameter
Conditions Typ. Unit
VCC
Grade(2)
GND
Military
0V
0V
0V
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
CIN
VIN = 0V
pF
pF
–55°C to +125°C
–40°C to +85°C
0°C to +70°C
Input Capacitance
Output Capacitance
5
7
Industrial
Commercial
COUT
V
OUT = 0V
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2)
P4C187
P4C187L
Symbol
Parameter
Test Conditions
Unit
Min
Max
Min
Max
VIH
VIL
Input High Voltage
2.2
V
CC +0.5
2.2
V
CC +0.5
V
Input Low Voltage
–0.5(3)
0.8
–0.5(3)
0.8
V
V
V
V
V
VHC
VLC
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage
VCC –0.2 VCC +0.5 VCC –0.2 VCC +0.5
–0.5(3)
0.2
–1.2
0.4
–0.5(3)
0.2
–1.2
0.4
VCD
VOL
VCC = Min., IIN = 18 mA
IOL = +8 mA, VCC = Min.
Output Low Voltage
(TTL Load)
VOH
ILI
Output High Voltage
(TTL Load)
IOH = –4 mA, VCC = Min.
2.4
2.4
V
VCC = Max.
Mil.
Com’l.
Mil.
Input Leakage Current
–10
–5
+10
+5
–5
n/a
+5
n/a
µA
VIN = GND to VCC
VCC = Max., CE = VIH,
VOUT = GND to VCC
ILO
Output Leakage Current
–10
–5
+10
+5
–5
n/a
+5
n/a
µA
Com’l.
___
___
___
___
Standby Power Supply
Current (TTL Input Levels)
ISB
CE ≥ VIH
Mil.
Ind./Com’l.
40
35
40
n/a
mA
VCC = Max .,
f = Max., Outputs Open
___
___
___
___
ISB1
Standby Power Supply
Current
(CMOS Input Levels)
20
15
1.0
n/a
mA
CE ≥ VHC
Mil.
Ind./Com’l.
VCC = Max.,
f = 0, Outputs Open
VIN ≤ VLC or VIN ≥ VHC
n/a = Not Applicable
Notes:
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20ns.
4. This parameter is sampled and not 100% tested.
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
Document # SRAM111 REV B
Page 2 of 12
P4C187/187L
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Temperature
Range
Parameter
Symbol
–10 –12 –15 –20 –25 –35 –45 –55 –70 –85 Unit
Commercial
mA
180 170 160 155 150 N/A N/A N/A N/A N/A
Dynamic
Operating
Current*
ICC
N/A 180 170 160 155 150 N/A N/A N/A N/A mA
N/A N/A 170 160 155 150 145 145 145 145 mA
Industrial
Military
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL.
DATA RETENTION CHARACTERISTICS (P4C187L Military Temperature Only)
Typ.*
Max
VCC
2.0V
Symbol
Parameter
Test Conditons
Min
Unit
VCC
2.0V
=
3.0V
=
3.0V
VDR
VCC for Data Retention
Data Retention Current
2.0
V
10
ICCDR
tCDR
15
600
900
µA
ns
CE ≥ VCC –0.2V,
VIN ≥ VCC –0.2V
or VIN ≤ 0.2V
Chip Deselect to
Data Retention Time
0
§
†
tRC
tR
Operation Recovery Time
ns
*TA = +25°C
§tRC = Read Cycle Time
† This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
Document # SRAM111 REV B
Page 3 of 12
P4C187/187L
AC CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-10
-12
-15
-20
-25
-35
-45
-55
-70
-85
Symbol Parameter
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
tRC
tAA
tAC
tOH
tLZ
Read Cycle Time
10
12
15
20
25
35
45
55
70
85
Address Access Time
10
10
12
12
15
15
20
20
25
25
35
35
45
45
55
65
70
70
85
85
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Chip Enable to Power Up Time
Chip Disable to Power Down Time
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
tHZ
tPU
tPD
5
6
8
10
20
12
25
17
35
20
45
25
55
30
70
35
85
0
0
0
0
0
0
0
0
0
0
10
12
15
TIMING WAVEFORM OF READ CYCLE NO. 1(5)
TIMING WAVEFORM OF READ CYCLE NO. 2(6)
Notes:
5. CE is LOW and WE is HIGH for READ cycle.
6. WE is HIGH, and address must be valid prior to or coincident with CE
transition LOW.
7. Transition is measured ±200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is sampled
and not 100% tested.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document # SRAM111 REV B
Page 4 of 12
P4C187/187L
AC CHARACTERISTICS - WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-10
-12
-15
-20
-25
-35
-45
-55
-70
-85
Symbol Parameter
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
tWC
tCW
tAW
tAS
Write Cycle Time
10
8
12
10
10
0
15
12
12
0
20
15
15
0
25
20
20
0
35
25
25
0
45
30
30
0
55
35
35
0
70
40
40
0
85
45
45
0
Chip Enable Time to
End of Write
Address Valid to End
of Write
8
Address Set-up Time
Write Pulse Width
0
tWP
tAH
8
10
0
12
0
15
0
20
0
25
0
30
0
35
0
40
0
45
0
Address Hold Time
from End of Write
Data Valid to End of
Write
0
tDW
tDH
tWZ
tOW
6
7
10
0
13
0
15
0
20
0
25
0
30
0
35
0
40
0
Data Hold Time
0
0
Write Enable to
Output in High Z
Output Active from
End of Write
6
7
8
12
15
17
20
25
30
35
0
0
0
0
0
0
0
0
0
0
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(9)
Notes:
9. CE and WE must be LOW for WRITE cycle.
10. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state.
11. Write Cycle Time is measured from the last valid address to the first
transition address.
Document # SRAM111 REV B
Page 5 of 12
P4C187/187L
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(9)
AC TEST CONDITIONS
TRUTH TABLE
Mode
Standby
Read
CE
H
L
WE
X
Output
High Z
DOUT
Power
Standby
Active
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
3ns
1.5V
H
Write
L
L
High Z
Active
1.5V
See Figures 1 and 2
Figure 2. Thevenin Equivalent
Figure 1. Output Load
* including scope and test fixture.
Note:
proper termination must be used; for example, a 50Ω test environment
should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at
the comparator input, and a 116Ω resistor must be used in series with
DOUT to match 166Ω (Thevenin Resistance).
Due to the ultra-high speed of the P4C187/L, care must be taken when
testing this device; an inadequate setup can cause a normal functioning
part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the VCC and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
is also required between VCC and ground. To avoid signal reflections,
Document # SRAM111 REV B
Page 6 of 12
P4C187/187L
LCC PIN CONFIGURATIONS
22-PIN LCC (L3)
28-PIN LCC (L5)
Document # SRAM111 REV B
Page 7 of 12
P4C187/187L
ORDERING INFORMATION
SELECTION GUIDE
The P4C187 is available in the following temperature, speed and package options. The P4C187L is only available over
the military temperature range.
Speed (ns)
Temperature
Range
Package
Plastic DIP
10
-10PC
-10JC
N/A
12
-12PC
-12JC
-12PI
-12JI
N/A
15
20
25
35
45
55
N/A
70
N/A
85
N/A
Commercial
-15PC
-15JC
-20PC
-20JC
-25PC
-25JC
-35PC
-35JC
-45PC
-45JC
Plastic SOJ
Plastic DIP
N/A
N/A
N/A
Industrial
-15PI
-20PI
-25PI
-35PI
-45PI
N/A
N/A
N/A
Plastic SOJ
Side Brazed DIP
CERDIP
N/A
-15JI
-20JI
-25JI
-35JI
-45JI
N/A
N/A
N/A
Military
Temperature
N/A
-15CM
-15DM
-15L28M
-15LM
-15CMB
-15DMB
-20CM
-20DM
-20L28M
-20LM
-20CMB
-20DMB
-25CM
-25DM
-25L28M
-25LM
-25CMB
-25DMB
-35CM
-35DM
-35L28M
-35LM
-35CMB
-35DMB
-45CM
-45DM
-45L28M
-45LM
-45CMB
-45DMB
-55CM
-55DM
-55L28M
-55LM
-55CMB
-55DMB
-70CM
-70DM
-70L28M
-70LM
-70CMB
-70DMB
-85CM
-85DM
-85L28M
-85LM
-85CMB
-85DMB
N/A
N/A
LCC (28 Pin)
LCC (22 Pin)
Side Brazed DIP
CERDIP
N/A
N/A
N/A
N/A
Military
Processed*
N/A
N/A
N/A
N/A
LCC (28 Pin)
LCC (22 Pin)
N/A
N/A
-15L28MB -20L28MB -25L28MB -35L28MB -45L28MB -55L28MB -70L28MB -85L28MB
-15LMB -20LMB -25LMB -35LMB -45LMB -55LMB -70LMB -85LMB
N/A
N/A
* Military temperature range with MIL-STD-883, Class B processing.
N/A = Not Available
Document # SRAM111 REV B
Page 8 of 12
P4C187/187L
SIDE BRAZED DUAL IN-LINE PACKAGES
Pkg #
C3
# Pins
22 (300 mil)
Symbol
Min
Max
A
b
b2
C
D
E
0.100
0.014
0.030
0.008
1.050
0.260
0.200
0.023
0.060
0.015
1.260
0.310
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
Q
S1
S2
0.015
0.005
0.005
0.070
-
-
CERDIP DUAL IN-LINE PACKAGE
Pkg #
D3
# Pins
22 (300 mil)
Symbol
Min
-
Max
A
b
b2
C
D
E
0.225
0.020
0.065
0.012
1.110
0.320
0.015
0.045
0.009
1.060
0.290
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
0.060
-
Q
S1
α
0.015
0.005
0°
15°
Document # SRAM111 REV B
Page 9 of 12
P4C187/187L
SOJ SMALL OUTLINE IC PACKAGE
Pkg #
J4
# Pins
24 (300 mil)
Symbol
Min
Max
0.148
-
0.020
0.010
0.630
A
A1
b
C
D
0.128
0.082
0.016
0.007
0.620
e
E
E1
E2
Q
0.050 BSC
0.335 BSC
0.292 0.300
0.267 BSC
0.025
-
RECTANGULAR LEADLESS CHIP CARRIER
Pkg #
# Pins
Symbol
A
L3
22
Min
Max
0.060
0.050
0.022
0.284
0.080
0.068
0.028
0.296
A1
B1
D
D1
D2
D3
E
0.150 BSC
0.075 BSC
-
0.296
0.496
0.484
E1
E2
E3
e
h
j
0.300 BSC
0.150 BSC
-
0.496
0.050 BSC
R = .012
R = .012
L
L1
L1
0.039
0.039
0.058
0.051
0.051
0.072
ND
NE
4
7
Document # SRAM111 REV B
Page 10 of 12
P4C187/187L
RECTANGULAR LEADLESS CHIP CARRIER
Pkg #
# Pins
Symbol
A
L5
28
Min
Max
0.060
0.050
0.022
0.342
0.075
0.065
0.028
0.358
A1
B1
D
D1
D2
D3
E
0.200 BSC
0.100 BSC
-
0.358
0.560
0.540
E1
E2
E3
e
h
j
0.400 BSC
0.200 BSC
-
0.558
0.050 BSC
0.040 REF
0.020 REF
L
L1
L2
0.045
0.045
0.075
0.055
0.055
0.095
ND
NE
5
9
PLASTIC DUAL IN-LINE PACKAGE
Pkg #
P3
# Pins
22 (300 Mil)
Symbol
Min
-
Max
0.210
-
0.022
0.070
0.014
1.165
0.280
0.325
A
A1
b
b2
C
D
E1
E
0.015
0.014
0.045
0.008
1.145
0.240
0.300
e
0.100 BSC
eB
L
α
-
0.430
0.150
15°
0.115
0°
Document # SRAM111 REV B
Page 11 of 12
P4C187/187L
REVISIONS
DOCUMENTNUMBER:
DOCUMENTTITLE:
SRAM111
P4C187 / P4C187L ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS
ORIG. OF
CHANGE
ISSUE
DATE
REV.
DESCRIPTIONOFCHANGE
OR
A
1997
Oct-05
Apr-07
DAB
NewDataSheet
JDB
JDB
Change logo to Pyramid
B
Added 55, 70, and 85 ns speeds
Document # SRAM111 REV B
Page 12 of 12
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