P4C168-20LMB [PYRAMID]
Standard SRAM, 4KX4, 20ns, CMOS, CQCC20, 0.290 X 0.430 INCH, CERAMIC, LCC-20;
| 型号： | P4C168-20LMB |
| 厂家： | 
PYRAMID SEMICONDUCTOR CORPORATION |
| 描述： | Standard SRAM, 4KX4, 20ns, CMOS, CQCC20, 0.290 X 0.430 INCH, CERAMIC, LCC-20 静态存储器 |
| 文件： | 总14页 (文件大小：628K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P4C168/P4C168L , P4C169, P4C170
ULTRA HIGH SPEED 4K x 4
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
Three Options
– P4C168 Low Power Standby Mode
– P4C169 Fast Chip Select Control
– P4C170 Fast Chip Select, Output Enable
Controls
High Speed (Equal Access and Cycle Times)
– 12/15/20/25/35ns (Commercial)
– 20/25/35/45/55/70ns (P4C168 Military)
Low Power Operation (Commercial)
– 715 mW Active
– 193 mW Standby (TTL Input) P4C168
– 83 mW Standby (CMOS Input) P4C168
Standard Pinout (JEDEC Approved)
– P4C168: 20-pin DIP, SOJ, LCC, SOIC,
CERPACK, and Flat Pack
– P4C169: 20-pin DIP and SOIC
– P4C170: 22-pin DIP
Single 5V±10% Power Supply
Fully TTL Compatible, Common I/O Ports
DESCRIPTION
The P4C168, P4C169 and P4C170 are a family of
16,384-bit ultra high-speed static RAMs organized as
4K x 4. All three devices have common input/output
ports.The P4C168 enters the standby mode when the
chip enable (CE) control goes HIGH; with CMOS input
levels, power consumption is only 83mW in this mode.
Both the P4C169 and the P4C170 offer a fast chip select
access time that is only 67% of the address access time.
In addition, the P4C170 includes an output enable (OE)
controltoeliminatedatabuscontention.TheRAMsoper-
ate from a single 5V ± 10% tolerance power supply.
Access times as fast as 12 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption to a low
715 mW active, 193 mW standby.
TheP4C168andP4C169areavailablein20-pin(P4C170
in 22-pin) 300 mil DIP packages providing excellent
board level densities. The P4C168 is also available in
20-pin 300 mil SOIC, SOJ, CERPACK, and Flat Pack
packages.
The P4C169 is also available in a 20-pin 300 mil SOIC
package.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
P4C170
DIP (P3)
P4C168
DIP (P2, C6, D2)
SOIC (S2)
P4C169
DIP (P2)
SOIC (S2)
SOJ (J2)
CERPACK (F2)
SOLDER SEAL FLAT PACK (FS-2)
Document # SRAM107 REV E
Revised March 2010
1
P4C168/P4C168L, P4C169, P4C170
MAꢀIMUM RATINGS(1)
Symbol Parameter
Value
Unit
Symbol Parameter
Value
Unit
VCC
Power Supply Pin with -0.5 to +7
Respect to GND
V
TBIAS
Temperature Under
Bias
Storage Temperature -65 to +150 °C
-55 to +125 °C
VTERM
Terminal Voltage with
respect to GND (up to
7.0V)
-0.5 to VCC
+ 0.5
V
TSTG
PT
Power Dissipation
DC Output Current
1.0
50
W
TA
Operating Temperature -55 to +125
°C
IOUT
mA
CAPACITANCES(2)
RECOMMENDED OPERATING CONDITIONS
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
Grade(2)
Commercial 0°C to 70°C
Military -55°C to +125°C 0V
Ambient Temp
Gnd VCC
0V 5.0V ± 10%
5.0V ± 10%
Sym Parameter
CIN Input Capacitance
COUT Output Capacitance VOUT=0V
Conditions Typ. Unit
VIN=0V
5
pF
7
pF
DC ELECTRICAL CHARACTERISTICS
P4C168/169/170
P4C168L
Sym Parameter
Test Conditions
Unit
Min
Max
Min
Max
VIH
VIL
VOL
VOH
ILI
Input High Voltage
2.2
VCC+0.5
2.2
VCC+0.5
V
V
V
V
-0.5(3)
0.8
0.4
-0.5(3)
0.8
0.4
Input Low Voltage
Output Low Voltage (TTL Load)
Output High Voltage (TTL Load)
IOL=+8 mA, VCC=Min
IOH=-4 mA, VCC=Min
2.4
2.4
Input Leakage Current (Military)
Input Leakage Current (Commercial)
Output Leakage Current (Military)
-10
-5
+10
+5
-5
-2
-5
+5
+2
+5
VCC=Max, VIN=GND to VCC
µA
ILO
ICC
ISB
-10
+10
VCC=Max, CS=VIH, VOUT=GND to
VCC
µA
Output Leakage Current (Commer-
cial)
-5
—
—
+5
-2
—
—
+2
Dynamic Operating Current (Military)
120
100
120
100
mA
VCC=Max,f=Max, Outputs Open
Dynamic Operating Current (Com-
mercial)
Standby Power Supply Current (TTL
Input Levels) (Military)
—
—
—
—
40
35
20
15
—
—
—
—
40
35
1
CE1≥VIH,VCC=Max,f=Max,Outputs
Open
mA
mA
Standby Power Supply Current (TTL
Input Levels) (Commercial)
ISB1
Standby Power Supply Current
(CMOS Input Levels) (Military)
CE1≥VHC,VCC=Max,f=0,Outputs
Open,VIN≤VLC or VIN≥VHC
Standby Power Supply Current
(CMOS Input Levels) (Commercial)
0.2
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only 2. This parameter is sampled and not 100% tested.
and functional operation of the device at these or any other conditions 3. Transient inputs with VIL and IIL not more negative than -3.0V and -100mA,
periods may affect reliability..
above those indicated in the operational sections of this specification
respectively, are permissible for pulse widths up to 20 ns.
is not implied. Exposure to MAXIMUM rating conditions for extended
Document # SRAM107 REV E
Page 2 of 14
P4C168/P4C168L, P4C169, P4C170
DATA RETENTION CHARACTERISTICS (P4C168L ONLY)
Typ. *
VCC
Max
VCC
=
=
Sym
Parameter
Test Condition
Min
2.0V 3.0V 2.0V 3.0V Unit
VDR
VCC for Data Retention
2.0
V
Data Retention Current (Military)
Data Retention Current (Commercial)
Chip Deselect to Data Retention Time
Operation Recovery Time
2
3
200
20
300
30
µA
µA
ns
ns
ICCDR
CE ≥ VCC - 0.2V,
VIN ≥ VCC - 0.2V,
or VIN ≤ 0.2V
0.5
1.0
tCDR
0
†
§
tR
tRC
DATA RETENTION WAVEFORM
AC CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(4)
-12
-15
-20
-25
-35
Sym Parameter
Unit
Min Max Min Max Min Max Min Max Min Max
Read Cycle Time
tRC
tAA
12
15
20
25
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
12
12
8
15
15
9
20
20
12
25
25
15
35
35
20
§
Chip Enable Access Time
tAC
‡
Chip Select Access Time
tAC
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Output Enable to Data Valid
Output Enable to Output in Low Z
Output Disable to Output in High Z
Read Command Setup Time
Read Command Hold Time
Chip Enable to Power Up Time
Chip Disable to Power Down Time
tOH
2
2
2
2
2
2
2
2
2
2
‡
tLZ
†
tHZ
7
8
8
9
10
15
15
15
†
tOE
10
12
†
tOLZ
0
0
0
0
0
†
tOHZ
tRCS
tRCH
6
7
9
11
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
§
tPU
§
tPD
12
15
20
25
35
Notes:
4. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
Document # SRAM107 REV E
Page 3 of 14
P4C168/P4C168L, P4C169, P4C170
AC CHARACTERISTICS—READ CYCLE (CONTINUED)
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-45
-55
-70
Sym Parameter
Unit
Min Max Min Max Min Max
Read Cycle Time
tRC
tAA
45
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
45
45
25
55
55
30
70
70
35
§
Chip Enable Access Time
tAC
‡
Chip Select Access Time
tAC
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Output Enable to Data Valid
Output Enable to Output in Low Z
Output Disable to Output in High Z
Read Command Setup Time
Read Command Hold Time
Chip Enable to Power Up Time
Chip Disable to Power Down Time
tOH
2
2
2
2
2
2
‡
tLZ
†
tHZ
25
20
25
25
30
30
†
tOE
†
tOLZ
0
0
0
†
tOHZ
tRCS
tRCH
20
25
30
0
0
0
0
0
0
0
0
0
§
tPU
§
tPD
45
55
70
§ P4C168 only
† P4C170 only
‡ Chip Select/Deselect for P4C169 and P4C170
TIMING WAVEFORM OF READ CYCLE NO. 1 (ADDRESS CONTROLLED)(5,6)
Notes:
5. WE is HIGH for READ cycle.
6. CE/CS and OE are LOW for READ cycle.
Document # SRAM107 REV E
Page 4 of 14
P4C168/P4C168L, P4C169, P4C170
TIMING WAVEFORM OF READ CYCLE NO. 2 (CE/CS CONTROLLED)(5,7)
TIMING WAVEFORM OF READ CYCLE NO. 3—P4C170 ONLY (OE CONTROLLED)(5)
Notes:
7. ADDRESS must be valid prior to, or coincident with CE/CS transition
low. For Fast CS, tAA must still be met.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
8. Transition is measured ±200mV from steady state voltage prior to
change, with loading as specified in Figure 1.
Document # SRAM107 REV E
Page 5 of 14
P4C168/P4C168L, P4C169, P4C170
AC ELECTRICAL CHARACTERISTICS - WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-12
-15
-20
-25
-35
Sym Parameter
Unit
Min Max Min Max Min Max Min Max Min Max
tWC
tCW
tAW
tAS
Write Cycle Time
12
12
12
0
15
15
15
0
18
18
18
0
20
20
20
0
30
30
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable Time to End of Write
Address Valid to End of Write
Address Setup Time
tWP
tAH
tDW
tDH
tWZ
tOW
Write Pulse Width
12
0
15
0
18
0
20
0
30
0
Address Hold Time
Data Valid to End of Write
Data Hold Time
7
8
10
0
10
0
15
0
0
0
Write Enable to Output in High Z
Output Active from End of Write
4
5
6
7
13
0
0
0
0
0
AC ELECTRICAL CHARACTERISTICS - WRITE CYCLE (CONTINUED)
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-45
-55
-70
Sym Parameter
Unit
Min Max Min Max Min Max
tWC
tCW
tAW
tAS
Write Cycle Time
45
40
40
0
55
50
50
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable Time to End of Write
Address Valid to End of Write
Address Setup Time
tWP
tAH
tDW
tDH
tWZ
tOW
Write Pulse Width
40
0
50
0
60
0
Address Hold Time
Data Valid to End of Write
Data Hold Time
20
3
20
3
25
3
Write Enable to Output in High Z
Output Active from End of Write
20
25
30
0
0
0
Document # SRAM107 REV E
Page 6 of 14
P4C168/P4C168L, P4C169, P4C170
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(10)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE/CS CONTROLLED)(10)
TRUTH TABLES
P4C168 (P4C169)
P4C170
Mode
Mode
CE (CS)
WE
Output
CE
WE
OE
Output
Standby (Deselect)
H
X
High Z
Deselect
H
X
X
High Z
Read
Write
L
L
H
L
DOUT
Read
L
L
L
H
H
L
L
H
X
DOUT
High Z
Output Inhibit
Write
High Z
High Z
Notes:
12. Write Cycle Time is measured from the last valid address to the first
10. CE/CS and WE must be LOW for WRITE cycle.
11. If CE/CS goes HIGH simultaneously with WE HIGH, the output
transitioning address.
remains in a high impedance state.
Document # SRAM107 REV E
Page 7 of 14
P4C168/P4C168L, P4C169, P4C170
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
3ns
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
1.5V
1.5V
Output Load
See Figures 1 and 2
Figure 2. Thevenin Equivalent
Figure 1. Output Load
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C168, P4C169AND P4C170
care must be taken when testing these devices; an inadequate setup
can cause a normal functioning part to be rejected as faulty. Long
high-inductance leads that cause supply bounce must be avoided by
bringing the VCC and ground planes directly up to the contactor fingers.
A high frequency capacitor of 0.01 µF is also required between VCC
and ground. To avoid signal reflections, proper termination must be
used; for example, a 50Ω test environment should be terminated into
a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input,
and a 116Ω resistor must be used in series with DOUT to match 166Ω
(Thevenin Resistance).
LCC PIN CONFIGURATION
LCC (L9)
Document # SRAM107 REV E
Page 8 of 14
P4C168/P4C168L, P4C169, P4C170
ORDERING INFORMATION
SELECTION GUIDE
The P4C168/P4C168L, P4C169 and P4C170 are available in the following temperature, speed and package options.
Temperature Package
Range
Speed
12
-12PC
-12SC
-12JC
N/A
15
20
25
35
45
55
70
Commercial
Temperature
Plastic DIP
-15PC
-15SC
-15JC
-20PC
-20SC
-20JC
-25PC
-25SC
N/A
N/A
N/A
N/A
Plastic SOIC†
Plastic SOJ††
LCC
N/A
N/A
N/A
N/A
-25JC
N/A
N/A
N/A
N/A
Military Tem-
perature
(P4C168
Only)
-15LM
-15DM
-15CM
-15FM
-15FSM
-15LMB
-15DMB
-15CMB
-15FMB
-20LM
-20DM
-20CM
-20FM
-20FSM
-20LMB
-20DMB
-20CMB
-20FMB
-25LM
-35LM
-35DM
-35CM
-35FM
-35FSM
-35LMB
-35DMB
-35CMB
-35FMB
-45LM
-45DM
-45CM
-45FM
-45FM
-45LMB
-45DMB
-45CMB
-45FMB
-55LM
-55DM
-55CM
-55FM
-55FM
-55LMB
-55DMB
-55CMB
-55FMB
-70LM
-70DM
-70CM
-70FM
-70FM
-70LMB
-70DMB
-70CMB
-70FMB
CERDIP
N/A
-25DM
-25CM
-25FM
Side Brazed DIP
CERPACK
N/A
N/A
Solder Seal Flat Pack
LCC
N/A
-25FSM
-25LMB
-25DMB
-25CMB
-25FMB
Military Pro-
cessed*
(P4C168
Only)
N/A
CERDIP
N/A
Side Brazed DIP
CERPACK
N/A
N/A
Solder Seal Flat Pack
N/A
-15FSMB -20FSMB -25FSMB -35FSMB -45FSMB -55FSMB -70FSMB
† P4C168 and P4C169 only.
†† P4C168
* Military temperature range with MIL-STD-883, Class B processing.
N/A = Not available
Document # SRAM107 REV E
Page 9 of 14
P4C168/P4C168L, P4C169, P4C170
SOLDER SEAL FLAT PACKAGE
Pkg #
FS-2
# Pins
20
Symbol
Min
Max
0.115
0.022
0.019
0.009
0.006
0.540
0.300
0.330
-
A
b
0.045
0.015
0.015
0.004
0.004
-
b1
c
c1
D
E
0.245
-
E1
E2
E3
e
0.130
0.030
-
0.050 BSC
k
0.008
0.250
0.026
0.000
-
0.015
0.370
0.045
-
L
Q
S1
M
N
0.002
20
SOJ SMALL OUTLINE IC PACKAGE
Pkg #
J2
# Pins
20 (300 mil)
Symbol
Min
Max
0.140
-
A
A1
b
0.120
0.080
0.014
0.008
0.496
0.020
0.013
0.512
C
D
e
0.050 BSC
E
0.335
0.292
0.347
0.300
E1
E2
Q
0.267 BSC
0.025
-
Document # SRAM107 REV E
Page 10 of 14
P4C168/P4C168L, P4C169, P4C170
RECTANGULAR LEADLESS CHIP CARRIER
Pkg #
# Pins
Symbol
A
L9
20
Min
Max
0.060
0.050
0.022
0.280
0.075
0.066
0.028
0.305
A1
B1
D
D1
D2
D3
E
0.150 BSC
0.075 BSC
-
0.305
0.440
0.420
E1
E2
E3
e
0.250 BSC
0.125 BSC
-
0.440
0.050 BSC
0.020 REF
0.010 REF
h
j
L
0.045
0.055
0.055
0.098
L1
0.045
0.075
L2
ND
NE
4
6
PLASTIC DUAL IN-LINE PACKAGE (P4C168, P4C169)
Pkg #
P2
# Pins
20 (300 mil)
Symbol
Min
-
Max
0.210
-
A
A1
b
0.015
0.014
0.045
0.008
0.980
0.240
0.300
0.022
0.070
0.014
1.060
0.280
0.325
b2
C
D
E1
E
e
0.100 BSC
eB
L
-
0.430
0.150
15°
0.115
0°
α
Document # SRAM107 REV E
Page 11 of 14
P4C168/P4C168L, P4C169, P4C170
PLASTIC DUAL IN-LINE PACKAGE (P4C170)
Pkg #
P3
# Pins
22 (300 Mil)
Symbol
Min
-
Max
0.210
-
A
A1
b
0.015
0.014
0.045
0.008
1.145
0.240
0.300
0.022
0.070
0.014
1.165
0.280
0.325
b2
C
D
E1
E
e
0.100 BSC
eB
L
-
0.430
0.150
15°
0.115
0°
α
SOIC/SOP SMALL OUTLINE IC PACKAGE
Pkg #
S2
# Pins
20 (300 mil)
Symbol
Min
Max
0.104
0.012
0.020
0.012
0.511
A
A1
b2
C
D
e
0.093
0.004
0.013
0.009
0.496
0.050 BSC
E
0.291
0.394
0.010
0.016
0°
0.299
0.419
0.029
0.050
8°
H
h
L
α
Document # SRAM107 REV E
Page 12 of 14
P4C168/P4C168L, P4C169, P4C170
CERDIP DUAL IN-LINE PACKAGE
Pkg #
D2
# Pins
20 (300 mil)
Symbol
Min
-
Max
0.200
0.026
0.065
0.018
1.060
0.310
A
b
0.014
0.045
0.008
-
b2
C
D
E
0.220
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
0.070
-
Q
S1
α
0.015
0.005
0°
15°
SIDEBRAZED DUAL IN-LINE PACKAGE
Pkg #
C6
# Pins
20 (300 mil)
Symbol
Min
-
Max
A
b
0.200
0.026
0.065
0.018
1.060
0.310
0.014
0.045
0.008
-
b2
C
D
E
0.220
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
Q
0.015
0.005
0.005
0.070
S1
S2
-
-
Document # SRAM107 REV E
Page 13 of 14
P4C168/P4C168L, P4C169, P4C170
REVISIONS
DOCUMENT NUMBER SRAM 107
DOCUMENT TITLE
P4C168, P4C169, P4C170 ULTRA HIGH SPEED 4K x 4 STATIC CMOS RAMS
REV ISSUE DATE
ORIGINATOR DESCRIPTION OF CHANGE
OR
A
1997
DAB
JDB
JDB
JDB
JDB
JDB
New Data Sheet
Oct-05
May-08
Jun-08
Mar-09
Mar-10
Change logo to Pyramid
B
Added P4C168L, updated document formatting
Corrected Order Info drawing
Added C6 package drawing
C
D
E
Updated DC Electrical Characteristics table
Document # SRAM107 REV E
Page 14 of 14
相关型号：
P4C168-25CMB
Standard SRAM, 4KX4, 25ns, CMOS, CDIP20, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-20
PYRAMID
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