P4C147-15LSMB [PYRAMID]
ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM; 超高速4K ×1静态CMOS RAM
| 型号： | P4C147-15LSMB |
| 厂家： | 
PYRAMID SEMICONDUCTOR CORPORATION |
| 描述： | ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM |
| 文件： | 总10页 (文件大小：189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P4C147
ULTRA HIGH SPEED 4K x 1
STATIC CMOS RAM
FEATURES
Full CMOS, 6T Cell
Single 5V ± 10% Power Supply
Separate Input and Output Ports
Three-State Outputs
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25 ns (Commercial)
– 15/20/25/35 ns (Military)
Fully TTL Compatible Inputs and Outputs
Low Power Operation
– 715 mW Active
– 550 mW Active
–10 (Commercial)
–25 (Commercial)
Standard Pinout (JEDEC Approved)
– 18 Pin 300 mil DIP
– 110 mW Standby (TTL Input)
– 55 mW Standby (CMOS Input)
– 18 Pin CERPACK
– 18 Pin LCC (290 x 430 mils)
– 18 Pin LCC (295 x 335 mils)
DESCRIPTION
CMOS is utilized to reduce power consumption in both
active and standby modes. In addition to very high
performance, this device features latch-up protection
and single-event-upset protection.
The P4C147 is a 4,096-bit ultra high speed static RAM
organized as 4K x 1. The CMOS memory requires no
clocks or refreshing, and have equal access and cycle
times. InputsarefullyTTL-compatible. TheRAMoperates
from a single 5V ± 10% tolerance power supply.
Access times as fast as 10 nanoseconds are available,
permitting greatly enhanced system operating speeds.
The P4C147 is available in 18 pin 300 mil DIP packages,
an 18-pin CERPACK package, and 2 different LCC
packages.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P1, D1, C9),
LCC (L7, L7-1)
CERPACK (F1) SIMILAR
Document # SRAM103 REV A
Revised October 2005
1
P4C147
MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
Symbol
Parameter
Value
Unit
TBIAS
Temperature Under
Bias
–55 to +125 °C
VCC
Power Supply Pin with
Respect to GND
–0.5 to +7
V
TSTG
PT
IOUT
Storage Temperature
Power Dissipation
DC Output Current
–65 to +150 °C
Terminal Voltage with
Respect to GND
(up to 7.0V)
–0.5 to
VTERM
TA
VCC +0.5
V
1.0
50
W
mA
Operating Temperature –55 to +125 °C
RECOMMENDED OPERATING
CONDITIONS
CAPACITANCES(4)
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
Grade(2)
Commercial
Military
Ambient Temp
Gnd
VCC
Symbol
CIN
Parameter
Input Capacitance VIN = 0V
Conditions Typ. Unit
5
pF
0°C to 70°C
0V 5.0V ± 10%
0V 5.0V ± 10%
-55°C to +125°C
COUT
Output Capacitance VOUT= 0V
7
pF
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage (2)
P4C147
Unit
Symbol
Test Conditions
IOH = –4 mA, VCC = Min.
Parameter
Max.
Min.
VOH
Output High Voltage
(TTL Load)
2.4
V
VOL
Output Low Voltage
(TTL Load)
IOL = +8 mA, VCC = Min
0.4
V
VIH
VIL
Input High Voltage
Input Low Voltage
2.2
V
CC =+0.5
V
V
–0.5(3)
0.8
–10
–5
+10
+5
Mil.
ILI
Input Leakage Current
Output Leakage Current
VCC = Max., VIN = GND to VCC
µA
Comm’l
VCC = Max., CE = VIH,
Mil.
–10
–5
+10
+5
ILO
µA
VOUT = GND to VCC
Comm’l
__
Standby Power Supply
mA
CE ≥ VIH, VCC = Max.,
Mil.
30
23
ISB
__
Current (TTL Input Levels)
f=Max., Output Open
Comm’l
__
__
ISB1
Standby Power Supply
Current
CE ≥ V , VCC = Max., f= 0,
OutputHOC pen
Mil.
15
10
mA
Comm’l
(CMOS Input Levels)
VIN ≤ 0.2V or VIN ≥ VCC -0.2V
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Temperature
Symbol
Parameter
Unit
Range
-10
-12
-15
-20
-25
-35
Commercial
130 130 120
115
100
N/A
mA
mA
ICC
Dynamic Operating Current
Military
N/A N/A 145
135
125
120
Document # SRAM103 REV A
Page 2 of 10
P4C147
AC CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-12
-20
-25
-35
-10
Min Max
-15
Sym.
Parameter
Unit
Max
Max
Max
Max Max
Min
Min
Min
Min
Min
tRC
tAA
tAC
Read Cycle Time
10
10
10
12
15
20
25
35
ns
ns
ns
12
12
15
15
20
20
25
25
35
35
Address Access Time
Chip Enable Access Time
Output Hold from
2
2
tOH
tLZ
tHZ
tPU
2
2
4
0
2
2
2
2
2
2
2
2
ns
ns
ns
ns
Address Change
Chip Enable to
Output in Low Z
Chip Disable to
5
6
8
10
25
14
35
Output in High Z
Chip Enable to
Power Up Time
0
0
0
0
0
Chip Disable to
tPD
10
12
15
20
ns
Power Down Time
TIMING WAVEFORM OF READ CYCLE NO. 1(5)
TIMING WAVEFORM OF READ CYCLE NO. 2
(6)
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
4. This parameter is sampled and not 100% tested.
5. CE is LOW and WE is HIGH for READ cycle.
6. WE is HIGH, and address must be valid prior to or coincident with CE
transition LOW.
7. Transition is measured ±200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is sampled
and not 100% tested.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20ns.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document # SRAM103 REV A
Page 3 of 10
P4C147
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-10
-25
-12
-15
-20
-35
Unit
Sym.
Parameter
Min Max Min Max Min Max Min Max Min Max Min Max
tWC Write Cycle Time
10
12
15
20
25
20
20
0
35
ns
tCW Chip Enable Time to End of Write
tAW Address Valid to End of Write
tAS Address Set-up Time
8
8
0
8
10
10
0
12
12
0
15
15
0
25
25
0
ns
ns
ns
ns
tWP Write Pulse Width
10
12
14
15
18
Address Hold Time from
tAH
0
0
0
0
0
ns
0
End of Write
tDW Data Valid to End of Write
tDH Data Hold Time
5
0
6
0
7
0
9
0
12
0
15
0
ns
ns
ns
ns
Write Enable to Output in High Z
Output Active from End of Write
6
15
tWZ
tOW
5
7
9
12
0
0
0
0
0
0
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(9)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(9)
Notes:
11. Write Cycle Time is measured from the last valid address to the first
transition address.
9. CE and WE must be LOW for WRITE cycle.
10. If CE goes HIGH simultaneously with WE high, the output remains
in a high impedance state.
Document # SRAM103 REV A
Page 4 of 10
P4C147
AC TEST CONDITIONS
TRUTH TABLE
Mode
Standby
Read
CE
H
L
WE
X
H
Output
High Z
DOUT
Power
Standby
Active
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
3ns
1.5V
1.5V
Write
L
L
High Z
Active
See Figures 1 and 2
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
is also required between VCC and ground. To avoid signal reflections,
proper termination must be used; for example, a 50Ω test environment
should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at
the comparator input, and a 116Ω resistor must be used in series with
DOUT to match 166Ω (Thevenin Resistance).
Due to the ultra-high speed of the P4C147, care must be taken when
testing this device; an inadequate setup can cause a normal functioning
part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the VCC and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
Document # SRAM103 REV A
Page 5 of 10
P4C147
ORDERING INFORMATION
SELECTION GUIDE
The P4C147 is available in the following temperature, speed and package options.
Speed (ns)
Temperature
Range
Package
10
12
15
20
25
35
Commercial
Temperature
Plastic DIP
-10PC
-12PC
-15PC
-20PC
-25PC
N/A
CERDIP
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
-15DM
-15CM
-15LM
-15LSM
-15FM
-15DMB
-15CMB
-15LMB
-15LSMB
-15FMB
-20DM
-20CM
-20LM
-20LSM
-20FM
-20DMB
-20CMB
-20LMB
-20LSMB
-20FMB
-25DM
-25CM
-25LM
-25LSM
-25FM
-25DMB
-25CMB
-25LMB
-25LSMB
-25FMB
-35DM
-35CM
-35LM
-35LSM
-35FM
-35DMB
-35CMB
-35LMB
-35LSMB
-35FMB
Side Brazed DIP
LCC (290 x 430 mil)
LCC (295 x 335 mil)
CERPACK
Military
Temperature
CERDIP
Side Brazed DIP
LCC (290 x 430 mil)
LCC (295 x 335 mil)
CERPACK
Military
Processed*
* Military temperature range with MIL-STD-883, Class B processing.
N/A = Not Available
Document # SRAM103 REV A
Page 6 of 10
P4C147
SIDE BRAZED DUAL IN-LINE PACKAGE
Pkg #
C9
# Pins
18 (300 Mil)
Symbol
Min
-
Max
A
b
0.200
0.026
0.065
0.018
0.960
0.320
0.014
0.030
0.008
-
b2
C
D
E
0.220
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
Q
S1
S2
0.015
0.005
0.005
0.070
-
-
CERDIP DUAL IN-LINE PACKAGE
Pkg #
D1
# Pins
18 (300 Mil)
Symbol
Min
-
Max
A
b
0.200
0.026
0.065
0.018
0.960
0.310
0.014
0.045
0.008
-
b2
C
D
E
0.220
eA
e
0.300 BSC
0.100 BSC
L
0.125
0.200
0.070
-
Q
S1
α
0.015
0.005
0°
15°
Document # SRAM103 REV A
Page 7 of 10
P4C147
CERPACK CERAMIC FLAT PACKAGES
Pkg #
F1
# Pins
18
Symbol
Min
0.045
0.015
0.004
-
Max
A
0.092
0.022
0.009
0.540
0.370
b
c
D
E
e
0.245
0.050 BSC
k
L
Q
S
S1
0.005
0.018
0.370
0.045
0.085
-
0.250
0.026
-
0.005
RECTANGULAR LEADLESS CHIP CARRIER
Pkg #
# Pins
Symbol
A
L7
18
Min
Max
0.060
0.050
0.022
0.280
0.075
0.065
0.028
0.305
A1
B1
D
D1
D2
D3
E
.150 BSC
.075 BSC
-
0.305
0.440
0.417
E1
E2
E3
e
0.200 BSC
0.100 BSC
-
0.440
0.050 BSC
0.040 REF
0.020 REF
h
j
L
0.045
0.075
0.075
0.055
0.090
0.148
L1
L2
ND
NE
4
5
Document # SRAM103 REV A
Page 8 of 10
P4C147
RECTANGULAR LEADLESS CHIP CARRIER
Pkg #
# Pins
Symbol
A
L7-1
18
Min
Max
0.060
0.050
0.022
0.280
0.075
0.065
0.028
0.305
A1
B1
D
D1
D2
D3
E
.150 BSC
.075 BSC
-
0.305
0.365
0.345
E1
E2
E3
e
0.200 BSC
0.100 BSC
-
0.365
0.050 BSC
0.040 REF
0.020 REF
h
j
L
0.045
0.045
0.075
0.055
0.055
0.125
L1
L2
ND
NE
4
5
PLASTIC DUAL IN-LINE PACKAGE
Pkg #
# Pins
Symbol
P1
18
Min
-
Max
0.210
-
0.022
0.070
0.014
0.920
0.280
0.325
A
A1
b
0.015
0.014
0.045
0.008
0.880
0.240
0.300
b2
C
D
E1
E
e
0.100 BSC
eB
L
-
0.430
0.150
15°
0.115
0°
α
Document # SRAM103 REV A
Page 9 of 10
P4C147
REVISIONS
DOCUMENTNUMBER:
DOCUMENTTITLE:
SRAM103
P4C147 ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM
ORIG. OF
CHANGE
ISSUE
REV.
DESCRIPTIONOFCHANGE
DATE
OR
A
1997
DAB
NewDataSheet
Oct-05
JDB
Change logo to Pyramid
Document # SRAM103 REV A
Page 10 of 10
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