P4C1026-20J3C [PYRAMID]
ULTRA HIGH SPEED 256K x 4 STATIC CMOS RAM; 超高速256K ×4的静态CMOS RAM
| 型号： | P4C1026-20J3C |
| 厂家： | 
PYRAMID SEMICONDUCTOR CORPORATION |
| 描述： | ULTRA HIGH SPEED 256K x 4 STATIC CMOS RAM |
| 文件： | 总10页 (文件大小：290K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P4C1026
ULTRA HIGH SPEED 256K x 4
STATIC CMOS RAM
FEATURES
TTL/CMOSCompatibleOutputs
Fully TTL Compatible Inputs
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
–15/20/25/35ns(Commercial/Industrial)
– 20/25/35 ns (Military)
StandardPinout(JEDECApproved)
– 28-Pin 300 mil SOJ
Low Power
– 28-Pin 400 mil SOJ
– 28-Pin 400 mil Ceramic DIP
– 32-Pin Ceramic LCC
Single 5V±10% Power Supply
Data Retention with 2.0V Supply
Three-StateOutputs
DESCRIPTION
Access times as fast as 15 nanoseconds are available,
permitting greatly enhanced system speeds. CMOS is
utilized to reduce power consumption.
The P4C1026 is a 1 Meg ultra high speed static RAM
organizedas256Kx4.TheCMOSmemoryrequiresnoclock
orrefreshingandhasequalaccessandcycletimes. Inputs
and outputs are fully TTL-compatible. The RAM operates
fromasingle5V±10%tolerancepowersupply.Withbattery
backup,dataintegrityismaintainedforsupplyvoltagesdown
to 2.0V.
TheP4C1026is availableina28-pin300miland400milSOJ
packages, as well as Ceramic DIP and LCC packages,
providingexcellentboardleveldensities.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
SOJ (J5, J7), DIP (C7)
LCC(L13)
Document # SRAM127 REV E
Revised April 2007
1
P4C1026
MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
Symbol
Parameter
Value
Unit
TBIAS
Temperature Under
Bias
–55 to +125
°C
VCC
Power Supply Pin with
Respect to GND
–0.5 to +7
V
TSTG
PT
Storage Temperature
Power Dissipation
DC Output Current
–65 to +150
°C
W
Terminal Voltage with
Respect to GND
(up to 7.0V)
–0.5 to
VCC +0.5
VTERM
TA
V
1.0
50
IOUT
mA
Operating Temperature –55 to +125 °C
CAPACITANCES(4)
VCC = 5.0V, TA = 25°C, f = 1.0MHz
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
Temperature
Symbol
Parameter
Conditions Typ. Unit
VCC
Grade(2)
GND
Industrial
Commercial
Military
CIN
VIN = 0V
pF
pF
Input Capacitance
Output Capacitance
7
–40°C to +85°C
0°C to +70°C
0V
0V
5.0V ± 10%
5.0V ± 10%
COUT
10
VOUT = 0V
-55°Cto+125°C
0V
5.0V ± 10%
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2)
P4C1026
Symbol
Parameter
Test Conditions
Unit
Min
Max
VIH
VIL
Input High Voltage
2.2
VCC +0.5
V
–0.5(3)
0.8
V
V
Input Low Voltage
VHC
VLC
VCD
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage
VCC –0.2
VCC +0.5
–0.5(3)
V
V
0.2
VCC = Min., IIN = –18 mA
IOL = +8 mA, VCC = Min.
–1.2
Output Low Voltage
(TTL Load)
VOL
0.4
V
V
Output High Voltage
(TTL Load)
VOH
IOH = –4 mA, VCC = Min.
2.4
–5
VCC = Max.
µA
ILI
+5
Input Leakage Current
Output Leakage Current
VIN = GND to VCC
VCC = Max., CE = VIH
VOUT = GND to VCC
ILO
–5
+5
35
µA
CE ≥ VIH
Standby Power Supply
Current (TTL Input Levels)
___
ISB
mA
VCC = Max ., f = Max., Outputs Open
CE ≥ VHC
VCINC≤ VLC or VIN ≥ VHC
Standby Power Supply
Current
(CMOS Input Levels)
___
ISB1
V
= Max., f = 0, Outputs Open
10
mA
Document # SRAM127 REV E
Page 2 of 10
P4C1026
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Temperature
Symbol
Parameter
Unit
Range
Commercial
Industrial
–15 –20 –25 –35
mA
mA
80
90
75
80
75
80
75
80
ICC
Dynamic Operating Current*
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL
DATA RETENTION CHARACTERISTICS
Typ.*
VCC
2.0V
Max
=
VCC
=
Symbol
Parameter
Test Conditions
Min
Unit
3.0V
2.0V 3.0V
VDR
VCC for Data Retention
Data Retention Current
2.0
V
ICCDR
tCDR
10
15
250
500
µA
ns
CE ≥ VCC –0.2V,
VIN ≥ VCC –0.2V or
VIN ≤ 0.2V
Chip Deselect to
Data Retention Time
0
†
§
tR
Operation Recovery Time
tRC
ns
*TA = +125°C
§tRC = Read Cycle Time
† This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
Document # SRAM127 REV E
Page 3 of10
P4C1026
AC CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-25
-15
-35
-20
Sym.
Parameter
Unit
Max
Min
Min Max
Min Max
Min Max
tRC
tAA
tAC
tOH
ReadCycleTime
35
25
25
25
2
ns
ns
15
20
20
Address Access Time
15
15
35
20
35
ns
ns
Chip Enable Access Time
2
2
2
2
3
OutputHoldfromAddressChange
ns
3
3
tLZ
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Chip Enable to Power Up Time
Chip Disable to Power Down Time
tHZ
ns
ns
11
10
8
9
0
0
0
tPU
tPD
0
ns
35
25
15
20
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)(5)
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20ns.
4. This parameter is sampled and not 100% tested.
5. WE is HIGH for READ cycle.
6. CE is LOW and OE is LOW for READ cycle.
7. ADDRESSmustbevalidpriorto,orcoincidentwithCE transitionLOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document # SRAM127 REV E
Page 4 of 10
P4C1026
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)(5,7)
AC CHARACTERISTICS - WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
-15
-20
-25
-35
Sym.
Parameter
Unit
Min Max Min Max Min Max Min
Max
tWC
tCW
tAW
Write Cycle Time
13
12
20
15
25
18
35
25
ns
ns
Chip Enable Time to End of Write
Address Valid to End of Write
AddressSet-upTime
18
0
12
0
15
0
25
0
ns
ns
ns
tAS
tWP
tAH
18
Write Pulse Width
12
15
25
Address Hold Time from End of Write
0
7
0
0
8
0
0
10
0
0
15
0
ns
ns
ns
ns
ns
tDW
tDH
tWZ
tDW
Data Valid to End of Write
DataHoldTime
Write Enable to Output in High Z
6
8
10
15
Output Active from End of Write
2
2
2
3
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)(10,11)
Notes:
10. CE and WE must be LOW for WRITE cycle.
11. OE is LOW for this WRITE cycle to show tWZ and tOW
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
.
12. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state
Document # SRAM127 REV E
Page 5 of10
P4C1026
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(10)
AC TEST CONDITIONS
TRUTH TABLE
Input Pulse Levels
GND to 3.0V
Mode
CE OE W E
I/O
Power
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
3ns
1.5V
Standby
H
X
X
HighZ
Standby
DOUT
Disabled
L
L
L
H
L
H
H
L
HighZ
DOUT
Active
Active
Active
1.5V
Read
Write
See Figures 1 and 2
X
HighZ
Figure 2. Thevenin Equivalent
Figure 1. Output Load
* including scope and test fixture.
Note:
frequency capacitor is also required between VCC and ground. To avoid
signal reflections, proper termination must be used; for example, a 50Ω
test environment should be terminated into a 50Ω load with 1.73V
(Thevenin Voltage) at the comparator input, and a 116Ω resistor must
be used in series with DOUT to match 166Ω (Thevenin Resistance).
Because of the ultra-high speed of the P4C1258, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance leads
that cause supply bounce must be avoided by bringing the VCC and
ground planes directly up to the contactor fingers. A 0.01 µF high
Document # SRAM127 REV E
Page 6 of 10
P4C1026
ORDERING INFORMATION
SELECTION GUIDE
The P4C1026 is available in the following temperature, speed and package options.
Speed
Temperature
Range
Package
15
-15J3C
-15J4C
-15J3I
-15J4I
N/A
20
25
35
Commercial
Plastic SOJ, 300 mil
Plastic SOJ, 400 mil
Plastic SOJ, 300 mil
Plastic SOJ, 400 mil
Ceramic DIP, 400 mil
28-Pin Ceramic LCC
32-Pin Ceramic LCC
Ceramic DIP, 400 mil
28-Pin Ceramic LCC
32-Pin Ceramic LCC
-20J3C
-20J4C
-20J3I
-25J3C
-25J4C
-25J3I
-35J3C
-35J4C
-35J3I
Industrial
-20J4I
-25J4I
-35J4I
Military
Temperature
-20CM
-25CM
-35CM
N/A
-20L28M
-20L32M
-20CMB
-20L28MB
-20L32MB
-25L28M
-25L32M
-25CMB
-25L28MB
-25L32MB
-35L28M
-35L32M
-35CMB
-35L28MB
-35L32MB
N/A
Military
Processeed*
N/A
N/A
N/A
* Military temperature range with MIL-STD-883, Class B compliance
N/A = Not Available
Document # SRAM127 REV E
Page 7 of10
P4C1026
SOJ SMALL OUTLINE IC PACKAGE
Pkg #
J5
# Pins
28 (300 mil)
Symbol
Min
Max
0.148
-
0.020
0.011
0.730
A
A1
b
C
D
0.120
0.078
0.014
0.007
0.700
e
E
E1
E2
Q
0.050 BSC
0.335 BSC
0.292 0.300
0.267 BSC
0.025
-
SOJ SMALL OUTLINE IC PACKAGE
Pkg #
J7
# Pins
28 (400 mil)
Symbol
Min
Max
0.148
-
0.019
0.013
0.730
A
A1
b
C
D
0.128
0.082
0.013
0.007
0.720
e
0.050 BSC
E
0.435
0.395
0.360
0.025
0.445
0.405
0.380
-
E1
E2
Q
Document # SRAM127 REV E
Page 8 of 10
P4C1026
SIDEBRAZED DUAL IN-LINE PACKAGE
Pkg #
C7
# Pins
28 (400 mil)
Symbol
Min
Max
A
b
b2
C
D
E
0.115
0.016
0.045
0.008
1.384
0.387
0.255
0.020
0.065
0.018
1.416
0.403
eA
e
0.400 BSC
0.100 TYP
L
0.125
0.200
0.070
—
Q
S1
S2
0.015
0.005
0.005
—
RECTANGULAR LEADLESS CHIP CARRIER
Pkg #
# Pins
Symbol
A
L13
32
Min
Max
0.070
0.054
0.025
0.442
0.093
0.066
0.031
0.458
A1
B1
D
D1
D2
D3
E
0.300 BSC
0.150 BSC
—
0.458
0.758
0.742
E1
E2
e
0.400 BSC
0.200 BSC
0.050 TYP
h
j
L
L1
0.045
0.045
0.055
0.055
L2
0.090 REF
ND
NE
7
9
Document # SRAM127 REV E
Page 9 of10
P4C1026
REVISIONS
DOCUMENTNUMBER:
DOCUMENTTITLE:
SRAM127
P4C1026 ULTRA HIGH SPEED 256K x 4 STATIC CMOS RAM
ORIG. OF
CHANGE
ISSUE
DATE
REV.
DESCRIPTIONOFCHANGE
OR
A
Oct-05
Aug-06
Oct-06
JDB
NewDataSheet
JDB
JDB
JDB
UpdatedSOJpackageinformation
Added Ceramic DIP, LCC packages and military processing
B
C
Dec-06
AddedL13package,removedL12package
D
E
Mar-07
Apr-07
JDB
JDB
Minortypographiccorrections
CorrectedLCCpinconfiguration
Document # SRAM127 REV E
Page 10 of 10
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