P1753-40QGMB [PYRAMID]
SINGLE CHIP, 40MHz CMOS MMU/COMBO; 单芯片的40MHz CMOS MMU / COMBO
| 型号： | P1753-40QGMB |
| 厂家： | 
PYRAMID SEMICONDUCTOR CORPORATION |
| 描述： | SINGLE CHIP, 40MHz CMOS MMU/COMBO |
| 文件： | 总21页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PACE1753
SINGLE CHIP, 40MHz
CMOS MMU/COMBO
FEATURES
— Illegal address error detection—
programmable
— Multi-Master arbitration
Implements the MIL-STD-1750A Instruction Set
Architecture for Memory Management and
Protection of up to 1 Megaword. All mapping
memory (10,240 bits) for both the MMU and
BPU functions are included on the chip.
8-bit extended address latches and drivers on
chip
Designed to interface memory to the
PACE1750A/AE 16-bit, 40 MHz processor.
Systems can be designed where no WAIT
states are required up to 40 MHz clock rates
when using these PACE products.
Information bus and EDAC transceivers on chip
20, 30 and 40 MHz operation over the Military
Temperature Range
Single 5V ± 10% Power Supply
System performance and device count are
optimized when used with the PACE1754
Processor Interface Circuit (PIC).
Power Dissipation over Military Temperature
Range (P Outputs Open)
D
< 0.20 watts at 20 MHz
< 0.30 watts at 30 MHz
< 0.40 watts at 40 MHz
Provides the following additional functions:
— EDAC, Error Detection and Correction—or
parity generation and detection
Available in:
— Correct data register—for diagnostics
— First memory failing address register
— 64-Pin DIP or Gull Wing (50 Mil Pin centers)
— 68-Pin Pin Grid Array (PGA) (100 Mil centers)
— 68-Lead Quad Pack (Leaded Chip Carrier)
MEMORY MANAGEMENT UNIT AND
BLOCK PROTECT UNIT “COMBO” —
FUNCTIONAL DESCRIPTION
The PACE1753 (COMBO) is a support chip for the
PACE1750A/AE microprocessor family. It provides the
following supporting functions to the system:
1. Memory management and access protection for up
to 1M words.
2
Physical memory write protection for up to 1M words
memory in pages of 1K words each. Separate
protection is provided for the CPU and for DMA in
systems which include DMA.
3. Detection of illegal l/O accesses (as defined by MIL-
STD-1750A) or access to an unimplemented block
of memory. In each case an error flag is generated
to the processor.
4
Detection of double errors on the data bus and
correctionofsingleerrors. Anerrorsignalisgenerated
to the processor when a multiple error is detected.
5. RDYA generation. Up to three wait states can be
insertedintheaddressphaseofthebusbygenerating
a not-ready, RDYA low signal. The number of wait
states required can be programmed in an internal
register in the COMBO.
6. Bus arbitration for up to 4 masters. Arbitration is
done on a fixed priority basis (i.e. by interconnection
of hardware). (In 68 pin package only).
Do c um e nt # MICRO-4 REV D
Re vise d No ve m b e r 2005
PACE1753
1
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING
CONDITIONS
Supply Voltage Range
Input Voltage Range
0.5V to +7.0V
Supply Voltage Range
4.5V to +5.5V
0.5V to V + 0.5V
CC
Case Operating
Temperature Range
–55°C to +125°C
Storage Temperature Range
Input Current Range
–65°C to +150°C
–30mA to +5mA
150mA
Operating Maximum Power
Dissipation (Outputs Open)
Device Type 20MHz
3
Current applied to any output
2
Maximum Power Dissipation
1.5W
0.20W
0.30W
0.40W
Device Type 30MHz
Device Type 40MHz
Lead Temperature Range
(soldering 10 seconds)
300°C
4
Thermal resistance (θ ):
JC
Cases X and T
Cases Y and U
Case Z
8°C/W
5°C/W
6°C/W
Notes
1. Stresses above the absolute maximum rating may cause
permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2. Must withstand the added power dissipation due to short circuit
test e.g., I
.
OS
3. Duration 1 second or less.
4. Device Type Definitions from 5962-89505 SMD:
CaseX:DualIn-Line
Case T: Dual In-Line with Gull-Wing Leads
Case Y: Leaded Chip Carrier with Gull-Wing Leads
CaseU:LeadedChipCarrierwithUnformedLeads
Case Z: Pin Grid Array
Do c um e nt # MICRO-4 REV D
Pa g e 2 o f 21
PACE1753
DC ELECTRICAL SPECIFICATIONS (Over recommended operating conditions)
1
Symbol
Parameter
Min
2.0
Max
V + 0.5
CC
Unit
V
Conditions
V
V
V
Input HIGH Voltage
IH
IL
2
Input LOW Voltage
–0.5
0.8
V
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage,
–1.2
V
V
V
V
V
V
V
V
= 4.5V, I = –18mA
IN
CD
CC
2.4
V
= 4.5V,
= 0.8V, 2.0V
I
I
I
I
I
I
= –8.0mA
= –300µA
= 8.0mA
= 300µA
= 20.0mA
= 300µA
CC
OH
OH
OL
OL
OL
OL
V
OH
V
OL
V
OL
V
– 0.2
V
CC
IN
0.5
0.2
0.5
0.2
V
= 4.5V,
CC
except EXT ADR – EXT ADR
V
= 0.8V, 2.0V
0
7
IN
Output LOW Voltage,
V
= 4.5V,
CC
EXT ADR – EXT ADR
V
= 0.8V, 2.0V
0
7
IN
Input HIGH Current,
I
IH
except IB – IB ,
10
µA
V
V
= V
,
CC
0
15
IN
EDC – EDC ,
= 5.5V
0
5
CC
EXT ADR – EXT ADR
0
7
Input HIGH Current,
V
V
= V
,
CC
IN
I
I
IB – IB , EDC – EDC ,
50
µA
µA
= 5.5V
IH
0
15
0
5
CC
EXT ADR – EXT ADR
0
7
Input LOW Current,
except IB – IB ,
–10
V
V
= GND,
= 5.5V
IL
0
15
IN
EDC – EDC ,
0
5
CC
EXT ADR – EXT ADR
0
7
Input LOW Current,
V
V
= GND,
IN
I
IL
IB – IB , EDC – EDC ,
–50
µA
= 5.5V
0
15
0
5
CC
EXT ADR – EXT ADR
0
7
I
I
Output Three-State Current
Output Three-State Current
50
µA
µA
V
V
V
= 2.4V, V = 5.5V
CC
OZH
OUT
–50
= 0.5V, V = 5.5V
CC
OZL
OUT
Quiescent Power Supply
Current (CMOS Input
Levels, Active)
< 0.2V or < V – 0.2V
CC
IN
I
60
mA
mA
f = 0MHz, Outputs Open,
CCQC
CCQT
V
CC
= 5.5V
Quiescent Power Supply
Current (TTL Input
Levels, Active)
V
IN
= 3.4V, f = 0MHz,
I
110
All Inputs, Outputs Open,
= 5.5V
V
CC
VCC = 0V to VCC
tr = tf = 2.5 ns,
Outputs Open,
VCC = 5.5V
,
Dynamic Power Supply
Current
40
50
60
mA
mA
mA
mA
pF
F = 20MHz
F = 30MHz
F = 40MHz
I
I
CCD
3
Output Short Circuit Current
Input Capacitance
–25
V = GND, V = 5.5V
OUT CC
OS
C
10
15
Inputs Only
IN
C
Output/Bi-directional
Capacitance
pF
Outputs Only
(Including I/O Buffers)
OUT
Notes
1. 4.5V ≤ V ≤ 5.5V, –55°C ≤ T ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions.
CC
C
2. V = –3.0V for pulse widths less than or equal to 20ns.
IL
3. Duration of the short should not exceed one second; only one output may be shorted at a time.
Do c um e nt # MICRO-4 REV D
Pa g e 3 o f 21
PACE1753
AC ELECTRICAL CHARACTERISTICS
(V = 4.5V)
CC
20 MHz
30MHz
40 MHz
Symbol
Parameter
MMU Cache Hit
TSTRBD (EXT ADR ERR) External Address Error
Min Max Min Max Min Max Unit
TD/I (EXT ADR)
25
25
23
20
23
16
ns
ns
V
L
TC (IBD CORR)
IBD (SING ERR)
Error Correction Read Cycle
Error Correction Read Cycle
25
35
20
30
19
25
ns
ns
V
H
TC (SING ERR)
Error Correction Read Cycle
EDAC or Parity Write Cycle
MMU Cache Miss
25
30
25
25
25
25
35
35
35
35
30
30
34
50
25
25
25
50
40
45
25
32
20
25
20
20
22
20
25
25
25
25
25
28
30
45
20
22
22
45
35
35
20
30
12
23
12
12
18
16
18
18
18
18
17
25
25
40
16
18
18
40
30
30
20
23
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
L
TIBD (EDC GEN)
V
V
TSTRBD (EX RDY)
L
TC (EX RDY)
MMU Cache Miss
H
TC (WR PROT)
MMU Cache Miss
L
TSTRBD (WR PROT)
MMU Cache Miss
H
H
TC (GNT1)
TC (GNT0)
TC (GNT0)
TC (GNT1)
Arbiter LOW to HIGH Priority
Arbiter LOW to HIGH Priority
Arbiter HIGH to LOW Priority
Arbiter HIGH to LOW Priority
Address Ready
H
L
H
L
TC (RDYA)
TFC (IB OUT)
Clock to IB Out Valid (I/O Read)
Parity Mode
V
TIBD (MEM PAR ERR)
IN
TC (MEM PRT ERR)
TSTRBD (WR PROT)
Memory Protect Error
Write Protect Cache Hit
Write Protect Cache Miss
Write Protect Cache Miss
Cache Hit (BPU Protection Error)
Cache Hit (MMU Key-Lock Error)
Cache Miss (BPU Protection Error)
Cache Hit (MMU Key-Lock Error)
Clock to EXT ADR Valid (Miss)
TC (WR PROT)
L
TSTRBD (WR PROT)
H
H
TD/I (PROT FLAG)
TD/I (PROT FLAG)
TC (PROT FLAG)
TC (PROT FLAG)
TC (EXT ADR)
Notes:
1. 4.5V ≤ V ≤ 5.5V, –55°C ≤ T ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions.
CC
C
2. V = –3.0V for pulse widths less than or equal to 20ns.
IL
3. Duration of the short should not exceed one second; only one output may be shorted at a time.
4. Pulse width of WR PROT/PROT FLAG shall be ≥ 80% of STRBD pulse width.
Do c um e nt # MICRO-4 REV D
Pa g e 4 o f 21
PACE1753
TERMINAL CONNECTIONS
Case Outlines: Dual-In-Line (Case X) and Dual-In-Line with Gull-Wing Leads (Case T)
Terminal
Number
Terminal
Symbol
Terminal
Number
Terminal
Symbol
Terminal
Number
Terminal
Symbol
1
GND
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
IB
IB
IB
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
AS
AS
13
14
15
1
0
2
EDC
EDC
EDC
0
1
2
3
GND
4
MEM PRT ER
MEM PAR ER
EXT ADR ER
RAM DIS
AK
AK
AK
AK
3
2
1
0
5
RESET
6
EDC
EDC
EDC
3
4
5
7
8
SING ERR
DMA ACK
GND
CLK
9
IB
IB
IB
IB
IB
IB
IB
IB
IB
IB
STRBA
STRBD
GND
0
1
10
11
12
13
14
15
16
17
18
19
20
21
22
EXT ADR
EXT ADR
EXT ADR
EXT ADR
EXT ADR
EXT ADR
EXT ADR
EXT ADR
2
0
1
2
3
4
5
6
7
EX RDY
3
WR PROT/PROT FLAG
4
R/W
D/I
5
6
M/IO
RDYA
NC
7
8
9
V
CC
V
CC
NC
IB
IB
IB
AS
AS
NC
10
11
12
3
2
V
CC
Do c um e nt # MICRO-4 REV D
Pa g e 5 o f 21
PACE1753
TERMINAL CONNECTIONS
Case Outlines: Leaded Chip Carrier with unformed leads (Case U) and Leaded Chip Carrier with Gull-
Wing Leads (Case Y)
Terminal
Number
Terminal
Symbol
Terminal
Number
Terminal
Symbol
Terminal
Number
Terminal
Symbol
1
2
GND
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
IB
IB
IB
IB
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
AS
AS
12
13
14
15
1
0
EDC
EDC
EDC
0
1
2
3
BUS REQ
2
1
4
AK
AK
3
2
5
RESET
MEM PRT ERR
MEM PAR ERR
EXT ADR ERR
RAM DIS
6
EDC
EDC
EDC
BUS GNT
3
4
5
7
AK
AK
1
8
0
9
BUS GNT
SING ERR
DMA ACK
CLK
2
10
11
12
13
14
15
16
17
18
19
20
21
IB
0
IB
1
IB
2
IB
3
IB
4
IB
5
IB
6
IB
7
STRBA
STRBD
BUS REQ
EX RDY
GND
V
CC
0
EXT ADR
EXT ADR
EXT ADR
EXT ADR
EXT ADR
EXT ADR
EXT ADR
EXT ADR
GND
0
1
2
3
4
5
6
7
WR PROT/PROT FLAG
R/W
D/I
M/IO
RDYA
BUS REQ
3
3
IB
IB
BUS GNT
8
0
BUS LOCK
9
BUS GNT
BUS REQ
1
22
23
IB
IB
45
46
AS
AS
V
CC
10
11
3
2
Do c um e nt # MICRO-4 REV D
Pa g e 6 o f 21
PACE1753
TERMINAL CONNECTIONS
Case Outline: Pin Grid Array (Case Z)
Terminal
Number
Terminal
Symbol
Terminal
Number
Terminal
Symbol
Terminal
Number
Terminal
Symbol
B1
B2
C1
C2
D1
D2
E1
E2
F1
F2
G1
G2
H1
H2
J1
IB
IB
IB
IB
IB
L5
EDC
EDC
D11
D10
C11
C10
B11
A10
B10
A9
AS
AS
AS
AS
14
13
12
11
10
1
0
1
K5
0
L6
GND
2
K6
V
CC
3
L7
BUS REQ
V
CC
1
BUS GNT
K7
BUS LOCK
GND
3
3
IB
IB
L8
BUS GNT
RDYA
M/IO
EXT ADR
EXT ADR
EXT ADR
EXT ADR
EXT ADR
EXT ADR
EXT ADR
EXT ADR
GND
9
0
7
K8
8
6
5
4
3
2
1
0
BUS REQ
L9
B9
IB
IB
IB
IB
IB
IB
IB
IB
K9
D/I
A8
7
6
5
4
3
2
1
0
L10
K11
K10
J11
J10
H11
H10
G11
G10
F11
F10
E11
E10
R/W
B8
WR PROT/PROT FLAG
A7
EX RDY
B7
BUS REQ
STRBD
STRBA
CLK
A6
0
B6
J2
A5
DMA ACK
K1
L2
K2
L3
K3
L4
K4
B5
SING ERR
BUS GNT
AK
AK
A4
RAM DIS
2
0
1
EDC
EDC
EDC
B4
EXT ADR ERR
MEM PAR ERR
MEM PRT ERR
5
4
3
BUS GNT
A3
1
2
AK
AK
B3
2
3
RESET
EDC
A2
IB
15
BUS REQ
2
Do c um e nt # MICRO-4 REV D
Pa g e 7 o f 21
PACE1753
MMU Cache Hit
External Address Error
Note:
All time measurements on active signals relate to 1.5V levels.
Do c um e nt # MICRO-4 REV D
Pa g e 8 o f 21
PACE1753
Error Correction (Write Cycle)
Memory Protect Error
Error Correction (Read Cycle)
Ready Address
Memory Parity Error
Note:
All time measurements on active signals relate to 1.5V levels.
Do c um e nt # MICRO-4 REV D
Pa g e 9 o f 21
PACE1753
MMU Cache Miss Cycle (WA = 0)
MMU Cache Miss Cycle (WA > 0)
* The WR PROT/PROT FLAG signal is programmed as WR PROT or PROT FLAG. (See BPU Description), T = 1 Clock Period.
Note:
All time measurements on active signals relate to 1.5V levels.
Do c um e nt # MICRO-4 REV D
Pa g e 10 o f 21
PACE1753
Low Priority to High Priority Transition
B0
B1
B2
B3
B0
B0
B1
CLK
REQ1
GNT1
REQ0
LOCK
GNT0
TC (GNT1)H
TC (GNT0)L
Bus Arbitrator High Priority to Low Priority Transition
Note:
All time measurements on active signals relate to 1.5V levels.
Do c um e nt # MICRO-4 REV D
Pa g e 11 o f 21
PACE1753
SWITCHING WAVEFORMS AND TEST CIRCUIT (Continued)
IB Bus Output (0:15)
Standard Output (Non Three-State)
Three-S
Note:
All time measurements on active signals relate to 1.5V levels.
Parameter
TPLZ
V
V
MEA
O
≥ 3V
0.5V
V – 0.5V
CC
TPHZ
0V
TPXL
V
/2
1.5V
1.5V
CC
CC
TPXH
V
/2
Do c um e nt # MICRO-4 REV D
Pa g e 12 o f 21
PACE1753
PIN FUNCTIONS
Symbol
Name
Description
Active LOW inputs that indicate a requirement for the bus from 4
masters on the bus. The master assigned to pin BUS-REQ has
1
BUS REQ -
Bus Request
0
BUS REQ
3
0
highest priority; the master assigned to pin BUS-REQ has lowest
3
priority.
1
BUS LOCK
Bus Lock
An active LOW input that indicates that the one master assigned
the bus is using the bus. A new master will receive a bus grant only
after this signal becomes inactive.
1
BUS GNT -
Bus Grant
Active LOW outputs indicating which master was granted the
bus. It remains active during BUS LOCK unless a higher master
request occurs, which resets it. However, the higher master will be
granted the bus only after the present master’s BUS LOCK releases
the bus.
0
BUS GNT
3
M/IO
D/I
Memory or I/O
Data or Instruction
Read or Write
An input signal that indicates whether the current bus cycle is a
memory (HIGH) or l/O (LOW) cycle.
An input signal that indicates whether the current bus cycle access
is for data (HIGH) or instruction (LOW).
R/W
An input signal that indicates the direction of data flow on the bus.
A HIGH indicates a memory read or input operation into the master
and a LOW indicates a memory write or output operation from the
master.
STRBA
Address Strobe
An active HIGH input used to latch the address at the HIGH-to-
LOW transition of the strobe.
STRBD
Data Strobe
CPU Clock
An active LOW input used to strobe data in memory and I/O cycles.
CPU-CLK
A single-phase input clock signal (0-40MHz, 40% to 60% duty
cycle.)
RESET
Reset
An active LOW input that initializes the device.
AK - AK
Access Key
Active HIGH inputs used to match the access lock in the MMU page
for memory accesses. A mismatch will cause the MEM PRT ERR
signal to become active.
0
3
3
AS - AS
Address State
Active HIGH inputs that select the page register group in the MMU.
In the DMA physical demultiplexed mode, AS(0:1) will receive the
9th and 10th most significant bits of the physical address for use in
the BPU function.
0
EXT ADR -
Extended Addresses Bus A bi-directional active HIGH bus. In CPU cycles, it is an
output bus which is used to select one of 256 pages, 4K words
each, expanding the direct addressing space to 1M word. In DMA
cycles, indicated by DMA-ACK being active, it is also an output bus
except when programmed for the physical demultiplexed DMA
mode. In this case it becomes an input to receive the 8 most
significant bits of the DMA physical address for use in the BPU
function.
0
EXT ADR
7
IB - IB
Information Bus
An active HIGH bi-directional time multiplexed address/data bus.
0
15
IB is the most significant bit.
0
EDC - EDC
Detection/Correction
Bus
An active HIGH bi-directional bus used for detection of errors on
0
5
the data bus (IB - IB ) and correction of single errors. When
0
15
working in parity mode EDC is the parity bit. EDC - EDC are
0
0
5
undefined in this case.
Do c um e nt # MICRO-4 REV D
Pa g e 13 o f 21
PACE1753
PIN FUNCTIONS (Continued)
Symbol
Name
Description
MEM PRT ERR Memory Protect Error
An active LOW output generated by the MMU or BPU blocks to
signal to the CPU a protected memory violation. The error is
generated in one of the following conditions: a mismatch in the
access keys in the MMU page, an access to an execution protected
page during instruction cycles, an access to a write-protected page
during data cycles, or an access to a page write-protected by the
BPU.
MEM PAR ERR Memory Parity Error
An active LOW output which signals to the CPU an error on the
data bus during a memory cycle. Two detection modes can be
selected by programming the control register: EDAC mode (6
Hamming code parity bits) or single bit parity mode (even or odd
parity). The signal is inactive when none of the above modes are
selected (default after Reset).
EXT ADR ERR
External Address Error
Single Error
An active LOW output which signals to the CPU an unimplemented
memory or illegal I/O access.
SING ERR
An active HIGH output to signal detection of a single error on the
data bus in memory cycles. It is high impedance when the EDAC
function is disabled by the program (default state after Reset).
RAM DIS
RAM-Disable
An active HIGH input from the P1754 device which enables the
corrected data on the data bus when the EDAC function is enabled.
An internal one clock delay is generated before the data is output
on the bus to allow external memory to disconnect itself from the
bus.
EX RDY
RDYA
Data Ready
An active HIGH output that indicates that no wait states are
requested. It becomes inactive for one clock (inserting one wait
state) whenever a memory page different than the current one is
accessed (causing a miss).
Address Ready
An active HIGH output that indicates that no wait states are
requested when STRBA is active. Wait states are inserted when
this signal becomes inactive during STRBA. Up to three wait states
can be inserted by programming an internal register. Three wait
states are inserted after Reset (default).
WR PROT/
PROT FLAG
Write Protected/
Protection Flag
Either an active LOW output (following STRBD timing) during legal
memory write cycles, when no protection error occurs, or an active
HIGH level indicating a protection error in a write cycle. Each mode
can be selected by programming the control register. Default mode
after Reset is write-protected.
DMA ACK
DMA Acknowledge
An active HIGH input from the DMA controller which indicates a
DMA cycle. Used to select the DMA table in the BPU memory for
protection. For example, this could allow the DMA channel to
update the program which could be write-protected from the
processor. In the physical DMA mode, it will cause the Extended
Address Lines (EXT ADR ) to become inputs, providing BPU
0-7
protection of the DMA transfers.
Note:
1. Used for Bus Arbitration; only available on 68-lead devices.
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PACE1753
Standardized Military
Drawing PIN
Vendor
CAGE Number
Vendor similar
PIN
5962-8950501UX
5962-8950501YX
5962-8950501ZX
5962-8950502UX
5962-8950502YX
5962-8950502ZX
5962-8950503UX
5962-8950503YX
5962-8950503ZX
5962-8950504TX
5962-8950504XX
5962-8950505TX
5962-8950505XX
5962-8950506TX
5962-8950506XX
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
3DTT2
P1753-20QLMB
P1753-20QGMB
P1753-20PGMB
P1753-30QLMB
P1753-30QGMB
P1753-30PGMB
P1753-40QLMB
P1753-40QGMB
P1753-40PGMB
P1753-20GMB
P1753-20CMB
P1753-30GMB
P1753-30CMB
P1753-40GMB
P1753-40CMB
ORDERING INFORMATION
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PACE1753
CASE OUTLINE X:
64 Lead Top Brazed DIP Package, Straight Lead Version (Ordering Code C)
Inches
.002
.005
.008
.010
.015
.016
.018
.025
.040
.050
.185
.265
.470
.530
.590
.620
.645
1.550
1.563
mm
0.05
0.12
0.20
0.25
0.38
0.40
0.45
0.63
1.01
1.27
4.70
6.73
11.93
13.46
14.98
15.74
16.38
39.37
39.70
NOTES:
1) Dimensions are in inches.
2)Metricequivalentsaregivenforgeneralinformationonly.
3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals.
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PACE1753
CASE OUTLINE T:
64 Lead Top Brazed DIP Package, Gullwing Lead Version (Ordering Code G)
Inches
.001
.003
.005
.008
.010
.015
.016
.022
.030
.040
.050
.150
.470
.530
.590
.620
.868
1.663
mm
0.03
0.08
0.12
0.20
0.25
0.38
0.41
0.55
0.76
1.01
1.27
3.81
11.93
13.46
14.98
15.74
22.04
42.24
NOTES:
1) Dimensions are in inches.
2)Metricequivalentsaregivenforgeneralinformationonly.
3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals.
4) Case T is derived from Case X by forming the leads to the shown gullwing configuration.
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PACE1753
CASE OUTLINE U:
68 Lead Quad Pack with Straight Leads (Ordering Code QL)
Inches
.002
.004
.006
.010
.012
.020
.050
.100
.116
.250
.560
.570
.800
.955
1.090
mm
0.05
0.10
0.15
0.25
0.30
0.51
1.27
2.54
2.95
6.40
14.22
14.48
20.32
24.25
27.69
NOTES:
1) Dimensions are in inches.
2)Metricequivalentsaregivenforgeneralinformationonly.
3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals.
4)Pin1indicatorcanbeeitherrectangle, dot, ortriangleatspecifiedlocationorreferencedtotheuniquelybeveledcorner.
5)Cornersindicatedasnotchedmaybeeithernotchedorsquare.
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PACE1753
CASE OUTLINE Y:
68 Lead Quad Pack with Gullwing Leads (Ordering Code QG)
Inches
.004
.005
.008
.010
.012
.015
.016
.020
.024
.040
.050
.100
.115
.570
.800
.955
1.010
1.090
mm
0.10
0.12
0.20
0.25
0.30
0.38
0.41
0.50
0.60
1.02
1.27
2.54
2.92
14.48
20.32
24.25
25.65
27.68
NOTES:
1) Dimensions are in inches.
2)Metricequivalentsaregivenforgeneralinformationonly.
3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals.
4)Pin1indicatorcaneitherberectangle, dot, ortriangleatspecifiedlocationorreferencedtotheuniquelybeveledcorner.
5) Corners indicated as notched my be either notched or square (with radius).
6) Case Y is derived from Case U by forming the leads to the shown gullwing configuration.
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PACE1753
CASE OUTLINE Z:
68-Pin Pin Grid Array (PGA) (Ordering Code PG)
Inches
.016
.020
.040
.050
.059
.060
.098
.100
.120
.150
.170
1.010
1.089
1.160
mm
0.41
0.50
1.01
1.27
1.49
1.52
2.49
2.54
3.04
3.81
4.32
25.65
27.66
29.46
NOTES:
1) Dimensions are in inches.
2)Metricequivalentsaregivenforgeneralinformationonly.
3) Unless otherwise specified, tolerances are .02 (0.5 mm) for two place decimals and .005 (0.13 mm) for three place decimals.
4) Corners except pin number 1 (ref.) can be either rounded or square.
5) All pins must be on the .100" grid.
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PACE1753
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
MICRO-4
PACE1753 CMOS MMU/COMBO
ISSUE
REV.
ORIG. OF
CHANGE
DESCRIPTION OF CHANGE
DATE
ORIG
A
May-89
Jul-04
RKK
New Data Sheet
JDB
JDB
JDB
JDB
Added Pyramid logo
B
C
D
Aug-05
Oct-05
Re-created electronic version
Altered case outline drawing for case X and case T
Removed Commercial Temp
11/15/05
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相关型号：
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