ASM5P23S04AG-2-08-ST [PULSECORE]
3.3V ‘SpreadTrak’ Zero Delay Buffer; 3.3V “ SpreadTrak ”零延迟缓冲器
| 型号： | ASM5P23S04AG-2-08-ST |
| 厂家： | 
PulseCore Semiconductor |
| 描述： | 3.3V ‘SpreadTrak’ Zero Delay Buffer |
| 文件： | 总15页 (文件大小：412K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 2006
rev 1.4
ASMP5P23S04A
3.3V ‘SpreadTrak’ Zero Delay Buffer
Features
FBK pin, and can be obtained from one of the outputs. The
input-to-output propagation delay is guaranteed to be less
than 250 pS, and the output-to-output skew is guaranteed
to be less than 200 pS.
•
Zero input - output propagation delay, adjustable
by capacitive load on FBK input.
Multiple configurations - Refer “ASM5P23S04A
Configurations Table”.
•
•
•
•
•
•
•
Input frequency range: 15 MHz to 133 MHz
Multiple low-skew outputs.
Output-output skew less than 200 pS.
Device-device skew less than 500 pS.
Two banks of two outputs each.
The ASM5P23S04A has two banks of two outputs each.
Multiple ASM5P23S04A devices can accept the same input
clock and distribute it. In this case the skew between the
outputs of the two devices is guaranteed to be less than
500 pS.
Less than 200 pS cycle-to-cycle jitter
•
(-1, -1H, -2, -2H).
The ASM5P23S04A is available in two different
configurations (Refer “ASM5P23S04A Configurations
Table). The ASM5P23S04A-1 is the base part, where the
output frequencies equal the reference if there is no
counter in the feedback path. The ASM5P23S04A-1H is
the high-drive version of the -1 and the rise and fall times
on this device are much faster.
•
Available in space saving, 8-pin 150-mil SOIC
package.
3.3V operation.
Advanced 0.35µ CMOS technology.
Industrial temperature available.
‘SpreadTrak’.
•
•
•
•
The ASM5P23S04A-2 allows the user to obtain Ref and
1/2X frequencies on each output bank. The exact
configuration and output frequencies depend on which
output drives the feedback pin.
Functional Description
ASM5P23S04A is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed clocks in PC,
workstation, datacom, telecom and other high-performance
applications. It is available in a 8-pin package. The part has
an on-chip PLL, which locks to an input clock, presented on
the REF pin. The PLL feedback is required to be driven to
The ASM5P23S04A-2H is a high-drive version with REF/2
on both banks.
Block Diagram
PLL
REF
/2
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
November 2006
ASM5P23S04A
rev 1.4
ASM5P23S04A Configurations
Device
Feedback From
Bank A Frequency
Bank B Frequency
ASM5P23S04A-1
ASM5P23S04A-1H
ASM5P23S04A-2
ASM5P23S04A-2H
Bank A or Bank B
Bank A or Bank B
Bank A or Bank B
Bank A or Bank B
Reference
Reference
Reference
Reference
Reference
Reference
Reference /2
Reference /2
‘SpreadTrak’
significant amount of tracking skew which may cause
problems in the systems requiring synchronization.
Many systems being designed now utilize a technology
called Spread Spectrum Frequency Timing Generation.
ASM5P23S04A is designed so as not to filter off the
Spread Spectrum feature of the Reference Input, assuming
it exists. When a zero delay buffer is not designed to pass
the Spread Spectrum feature through, the result is a
Zero Delay and Skew Control
For applications requiring zero input-output delay, all
outputs must be equally loaded.
1500
1000
500
0
5
-30
30
-25
10
15
20
25
-20
-15
-10
-5
0
-500
-1000
-1500
Output Load Difference: FBK Load - CLKA/CLKB Load (pF)
REF Input to CLKA/CLKB Delay Vs Difference in Loading between FBK pin and CLKA/CLKB pins
To close the feedback loop of the ASM5P23S04A, the FBK
pin can be driven from any of the four available output pins.
The output driving the FBK pin will be driving a total load of
7pF plus any additional load that it drives. The relative
loading of this output (with respect to the remaining
outputs) can adjust the input output delay. This is shown in
the above graph.
For applications requiring zero input-output delay, all
outputs including the one providing feedback should be
equally loaded. If input-output delay adjustments are
required, use the above graph to calculate loading
differences between the feedback output and remaining
outputs. For zero output-output skew, be sure to load
outputs equally.
3.3 ‘SpreadTrak’ Zero Delay Buffer
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Notice: The information in this document is subject to change without notice.
November 2006
rev 1.4
ASM5P23S04A
Pin Configuration
FBK
VDD
1
REF
CLKA1
CLKA2
GND
8
2
3
4
7
6
ASM5P23S04A
CLKB2
CLKB1
5
Pin Description for ASM5P23S04A
Pin #
Pin Name
Description
1
2
3
4
5
6
7
8
REF1
CLKA12
CLKA22
GND
Input reference frequency, 5V tolerant input
Buffered clock output, bank A
Buffered clock output, bank A
Ground
CLKB12
CLKB2 2
VDD
Buffered clock output, bank B
Buffered clock output, bank B
3.3V supply
FBK
PLL feedback input
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3.3 ‘SpreadTrak’ Zero Delay Buffer
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Notice: The information in this document is subject to change without notice.
November 2006
rev 1.4
ASM5P23S04A
Absolute Maximum Ratings
Parameter
Min
Max
Unit
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage (REF)
-0.5
-0.5
-0.5
-65
+7.0
VDD + 0.5
7
V
V
V
Storage Temperature
+150
260
°C
°C
°C
Max. Soldering Temperature (10 sec)
Junction Temperature
150
Static Discharge Voltage
>2000
V
(per MIL-STD-883, Method 3015)
Note: These are stress ratings only and functional usage is not implied. Exposure to absolute maximum ratings for prolonged periods can
affect device reliability.
Operating Conditions for ASM5P23S04A Commercial Temperature Devices
Parameter
Description
Min
Max
Unit
VDD
TA
Supply Voltage
3.0
0
3.6
70
30
15
7
V
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance3
°C
pF
pF
pF
CL
CL
CIN
Note:
3. Applies to both Ref Clock and FBK.
3.3 ‘SpreadTrak’ Zero Delay Buffer
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Notice: The information in this document is subject to change without notice.
November 2006
rev 1.4
ASM5P23S04A
Electrical Characteristics for ASM5P23S04A Commercial Temperature Devices
Parameter
Description
Test Conditions
Min
Max
Unit
VIL
VIH
IIL
Input LOW Voltage
0.8
V
V
Input HIGH Voltage
Input LOW Current
Input HIGH Current
2.0
VIN = 0V
50.0
µA
µA
IIH
VIN = VDD
100.0
I
I
OL = 8mA (-1, -2)
VOL
Output LOW Voltage 4
Output HIGH Voltage 4
0.4
V
V
OH = 12mA (-1H, -2H)
I
I
OL = -8mA (-1, -2)
VOH
2.4
OH = -12mA (-1H, -2H)
TBD
TBD
Unloaded outputs 100MHz REF,
Select inputs at VDD or GND
IDD
Supply Current
mA
Unloaded outputs, 66MHz REF
(-1, -2)
TBD
TBD
Unloaded outputs, 33MHz REF
(-1, -2)
Note:
4. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3 ‘SpreadTrak’ Zero Delay Buffer
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Notice: The information in this document is subject to change without notice.
November 2006
ASM5P23S04A
rev 1.4
Switching Characteristics for ASM5P23S04A Commercial Temperature Devices
Parameter
Description
Test Conditions
Min Typ Max Unit
1/t1
1/t1
1/t1
Output Frequency
30 pF load, All devices
20 pF load, -1H, -2H devices
15 pF load, -1, -2 devices
15
15
15
100 MHz
133 MHz
133 MHz
Output Frequency
Output Frequency
Duty Cycle 5= (t2 / t1) * 100
(-1, -2, -1H, -2H)
Measured at 1.4V, FOUT = 66.66 MHz
40.0 50.0 60.0
%
%
30 pF load
Duty Cycle 5 = (t2 / t1) * 100
(-1, -2,-1H, -2H)
Measured at 1.4V, FOUT = <50 MHz
15 pF load
45.0 50.0 55.0
Output Rise Time 5
(-1, -2)
Measured between 0.8V and 2.0V
t3
t3
t3
t4
t4
t4
2.20
1.50
1.50
2.20
1.50
1.25
nS
nS
nS
nS
nS
nS
30 pF load
Output Rise Time 5
(-1, -2)
Measured between 0.8V and 2.0V
15 pF load
Output Rise Time 5
(-1H, -2H)
Measured between 0.8V and 2.0V
30 pF load
Output Fall Time 5
(-1, -2)
Measured between 2.0V and 0.8V
30 pF load
Output Fall Time 5
(-1, -2)
Measured between 2.0V and 0.8V
15 pF load
Output Fall Time 5
(-1H, -2H)
Measured between 2.0V and 0.8V
30 pF load
Output-to-output skew on same bank
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
200
200
200
(-1, -2) 5
Output-to-output skew (-1H, -2H)
t5
pS
Output bank A -to- output bank B skew
(-1, -2H)
Output bank A to output bank B skew (-
2)
All outputs equally loaded
Measured at VDD /2
400
Delay, REF Rising Edge to FBK Rising
t6
t7
0
0
±250 pS
Edge 5
Measured at VDD/2 on the FBK pins of
the device
Device-to-Device Skew 5
Output Slew Rate5
500
pS
Measured between 0.8V and 2.0V
t8
using
1
V/nS
Test Circuit #2
Measured at 66.67 MHz, loaded
175
200
100
400
375
1.0
outputs, 15 pF load
Cycle-to-cycle jitter 5
(-1, -1H, -2H)
Measured at 66.67 MHz, loaded
outputs, 30 pF load
tJ
pS
Measured at 133 MHz, loaded outputs,
15 pF load
Measured at 66.67 MHz, loaded
outputs, 30 pF load
Cycle-to-cycle jitter 5
(-2)
tJ
pS
Measured at 66.67 MHz, loaded
outputs, 15 pF load
Stable power supply, valid clock
presented on REF and FBK pins
tLOCK
PLL Lock Time 5
mS
Note:
5. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3 ‘SpreadTrak’ Zero Delay Buffer
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Notice: The information in this document is subject to change without notice.
November 2006
rev 1.4
ASM5P23S04A
Operating Conditions for ASM5I23S04A Industrial Temperature Devices
Parameter
Description
Min
Max
Unit
VDD
TA
Supply Voltage
3.0
-40
3.6
85
30
15
7
V
Operating Temperature (Ambient Temperature)
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance6
°C
pF
pF
pF
CL
CL
CIN
Note:
6. Applies to both Ref Clock and FBK.
Electrical Characteristics for ASM5I23S04A Industrial Temperature Devices
Parameter
Description
Test Conditions
Min
Max
Unit
VIL
VIH
IIL
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
0.8
V
V
2.0
VIN = 0V
50.0
µA
µA
IIH
VIN = VDD
100.0
I
OL = 8mA (-1, -2)
VOL
Output LOW Voltage 7
Output HIGH Voltage 7
0.4
V
V
IOH = 12mA (-1H, -2H)
I
I
OL = -8mA (-1, -2)
VOH
2.4
OH = -12mA (-1H, -2H)
TBD
TBD
TBD
TBD
Unloaded outputs 100MHz REF, Select
inputs at VDD or GND
IDD
Supply Current
mA
Unloaded outputs, 66MHz REF (-1, -2)
Unloaded outputs, 33MHz REF (-1, -2)
Note:
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3 ‘SpreadTrak’ Zero Delay Buffer
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Notice: The information in this document is subject to change without notice.
November 2006
rev 1.4
ASM5P23S04A
Switching Characteristics for ASM5I23S04A Industrial Temperature Devices
Parameter
Description
Test Conditions
Min Typ Max Unit
t1
t1
t1
Output Frequency
30 pF load, All devices
15
15
15
100
133
133
MHz
MHz
MHz
Output Frequency
Output Frequency
20 pF load, -1H, -2H devices
15 pF load, -1 and -2 devices
Duty Cycle 8 = (t2 / t1) * 100
(-1, -2, -1H, -2H)
Measured at 1.4V, FOUT = <66.66 MHz
40.0 50.0 60.0
%
30 pF load
Duty Cycle 8= (t2 / t1) * 100
(-1, -2, -1H, -2H)
Measured at 1.4V, FOUT = <50 MHz
15 pF load
45.0 50.0 55.0
%
Output Rise Time 8
(-1, -2)
Measured between 0.8V and 2.0V
t3
t3
t3
t4
t4
t4
2.50
1.50
1.50
2.50
1.50
1.25
nS
nS
nS
nS
nS
nS
30 pF load
Output Rise Time 8
(-1, -2)
Measured between 0.8V and 2.0V
15 pF load
Output Rise Time 8
(-1H, -2H)
Measured between 0.8V and 2.0V
30 pF load
Output Fall Time 8
(-1, -2)
Measured between 2.0V and 0.8V
30 pF load
Output Fall Time 8
(-1, -2)
Measured between 2.0V and 0.8V
15 pF load
Output Fall Time 8
(-1H, -2H)
Measured between 2.0V and 0.8V
30 pF load
Output-to-output skew on same bank (-
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
200
200
200
1, -2) 8
Output-to-output skew (-1H, -2H)
t5
pS
Output bank A -to- output bank B skew
(-1, -2H)
Output bank A -to- output bank B skew
(-2)
All outputs equally loaded
Measured at VDD /2
400
Delay, REF Rising Edge to FBK Rising
t6
t7
t8
0
0
±250
500
pS
pS
Edge 8
Measured at VDD/2 on the FBK pins of
the device
Device-to-Device Skew 8
Output Slew Rate8
Measured between 0.8V and 2.0V
1
V/nS
using Test Circuit #2
Measured at 66.67 MHz, loaded
outputs,15 pF load
180
200
Cycle-to-cycle jitter 8
(-1, -1H, -2H)
Measured at 66.67 MHz, loaded
tJ
pS
outputs,
30 pF load
Measured at 133 MHz, loaded
100
400
380
1.0
outputs, 15 pF load
Measured at 66.67 MHz, loaded
outputs, 30 pF load
Cycle-to-cycle jitter 8
(-2)
tJ
pS
Measured at 66.67 MHz, loaded
outputs, 15 pF load
Stable power supply, valid clock
presented on REF and FBK pins
tLOCK
PLL Lock Time 8
mS
Note:
8. Parameter is guaranteed by design and characterization. Not 100% tested in production.
3.3 ‘SpreadTrak’ Zero Delay Buffer
8 of 15
Notice: The information in this document is subject to change without notice.
November 2006
rev 1.4
ASM5P23S04A
Switching Waveforms
Duty Cycle Timing
t
1
t
2
1.4 V
1.4 V
1.4 V
All Outputs Rise/Fall Time
3.3 V
0 V
2.0 V
2.0 V
0.8 V
OUTPUT
0.8 V
t4
t3
Output - Output Skew
1.4 V
OUTPUT
1.4 V
OUTPUT
t5
Input - Output Propagation Delay
V
/2
DD
INPUT
V
/2
DD
OUTPUT
t6
Device - Device Skew
V
/2
DD
FBK, Device 1
FBK, Device 2
V
/2
DD
t7
3.3 ‘SpreadTrak’ Zero Delay Buffer
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Notice: The information in this document is subject to change without notice.
November 2006
rev 1.4
ASM5P23S04A
Test Circuits
TEST CIRCUIT #1
+3.3V
CLOAD
OUTPUT
VDD
0.1uF
GND
TEST CIRCUIT # 2
1KΩ
1KΩ
+3.3V
OUTPUT
VDD
10pF
0.1uF
GND
For parameter t8 (output skew rate) on -1H devices
3.3 ‘SpreadTrak’ Zero Delay Buffer
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Notice: The information in this document is subject to change without notice.
November 2006
rev 1.4
ASM5P23S04A
Package Information:
8-lead (150 Mil) Molded SOIC
H
E
D
A2
A
C
θ
e
A1
L
B
Dimensions
Symbol
Inches
Millimeters
Min
Max
0.010
0.069
0.059
0.020
0.010
Min
0.10
1.35
1.25
0.31
0.18
Max
0.25
1.75
1.50
0.51
0.25
A1
A
0.004
0.053
0.049
0.012
0.007
A2
B
C
D
E
0.193 BSC
0.154 BSC
0.050 BSC
0.236 BSC
4.90 BSC
3.91 BSC
1.27 BSC
6.00 BSC
e
H
L
0.016
0°
0.050
8°
0.41
0°
1.27
8°
θ
3.3 ‘SpreadTrak’ Zero Delay Buffer
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Notice: The information in this document is subject to change without notice.
November 2006
rev 1.4
ASM5P23S04A
Ordering Codes
Ordering Code
Marking
Package Type
Temperature
ASM5P23S04AF-1-08-SR
ASM5P23S04AF-1-08-ST
ASM5I23S04AF-1-08-SR
ASM5I23S04AF-1-08-ST
ASM5P23S04AF-1H-08-SR
ASM5P23S04AF-1H-08-ST
ASM5I23S04AF-1H-08-SR
ASM5I23S04AF-1H-08-ST
ASM5P23S04AF-2-08-SR
ASM5P23S04AF-2-08-ST
ASM5I23S04AF-2-08-SR
ASM5I23S04AF-2-08-ST
ASM5P23S04AF-2H-08-SR
ASM5P23S04AF-2H-08-ST
ASM5I23S04AF-2H-08-SR
ASM5I23S04AF-2H-08-ST
5P23S04AF-1
5I23S04AF-1
5P23S04AF-1
5I23S04AF-1
5P23S04AF-1H
5I23S04AF-1H
5P23S04AF-1H
5I23S04AF-1H
5P23S04AF-2
5I23S04AF-2
5P23S04AF-2
5I23S04AF-2
5P23S04AF-2H
5I23S04AF-2H
5P23S04AF2H
5I23S04AFH
8-pin 150-mil SOIC-TAPE & REEL, Pb free
8-pin 150-mil SOIC-TUBE, Pb free
Commercial
Commercial
Industrial
8-pin 150-mil SOIC-TAPE & REEL, Pb free
8-pin 150-mil SOIC-TUBE, Pb free
Industrial
8-pin 150-mil SOIC-TAPE & REEL, Pb free
8-pin 150-mil SOIC-TUBE, Pb free
Commercial
Commercial
Industrial
8-pin 150-mil SOIC-TAPE & REEL, Pb free
8-pin 150-mil SOIC-TUBE, Pb free
Industrial
8-pin 150-mil SOIC-TAPE & REEL, Pb free
8-pin 150-mil SOIC-TUBE, Pb free
Commercial
Commercial
Industrial
8-pin 150-mil SOIC-TAPE & REEL, Pb free
8-pin 150-mil SOIC-TUBE, Pb free
Industrial
8-pin 150-mil SOIC-TAPE & REEL, Pb free
8-pin 150-mil SOIC-TUBE, Pb free
Commercial
Commercial
Industrial
8-pin 150-mil SOIC-TAPE & REEL, Pb free
8-pin 150-mil SOIC-TUBE, Pb free
Industrial
3.3 ‘SpreadTrak’ Zero Delay Buffer
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Notice: The information in this document is subject to change without notice.
November 2006
rev 1.4
ASM5P23S04A
Ordering Codes (Contd…)
Ordering Code
Marking
Package Type
Temperature
ASM5P23S04AG-1-08-SR
ASM5P23S04AG-1-08-ST
ASM5I23S04AG-1-08-SR
ASM5I23S04AG-1-08-ST
5P23S04AG-1
5I23S04AG-1
5P23S04AG-1
5I23S04AG-1
8-pin 150-mil SOIC-TAPE & REEL, Green
8-pin 150-mil SOIC-TUBE, Green
Commercial
Commercial
Industrial
8-pin 150-mil SOIC-TAPE & REEL, Green
8-pin 150-mil SOIC-TUBE, Green
Industrial
ASM5P23S04AG-1H-08-SR 5P23S04AG-1H
8-pin 150-mil SOIC-TAPE & REEL, Green
8-pin 150-mil SOIC-TUBE, Green
Commercial
Commercial
Industrial
ASM5P23S04AG-1H-08-ST
ASM5I23S04AG-1H-08-SR
ASM5I23S04AG-1H-08-ST
ASM5P23S04AG-2-08-SR
ASM5P23S04AG-2-08-ST
ASM5I23S04AG-2-08-SR
ASM5I23S04AG-2-08-ST
5I23S04AG-1H
5P23S04AG-1H
5I23S04AG-1H
5P23S04AG-2
5I23S04AG-2
5P23S04AG-2
5I23S04AG-2
8-pin 150-mil SOIC-TAPE & REEL, Green
8-pin 150-mil SOIC-TUBE, Green
Industrial
8-pin 150-mil SOIC-TAPE & REEL, Green
8-pin 150-mil SOIC-TUBE, Green
Commercial
Commercial
Industrial
8-pin 150-mil SOIC-TAPE & REEL, Green
8-pin 150-mil SOIC-TUBE, Green
Industrial
ASM5P23S04AG-2H-08-SR 5P23S04AG-2H
8-pin 150-mil SOIC-TAPE & REEL, Green
8-pin 150-mil SOIC-TUBE, Green
Commercial
Commercial
Industrial
ASM5P23S04AG-2H-08-ST
ASM5I23S04AG-2H-08-SR
ASM5I23S04AG-2H-08-ST
5I23S04AG-2H
5P23S04AG2H
5I23S04AGH
8-pin 150-mil SOIC-TAPE & REEL, Green
8-pin 150-mil SOIC-TUBE, Green
Industrial
3.3 ‘SpreadTrak’ Zero Delay Buffer
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Notice: The information in this document is subject to change without notice.
November 2006
rev 1.4
ASM5P23S04A
Device Ordering Information
A S M 5 P 2 3 S 0 4 A F - 0 8 T R
R = Tape & Reel, T = Tube or Tray
O = SOT
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
D = QSOP
X = SC-70
Q = QFN
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE, LEAD FREE, and RoHS
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(0C to +70C)
(-40C to +125C) (-40C to +85C)
1 = Reserved
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
PulseCore Semiconductor Mixed Signal Product
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
3.3 ‘SpreadTrak’ Zero Delay Buffer
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Notice: The information in this document is subject to change without notice.
November 2006
rev 1.4
ASM5P23S04A
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200
Campbell, CA 95008
Copyright © PulseCore Semiconductor
All Rights Reserved
Part Number: ASM5P23S04A
Document Version: 1.4
Tel: 408-879-9077
Fax: 408-879-9018
www.pulsecoresemi.com
Note: This product utilizes US# 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
© Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or
registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their
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notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein
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3.3 ‘SpreadTrak’ Zero Delay Buffer
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Notice: The information in this document is subject to change without notice.
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