PT6302LQ-007 [PTC]
VFD Driver/Controller IC with Character RAM; VFD驱动器/控制器IC的字符RAM
| 型号： | PT6302LQ-007 |
| 厂家： | 
PRINCETON TECHNOLOGY CORP |
| 描述： | VFD Driver/Controller IC with Character RAM |
| 文件： | 总27页 (文件大小：1123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PT6302
VFD Driver/Controller IC with Character RAM
DESCRIPTION
FEATURES
PT6302 is a dot matrix VFD Driver/Controller IC
utilizing CMOS Technology specially designed to
display characters, numerals, and symbols. PT6302
provides 35 dot matrix, 2 additional segment drivers
and 16 grid drivers. 248 types of character data
(CGROM), 8 types of character data (CGRAM), 16
display digits x 2 bits symbol data, 16 display digits x 8
bits register for character data display and 2 general
output bits for static operation are provided. Pin
assignments and application circuit are optimized for
easy PCB layout and cost saving advantages.
•
•
•
•
•
CMOS technology
Logic power supply: VDD=3.3V 10% or 5.0V 10%
VFD drive power supply: VEE=-20V to -35V
Built-in oscillation circuit (External RC)
One-byte instruction execution (not including Data
Write to RAM)
•
•
Microcontroller interface
Display contents:
- Character generator ROM (CGROM): 5x7 Dots
(248 Character data types)
- Character generator RAM (CGRAM): 5x7 Dots (8
Character data types)
- Additional data RAM (ADRAM): 16 Display digits
x 2 Bits (Symbol data)
- Data control RAM (DCRAM): 16 Display digits x 8
Bits (Character data display register)
- General output port: 2 bits (Static operation)
Display control function:
APPLICATIONS
•
•
Microcontroller peripheral device
Audio/Video equipment
•
- Display digits: 9 to 16 digits
- Display duty (Contrast adjustment): 8 stages
- All display lights: ON/OFF mode
BLOCK DIAGRAM
Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan
PT6302
APPLICATION CIRCUIT
V2.1
2
August 2010
PT6302
ORDER INFORMATION
Valid Part Number
PT6302LQ-001
PT6302LQ-002
PT6302LQ-003
PT6302LQ-005
PT6302LQ-006
PT6302LQ-007
Package Type
64 pins, LQFP
64 pins, LQFP
64 pins, LQFP
64 pins, LQFP
64 pins, LQFP
64 pins, LQFP
Top Code
PT6302LQ-001
PT6302LQ-002
PT6302LQ-003
PT6302LQ-005
PT6302LQ-006
PT6302LQ-007
PIN CONFIGURATION
PIN DESCRIPTION
Pin Name
I/O
Description
Segment driver output pin
Pin No.
SG5 to SG35
SG4 to SG1
GR1 to GR16
VEE
1 ~ 31
64 ~ 61
32 ~ 47
48
O
O
-
Grid driver output pin
Power supply
VSS
-
Ground pin
49
OSCI
OSCO
I
O
Oscillator input pin
Oscillator output pin
Reset input pin
When this pin is set to "LOW", all functions are initialized.
Chip select input pin
When this pin is set to "High" Level, the serial data transfer is
disabled.
Shift clock input pin
50
51
RSTB
I
I
I
52
53
54
CSB
CLKB
The serial data is shifted at the rising edge of CLKB.
DIN
VDD
I
-
Serial data input pin
Positive power supply
55
56
P1 to P2
AD2 to AD1
O
O
General purpose output pin
Segment driver output pin
57 ~ 58
59 ~ 60
V2.1
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August 2010
PT6302
INPUT & OUTPUT CONFIGURATION
LOGIC INPUT PINS
LOGIC OUTPUT PINS
DRIVER OUTPUT PINS
V2.1
4
August 2010
PT6302
FUNCTION DESCRIPTION
OSCILLATION CIRCUIT
An oscillation circuit may be constructed by connecting external Resistor (R1) and Capacitor (C1) between the oscillator
pins -- OSCO and OSCI. The RC time constant depends on the value of VDD voltage used. The target oscillation
frequency is 2MHz. Please refer to the diagram below.
RESET FUNCTION
The Reset Function is enabled when the RSTB Pin is set to "Low" Level. All functions are initialized. The initial status of
the various functions is given below:
1. Address of each RAM: Address "00"H
2. Data of each RAM: All contents are undefined.
3. General Output Ports: All General Output Ports are set to "LOW".
4. Display Digit: 16 Digits
5. Contrast Adjustment: 8/16
6. All Display Lights: OFF Mode
7. Segment Output: All Segment Outputs are set to "LOW".
8. AD Output: All AD Outputs are set to "LOW".
The RSTB Pin may be connected to either the microcontroller or an external Resistor and capacitor. For an external RC
connection, please refer to the diagram below.
V2.1
5
August 2010
PT6302
After reset, the PT6302 must be set according to the Initial Setting Flowchart shown below.
V2.1
6
August 2010
PT6302
RELATIONSHIP BETWEEN SEGMENT DRIVERS SGN AND ADN (ONE
DIGIT)
The following diagram best describes the relationship between the Segment Drivers -- SGn and ADn.
C0 AD1
C1 AD2
C0
DATA IS WRITTEN BY ADRAM.
THIS CORRESPONDS TO THE 2ND BYTE
C1
SG2
C6
C2
SG3
C7
C3
SG4
C8
C4
SG5
C9
SG1
C5
SG6
C10
SG7
C11
SG8
C12
SG9
C13
SG10
C14
SG11
C15
SG12
C16
SG13
C17
SG14
C18
SG15
C19
SG16
C20
SG17
C21
SG18
C22
SG19
C23
SG20
C24
SG21
C25
SG22
C26
SG23
C27
SG24
C28
SG25
C29
SG26
C30
SG27
C31
SG28
C32
SG29
C33
SG30
C34
SG31
SG32
SG33
SG34
SG35
DATA IS WRIITEN BY THE CGRAM
THIS CORRESPONDS TO THE 6TH
DATA IS WRITTEN BY THE
CGRAM. THIS CORRESPONDS
TO THE 2ND BYTE
DATA IS WRITTEN BY THE CGRAM
THIS CORRESPONDS TO THE 5TH
DATA IS WRIITEN BY THE CGRAM THIS
CORRESPONDS TO THE 3RD BYTE.
DATA IS WRITTEN BY THE CGRAM
THIS CORRESPONDS TO THE 4TH
DATA TRANSFER
The Display Control Command and the data are written by an 8-bit serial data transfer. Please refer to the Write Timing
Diagram below.
Note: When data is written into the RAM (DCRAM, ADRAM, CGRAM) in a continuous manner, the address are automatically incremented. Therefore
it is not necessary to specify the first byte of the 2nd and later bytes when writing the RAM data.
When the CSB pin is set to "LOW" Level, data transfer operation is enabled. 8 bits of data are sequentially inputted into
the DIN Pin (LSB first). The shift clock is inputted into CLKB pin and the shift register reads the data at rising edge of the
shift clock. The internal load signals are automatically generated and the data is written to each register and RAM. Thus,
it is not necessary to input load signals externally.
When the CSB Pin is set to "HIGH" Level, the data transfer operation is disabled. The data input when the CSB Pin
changes from "HIGH" to "LOW" is recognized in 8-bit units.
V2.1
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August 2010
PT6302
COMMANDS
The following are the list of commands issued by PT6302. When data is written into the RAM (DCRAM, CGRAM, or
ADRAM) in a continuous manner, the addresses are automatically incremented internally. It is therefore not necessary
to specify the first byte.
LSB
B0 B1 B2
FIRST BYTE
MSB LSB
SECOND BYTE
MSB
B7
NO.
COMMAND
B3
B4 B5
B6 B7
B0
B1
B2
B3
B4
B5
B6
1
DCRAM DATA WRITE
X0 X1
X2
X3
1
0
0
0
C0
C1
C2
C3
C4
C5
C6
C7
2ND
BYTE
3RD
BYTE
4TH
BYTE
5TH
BYTE
6TH
BYTE
C0
C1
C2
C3
C5
C6
C7
C8
C10 C15 C20 C25 C30
C11 C16 C21 C26 C31
C12 C17 C22 C27 C32
C13 C18 C23 C28 C33
C14 C19 C24 C29 C34
*
*
*
*
2
CGRAM DATA WRITE
X0 X1
X2
*
0
1
0
0
C4
C0
C9
C1
*
*
3
4
ADRAM DATA WRITE
GENERAL OUTPUT
PORT SET
X0 X1
P1 P2
X2
*
X3
*
1
0
1
0
0
1
0
0
*
*
*
*
*
5
6
7
DISPLAY DUTY SET
NO. OF DIGITS SET
ALL LIGHTS ON/OFF
TEST MODE
D0 D1 D2
*
*
*
*
1
0
1
0
0
1
1
0
1
1
1
0
0
0
0
1
K0 K1
K2
*
L
0
H
0
0
Notes:
1. The Test Mode is not a user function, but an IC internal function
2. *=Not relevant
3. Xn=RAM address bit, n = 0 to 3
4. Cn=RAM character code bit, n=0 to 34
5. Pn=General output port status bit, n=1 to 2
6. Dn=Display duty bit, n=0 to 2
7. Kn=Number of digits bit, n=0 to 2
8. H=All lights on
9. L=All lights off
DATA CONTROL RAM (DCRAM) DATA WRITE COMMAND
The DCRAM Data Write Command is used to specify the address of the DCRAM and writes the character code of the
CGROM and CGRAM. The DCRAM consists of 4 address bits which are used to store the CGRAM & CGROM character
codes. The character codes specified by the DCRAM is converted to a 5 x 7 dot matrix character pattern via the CGROM
and CGRAM. The DCRAM can store up to 16 characters. The DCRAM Data Write Command Format is shown below.
LSB
B0
MSB
DCRAM Data Write Mode is selected and the
DCRAM Address is specified. (i.e. DCRAM Address =
0H)
B1
X1
B2
X2
B3
X3
B4
1
B5
0
B6 B7
1st Byte
(1st)
X0
0
0
LSB
B0
MSB
CGROM & CGRAM Character Codes are specified.
(They are written into the DCRAM Address 0H)
2nd Byte
(2nd)
B1
C1
B2
C2
B3
C3
B4
C4
B5
C5
B6 B7
C6 C7
C0
During a continuous data write operation from one DCRAM Address to the next, it is not necessary to specify the
DCRAM address since they are automatically incremented; however, the character code must be specified. Please refer
to the information below.
LSB
B0
MSB
Character Code of CGRAM & CGROM are specified and
written into the DCRAM Address 1H.
2nd Byte
(3rd)
B1
C1
B2
C2
B3
C3
B4
C4
B5
C5
B6 B7
C0
C6 C7
V2.1
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August 2010
PT6302
LSB
B0
MSB
B7
B1 B2
C1 C2
B3
C3
B4
C4
B5
C5
B6
Character Code of CGRAM & CGROM are specified and
written into the DCRAM Address 2H.
2nd Byte
(4th)
C0
C6 C7
:
:
LSB
B0
MSB
B1
C1
B2
C2
B3
C3
B4
C4
B5
C5
B6 B7
Character Code of CGRAM & CGROM are specified and
written into the DCRAM Address FH.
2nd Byte
(17th)
C0
C6 C7
LSB
B0
MSB
B6 B7
Character Code of CGRAM & CGROM are specified and
rewritten into the DCRAM Address 0 H.
2nd Byte
(18th)
B1
C1
B2
C2
B3
C3
B4
C4
B5
C5
C0
C6 C7
where:
1. X0 (LSB) to X3 (MSB): DCRAM Address Bits (16 Characters)
2. C0 (LSB) to C7 (MSB): CGROM & CGRAM Character Code Bits (256 Characters)
Please refer to the table below for the GRID position and DCRAM Address setting relationship.
Hex
0
1
2
3
4
5
6
7
X0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
GRID Position
GR1
GR2
GR3
GR4
GR5
GR6
GR7
GR8
GR9
GR10
GR11
GR12
GR13
GR14
GR15
GR16
8
9
A
B
C
D
E
F
V2.1
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August 2010
PT6302
CGRAM DATA WRITE COMMAND
The Character Generator RAM (CGRAM) Data Write Command is used to specify the CGRAM address (00H to 07H)
and write the character pattern data. It consists of 3 address bits which is used to store the 5 x 7 dot matrix character
patterns. The CGRAM can store up to 8 types of character patterns which may be displayed by specifying the Character
Code (DCRAM Address). The CGRAM Data Write Command Format is given below.
LSB
B0
MSB
CGRAM Data Write Mode is selected and the CGRAM
Address is specified (i.e. CGRAM Address = 00H).
1st Byte
(1st)
B1
X1
B2
X2
B3
*
B4
0
B5
1
B6 B7
X0
0
0
LSB
MSB
2nd Byte
(2nd)
1st Column Data is specified and rewritten into the
CGRAM Address 00H.
B0
C0
B1
B2
B3
B4
B5
B6 B7
C5 C10 C15 C20 C25 C30
*
LSB
MSB
3rd Byte
(3rd)
2nd Column Data is specified and rewritten into the
CGRAM Address 00H.
B0
C1
B1
B2
B3
B4
B5
B6 B7
C6 C11 C16 C21 C26 C31
*
LSB
B0
MSB
B7
*
4th Byte
(4th)
3rd Column Data is specified and rewritten into the
CGRAM Address 00H.
B1
B2
B3
B4
B5
B6
C2 C7 C12 C17 C22 C27 C32
LSB
B0 B1
MSB
B2
B3
B4
B5
B6
B7
*
5th Byte
(5th)
4th Column Data is specified and rewritten into the
CGRAM Address 00H.
C3 C8 C13 C18 C23 C28 C33
LSB
MSB
B0
C4
B1
C9
B2
B3
B4
B5
B6
B7
*
6th Byte
(6th)
5th Column Data is specified and rewritten into the
CGRAM Address 00H.
C14
C19
C24
C29
C34
During a continuous data write operation from one CGRAM Address to the next, it is not necessary to specify the
CGRAM address since they are automatically incremented; however, the character pattern data must be specified. The
2nd to the 6th character pattern data byte are considered as one data item, therefore 300ns is sufficient value for
parameter tDOFF between bytes. Please refer to the information below.
LSB
B0
MSB
B7
*
B1
C5
B2
B3
B4
B5
B6
2nd Byte
(7th)
1st Column Data is specified and rewritten into the
CGRAM Address 01H.
C0
C10
C15
C20 C25
C30
:
:
LSB
MSB
B0
C4
B1
C9
B2
B3
B4
B5
B6
B7
*
6th Byte
(11th)
5th Column Data is specified and rewritten into the
CGRAM Address 01H.
C14
C19
C24 C29 C34
where:
1. X0 (LSB) to X2 (MSB): CGRAM Address Bits (8 Characters)
2. C0 (LSB) to C34 (MSB): Character Pattern Data Bits (35 outputs/digit)
V2.1 10
August 2010
PT6302
Please refer below for the CGROM Address and CGRAM Address Setting relationship.
HEX
00
01
02
03
04
05
06
07
X0
0
1
0
1
0
1
0
1
X1
0
0
1
1
0
0
1
1
X2
0
0
0
0
1
1
1
1
CGROM Address
RAM00(00000000B)
RAM01(00000001B)
RAM02(00000010B)
RAM03(00000011B)
RAM04(00000100B)
RAM05(00000101B)
RAM06(00000110B)
RAM07(00000111B)
The CGROM and CGRAM output area placement is given in the table below.
C0
C5
C1
C6
C2
C7
C3
C8
C4
C9
C10
C15
C20
C25
C30
C11
C16
C21
C26
C31
C12
C17
C22
C27
C32
C13
C18
C23
C28
C33
C14
C19
C24
C29
C34
Area corresponds to the 6th Byte (5th Column)
Area corresponds to the 5th Byte (4th Column)
Area corresponds to the 4th Byte (3rd Column)
Area corresponds to the 3rd Byte (2nd Column)
Area corresponds to the 2nd Byte (1st Column)
Note: The Character Generator ROM (CGROM) consists of 8 CGROM Address bits generating 5 x 7 dot matrix character patterns. It can store up to a
maximum of 248 types of character patterns.
V2.1
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August 2010
PT6302
ADRAM DATA WRITE COMMAND
The Additional Data RAM (ADRAM) consists of 4 address bits used to store the symbol data. It can store up to 2 types of
symbol patterns per digit. The symbol data specified by the ADRAM is directly outputted. The terminals to which the
ADRAM data are outputted may be used as a cursor. The ADRAM command format is given below.
LSB
MSB
B7
0
1st Byte
(1st)
ADRAM Data Write Mode is selected and the
ADRAM address is specified. (i.e. ADRAM Address
= 0H)
B0
X0
B1
X1
B2
X2
B3
X3
B4
1
B5
1
B6
0
LSB
MSB
B7
*
2nd Byte
(2nd)
Symbol Data is specified and written into the ADRAM
Address 0H.
B0
C0
B1
C1
B2
B3
*
B4
*
B5
*
B6
*
*
During a continuous data write operation from one ADRAM Address to the next, it is not necessary to specify the
ADRAM address since they are automatically incremented; however, the symbol data must be specified. Please refer to
the information below.
LSB
MSB
B7
*
2nd Byte
(3rd)
Symbol Data is specified and written into the ADRAM
Address 1H.
B0
C0
B1
C1
B2
*
B3
*
B4
*
B5
*
B6
*
LSB
MSB
B7
*
2nd Byte
(4th)
Symbol Data is specified and written into the ADRAM
Address 2H.
B0
C0
B1
C1
B2
*
B3
*
B4
*
B5
*
B6
*
:
:
LSB
MSB
B7
*
2nd Byte
(17th)
Symbol Data is specified and written into the ADRAM
Address FH.
B0
C0
B1
C1
B2
*
B3
*
B4
*
B5
*
B6
*
LSB
MSB
B7
*
2nd Byte
(18th)
Symbol Data is specified and rewritten into the
ADRAM Address 0H.
B0
C0
B1
C1
B2
B3
B4
*
B5
*
B6
*
*
*
where:
1. X0 (LSB) to X3 (MSB): ADRAM address bits (16 Characters)
2. C0 (LSB) to C1 (MSB): Symbol data bits (2 symbol data per digit)
V2.1
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August 2010
PT6302
Please refer to the table below for the GRID and ADRAM Address relationship.
HEX
0
1
2
3
4
5
6
7
X0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
GRID Position
GR1
GR2
GR3
GR4
GR5
GR6
GR7
GR8
GR9
GR10
GR11
GR12
GR13
GR14
GR15
GR16
8
9
A
B
C
D
E
F
GENERAL OUTPUT PORT SET COMMAND
The General Output Port Set Command is used to specify the general output port status. The general output port is used
to control other input/output devices as well as turn on the LED Display. When the general output port is set to "HIGH",
the output is equivalent to the VDD voltage. When the general output port is set to "LOW" Level, the output becomes
ground potential. The command format is given below.
LSB
MSB
B5
A General Output Port is selected and the output
status is specified.
B0
P1
B1
P2
B2
*
B3
*
B4
0
B6
1
B7
0
1st Byte
where:
0
1. P1, P2: General output port
2. *=Not relevant
The following table shows the data setting in relation to the Status of the General Output Port
P1
0
1
P2
0
0
General Output Port Display Status
P1 ="LOW", P2="LOW" (see note 1)
P1="HIGH", P2="LOW"
0
1
P1="LOW", P2="HIGH"
1
1
P1="HIGH", P2="HIGH"
Note: The state when the power is applied or when the RSTB is inputted.
V2.1
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August 2010
PT6302
DISPLAY DUTY SET COMMAND
The Display Duty Set Command is used to write the display duty value to the duty cycle register. Using a 3-bit data, the
display duty adjusts the contrast in 8 stages. When the power is turned ON or when the RSTB signal is inputted, the duty
cycle register value is set to "0". It is advisable to always execute this command before turning on the display, after which
the desired duty value may be set. The command format is given below.
LSB
MSB
B7
0
1st Byte
Display Duty Set Mode is selected and the duty value
is specified.
B0
D0
B1
D1
B2
D2
B3
*
B4
1
B5
0
B6
1
where:
1. D0 (LSB) to D2 (MSB): Display duty data bits (8 stages)
2. *=Not relevant
The Relationship between the Setup Data and the Controlled GRID Duty is given in the table below.
HEX
D2
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
GRID Duty
8/16
The state when the Power is turned ON or when
the RSTB signal is inputted
0
1
2
3
4
5
6
7
9/16
10/16
11/16
12/16
13/16
14/16
15/16
NUMBER OF DIGITS SET COMMAND
The Number of Digits Set Command is used to write the number of display digits into the display digit register. Using a
3-bit data, the Number of Digits Set Command can display 9 to 16 digits. When the power is turned ON or when the
RSTB signal is inputted, the value is set to "0". It is advisable to always execute this command before the turning on the
display. The command format is given below.
LSB
MSB
B7
0
1st Byte
The Number of Digits Set Mode is selected and the
number of digit value is specified.
B0
K0
B1
K1
B2
K2
B3
*
B4
0
B5
1
B6
1
The table below shows the relationship between the setup data and the controlled GR.
HEX
K2
0
0
0
0
1
1
1
1
K1
0
0
1
1
0
0
1
1
K0
0
1
0
1
0
1
0
1
Number of Digits of GR
GR1 ~ GR16
GR1 ~ GR9
The state when the Power is turned ON or
when the RSTB signal is inputted.
0
1
2
3
4
5
6
7
GR1 ~ GR10
GR1 ~ GR11
GR1 ~ GR 12
GR1~ GR13
GR1~ GR14
GR1~ GR15
V2.1
14
August 2010
PT6302
DISPLAY LIGHT SET COMMAND
The Display Light Set Command is used to turn all display lights ON or OFF. All Display Lights ON Mode is primarily
used for testing the display. The All Display Light OFF Mode is used for the blinking display and to prevent any
malfunction when the power is turned ON. The general output port cannot be controlled by this command. The command
format is given below.
LSB
MSB
B0
L
B1
H
B2
*
B3
*
B4
1
B5
1
B6
1
B7
0
1st Byte
where:
The Display Light Set Command is selected.
1. L=All display lights are turned off
2. H=All display lights are turned on
3. *=Not relevant
The table below shows the SG and AD Display Status in relation to the Display Light Set Command data.
L
0
1
0
1
H
0
0
1
1
SG and AD Display State
Normal Display Mode
All Outputs ="LOW"
All Outputs ="HIGH"
All Outputs = "HIGH"
The state when the power is applied or when the RSTB
signal is inputted
All Display Light ON Mode has the first priority.
RECOMMENDED SOFTWARE FLOWCHART
Notes:
1. Display light active mode (ex. 0111XX00B)
2. Test mode off (ex. 1000X000B)
V2.1
15
August 2010
PT6302
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply voltage 1
Symbol
VDD
VEE
VIN
Condition
Rating
-0.3 to 6.5
-35 to VDD+0.3
-0.3 to VDD+0.3
541
Unit
V
V
-
Supply voltage 2
Input voltage
-
-
V
Ta ≤ 25℃
GR1 to GR16
AD1 to AD2
SG1 to SG35
P1 to P2
-
Power dissipation
Output current 1
Output current 2
Output current 3
Output current 4
Operating temperature
Storage temperature
PD
IO1
IO2
IO3
IO4
Topr
Tstg
mW
mA
mA
mA
mA
℃
-40 to 0
-20 to 0
-10 to 0
-4.0 to 4.0
-40 to +85
℃
-
-65 to +150
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
Min.
4.5
Typ.
5.0
3.3
-
Max.
5.5
3.6
-20
-20
Unit
V
V
V
V
Supply voltage 1
VDD
3.0
Power supply voltage=5V
Power supply voltage=3.3V
Power supply voltage=5V
All input pins except OSCI.
Power supply voltage=3.3V
All input pins except OSCI.
Power supply voltage=5V
All input pins except OSCI.
Power supply voltage=3.3V
All input pins except OSCI.
Power supply voltage=5V
Power supply voltage=3.3V
Power supply voltage=5V
R1=3.3KΩ, C1=47pF
-35
-35
Supply voltage 2
VEE
VIH
-
0.7VDD
-
-
-
-
-
-
V
V
High level input
voltage
0.8VDD
-
-
0.3VDD
0.2VDD
V
V
Low level input
voltage
VIL
fc
-
-
-
-
1.0
1.0
MHz
MHz
CLKB frequency
1.5
1.5
2.0
2.0
2.5
2.5
MHz
MHz
Hz
Oscillation frequency
fosc
Power supply voltage=3.3V
R1=3.3KΩ, C1=39pF
Power supply voltage=5V
DIGIT=1 to 16, R1=3.3KΩ, C1=47pF
Power supply voltage=3.3V
DIGIT=1 to 16, R1=3.3KΩ, C1=39pF
Power supply voltage=5V
Power supply voltage=3.3V
Power supply voltage=5V
183
183
244
244
305
305
Frame frequency
RSTB input time
fFR
Hz
200
200
-40
-40
-
-
-
-
-
-
85
85
tRSON
Topr
µs
℃
℃
Operating
temperature
Power supply voltage=3.3V
V2.1
16
August 2010
PT6302
DC ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, VEE=-35V, Ta=-40 to +85℃)
Parameter
Symbol
Condition
Min.
Max.
Unit
VDD=5.0 10%
CSB, CLKB, DIN, RSTB
0.7VDD
-
V
High level input voltage
VIH
VDD=3.3 10%
0.8VDD
-
-
V
V
CSB, CLKB, DIN, RSTB
VDD=5.0 10%
CSB, CLKB, DIN, RSTB
0.3VDD
Low level input Voltage
High level input current
Low level input current
VIL
VDD=3.3 10%
CSB, CLKB, DIN, RSTB
VDD=5.0 10%
CSB, CLKB, DIN, RSTB; VIH=VDD
VDD=3.3 10%
CSB, CLKB, DIN, RSTB; VIH=VDD
VDD=5.0 10%
CSB, CLKB, DIN, RSTB; VIL=0V
VDD=3.3 10%
CSB, CLKB, DIN, RSTB; VIL=0V
VDD=5.0 10%
GR1 to GR16; IOH=-30mA
VDD=3.3 10%
GR1 to GR16; IOH=-30mA
VDD=5.0 10%
AD1 to AD2, IOH=-15mA
VDD=3.3 10%
AD1 to AD2, IOH=-15mA
VDD=5.0 10%
SG1 to SG35, IOH=-6mA
VDD=3.3 10%
SG1 to SG35, IOH=-6mA
VDD=5.0 10%
P1 to P2, IOH=-5mA
VDD=3.3 10%
P1 to P2, IOH=-2.5mA
VDD=5.0 10%
GR1 to GR16, AD1 to AD2,SG1 to SG35
VDD=3.3 10%
GR1 to GR16, AD1 to AD2; SG1 to SG35
VDD=5.0 10%
-
0.2VDD
V
-1.0
1.0
µA
µA
µA
µA
V
IIH
-1.0
1.0
-1.0
1.0
IIL
-1.0
1.0
VDD-1.5
VDD-1.5
VDD-1.5
VDD-1.5
VDD-1.5
VDD-1.5
VDD-1.0
VDD-1.0
-
-
-
-
-
-
-
-
-
High level output voltage 1
High level output voltage 2
High level output voltage 3
High level output voltage 4
Low level output voltage 1
Low level output voltage
VOH1
V
V
VOH2
V
VOH3
V
V
V
VOH4
VOL1
VOL2
V
VEE+1.0
VEE+1.0
1.0
V
V
V
V
-
-
P1, P2, IOL=15mA
VDD=3.3 10%
P1, P2, IOL=7.5mA
1.0
VDD=5.0 10%
-
-
-
-
4
3
3
2
mA
mA
mA
mA
VDD, fosc=2MHz, No Load
Duty 15/16, DIGIT 1 to 16; All outputs lights ON
VDD=3.3 10%
VDD, fosc=2MHz, No Load
Duty 15/16, DIGIT 1 to 16; All outputs lights ON
VDD=5.0 10%
VDD, fosc=2MHz, No Load
Duty 8/16, DIGIT 1 to 9; All outputs lights OFF
VDD=3.3 10%
VDD, fosc=2MHz, No Load
Duty 8/16, DIGIT 1 to 9; All outputs lights OFF
Current consumption 1
Current consumption 2
IDD1
IDD2
V2.1
17
August 2010
PT6302
AC CHARACTERISTICS
(Unless otherwise specified, VEE=-35V, Ta=-40 to +85℃)
Parameter
Symbol
Condition
VDD=5.0V+10%
Min.
1.0
Max.
Unit
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
-
-
-
-
-
CLKB cycle time
fc
VDD=3.3V+10%
VDD=5.0V+10%
VDD=3.3V+10%
VDD=5.0V+10%
VDD=3.3V+10%
VDD=5.0V+10%
VDD=3.3V+10%
VDD=5.0V+10%
VDD=3.3V+10%
1.0
300
300
300
300
300
300
300
300
CLKB pulse width
DIN setup time
DIN hold time
tCW
tDS
tDH
CSB setup time
tCSS
VDD=5.0V+10%
R1=3.3KΩ, C1=47pF
16
16
-
-
µs
µs
CSB hold time
tCSH
tCSW
tDOFF
VDD=3.3V+10%
R1=3.3KΩ, C1=39pF
VDD=5.0V+10%
VDD=3.3V+10%
300
300
-
-
ns
ns
CSB wait time
VDD=5.0V+10%
R1=3.3KΩ, C1=47pF
8
8
-
-
µs
µs
Data processing time
VDD=3.3V+10%
R1=3.3KΩ, C1=39pF
VDD=5.0V+10%
When the RSTB signal is externally
inputted from the microcontroller.
300
300
-
-
ns
ns
RSTB pulse width
DIN wait time
tWRSTB
VDD=3.3V+10%
When the RSTB signal is externally
inputted from the microcontroller.
VDD=5.0V+10%
VDD=3.3V+10%
300
300
-
-
ns
ns
tRSOFF
VDD=5.0V+10%
Ci=100pF, tR=20% to 80%
-
-
4.0
4.0
4.0
4.0
-
µs
µs
µs
µs
tR
VDD=3.3V+10%
Ci=100pF, tR=20% to 80%
All outputs slew rate
VDD=5.0V+10%
Ci=100pF, tF=80% to 20%
-
tF
VDD=3.3V+10%
Ci=100pF, tF=80% to 20%
-
VDD=5.0V+10%
Mounted in the Unit
100
100
5.0
VDD rise time
VDD off time
tPRZ
µs
VDD=3.3V+10%
Mounted in the Unit
-
VDD=0V
Mounted in the Unit
tPOF
-
ms
V2.1
18
August 2010
PT6302
TIMING CHARACTERISTICS
Parameter
Symbol
VIH
VDD=3.3V 10%
0.8VDD
VDD=5.0 10%
High level input voltage
Low level input voltage
0.7VDD
0.3VDD
VIL
0.2VDD
DATA TIMING
RESET (RSTB) TIMING
OUTPUT TIMING
DIGIT OUTPUT TIMING (16-DIGIT DISPLAY, DUTY= 15/16)
where: T=8/fosc
V2.1
19
August 2010
PT6302
PT6302-001 CHARACTER FONT TABLE
V2.1
20
August 2010
PT6302
PT6302-002 CHARACTER FONT TABLE
V2.1
21
August 2010
PT6302
PT6302-003 CHARACTER FONT TABLE
V2.1
22
August 2010
PT6302
PT6302-005 CHARACTER FONT TABLE
V2.1
23
August 2010
PT6302
PT6302-006 CHARACTER FONT TABLE
V2.1
24
August 2010
PT6302
PT6302-007 CHARACTER FONT TABLE
V2.1
25
August 2010
PT6302
PACKAGE INFORMATION
64 PINS, LQFP
Symbol
Min.
-
0.05
1.35
0.30
0.09
Nom.
-
Max.
1.60
0.15
1.45
0.40
0.16
A
A1
A2
b
-
1.40
0.35
-
c
D
D1
E
E1
e
L
16.00 BSC
14.00 BSC
16.00 BSC
14.00 BSC
0.80 BSC
0.60
0.45
0.75
L1
θ
1.00 REF.
3.5°
0°
7°
Notes:
1. All dimensions are in millimeter
2. Refer to JEDEC MS-022 BE
V2.1
26
August 2010
PT6302
IMPORTANT NOTICE
Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and to discontinue any product without notice at any time.
PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No
circuit patent licenses are implied.
Princeton Technology Corp.
2F, 233-1, Baociao Road,
Sindian, Taipei 23145, Taiwan
Tel: 886-2-66296288
Fax: 886-2-29174598
http://www.princeton.com.tw
V2.1
27
August 2010
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