42672-00 [PSEMI]
SP7T UltraCMOS? 2.75 V Switch 100 - 3000 MHz, +68 dBM IIP3; SP7T的UltraCMOS ？ 2.75 V开关100 - 3000兆赫， 68为dBM IIP3
| 型号： | 42672-00 |
| 厂家： | 
Peregrine Semiconductor |
| 描述： | SP7T UltraCMOS? 2.75 V Switch 100 - 3000 MHz, +68 dBM IIP3 |
| 文件： | 总4页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advance Information
PE42672 DIE
SP7T UltraCMOS™ 2.75 V Switch
100 – 3000 MHz, +68 dBM IIP3
Figure 1. Functional Diagram
Features
• Dedicated TX1 port for WCDMA, TX2
and TX3 ports for GSM/EDGE
• Three pin CMOS logic control with
integral decoder/driver
• Exceptional harmonic performance:
2fo = -84 dBc and 3fo = -77 dBc
• Low TX insertion loss: 0.50 dB at
900 MHz, 0.70 dB at 1900 MHz
• TX – RX Isolation of 44 dB at 900 MHz,
38 dB at 1900 MHz
TX1
TX2
RX1
RX2
WCDMA
GSM/EDGE
RX3
RX4
TX3
GSM/EDGE
• 1500 V HBM ESD tolerance all ports
• +68 dBm IIP3
CMOS
Control/Driver
and ESD
• -111 dBm IMD3
• No blocking capacitors required
V1
V2
V3
Product Description
Figure 2. Die Top View*
TX1
The PE42672 is a HaRP™-enhanced SP7T
RF Switch developed on the UltraCMOS™
process technology. It addresses the specific
design needs of the Quad-Band GSM Handset
Antenna Switch Module Market for use in
GSM/EDGE/PCS/DCS/WCDMA handsets.
The switch is comprised of three TX ports and
four RX ports. TX1 is designed for WCDMA
and TX2 and TX3 are designed for GSM/
EDGE. The four symmetric RX ports can be
used for GSM/EDGE/PCS RX. On-chip CMOS
decoder logic facilitates three-pin low voltage
CMOS control, while high ESD tolerance of
1500 V at all ports, no blocking capacitor
requirements, and on-chip SAW filter over-
voltage protection devices make this the
ultimate in integration and ruggedness.
ANT RX1
GND
RX2
GND
TX2
GND
RX3
GND
RX4
GND
TX3
GND
GND
GND VDD
V3 GN V2 V1 GND
Peregrine’s HaRP™ technology
enhancements deliver high linearity and
exceptional harmonics performance. It is an
innovative feature of the UltraCMOS™
process, providing performance superior to
GaAs with the economy and integration of
conventional CMOS.
1006 µm
* Dimensions shown are drawn die size.
Document No. 70-0197-01 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Contact sales@psemi.com for full version of datasheet
Page 1 of 4
PE42672
Advance Information
Table 1. Target Electrical Specifications @ 25 °C, VDD = 2.75 V
Parameter
Condition
Typ
Units
TX - Ant (850 / 900)
TX - Ant (1800 / 1900)
TX - Ant ( 2200 UMTS )
RX - Ant (850 / 900)
RX - Ant (1800 / 1900)
0.5
0.7
0.8
0.8
1.0
dB
dB
dB
dB
dB
Insertion loss1
Return Loss
Isolation
Port under test in on state
20
dB
TX - RX (850 / 900)
TX - RX (1800 / 1900)
TX - TX (850 / 900)
TX - TX (1800 / 1900)
TX1 - RX (1900 / 2200)
44
38
29
23
37
dB
dB
dB
dB
dB
-84
-80
dBc
dBc
TX 850 / 900 MHz, +35 dBm output power, 50 Ω
TX 1800 / 1900 MHz, +33 dBm output power, 50 Ω
2nd Harmonic
-77
-73
dBc
dBc
TX 850 / 900 MHz, +35 dBm output power, 50 Ω
TX 1800 / 1900 MHz, +33 dBm output power, 50 Ω
3rd Harmonic
TX1 Measured at 2.14 GHz at Ant port, input +20 dBm CW signal
at 1.95 GHz and -15 dBm CW signal at 1.76 GHz
IMD3 distortion at 2.14 GHz
-111
dBm
Note: 1. Insertion loss specified with optimal impedance matching.
Table 2. Operating Ranges
Table 3. Absolute Maximum Ratings
Symbol
Parameter/Conditions
Min
Max
Units
Parameter
Symbol
Min
Typ Max Units
VDD
VI
Power supply voltage
Voltage on any input
-0.3
4.0
V
V
Temperature range
TOP
-40
+85
°C
V
-0.3 VDD+ 0.3
VDD Supply Voltage
VDD
2.65 2.75 2.85
TST
Storage temperature range
-65
+150
+38
+23
+35
°C
IDD Power Supply Current
(VDD = 2.75 V)
3,4
IDD
µA
13
50
TX input power (50 Ω)
PIN(50 Ω)
dBm
3,4
RX input power (50 Ω)
TX input power2
(VSWR ≤ 3:1)
PIN
PIN
+35
+20
dBm
dBm
dBm
V
P
IN (∞:1) TX input power (VSWR = ∞:1) 3,4
RX input power2
(VSWR =1:1)
ESD Voltage (HBM, MIL_STD
883 Method 3015.7)
1500
1700
VESD
Control Voltage High
Control Voltage Low
VIH
VIL
1.4
V
V
ESD Voltage at ANT Port
(IEC 61000-4-2)
V
0.4
Note: 3. Assumes RF input period of 4620 µs and duty cycle of 50%.
Note: 2. Assumes RF input period of 4620 µs and duty cycle of 50%.
4. VDD within operating range specified in Table 2.
Part performance is not guaranteed under these
conditions. Exposure to absolute maximum
conditions for extended periods of time may
adversely affect reliability. Stresses in excess of
absolute maximum ratings may cause permanent
damage.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0197-01 │ UltraCMOS™ RFIC Solutions
Page 2 of 4
Contact sales@psemi.com for full version of datasheet
PE42672
Advance Information
Table 4. Pin Descriptions
Figure 3. Pad Configuration (Top View)
Pin No.
Pin Name
Description
RF Common – Antenna
1
ANT
2
22
1
TX1
RX1
26
35
TX1
GND
TX2
GND
TX3
GND
GND
VDD
RF I/O - TX1
21
20
GND
RX2
GND
RX3
3
4
Ground (Requires two bond wires)
GND
TX2
19
18
46
RF I/O – TX2
PE42672
Die
55
Ground
5
6
17
16
GND
RX4
GND
TX3
65
RF I/O – TX3
15
14
GND
75
Ground
7
GND
GND
85
Ground
6
8
9
11
13
10
12
9
Supply
10
115
12
13
145
155
166
175
186
195
206
215
226
V3
Switch control input, CMOS logic level
GND
V2
Ground
Switch control input, CMOS logic level
Table 5. Truth Table
V1
Switch control input, CMOS logic level
Path
RX1 - ANT
RX2 - ANT
RX3 - ANT
RX4 - ANT
TX1 - ANT
TX2 - ANT
TX3 - ANT
All Off
V1
0
1
V2
0
0
V3
0
0
GND
GND
RX4
GND
RX3
GND
RX2
GND
RX1
Ground
Ground
0
1
0
RF I/O – RX4
Ground
1
1
0
0
1
0
0
1
1
RF I/O – RX3
Ground
0
1
1
1
1
1
RF I/O – RX2
Ground
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
RF I/O – RX1
Notes: 5. Bond wires should be physically short and connected to
ground plane for best performance.
6. Blocking capacitors needed only when non-zero DC
voltage present.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 6. Ordering Information
Order Code
Description
PE42672-DIE-D
Package
Film Frame
Shipping Method
42672-90
42672-99
42672-00
Wafer (Gross Die / Wafer Quantity)
400 Dice / Waffle Pack
1/ box
PE42672-DIE-400G
PE42672-DIE-1H
Waffle Pack
Evaluation Kit
Document No. 70-0197-01 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
Contact sales@psemi.com for full version of datasheet
Page 3 of 4
PE42672
Advance Information
Sales Offices
The Americas
North Asia Pacific
Peregrine Semiconductor Corp.
9450 Carroll Park Drive
San Diego, CA 92121
Peregrine Semiconductor K.K.
5A-5, 5F Imperial Tower
1-1-1 Uchisaiwaicho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel 858-731-9400
Fax 858-731-9499
Tel: +81-3-3502-5211
Fax: +81-3-3502-5213
Europe
South Asia Pacific
Peregrine Semiconductor Europe
Commercial Products:
Bâtiment Maine
13-15 rue des Quatre Vents
F- 92380 Garches, France
Tel: +33-1-47-41-91-73
Peregrine Semiconductor
28G, Times Square,
No. 500 Zhangyang Road,
Shanghai, 200122, P.R. China
Tel: +86-21-5836-8276
Fax: +86-21-5836-7652
Fax : +33-1-47-41-91-73
Space and Defense Products:
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Tel: +33(0) 4 4239 3361
Fax: +33(0) 4 4239 7227
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Preliminary Specification
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS and HaRP are trademarks of Peregrine
Semiconductor Corp.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0197-01 │ UltraCMOS™ RFIC Solutions
Page 4 of 4
Contact sales@psemi.com for full version of datasheet
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