LCD24C [PROTEC]
5LOW CAPACITANCE TVS ARRAY; 5LOW电容TVS阵列
| 型号： | LCD24C |
| 厂家： | 
PROTEK DEVICES |
| 描述： | 5LOW CAPACITANCE TVS ARRAY |
| 文件： | 总5页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LCD05C
thru
LCD24C
LOW CAPACITANCE TVS ARRAY
APPLICATIONS
✔ Ethernet - 10/100 Base T
✔ RS-458
✔ xDSL&ATM
✔ SCSI & USB
✔ Audio/Video I/O Ports
IEC COMPATIBILITY (EN61000-4)
✔ 61000-4-2 (ESD): Air - 15kV, Contact - 8kV
✔ 61000-4-4 (EFT): 40A - 5/50ns
16 PIN DIP
✔ 61000-4-5 (Surge): 24A, 8/20µs Level 2 (Line-Ground) & Level 3 (Line-Line)
FEATURES
✔ 800 Watts Peak Pulse Power per Line (tp=8/20µs)
✔ Bidirectional Configuration
✔ ESD Protection > 40 kilovolts
✔ Available in 5 Voltage Types: 5V to 24V
✔ Standard Dual-In-Line Package
✔ Protects up to 8 Lines
✔ Low Capacitance: 15pF
✔ RoHS Compliant
MECHANICAL CHARACTERISTICS
✔ Molded 16 Pin Dual-In-Line (DIP) Package
✔ Weight 1.2 grams (Approximate)
✔ Available in Lead-Free Pure-Tin Plating(Annealed)
✔ Solder Reflow Temperature:
Pure-Tin - Sn, 100: 260-270°C
✔ Consult Factory for Leaded Device Availability
✔ Flammability Rating UL 94V-0
✔ Packaging: 25 Pieces Per Tube
✔ Marking: Logo, Part Number, Date Code & Pin One Defined By Dot on Top of Package
PIN CONFIGURATION
13
12
11
10
9
8
15
14
16
1
3
5
7
2
4
6
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DEVICE CHARACTERISTICS
MAXIMUM RATINGS @ 25°C Unless Otherwise Specified
SYMBOL
VALUE
800
UNITS
Watts
°C
PARAMETER
Peak Pulse Power (tp = 8/20µs) - See Figure 1
Operating Temperature
PPP
TL
-55 to 150
-55 to 150
Storage Temperature
TSTG
°C
ELECTRICAL CHARACTERISTICS PER LINE @ 25°C Unless Otherwise Specified
PART
NUMBER
(See Note 1)
RATED
STAND-OFF
VOLTAGE
MINIMUM
BREAKDOWN
VOLTAGE
MAXIMUM
CLAMPING
VOLTAGE
(See Fig. 2)
MAXIMUM
CLAMPING
VOLTAGE
(See Fig. 2)
MAXIMUM
LEAKAGE
CURRENT
MAXIMUM
CAPACITANCE
TEMPERATURE
COEFFICIENT
OF V(BR)
@ 1mA
V(BR)
VOLTS
@ IP = 1A
VC
VOLTS
@VWM
0V @ 1 MHz
qV(BR)
mV/°C
VWM
VOLTS
@8/20µs
VC @ IPP
I
C
pF
µDA
LCD05C
LCD08C
LCD12C
LCD15C
LCD24C
5.0
8.0
12.0
15.0
24.0
6.0
8.5
13.3
16.7
26.7
9.8
24V @ 45A
25.5V @ 40A
32V @ 34A
38V @ 27A
48V @ 22A
100
10
4
4
4
15
15
15
15
15
3
9
16
17
26
12.3
19.0
25.5
40.0
Note 1: Tested on pin pairs 1 & 16, 2 & 15, 3 &14, 4 & 13, 5 & 12, 6 & 11, 7 & 10 and 8 & 9.
FIGURE 1
FIGURE 2
PEAK PULSE POWER VS PULSE TIME
PULSE WAVE FORM
120
100
10,000
TEST
tf
WAVEFORM
PARAMETERS
tf = 8µs
Peak Value IPP
800W 8/20µs Waveform
1,000
80
60
40
td = 20µs
e-t
100
10
td = t
IPP/2
20
0
0
5
10
15
20
25
30
0.1
1
10
100
1,000
10,000
t - Time - µs
td - Pulse Duration - µs
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GRAPHS
FIGURE 3
POWER DERATING CURVE
100
80
Peak Pulse Power
8/20µs
60
40
20
0
Average Power
0
25
50
75
100
125 150
TL - Lead Temperature - °C
FIGURE 4
OVERSHOOT & CLAMPING VOLTAGE FOR LCD05C
25
15
5
-5
-15
ESD Test Pulse: 12 kilovolt, 1/30ns (waveform)
FIGURE 5
TYPICAL CLAMPING VOLTAGE VS PEAK PULSE CURRENT FOR LCD05C
16
12
8
4
0
0
2
4
6
8
10
12
14
16
18
IPP - Peak Pulse Current - Amps
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APPLICATION NOTE
The LCD Series are low capacitance, bidirectional TVS arrays that are designed to protect I/O or high speed data lines from the damaging effects of
ESD or EFT. This product series has a surge capability of 800 Watts PPP per line for an 8/20µs waveshape and offers ESD protection > 40kV.
BIDIRECTIONAL COMMON-MODE CONFIGURATION (Figure 1)
Ideal for use in USB applications, the LCD Series provides up to eight (8) lines of protection in a common-mode configuration as depicted in Figure 1.
Circuit connectivity is as follows:
✔
✔
✔
✔
Pins 2, 3, 4, 5, 6, and 7 are connected to ground.
Pins 15 and 14 connected to Port #1 D- and D+.
Pins 13 and 12 connected to Port #2 D+ and D-.
Pins 11 and 10 connected to Port #3 D+ and D-.
Figure1. Typical Common- Mode USB Protection Circuit
PORT #1
D+
PORT #2
D+
USB OUTPUT
USB OUTPUT
CONNECTOR
CONNECTOR
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
D-
D-
16
15
14
13
Circuit board layout is critical for Electromagnetic
Compatibility (EMC) protection. The following guidelines
are recommended:
USB
IC
✔
The protection device should be placed near the
input terminals or connectors. By placing the TVS
close to the connectors, the device will divert the
transient current immediately before it can be
coupled into the nearby traces.
1
2
3
4
D+
D-
D+
D-
✔
✔
✔
The path length between the TVS devices and the
protected line should be minimized
12
11
10
9
PORT #3
PORT #4
All conductive loops including power and ground
loops should be minimized
The transient current return path to ground should
be kept as short as possible to reduce parasitic
inductance.
5
6
7
8
✔
Ground planes should be used whenever possible.
For Multilayer PCBs, use ground vias.
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16 PIN DIP PACKAGE OUTLINE & DIMENSIONS
PACKAGE OUTLINE
16 PIN DIP
A
DIMENSIONS
INCHES
MILLIMETERS
Orientation Dot
(Pin #1)
DIM
MIN
MAX
MIN
MAX
A
B
C
D
E
F
G
H
I
-
19.8
7.87
6.60
0.50
10°
-
5.08
-
1.78
-
0.780
0.310
0.260
0.020
10°
B
7.37
6.10
0.25
0°
0.51
-
0.290
0.240
0.010
0°
I
C
12 Places
F
F
0.020
-
0.125
-
-
0.200
-
0.070
3.17
-
J
12 Places
G
J
0.84 TYP 0.84 TYP 0.033 TYP 0.033 TYP
K
L
0.38
2.54 TYP
0.53
0.015
2.54 TYP 0.100 TYP
0.021
0.100 TYP
D
K
L
16 Places
H
16 Places
E
NOTES:
1. Dimensions are exclusive of mold flash and metal
burrs.
BULK ORDERING NOMENCLATURE:
1. No Suffix = Product Shipped in Tubes of 25 pcs per Tube.
2. Suffix - LF = Lead-Free, Pure-Tin Plating,
i.e., LCD05C-LF.
Outline & Dimensions: Rev 1 - 11/01, 06003
ProTek Devices
2929 South Fair Lane, Tempe, AZ 85282
COPYRIGHT © ProTek Devices 2007
SPECIFICATIONS: ProTek reserves the right to change the electrical and or mechanical characteristics described herein without notice (except JEDEC).
Tel: 602-431-8101 Fax: 602-431-2288
E-Mail: sales@protekdevices.com
Web Site: www.protekdevices.com
DESIGN CHANGES: ProTek reserves the right to discontinue product lines without notice, and that the final judgement concerning selection and specifications is
the buyer’s and that in furnishing engineering and technical assistance, ProTek assumes no responsibility with respect to the selection or specifications of such
products.
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