PS11013 [POWEREX]
FLAT-BASE TYPE INSULATED TYPE; FLAT -BASE型绝缘型
| 型号： | PS11013 |
| 厂家： | 
POWEREX POWER SEMICONDUCTORS |
| 描述： | FLAT-BASE TYPE INSULATED TYPE |
| 文件： | 总6页 (文件大小：410K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHISEMICONDUCTOR<ApplicationSpecificIntelligentPowerModule>
PS11013
FLAT-BASETYPE
INSULATEDTYPE
PS11013
INTEGRATED FUNCTIONS AND FEATURES
• Converter bridge for 3 phase AC-to-DC power conversion.
• Circuit for dynamic braking of motor regenerative energy.
• 3-phase IGBT inverter bridge configured by the latest 3rd.
generation IGBT and diode technology.
• Inverter output current capability IO (Note 1):
Type Name
PS11013
100% load
3.0A (rms)
150% over load
4.5A (rms), 1min
(Note 1) : The inverter output current is assumed to be sinu-
soidal and the peak current value of each of the
above loading cases is defined as : IOP = IO × √2
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS:
• For inverter side upper-leg IGBTs : Drive circuit, High voltage isolated high-speed level shifting, Short circuit protection (SC).
Bootstrap circuit supply scheme (single drive power supply) and Under voltage protection (UV).
• For inverter side lower-leg IGBTs : Drive circuit, Short circuit protection (SC).
Control supply circuit under- & over- voltage protection (OV/UV).
System over temperature protection (OT). Fault output signaling circuit (FO) and Current limit warn-
ing signal output (CL).
• For Brake circuit IGBT : Drive circuit
• Warning and Fault signaling :
FO1 : Short circuit protection for lower-leg IGBTs and Input interlocking against spurious arm shoot-through.
FO2 : N-side control supply abnormality locking (OV/UV).
FO3 : System over-temperature protection (OT).
CL :Warning for inverter current overload condition
• For system feedback control : Analogue signal feedback reproducing actual inverter output phase currents (3φ).
• Input Interface : 5V CMOS/TTL compatible, Schmitt trigger input, and Arm-Shoot-Through interlock protection.
APPLICATION
Acoustic noise-less 0.4kW/AC200V class 3 phase inverter and other motor control applica-
tions
PACKAGE OUTLINES
4-R2
0.5
Terminals Assignment:
✽
6
1
2
3
4
5
6
7
8
9
CBU+
CBU–
CBV+
CBV–
CBW+
CBW–
GND
21 VN
22 WN
23 Br
12 3 4 5 6 7 8 910 11121314151617181920212223
2
± 0.3
24
2 4 2 4
NC
VDH
10 CL
11 FO1
12 FO2
13 FO3
14 CU
15 CV
16 CW
17 UP
18 VP
19 WP
20 UN
2
31
32
33
34 P1
35 P2
36
37
38
39
40
R
S
T
2-φ4
2-R4
N
B
U
V
4.14
5.08 ± 0.3 ✕ 9 = 45.72 ± 0.8
31
32 33 34 35 36 37 38 39 40
W
1.2
✽ Control Pin top
✽ Main terminal top
portion details
portion details
± 0.5
0
0.8
0.3
LABEL
54 ± 0.5
62 ± 1
0.35MAX
0.6
± 0.5
0
12
0.5 ± 0.03
(Fig. 1)
Jan. 2000
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11013
FLAT-BASE TYPE
INSULATED TYPE
INTERNAL FUNCTIONS BLOCK DIAGRAM
C3 ; 3.3µF or more, tight tolerance, temp-compensated electrolytic type (Note : the value may change
depending on the type PWM control scheme used in the applied system)
C4 ; 2µF R-category ceramic condenser for noise filtering.
Application Specific Intelligent
Power Module
Protection
Circuit
Level shifter
Drive Circuit
P2
Brake resistor
connection,
Inrush prevention
circuit, etc.
B
P1
AC200V line input
R
S
T
U
V
M
W
AC 200V line
output
Z
C
T.S.
N
Z : Surge absorber.
C : AC filter (Ceramic condenser 2.2~6.5nF)
[Note : Additionally an appropriate Line-to line
surge absorber circuit maybe necessary
depending on the application environment].
Current sensing
circuit
Drive Curcuit
Protection Control supply
circuit
fault sense
FO Logic
Trig signal conditioning
C2 ;
3.3µF or more
C2
CUCVCW
Analogue signal output corresponding to Each phase input (PWM) Fault output
each phase current (5V line) Note 1) (5V line) Note 2) (5V line) Note 3)
Note 1) To prevent chances of signal oscillation, an RC coupling at each output is recommended. (see also Fig.10)
U
P
V
P
W
P
U
N
V
N
W
N
B
r
CL FO1 FO2 FO3
GND VDH
(15V line)
Note 2) By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU, without any opto or transformer isolation ispossible. (see also Fig.10)
Note 3) All these outputs are open collector type. Each signal line should be pulled up to plus side of the 5V power supply with approximately 5.1kΩ resistance. (see also Fig.10)
Note 4) The wiring between power DC link capacitor and P/N terminals should be as short as possible to protect the ASIPM against catastrophic high surge voltage. For extra
precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P and N DC powerinput pins.
(Fig. 2)
MAXIMUM RATINGS (Tj = 25°C)
INVERTER PART (Including Brake Part)
Symbol
Item
Condition
Applied between P2-N
Ratings
450
Unit
V
VCC
Supply voltage
Supply voltage (surge)
VCC(surge)
Applied between P2-N, Surge-value
500
V
Applied between P-U, V, W, Br or U, V, W,
Br-N
V
V
Each output IGBT collector-emitter static voltage
VP or VN
600
600
Each output IGBT collector-emitter
switching surge voltage
Applied between P-U, V, W, Br or U, V, W,
Br-N
VP(S) or VN(S)
±IC(±ICP) Each output IGBT collector current
A
A
A
±8 (±16)
3 (6)
TC = 25°C
IC(ICP)
IF(IFP)
Brake IGBT collector current
Brake diode anode current
Note:“( )” means IC peak value
3 (6)
CONVERTER PART
Symbol
Item
Condition
Ratings
800
220
25
Unit
V
VRRM
Ea
Repetitive peak reverse voltage
Recommended AC input voltage
DC output current
V
IO
3φ rectifying circuit
A
IFSM
I2t
Surge (non-repetitive) forward current
I2t for fusing
1 cycle at 60Hz, peak value non-repetitive
Value for one cycle of surge current
138
80
A
A2s
CONTROL PART
Symbol
Item
Ratings
20
Unit
V
Condition
Applied between VDH-GND, CBU+-CBU–,
CBV+-CBV–, CBW+-CBW–
VDH, VDB
VCIN
Supply voltage
Applied between UP · VP · WP · UN · VN ·
WN · Br-GND
Input signal voltage
–0.5 ~ 7.5
V
Fault output supply voltage
Fault output current
Applied between FO1 · FO2 · FO3-GND
Sink current of FO1 · FO2 · FO3
Applied between CL-GND
Sink current of CL
VFO
IFO
–0.5 ~ 7
15
V
mA
V
Current-limit warning (CL) output voltage
CL output current
VCL
ICL
–0.5 ~ 7
15
mA
mA
Analogue current signal output current
ICO
Sink current of CU · CV · CW
±1
Jan. 2000
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11013
FLAT-BASE TYPE
INSULATED TYPE
TOTAL SYSTEM
Symbol
Condition
—
Ratings
Unit
°C
Item
Tj
Junction temperature
(Note 2)
(Fig. 3)
–20 ~ +125
–40 ~ +125
–20 ~ +100
Tstg
TC
Storage temperature
°C
Module case operating temperature
°C
60 Hz sinusoidal AC applied between all terminals and
the base plate for 1 minute.
Viso
Isolation voltage
Mounting torque
2500
Vrms
—
Mounting screw: M3.5
0.78 ~ 1.27
kg·cm
Note 2) The item defines the maximum junction temperature for the power elements (IGBT/Diode) of the ASIPM to ensure safe operation. How-
ever, these power elements can endure junction temperature as high as 150°C instantaneously . To make use of this additional tem-
perature allowance, a detailed study of the exact application conditions is required and, accordingly, necessary information is requested
to be provided before use.
CASE TEMPERATURE MEASUREMENT POINT (3mm from the base surface)
TC
(Fig. 3)
THERMAL RESISTANCE
Ratings
Symbol
Item
Condition
Unit
Min.
—
Typ.
—
Max.
4.1
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Rth(j-c)Q
Rth(j-c)F
Rth(j-c)QB
Rth(j-c)FB
Rth(j-c)FR
Rth(c-f)
Inverter IGBT (1/6)
Inverter FWDi (1/6)
Brake IGBT
—
—
6.1
Junction to case Thermal
Resistance
—
—
6.1
Brake FWDi
—
—
6.1
Converter Di (1/6)
—
—
4.8
Contact Thermal Resistance
Case to fin, thermal grease applied (1 Module)
—
—
0.053
ELECTRICAL CHARACTERISTICS (Tj = 25°C, VDH = 15V, VDB = 15V unless otherwise noted)
Ratings
Typ.
—
Symbol
Item
Condition
Unit
Min.
—
Max.
2.9
VCE(sat)
VEC
VDH = VDB = 15V, Input = ON, Tj = 25°C, IC = 8A
Tj = 25°C, IC = –8A, Input = OFF
V
V
Collector-emitter saturation voltage
FWDi forward voltage
—
—
2.9
Brake IGBT
Collector-emitter saturation voltage
VCE(sat)Br
VDH = 15V, Input = ON, Tj = 25°C, IC = 3A
—
—
3.5
V
VFBr
IRRM
VFR
ton
Brake diode forward voltage
Tj = 25°C, IF = 3A, Input = OFF
—
—
—
—
2.9
8
V
mA
V
Converter diode reverse current VR = VRRM, Tj = 125°C
Tj = 25°C, IF = 5A
—
—
1.5
1.5
Converter diode voltage
0.3
0.6
µs
µs
µs
µs
µs
1/2 Bridge inductive load, Input = ON
VCC = 300V, Ic = 8A, Tj = 125°C
VDH = 15V, VDB = 15V
tc(on)
toff
—
—
0.2
1.1
0.6
1.8
Switching times
tc(off)
trr
—
—
0.35
0.1
1.0
—
Note : ton, toff include delay time of the internal control
circuit
FWD reverse recovery time
Short circuit endurance
(Output, Arm, and Load,
Short Circuit Modes)
VCC ≤ 400V, Input = ON (one-shot)
Tj = 125°C start
• No destruction
• FO output by protection operation
13.5V ≤ VDH = VDB ≤ 16.5V
VCC ≤ 400V, Tj ≤ 125°C,
• No destruction
• No protecting operation
• No FO output
Ic < IOL(CL) operation level, Input = ON
13.5V ≤ VDH = VDB ≤ 16.5V
Switching SOA
Jan. 2000
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11013
FLAT-BASE TYPE
INSULATED TYPE
ELECTRICAL CHARACTERISTICS (Tj = 25°C, VDH = 15V, VDB = 15V unless otherwise noted)
Symbol Item Condition
VDH = 15V, VCIN = 5V
Ratings
Typ.
Unit
Max.
150
2.0
4.0
—
Min.
—
0.8
2.5
—
IDH
Circuit current
—
1.4
3.0
150
—
mA
V
Vth(on)
Vth(off)
Ri
Input on threshold voltage
Input off threshold voltage
Input pull-up resistor
V
Integrated between input terminal-VDH
TC ≤ 100°C, Tj ≤ 125°C
kΩ
kHz
µs
2
20
fPWM
txx
PWM input frequency
VDH = 15V, TC = –20°C ~ +100°C
Relates to corresponding input
(Note 3)
1
—
500
Allowable input on-pulse width
Allowable input signal dead time for
blocking arm shoot-through
tdead
2.2
—
—
µs
(Except brake part) T
C = –20°C ~ +100°C
Input inter-lock sensing
—
1.87
0.77
2.97
—
65
2.27
1.17
3.37
15
100
2.57
1.47
3.67
—
ns
Relates to corresponding input (Except brake part)
tint
VCO
V
V
Ic = 0A
VDH = 15V
Analogue signal linearity with
output current
Ic = IOP(200%)
Ic = –IOP(200%)
V
V
C+(200%)
C–(200%)
TC = –20°C ~ +100°C
(Fig. 4)
V
Offset change area vs temperature
Analogue signal output voltage limit
VDH = 15V, TC = –20°C ~ +100°C
|∆VCO|
VC+
mV
V
—
—
0.7
—
Ic > IOP(200%), VDH = 15V
4.0
—
(Fig. 4)
—
VC–
V
|VCO-VC±(200%)|
1.1
—
Analogue signal over all linear variation
Analogue signal data hold accuracy
∆VC(200%)
V
Correspond to max. 500µs data hold period
rCH
–5
—
5
%
only, Ic = IOP(200%)
(Fig. 5)
td(read)
±IOL
—
7.93
—
3
—
13.90
1
µs
A
Analogue signal reading time
After input signal trigger point
(Fig. 8)
10.80
—
Current limit warning (CL) operation level
VDH =15V, TC = –20°C ~ +100°C
(Note 4)
ICL(H)
ICL(L)
SC
µA
mA
A
Idle
Signal output current of
CL operation
Open collector output
—
1
—
Active
Short circuit over current trip level
Tj = 25°C
(Fig. 7) (Note 5)
13.2
100
—
24.0
110
90
34.3
120
—
OT
Trip level
°C
°C
V
Over temperature protection
VDH =15V
Reset level
Trip level
Reset level
Trip level
Reset level
Trip level
Reset level
Filter time
Idle
OTr
UVDH
UVDHr
OVDH
OVDHr
UVDB
UVDBr
tdV
11.05
11.55
18.00
16.50
10.0
10.5
—
12.00
12.50
19.20
17.50
11.0
11.5
10
12.75
13.25
20.15
18.65
12.0
12.5
—
V
V
TC = –20°C ~ +100°C
Tj ≤ 125°C
Supply circuit under &
over voltage protection
V
V
V
µs
µA
IFO(H)
IFO(L)
—
—
1
Fault output current
Open collector output
Active
mA
—
1
—
(Note 3) : (a) Allowable minimum input on-pulse width :This item applies to P-side circuit only.
(b) Allowable maximum input on-pulse width :This item applies to both P-side and N-side circuits excluding the brake circuit.
(Note4) : CL output : The "current limit warning (CL) operation circuit outputs warning signal whenever the arm current exceeds this limit. The
circuit is reset automatically by the next input signal and thus, it operates on a pulse-by-pulse scheme.
(Note5) : The short circuit protection works instantaneously when a high short circuit current flows through an internal IGBT rising up momen-
tarily.The protection function is, thus meant primarily to protect the ASIPM against short circuit distraction. Therefore, this function is
not recommended to be used for any system load current regulation or any over load control as this might, cause a failure due to
excessive temperature rise. Instead, the analogue current output feature or the over load warning feature (CL) should be appropri-
ately used for such current regulation or over load control operation. In other words, the PWM signals to the ASIPM should be shut
down, in principle, and not to be restarted before the junction temperature would recover to normal, as soon as a fault is feed back
from its FO1 pin of the ASIPM indicating a short circuit situation.
RECOMMENDED CONDITIONS
Item
Supply voltage
Ratings
Unit
V
Symbol
VCC
Condition
Applied across P2-N terminals
400 (max.)
Applied between VDH-GND, CBU+-CBU–, CBV+-CBV–,
CBW+-CBW–
VDH, VDB
15±1.5
V
Control supply voltage
∆VDH, ∆VDB
VCIN(on)
VCIN(off)
fPWM
±1 (max.)
0 ~ 0.3
Supply voltage ripple
Input on voltage
V/µs
V
4.8 ~ 5.0
2 ~ 20
Input off voltage
V
PWM Input frequency
Arm shoot-through blocking time
Using application circuit
Using application circuit
kHz
µs
tdead
2.2 (min.)
Jan. 2000
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11013
FLAT-BASE TYPE
INSULATED TYPE
Fig. 4 OUTPUT CURRENT ANALOGUE SIG-
Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING
“DATA HOLD” DEFINITION
NALING LINEARITY
5
VC
V
DH=15V
V
C
–
max
TC=–20~100˚C
4
min
500µs
VC–(200%)
3
0V
V
CH(5µs)
VCH(505µs)
V
C0
2
1
0
V
CH(505
µ
s)-VCH(5
µs)
r
CH=
VC+(200%)
VCH(5
µs)
Note ; Ringing happens around the point where the signal output
voltage changes state from “analogue” to “data hold” due
to test circuit arrangement and instrumentational trouble.
Therefore, the rate of change is measured at a 5 µs delayed point.
Analogue output signal
data hold range
VC+
–400 –300 –200 –100
0
100 200 300 400
Real load current peak value.(%)(Ic=Io✕ 2)
(Fig. 4)
Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART
Input signal VCIN(p) of each phase upper arm
0V
Input signal VCIN(n) of each phase lower arm
0V
Gate signal Vo(p) of each phase upper arm
(ASIPM internal)
0V
Gate signal Vo(n) of each phase upper arm
(ASIPM internal)
0V
0V
Error output FO1
Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta-
neously in “LOW” level.
By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and “F ” signal is outputted. After an “input
O
O
interlock” operation the circuit is latched. The “F ” is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input,
whichever comes in later.
Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION
Input signal VCIN of each phase
upper arm
0V
0V
0V
Short circuit sensing signal V
S
SC delay time
Gate signal Vo of each phase
upper arm(ASIPM internal)
Error output FO1
0V
Note : Short circuit protection operation. The protection operates with “F
O
” flag and reset on a pulse-by-pulse scheme. The protection by
gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the “Brake”).
Jan. 2000
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11013
FLAT-BASE TYPE
INSULATED TYPE
Fig. 8 INVERTER OUTPUT ANALOGUE CURRENT SENSING AND SIGNALING TIMING CHART
N-side IGBT Current
N-side FWDi Current
off
V
CIN
on
on
V(hold)
off
I
C
0
+ICL
(VS)
0
–ICL
t(hold)
Ref
V
C
0
off
V
CL
on
Delay time
td(read)
Fig. 9 START-UP SEQUENCE
Fig. 10 RECOMMENDED I/O INTERFACE CIRCUIT
Normally at start-up, Fo and CL output signals will be pulled-up
High to Supply voltage (OFF level); however, FO1 output may fall to
Low (ON) level at the instant of the first ON input pulse to an N-Side
IGBT. This can happen particularly when the boot-strap capacitor is
of large size. FO1 resetting sequence (together with the boot-strap
charging sequence) is explained in the following graph
5V
ASIPM
5.1kΩ
R
UP,VP,WP,UN,VN,WN,Br
DC-Bus voltage
PWM starts
a)
V
PN
0
R
CPU
Control voltage supply
Boot-strap voltage
N-Side input signal
F01,F02,F03,CL
V
DH
0
10kΩ
0.1nF
V
DB
CU,CV,CW
GND(Logic)
0
b)
0.1nF
V
CIN(N)
on
on
V
CIN(P)
P-Side input signal
Brake input signal
V
CIN(Br)
on
on
F
OI
FO1 output signal
a) Boot-strap charging scheme :
Apply a train of short ON pulses at all N-IGBT input pins for ad-
equate charging (pulse width = approx. 20µs number of pulses =10
~ 500 depending on the boot-strap capacitor size)
b) FO1 resetting sequence:
Apply ON signals to the following input pins : Br → Un/Vn/Wn →
Up/Vp/Wp in that order.
Jan. 2000
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